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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e5868a31 EE |
48 | static const u32 hpd_ibx[] = { |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
54 | }; | |
55 | ||
56 | static const u32 hpd_cpt[] = { | |
57 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 58 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
59 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
60 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
61 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
62 | }; | |
63 | ||
64 | static const u32 hpd_mask_i915[] = { | |
65 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
71 | }; | |
72 | ||
704cfb87 | 73 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
80 | }; | |
81 | ||
e5868a31 EE |
82 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
83 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
84 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
85 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
86 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
87 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
88 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
89 | }; | |
90 | ||
5c502442 | 91 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 92 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
93 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
94 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
95 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
96 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
97 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
98 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
99 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
100 | } while (0) | |
101 | ||
f86f3fb0 | 102 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 103 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 104 | POSTING_READ(type##IMR); \ |
a9d356a6 | 105 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
106 | I915_WRITE(type##IIR, 0xffffffff); \ |
107 | POSTING_READ(type##IIR); \ | |
108 | I915_WRITE(type##IIR, 0xffffffff); \ | |
109 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
110 | } while (0) |
111 | ||
337ba017 PZ |
112 | /* |
113 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
114 | */ | |
115 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
116 | u32 val = I915_READ(reg); \ | |
117 | if (val) { \ | |
118 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
119 | (reg), val); \ | |
120 | I915_WRITE((reg), 0xffffffff); \ | |
121 | POSTING_READ(reg); \ | |
122 | I915_WRITE((reg), 0xffffffff); \ | |
123 | POSTING_READ(reg); \ | |
124 | } \ | |
125 | } while (0) | |
126 | ||
35079899 | 127 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 128 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 | 129 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
130 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
131 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
132 | } while (0) |
133 | ||
134 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 135 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 | 136 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
137 | I915_WRITE(type##IMR, (imr_val)); \ |
138 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
139 | } while (0) |
140 | ||
c9a9a268 ID |
141 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
142 | ||
036a4a7d | 143 | /* For display hotplug interrupt */ |
47339cd9 | 144 | void |
2d1013dd | 145 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 146 | { |
4bc9d430 DV |
147 | assert_spin_locked(&dev_priv->irq_lock); |
148 | ||
9df7575f | 149 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 150 | return; |
c67a470b | 151 | |
1ec14ad3 CW |
152 | if ((dev_priv->irq_mask & mask) != 0) { |
153 | dev_priv->irq_mask &= ~mask; | |
154 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 155 | POSTING_READ(DEIMR); |
036a4a7d ZW |
156 | } |
157 | } | |
158 | ||
47339cd9 | 159 | void |
2d1013dd | 160 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 161 | { |
4bc9d430 DV |
162 | assert_spin_locked(&dev_priv->irq_lock); |
163 | ||
06ffc778 | 164 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 165 | return; |
c67a470b | 166 | |
1ec14ad3 CW |
167 | if ((dev_priv->irq_mask & mask) != mask) { |
168 | dev_priv->irq_mask |= mask; | |
169 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 170 | POSTING_READ(DEIMR); |
036a4a7d ZW |
171 | } |
172 | } | |
173 | ||
43eaea13 PZ |
174 | /** |
175 | * ilk_update_gt_irq - update GTIMR | |
176 | * @dev_priv: driver private | |
177 | * @interrupt_mask: mask of interrupt bits to update | |
178 | * @enabled_irq_mask: mask of interrupt bits to enable | |
179 | */ | |
180 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
181 | uint32_t interrupt_mask, | |
182 | uint32_t enabled_irq_mask) | |
183 | { | |
184 | assert_spin_locked(&dev_priv->irq_lock); | |
185 | ||
9df7575f | 186 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 187 | return; |
c67a470b | 188 | |
43eaea13 PZ |
189 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
190 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
191 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
192 | POSTING_READ(GTIMR); | |
193 | } | |
194 | ||
480c8033 | 195 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
196 | { |
197 | ilk_update_gt_irq(dev_priv, mask, mask); | |
198 | } | |
199 | ||
480c8033 | 200 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
201 | { |
202 | ilk_update_gt_irq(dev_priv, mask, 0); | |
203 | } | |
204 | ||
b900b949 ID |
205 | static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) |
206 | { | |
207 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
208 | } | |
209 | ||
a72fbc3a ID |
210 | static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) |
211 | { | |
212 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
213 | } | |
214 | ||
b900b949 ID |
215 | static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) |
216 | { | |
217 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
218 | } | |
219 | ||
edbfdb45 PZ |
220 | /** |
221 | * snb_update_pm_irq - update GEN6_PMIMR | |
222 | * @dev_priv: driver private | |
223 | * @interrupt_mask: mask of interrupt bits to update | |
224 | * @enabled_irq_mask: mask of interrupt bits to enable | |
225 | */ | |
226 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
227 | uint32_t interrupt_mask, | |
228 | uint32_t enabled_irq_mask) | |
229 | { | |
605cd25b | 230 | uint32_t new_val; |
edbfdb45 PZ |
231 | |
232 | assert_spin_locked(&dev_priv->irq_lock); | |
233 | ||
605cd25b | 234 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
235 | new_val &= ~interrupt_mask; |
236 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
237 | ||
605cd25b PZ |
238 | if (new_val != dev_priv->pm_irq_mask) { |
239 | dev_priv->pm_irq_mask = new_val; | |
a72fbc3a ID |
240 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
241 | POSTING_READ(gen6_pm_imr(dev_priv)); | |
f52ecbcf | 242 | } |
edbfdb45 PZ |
243 | } |
244 | ||
480c8033 | 245 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 | 246 | { |
9939fba2 ID |
247 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
248 | return; | |
249 | ||
edbfdb45 PZ |
250 | snb_update_pm_irq(dev_priv, mask, mask); |
251 | } | |
252 | ||
9939fba2 ID |
253 | static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, |
254 | uint32_t mask) | |
edbfdb45 PZ |
255 | { |
256 | snb_update_pm_irq(dev_priv, mask, 0); | |
257 | } | |
258 | ||
9939fba2 ID |
259 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
260 | { | |
261 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
262 | return; | |
263 | ||
264 | __gen6_disable_pm_irq(dev_priv, mask); | |
265 | } | |
266 | ||
3cc134e3 ID |
267 | void gen6_reset_rps_interrupts(struct drm_device *dev) |
268 | { | |
269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
270 | uint32_t reg = gen6_pm_iir(dev_priv); | |
271 | ||
272 | spin_lock_irq(&dev_priv->irq_lock); | |
273 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
274 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
275 | POSTING_READ(reg); | |
276 | spin_unlock_irq(&dev_priv->irq_lock); | |
277 | } | |
278 | ||
b900b949 ID |
279 | void gen6_enable_rps_interrupts(struct drm_device *dev) |
280 | { | |
281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
282 | ||
283 | spin_lock_irq(&dev_priv->irq_lock); | |
78e68d36 | 284 | |
b900b949 | 285 | WARN_ON(dev_priv->rps.pm_iir); |
3cc134e3 | 286 | WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
d4d70aa5 | 287 | dev_priv->rps.interrupts_enabled = true; |
78e68d36 ID |
288 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | |
289 | dev_priv->pm_rps_events); | |
b900b949 | 290 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 291 | |
b900b949 ID |
292 | spin_unlock_irq(&dev_priv->irq_lock); |
293 | } | |
294 | ||
295 | void gen6_disable_rps_interrupts(struct drm_device *dev) | |
296 | { | |
297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
298 | ||
d4d70aa5 ID |
299 | spin_lock_irq(&dev_priv->irq_lock); |
300 | dev_priv->rps.interrupts_enabled = false; | |
301 | spin_unlock_irq(&dev_priv->irq_lock); | |
302 | ||
303 | cancel_work_sync(&dev_priv->rps.work); | |
304 | ||
9939fba2 ID |
305 | spin_lock_irq(&dev_priv->irq_lock); |
306 | ||
b900b949 ID |
307 | I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ? |
308 | ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0); | |
9939fba2 ID |
309 | |
310 | __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
b900b949 ID |
311 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & |
312 | ~dev_priv->pm_rps_events); | |
9939fba2 ID |
313 | I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); |
314 | I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); | |
b900b949 | 315 | |
b900b949 | 316 | dev_priv->rps.pm_iir = 0; |
b900b949 | 317 | |
9939fba2 | 318 | spin_unlock_irq(&dev_priv->irq_lock); |
b900b949 ID |
319 | } |
320 | ||
fee884ed DV |
321 | /** |
322 | * ibx_display_interrupt_update - update SDEIMR | |
323 | * @dev_priv: driver private | |
324 | * @interrupt_mask: mask of interrupt bits to update | |
325 | * @enabled_irq_mask: mask of interrupt bits to enable | |
326 | */ | |
47339cd9 DV |
327 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
328 | uint32_t interrupt_mask, | |
329 | uint32_t enabled_irq_mask) | |
fee884ed DV |
330 | { |
331 | uint32_t sdeimr = I915_READ(SDEIMR); | |
332 | sdeimr &= ~interrupt_mask; | |
333 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
334 | ||
335 | assert_spin_locked(&dev_priv->irq_lock); | |
336 | ||
9df7575f | 337 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 338 | return; |
c67a470b | 339 | |
fee884ed DV |
340 | I915_WRITE(SDEIMR, sdeimr); |
341 | POSTING_READ(SDEIMR); | |
342 | } | |
8664281b | 343 | |
b5ea642a | 344 | static void |
755e9019 ID |
345 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
346 | u32 enable_mask, u32 status_mask) | |
7c463586 | 347 | { |
46c06a30 | 348 | u32 reg = PIPESTAT(pipe); |
755e9019 | 349 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 350 | |
b79480ba | 351 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 352 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 353 | |
04feced9 VS |
354 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
355 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
356 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
357 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
358 | return; |
359 | ||
360 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
361 | return; |
362 | ||
91d181dd ID |
363 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
364 | ||
46c06a30 | 365 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 366 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
367 | I915_WRITE(reg, pipestat); |
368 | POSTING_READ(reg); | |
7c463586 KP |
369 | } |
370 | ||
b5ea642a | 371 | static void |
755e9019 ID |
372 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
373 | u32 enable_mask, u32 status_mask) | |
7c463586 | 374 | { |
46c06a30 | 375 | u32 reg = PIPESTAT(pipe); |
755e9019 | 376 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 377 | |
b79480ba | 378 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 379 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 380 | |
04feced9 VS |
381 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
382 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
383 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
384 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
385 | return; |
386 | ||
755e9019 ID |
387 | if ((pipestat & enable_mask) == 0) |
388 | return; | |
389 | ||
91d181dd ID |
390 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
391 | ||
755e9019 | 392 | pipestat &= ~enable_mask; |
46c06a30 VS |
393 | I915_WRITE(reg, pipestat); |
394 | POSTING_READ(reg); | |
7c463586 KP |
395 | } |
396 | ||
10c59c51 ID |
397 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
398 | { | |
399 | u32 enable_mask = status_mask << 16; | |
400 | ||
401 | /* | |
724a6905 VS |
402 | * On pipe A we don't support the PSR interrupt yet, |
403 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
404 | */ |
405 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
406 | return 0; | |
724a6905 VS |
407 | /* |
408 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
409 | * A the same bit is for perf counters which we don't use either. | |
410 | */ | |
411 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
412 | return 0; | |
10c59c51 ID |
413 | |
414 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
415 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
416 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
417 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
418 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
419 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
420 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
421 | ||
422 | return enable_mask; | |
423 | } | |
424 | ||
755e9019 ID |
425 | void |
426 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
427 | u32 status_mask) | |
428 | { | |
429 | u32 enable_mask; | |
430 | ||
10c59c51 ID |
431 | if (IS_VALLEYVIEW(dev_priv->dev)) |
432 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
433 | status_mask); | |
434 | else | |
435 | enable_mask = status_mask << 16; | |
755e9019 ID |
436 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
437 | } | |
438 | ||
439 | void | |
440 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
441 | u32 status_mask) | |
442 | { | |
443 | u32 enable_mask; | |
444 | ||
10c59c51 ID |
445 | if (IS_VALLEYVIEW(dev_priv->dev)) |
446 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
447 | status_mask); | |
448 | else | |
449 | enable_mask = status_mask << 16; | |
755e9019 ID |
450 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
451 | } | |
452 | ||
01c66889 | 453 | /** |
f49e38dd | 454 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 455 | */ |
f49e38dd | 456 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 457 | { |
2d1013dd | 458 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 459 | |
f49e38dd JN |
460 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
461 | return; | |
462 | ||
13321786 | 463 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 464 | |
755e9019 | 465 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 466 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 467 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 468 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 469 | |
13321786 | 470 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
471 | } |
472 | ||
0a3e67a4 JB |
473 | /** |
474 | * i915_pipe_enabled - check if a pipe is enabled | |
475 | * @dev: DRM device | |
476 | * @pipe: pipe to check | |
477 | * | |
478 | * Reading certain registers when the pipe is disabled can hang the chip. | |
479 | * Use this routine to make sure the PLL is running and the pipe is active | |
480 | * before reading such registers if unsure. | |
481 | */ | |
482 | static int | |
483 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
484 | { | |
2d1013dd | 485 | struct drm_i915_private *dev_priv = dev->dev_private; |
702e7a56 | 486 | |
a01025af DV |
487 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
488 | /* Locking is horribly broken here, but whatever. */ | |
489 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
490 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 491 | |
a01025af DV |
492 | return intel_crtc->active; |
493 | } else { | |
494 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
495 | } | |
0a3e67a4 JB |
496 | } |
497 | ||
f75f3746 VS |
498 | /* |
499 | * This timing diagram depicts the video signal in and | |
500 | * around the vertical blanking period. | |
501 | * | |
502 | * Assumptions about the fictitious mode used in this example: | |
503 | * vblank_start >= 3 | |
504 | * vsync_start = vblank_start + 1 | |
505 | * vsync_end = vblank_start + 2 | |
506 | * vtotal = vblank_start + 3 | |
507 | * | |
508 | * start of vblank: | |
509 | * latch double buffered registers | |
510 | * increment frame counter (ctg+) | |
511 | * generate start of vblank interrupt (gen4+) | |
512 | * | | |
513 | * | frame start: | |
514 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
515 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
516 | * | | | |
517 | * | | start of vsync: | |
518 | * | | generate vsync interrupt | |
519 | * | | | | |
520 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
521 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
522 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
523 | * | | <----vs-----> | | |
524 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
525 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
526 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
527 | * | | | | |
528 | * last visible pixel first visible pixel | |
529 | * | increment frame counter (gen3/4) | |
530 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
531 | * | |
532 | * x = horizontal active | |
533 | * _ = horizontal blanking | |
534 | * hs = horizontal sync | |
535 | * va = vertical active | |
536 | * vb = vertical blanking | |
537 | * vs = vertical sync | |
538 | * vbs = vblank_start (number) | |
539 | * | |
540 | * Summary: | |
541 | * - most events happen at the start of horizontal sync | |
542 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
543 | * (depending on PIPECONF settings) after the start of vblank | |
544 | * - gen3/4 pixel and frame counter are synchronized with the start | |
545 | * of horizontal active on the first line of vertical active | |
546 | */ | |
547 | ||
4cdb83ec VS |
548 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
549 | { | |
550 | /* Gen2 doesn't have a hardware frame counter */ | |
551 | return 0; | |
552 | } | |
553 | ||
42f52ef8 KP |
554 | /* Called from drm generic code, passed a 'crtc', which |
555 | * we use as a pipe index | |
556 | */ | |
f71d4af4 | 557 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 558 | { |
2d1013dd | 559 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
560 | unsigned long high_frame; |
561 | unsigned long low_frame; | |
0b2a8e09 | 562 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
0a3e67a4 JB |
563 | |
564 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 565 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 566 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
567 | return 0; |
568 | } | |
569 | ||
391f75e2 VS |
570 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
571 | struct intel_crtc *intel_crtc = | |
572 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
573 | const struct drm_display_mode *mode = | |
574 | &intel_crtc->config.adjusted_mode; | |
575 | ||
0b2a8e09 VS |
576 | htotal = mode->crtc_htotal; |
577 | hsync_start = mode->crtc_hsync_start; | |
578 | vbl_start = mode->crtc_vblank_start; | |
579 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
580 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 581 | } else { |
a2d213dd | 582 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
391f75e2 VS |
583 | |
584 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
0b2a8e09 | 585 | hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1; |
391f75e2 | 586 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; |
0b2a8e09 VS |
587 | if ((I915_READ(PIPECONF(cpu_transcoder)) & |
588 | PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE) | |
589 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 VS |
590 | } |
591 | ||
0b2a8e09 VS |
592 | /* Convert to pixel count */ |
593 | vbl_start *= htotal; | |
594 | ||
595 | /* Start of vblank event occurs at start of hsync */ | |
596 | vbl_start -= htotal - hsync_start; | |
597 | ||
9db4a9c7 JB |
598 | high_frame = PIPEFRAME(pipe); |
599 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 600 | |
0a3e67a4 JB |
601 | /* |
602 | * High & low register fields aren't synchronized, so make sure | |
603 | * we get a low value that's stable across two reads of the high | |
604 | * register. | |
605 | */ | |
606 | do { | |
5eddb70b | 607 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 608 | low = I915_READ(low_frame); |
5eddb70b | 609 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
610 | } while (high1 != high2); |
611 | ||
5eddb70b | 612 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 613 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 614 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
615 | |
616 | /* | |
617 | * The frame counter increments at beginning of active. | |
618 | * Cook up a vblank counter by also checking the pixel | |
619 | * counter against vblank start. | |
620 | */ | |
edc08d0a | 621 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
622 | } |
623 | ||
f71d4af4 | 624 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 625 | { |
2d1013dd | 626 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 627 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
628 | |
629 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 630 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 631 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
632 | return 0; |
633 | } | |
634 | ||
635 | return I915_READ(reg); | |
636 | } | |
637 | ||
ad3543ed MK |
638 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
639 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 640 | |
a225f079 VS |
641 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
642 | { | |
643 | struct drm_device *dev = crtc->base.dev; | |
644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
645 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
646 | enum pipe pipe = crtc->pipe; | |
80715b2f | 647 | int position, vtotal; |
a225f079 | 648 | |
80715b2f | 649 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
650 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
651 | vtotal /= 2; | |
652 | ||
653 | if (IS_GEN2(dev)) | |
654 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
655 | else | |
656 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
657 | ||
658 | /* | |
80715b2f VS |
659 | * See update_scanline_offset() for the details on the |
660 | * scanline_offset adjustment. | |
a225f079 | 661 | */ |
80715b2f | 662 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
663 | } |
664 | ||
f71d4af4 | 665 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
666 | unsigned int flags, int *vpos, int *hpos, |
667 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 668 | { |
c2baf4b7 VS |
669 | struct drm_i915_private *dev_priv = dev->dev_private; |
670 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
671 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
672 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 673 | int position; |
78e8fc6b | 674 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
675 | bool in_vbl = true; |
676 | int ret = 0; | |
ad3543ed | 677 | unsigned long irqflags; |
0af7e4df | 678 | |
c2baf4b7 | 679 | if (!intel_crtc->active) { |
0af7e4df | 680 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 681 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
682 | return 0; |
683 | } | |
684 | ||
c2baf4b7 | 685 | htotal = mode->crtc_htotal; |
78e8fc6b | 686 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
687 | vtotal = mode->crtc_vtotal; |
688 | vbl_start = mode->crtc_vblank_start; | |
689 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 690 | |
d31faf65 VS |
691 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
692 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
693 | vbl_end /= 2; | |
694 | vtotal /= 2; | |
695 | } | |
696 | ||
c2baf4b7 VS |
697 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
698 | ||
ad3543ed MK |
699 | /* |
700 | * Lock uncore.lock, as we will do multiple timing critical raw | |
701 | * register reads, potentially with preemption disabled, so the | |
702 | * following code must not block on uncore.lock. | |
703 | */ | |
704 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 705 | |
ad3543ed MK |
706 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
707 | ||
708 | /* Get optional system timestamp before query. */ | |
709 | if (stime) | |
710 | *stime = ktime_get(); | |
711 | ||
7c06b08a | 712 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
713 | /* No obvious pixelcount register. Only query vertical |
714 | * scanout position from Display scan line register. | |
715 | */ | |
a225f079 | 716 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
717 | } else { |
718 | /* Have access to pixelcount since start of frame. | |
719 | * We can split this into vertical and horizontal | |
720 | * scanout position. | |
721 | */ | |
ad3543ed | 722 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 723 | |
3aa18df8 VS |
724 | /* convert to pixel counts */ |
725 | vbl_start *= htotal; | |
726 | vbl_end *= htotal; | |
727 | vtotal *= htotal; | |
78e8fc6b | 728 | |
7e78f1cb VS |
729 | /* |
730 | * In interlaced modes, the pixel counter counts all pixels, | |
731 | * so one field will have htotal more pixels. In order to avoid | |
732 | * the reported position from jumping backwards when the pixel | |
733 | * counter is beyond the length of the shorter field, just | |
734 | * clamp the position the length of the shorter field. This | |
735 | * matches how the scanline counter based position works since | |
736 | * the scanline counter doesn't count the two half lines. | |
737 | */ | |
738 | if (position >= vtotal) | |
739 | position = vtotal - 1; | |
740 | ||
78e8fc6b VS |
741 | /* |
742 | * Start of vblank interrupt is triggered at start of hsync, | |
743 | * just prior to the first active line of vblank. However we | |
744 | * consider lines to start at the leading edge of horizontal | |
745 | * active. So, should we get here before we've crossed into | |
746 | * the horizontal active of the first line in vblank, we would | |
747 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
748 | * always add htotal-hsync_start to the current pixel position. | |
749 | */ | |
750 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
751 | } |
752 | ||
ad3543ed MK |
753 | /* Get optional system timestamp after query. */ |
754 | if (etime) | |
755 | *etime = ktime_get(); | |
756 | ||
757 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
758 | ||
759 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
760 | ||
3aa18df8 VS |
761 | in_vbl = position >= vbl_start && position < vbl_end; |
762 | ||
763 | /* | |
764 | * While in vblank, position will be negative | |
765 | * counting up towards 0 at vbl_end. And outside | |
766 | * vblank, position will be positive counting | |
767 | * up since vbl_end. | |
768 | */ | |
769 | if (position >= vbl_start) | |
770 | position -= vbl_end; | |
771 | else | |
772 | position += vtotal - vbl_end; | |
0af7e4df | 773 | |
7c06b08a | 774 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
775 | *vpos = position; |
776 | *hpos = 0; | |
777 | } else { | |
778 | *vpos = position / htotal; | |
779 | *hpos = position - (*vpos * htotal); | |
780 | } | |
0af7e4df | 781 | |
0af7e4df MK |
782 | /* In vblank? */ |
783 | if (in_vbl) | |
3d3cbd84 | 784 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
785 | |
786 | return ret; | |
787 | } | |
788 | ||
a225f079 VS |
789 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
790 | { | |
791 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
792 | unsigned long irqflags; | |
793 | int position; | |
794 | ||
795 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
796 | position = __intel_get_crtc_scanline(crtc); | |
797 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
798 | ||
799 | return position; | |
800 | } | |
801 | ||
f71d4af4 | 802 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
803 | int *max_error, |
804 | struct timeval *vblank_time, | |
805 | unsigned flags) | |
806 | { | |
4041b853 | 807 | struct drm_crtc *crtc; |
0af7e4df | 808 | |
7eb552ae | 809 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 810 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
811 | return -EINVAL; |
812 | } | |
813 | ||
814 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
815 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
816 | if (crtc == NULL) { | |
817 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
818 | return -EINVAL; | |
819 | } | |
820 | ||
821 | if (!crtc->enabled) { | |
822 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
823 | return -EBUSY; | |
824 | } | |
0af7e4df MK |
825 | |
826 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
827 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
828 | vblank_time, flags, | |
7da903ef VS |
829 | crtc, |
830 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
831 | } |
832 | ||
67c347ff JN |
833 | static bool intel_hpd_irq_event(struct drm_device *dev, |
834 | struct drm_connector *connector) | |
321a1b30 EE |
835 | { |
836 | enum drm_connector_status old_status; | |
837 | ||
838 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
839 | old_status = connector->status; | |
840 | ||
841 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
842 | if (old_status == connector->status) |
843 | return false; | |
844 | ||
845 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 | 846 | connector->base.id, |
c23cc417 | 847 | connector->name, |
67c347ff JN |
848 | drm_get_connector_status_name(old_status), |
849 | drm_get_connector_status_name(connector->status)); | |
850 | ||
851 | return true; | |
321a1b30 EE |
852 | } |
853 | ||
13cf5504 DA |
854 | static void i915_digport_work_func(struct work_struct *work) |
855 | { | |
856 | struct drm_i915_private *dev_priv = | |
857 | container_of(work, struct drm_i915_private, dig_port_work); | |
13cf5504 DA |
858 | u32 long_port_mask, short_port_mask; |
859 | struct intel_digital_port *intel_dig_port; | |
860 | int i, ret; | |
861 | u32 old_bits = 0; | |
862 | ||
4cb21832 | 863 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
864 | long_port_mask = dev_priv->long_hpd_port_mask; |
865 | dev_priv->long_hpd_port_mask = 0; | |
866 | short_port_mask = dev_priv->short_hpd_port_mask; | |
867 | dev_priv->short_hpd_port_mask = 0; | |
4cb21832 | 868 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
869 | |
870 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
871 | bool valid = false; | |
872 | bool long_hpd = false; | |
873 | intel_dig_port = dev_priv->hpd_irq_port[i]; | |
874 | if (!intel_dig_port || !intel_dig_port->hpd_pulse) | |
875 | continue; | |
876 | ||
877 | if (long_port_mask & (1 << i)) { | |
878 | valid = true; | |
879 | long_hpd = true; | |
880 | } else if (short_port_mask & (1 << i)) | |
881 | valid = true; | |
882 | ||
883 | if (valid) { | |
884 | ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd); | |
885 | if (ret == true) { | |
886 | /* if we get true fallback to old school hpd */ | |
887 | old_bits |= (1 << intel_dig_port->base.hpd_pin); | |
888 | } | |
889 | } | |
890 | } | |
891 | ||
892 | if (old_bits) { | |
4cb21832 | 893 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 | 894 | dev_priv->hpd_event_bits |= old_bits; |
4cb21832 | 895 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
896 | schedule_work(&dev_priv->hotplug_work); |
897 | } | |
898 | } | |
899 | ||
5ca58282 JB |
900 | /* |
901 | * Handle hotplug events outside the interrupt handler proper. | |
902 | */ | |
ac4c16c5 EE |
903 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
904 | ||
5ca58282 JB |
905 | static void i915_hotplug_work_func(struct work_struct *work) |
906 | { | |
2d1013dd JN |
907 | struct drm_i915_private *dev_priv = |
908 | container_of(work, struct drm_i915_private, hotplug_work); | |
5ca58282 | 909 | struct drm_device *dev = dev_priv->dev; |
c31c4ba3 | 910 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
911 | struct intel_connector *intel_connector; |
912 | struct intel_encoder *intel_encoder; | |
913 | struct drm_connector *connector; | |
cd569aed | 914 | bool hpd_disabled = false; |
321a1b30 | 915 | bool changed = false; |
142e2398 | 916 | u32 hpd_event_bits; |
4ef69c7a | 917 | |
a65e34c7 | 918 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
919 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
920 | ||
4cb21832 | 921 | spin_lock_irq(&dev_priv->irq_lock); |
142e2398 EE |
922 | |
923 | hpd_event_bits = dev_priv->hpd_event_bits; | |
924 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
925 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
926 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
927 | if (!intel_connector->encoder) |
928 | continue; | |
cd569aed EE |
929 | intel_encoder = intel_connector->encoder; |
930 | if (intel_encoder->hpd_pin > HPD_NONE && | |
931 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
932 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
933 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
934 | "switching from hotplug detection to polling\n", | |
c23cc417 | 935 | connector->name); |
cd569aed EE |
936 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; |
937 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
938 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
939 | hpd_disabled = true; | |
940 | } | |
142e2398 EE |
941 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
942 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
c23cc417 | 943 | connector->name, intel_encoder->hpd_pin); |
142e2398 | 944 | } |
cd569aed EE |
945 | } |
946 | /* if there were no outputs to poll, poll was disabled, | |
947 | * therefore make sure it's enabled when disabling HPD on | |
948 | * some connectors */ | |
ac4c16c5 | 949 | if (hpd_disabled) { |
cd569aed | 950 | drm_kms_helper_poll_enable(dev); |
6323751d ID |
951 | mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work, |
952 | msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
ac4c16c5 | 953 | } |
cd569aed | 954 | |
4cb21832 | 955 | spin_unlock_irq(&dev_priv->irq_lock); |
cd569aed | 956 | |
321a1b30 EE |
957 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
958 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
959 | if (!intel_connector->encoder) |
960 | continue; | |
321a1b30 EE |
961 | intel_encoder = intel_connector->encoder; |
962 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
963 | if (intel_encoder->hot_plug) | |
964 | intel_encoder->hot_plug(intel_encoder); | |
965 | if (intel_hpd_irq_event(dev, connector)) | |
966 | changed = true; | |
967 | } | |
968 | } | |
40ee3381 KP |
969 | mutex_unlock(&mode_config->mutex); |
970 | ||
321a1b30 EE |
971 | if (changed) |
972 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
973 | } |
974 | ||
d0ecd7e2 | 975 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 976 | { |
2d1013dd | 977 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 978 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 979 | u8 new_delay; |
9270388e | 980 | |
d0ecd7e2 | 981 | spin_lock(&mchdev_lock); |
f97108d1 | 982 | |
73edd18f DV |
983 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
984 | ||
20e4d407 | 985 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 986 | |
7648fa99 | 987 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
988 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
989 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
990 | max_avg = I915_READ(RCBMAXAVG); |
991 | min_avg = I915_READ(RCBMINAVG); | |
992 | ||
993 | /* Handle RCS change request from hw */ | |
b5b72e89 | 994 | if (busy_up > max_avg) { |
20e4d407 DV |
995 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
996 | new_delay = dev_priv->ips.cur_delay - 1; | |
997 | if (new_delay < dev_priv->ips.max_delay) | |
998 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 999 | } else if (busy_down < min_avg) { |
20e4d407 DV |
1000 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
1001 | new_delay = dev_priv->ips.cur_delay + 1; | |
1002 | if (new_delay > dev_priv->ips.min_delay) | |
1003 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
1004 | } |
1005 | ||
7648fa99 | 1006 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 1007 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 1008 | |
d0ecd7e2 | 1009 | spin_unlock(&mchdev_lock); |
9270388e | 1010 | |
f97108d1 JB |
1011 | return; |
1012 | } | |
1013 | ||
549f7365 | 1014 | static void notify_ring(struct drm_device *dev, |
a4872ba6 | 1015 | struct intel_engine_cs *ring) |
549f7365 | 1016 | { |
93b0a4e0 | 1017 | if (!intel_ring_initialized(ring)) |
475553de CW |
1018 | return; |
1019 | ||
814e9b57 | 1020 | trace_i915_gem_request_complete(ring); |
9862e600 | 1021 | |
549f7365 | 1022 | wake_up_all(&ring->irq_queue); |
549f7365 CW |
1023 | } |
1024 | ||
31685c25 | 1025 | static u32 vlv_c0_residency(struct drm_i915_private *dev_priv, |
bf225f20 | 1026 | struct intel_rps_ei *rps_ei) |
31685c25 D |
1027 | { |
1028 | u32 cz_ts, cz_freq_khz; | |
1029 | u32 render_count, media_count; | |
1030 | u32 elapsed_render, elapsed_media, elapsed_time; | |
1031 | u32 residency = 0; | |
1032 | ||
1033 | cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); | |
1034 | cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4); | |
1035 | ||
1036 | render_count = I915_READ(VLV_RENDER_C0_COUNT_REG); | |
1037 | media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG); | |
1038 | ||
bf225f20 CW |
1039 | if (rps_ei->cz_clock == 0) { |
1040 | rps_ei->cz_clock = cz_ts; | |
1041 | rps_ei->render_c0 = render_count; | |
1042 | rps_ei->media_c0 = media_count; | |
31685c25 D |
1043 | |
1044 | return dev_priv->rps.cur_freq; | |
1045 | } | |
1046 | ||
bf225f20 CW |
1047 | elapsed_time = cz_ts - rps_ei->cz_clock; |
1048 | rps_ei->cz_clock = cz_ts; | |
31685c25 | 1049 | |
bf225f20 CW |
1050 | elapsed_render = render_count - rps_ei->render_c0; |
1051 | rps_ei->render_c0 = render_count; | |
31685c25 | 1052 | |
bf225f20 CW |
1053 | elapsed_media = media_count - rps_ei->media_c0; |
1054 | rps_ei->media_c0 = media_count; | |
31685c25 D |
1055 | |
1056 | /* Convert all the counters into common unit of milli sec */ | |
1057 | elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC; | |
1058 | elapsed_render /= cz_freq_khz; | |
1059 | elapsed_media /= cz_freq_khz; | |
1060 | ||
1061 | /* | |
1062 | * Calculate overall C0 residency percentage | |
1063 | * only if elapsed time is non zero | |
1064 | */ | |
1065 | if (elapsed_time) { | |
1066 | residency = | |
1067 | ((max(elapsed_render, elapsed_media) * 100) | |
1068 | / elapsed_time); | |
1069 | } | |
1070 | ||
1071 | return residency; | |
1072 | } | |
1073 | ||
1074 | /** | |
1075 | * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU | |
1076 | * busy-ness calculated from C0 counters of render & media power wells | |
1077 | * @dev_priv: DRM device private | |
1078 | * | |
1079 | */ | |
4fa79042 | 1080 | static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv) |
31685c25 D |
1081 | { |
1082 | u32 residency_C0_up = 0, residency_C0_down = 0; | |
4fa79042 | 1083 | int new_delay, adj; |
31685c25 D |
1084 | |
1085 | dev_priv->rps.ei_interrupt_count++; | |
1086 | ||
1087 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
1088 | ||
1089 | ||
bf225f20 CW |
1090 | if (dev_priv->rps.up_ei.cz_clock == 0) { |
1091 | vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei); | |
1092 | vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei); | |
31685c25 D |
1093 | return dev_priv->rps.cur_freq; |
1094 | } | |
1095 | ||
1096 | ||
1097 | /* | |
1098 | * To down throttle, C0 residency should be less than down threshold | |
1099 | * for continous EI intervals. So calculate down EI counters | |
1100 | * once in VLV_INT_COUNT_FOR_DOWN_EI | |
1101 | */ | |
1102 | if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) { | |
1103 | ||
1104 | dev_priv->rps.ei_interrupt_count = 0; | |
1105 | ||
1106 | residency_C0_down = vlv_c0_residency(dev_priv, | |
bf225f20 | 1107 | &dev_priv->rps.down_ei); |
31685c25 D |
1108 | } else { |
1109 | residency_C0_up = vlv_c0_residency(dev_priv, | |
bf225f20 | 1110 | &dev_priv->rps.up_ei); |
31685c25 D |
1111 | } |
1112 | ||
1113 | new_delay = dev_priv->rps.cur_freq; | |
1114 | ||
1115 | adj = dev_priv->rps.last_adj; | |
1116 | /* C0 residency is greater than UP threshold. Increase Frequency */ | |
1117 | if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) { | |
1118 | if (adj > 0) | |
1119 | adj *= 2; | |
1120 | else | |
1121 | adj = 1; | |
1122 | ||
1123 | if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit) | |
1124 | new_delay = dev_priv->rps.cur_freq + adj; | |
1125 | ||
1126 | /* | |
1127 | * For better performance, jump directly | |
1128 | * to RPe if we're below it. | |
1129 | */ | |
1130 | if (new_delay < dev_priv->rps.efficient_freq) | |
1131 | new_delay = dev_priv->rps.efficient_freq; | |
1132 | ||
1133 | } else if (!dev_priv->rps.ei_interrupt_count && | |
1134 | (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) { | |
1135 | if (adj < 0) | |
1136 | adj *= 2; | |
1137 | else | |
1138 | adj = -1; | |
1139 | /* | |
1140 | * This means, C0 residency is less than down threshold over | |
1141 | * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq | |
1142 | */ | |
1143 | if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit) | |
1144 | new_delay = dev_priv->rps.cur_freq + adj; | |
1145 | } | |
1146 | ||
1147 | return new_delay; | |
1148 | } | |
1149 | ||
4912d041 | 1150 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1151 | { |
2d1013dd JN |
1152 | struct drm_i915_private *dev_priv = |
1153 | container_of(work, struct drm_i915_private, rps.work); | |
edbfdb45 | 1154 | u32 pm_iir; |
dd75fdc8 | 1155 | int new_delay, adj; |
4912d041 | 1156 | |
59cdb63d | 1157 | spin_lock_irq(&dev_priv->irq_lock); |
d4d70aa5 ID |
1158 | /* Speed up work cancelation during disabling rps interrupts. */ |
1159 | if (!dev_priv->rps.interrupts_enabled) { | |
1160 | spin_unlock_irq(&dev_priv->irq_lock); | |
1161 | return; | |
1162 | } | |
c6a828d3 DV |
1163 | pm_iir = dev_priv->rps.pm_iir; |
1164 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a ID |
1165 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
1166 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
59cdb63d | 1167 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1168 | |
60611c13 | 1169 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1170 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1171 | |
a6706b45 | 1172 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
3b8d8d91 JB |
1173 | return; |
1174 | ||
4fc688ce | 1175 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1176 | |
dd75fdc8 | 1177 | adj = dev_priv->rps.last_adj; |
7425034a | 1178 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1179 | if (adj > 0) |
1180 | adj *= 2; | |
13a5660c D |
1181 | else { |
1182 | /* CHV needs even encode values */ | |
1183 | adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1; | |
1184 | } | |
b39fb297 | 1185 | new_delay = dev_priv->rps.cur_freq + adj; |
7425034a VS |
1186 | |
1187 | /* | |
1188 | * For better performance, jump directly | |
1189 | * to RPe if we're below it. | |
1190 | */ | |
b39fb297 BW |
1191 | if (new_delay < dev_priv->rps.efficient_freq) |
1192 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1193 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1194 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1195 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1196 | else |
b39fb297 | 1197 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 | 1198 | adj = 0; |
31685c25 D |
1199 | } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1200 | new_delay = vlv_calc_delay_from_C0_counters(dev_priv); | |
dd75fdc8 CW |
1201 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { |
1202 | if (adj < 0) | |
1203 | adj *= 2; | |
13a5660c D |
1204 | else { |
1205 | /* CHV needs even encode values */ | |
1206 | adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1; | |
1207 | } | |
b39fb297 | 1208 | new_delay = dev_priv->rps.cur_freq + adj; |
dd75fdc8 | 1209 | } else { /* unknown event */ |
b39fb297 | 1210 | new_delay = dev_priv->rps.cur_freq; |
dd75fdc8 | 1211 | } |
3b8d8d91 | 1212 | |
79249636 BW |
1213 | /* sysfs frequency interfaces may have snuck in while servicing the |
1214 | * interrupt | |
1215 | */ | |
1272e7b8 | 1216 | new_delay = clamp_t(int, new_delay, |
b39fb297 BW |
1217 | dev_priv->rps.min_freq_softlimit, |
1218 | dev_priv->rps.max_freq_softlimit); | |
27544369 | 1219 | |
b39fb297 | 1220 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
dd75fdc8 CW |
1221 | |
1222 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1223 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1224 | else | |
1225 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1226 | |
4fc688ce | 1227 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1228 | } |
1229 | ||
e3689190 BW |
1230 | |
1231 | /** | |
1232 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1233 | * occurred. | |
1234 | * @work: workqueue struct | |
1235 | * | |
1236 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1237 | * this event, userspace should try to remap the bad rows since statistically | |
1238 | * it is likely the same row is more likely to go bad again. | |
1239 | */ | |
1240 | static void ivybridge_parity_work(struct work_struct *work) | |
1241 | { | |
2d1013dd JN |
1242 | struct drm_i915_private *dev_priv = |
1243 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1244 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1245 | char *parity_event[6]; |
e3689190 | 1246 | uint32_t misccpctl; |
35a85ac6 | 1247 | uint8_t slice = 0; |
e3689190 BW |
1248 | |
1249 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1250 | * In order to prevent a get/put style interface, acquire struct mutex | |
1251 | * any time we access those registers. | |
1252 | */ | |
1253 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1254 | ||
35a85ac6 BW |
1255 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1256 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1257 | goto out; | |
1258 | ||
e3689190 BW |
1259 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1260 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1261 | POSTING_READ(GEN7_MISCCPCTL); | |
1262 | ||
35a85ac6 BW |
1263 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1264 | u32 reg; | |
e3689190 | 1265 | |
35a85ac6 BW |
1266 | slice--; |
1267 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1268 | break; | |
e3689190 | 1269 | |
35a85ac6 | 1270 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1271 | |
35a85ac6 | 1272 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1273 | |
35a85ac6 BW |
1274 | error_status = I915_READ(reg); |
1275 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1276 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1277 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1278 | ||
1279 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1280 | POSTING_READ(reg); | |
1281 | ||
1282 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1283 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1284 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1285 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1286 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1287 | parity_event[5] = NULL; | |
1288 | ||
5bdebb18 | 1289 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1290 | KOBJ_CHANGE, parity_event); |
e3689190 | 1291 | |
35a85ac6 BW |
1292 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1293 | slice, row, bank, subbank); | |
e3689190 | 1294 | |
35a85ac6 BW |
1295 | kfree(parity_event[4]); |
1296 | kfree(parity_event[3]); | |
1297 | kfree(parity_event[2]); | |
1298 | kfree(parity_event[1]); | |
1299 | } | |
e3689190 | 1300 | |
35a85ac6 | 1301 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1302 | |
35a85ac6 BW |
1303 | out: |
1304 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1305 | spin_lock_irq(&dev_priv->irq_lock); |
480c8033 | 1306 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
4cb21832 | 1307 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1308 | |
1309 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1310 | } |
1311 | ||
35a85ac6 | 1312 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1313 | { |
2d1013dd | 1314 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1315 | |
040d2baa | 1316 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1317 | return; |
1318 | ||
d0ecd7e2 | 1319 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1320 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1321 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1322 | |
35a85ac6 BW |
1323 | iir &= GT_PARITY_ERROR(dev); |
1324 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1325 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1326 | ||
1327 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1328 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1329 | ||
a4da4fa4 | 1330 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1331 | } |
1332 | ||
f1af8fc1 PZ |
1333 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1334 | struct drm_i915_private *dev_priv, | |
1335 | u32 gt_iir) | |
1336 | { | |
1337 | if (gt_iir & | |
1338 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1339 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1340 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1341 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1342 | } | |
1343 | ||
e7b4c6b1 DV |
1344 | static void snb_gt_irq_handler(struct drm_device *dev, |
1345 | struct drm_i915_private *dev_priv, | |
1346 | u32 gt_iir) | |
1347 | { | |
1348 | ||
cc609d5d BW |
1349 | if (gt_iir & |
1350 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1351 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1352 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1353 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1354 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1355 | notify_ring(dev, &dev_priv->ring[BCS]); |
1356 | ||
cc609d5d BW |
1357 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1358 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1359 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1360 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1361 | |
35a85ac6 BW |
1362 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1363 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1364 | } |
1365 | ||
abd58f01 BW |
1366 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1367 | struct drm_i915_private *dev_priv, | |
1368 | u32 master_ctl) | |
1369 | { | |
e981e7b1 | 1370 | struct intel_engine_cs *ring; |
abd58f01 BW |
1371 | u32 rcs, bcs, vcs; |
1372 | uint32_t tmp = 0; | |
1373 | irqreturn_t ret = IRQ_NONE; | |
1374 | ||
1375 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1376 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1377 | if (tmp) { | |
38cc46d7 | 1378 | I915_WRITE(GEN8_GT_IIR(0), tmp); |
abd58f01 | 1379 | ret = IRQ_HANDLED; |
e981e7b1 | 1380 | |
abd58f01 | 1381 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; |
e981e7b1 | 1382 | ring = &dev_priv->ring[RCS]; |
abd58f01 | 1383 | if (rcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 TD |
1384 | notify_ring(dev, ring); |
1385 | if (rcs & GT_CONTEXT_SWITCH_INTERRUPT) | |
1386 | intel_execlists_handle_ctx_events(ring); | |
1387 | ||
1388 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1389 | ring = &dev_priv->ring[BCS]; | |
abd58f01 | 1390 | if (bcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 TD |
1391 | notify_ring(dev, ring); |
1392 | if (bcs & GT_CONTEXT_SWITCH_INTERRUPT) | |
1393 | intel_execlists_handle_ctx_events(ring); | |
abd58f01 BW |
1394 | } else |
1395 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1396 | } | |
1397 | ||
85f9b5f9 | 1398 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
abd58f01 BW |
1399 | tmp = I915_READ(GEN8_GT_IIR(1)); |
1400 | if (tmp) { | |
38cc46d7 | 1401 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
abd58f01 | 1402 | ret = IRQ_HANDLED; |
e981e7b1 | 1403 | |
abd58f01 | 1404 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; |
e981e7b1 | 1405 | ring = &dev_priv->ring[VCS]; |
abd58f01 | 1406 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1407 | notify_ring(dev, ring); |
73d477f6 | 1408 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 TD |
1409 | intel_execlists_handle_ctx_events(ring); |
1410 | ||
85f9b5f9 | 1411 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
e981e7b1 | 1412 | ring = &dev_priv->ring[VCS2]; |
85f9b5f9 | 1413 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1414 | notify_ring(dev, ring); |
73d477f6 | 1415 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 | 1416 | intel_execlists_handle_ctx_events(ring); |
abd58f01 BW |
1417 | } else |
1418 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1419 | } | |
1420 | ||
0961021a BW |
1421 | if (master_ctl & GEN8_GT_PM_IRQ) { |
1422 | tmp = I915_READ(GEN8_GT_IIR(2)); | |
1423 | if (tmp & dev_priv->pm_rps_events) { | |
0961021a BW |
1424 | I915_WRITE(GEN8_GT_IIR(2), |
1425 | tmp & dev_priv->pm_rps_events); | |
38cc46d7 | 1426 | ret = IRQ_HANDLED; |
c9a9a268 | 1427 | gen6_rps_irq_handler(dev_priv, tmp); |
0961021a BW |
1428 | } else |
1429 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1430 | } | |
1431 | ||
abd58f01 BW |
1432 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
1433 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1434 | if (tmp) { | |
38cc46d7 | 1435 | I915_WRITE(GEN8_GT_IIR(3), tmp); |
abd58f01 | 1436 | ret = IRQ_HANDLED; |
e981e7b1 | 1437 | |
abd58f01 | 1438 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; |
e981e7b1 | 1439 | ring = &dev_priv->ring[VECS]; |
abd58f01 | 1440 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1441 | notify_ring(dev, ring); |
73d477f6 | 1442 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 | 1443 | intel_execlists_handle_ctx_events(ring); |
abd58f01 BW |
1444 | } else |
1445 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1446 | } | |
1447 | ||
1448 | return ret; | |
1449 | } | |
1450 | ||
b543fb04 EE |
1451 | #define HPD_STORM_DETECT_PERIOD 1000 |
1452 | #define HPD_STORM_THRESHOLD 5 | |
1453 | ||
07c338ce | 1454 | static int pch_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1455 | { |
1456 | switch (port) { | |
1457 | case PORT_A: | |
1458 | case PORT_E: | |
1459 | default: | |
1460 | return -1; | |
1461 | case PORT_B: | |
1462 | return 0; | |
1463 | case PORT_C: | |
1464 | return 8; | |
1465 | case PORT_D: | |
1466 | return 16; | |
1467 | } | |
1468 | } | |
1469 | ||
07c338ce | 1470 | static int i915_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1471 | { |
1472 | switch (port) { | |
1473 | case PORT_A: | |
1474 | case PORT_E: | |
1475 | default: | |
1476 | return -1; | |
1477 | case PORT_B: | |
1478 | return 17; | |
1479 | case PORT_C: | |
1480 | return 19; | |
1481 | case PORT_D: | |
1482 | return 21; | |
1483 | } | |
1484 | } | |
1485 | ||
1486 | static inline enum port get_port_from_pin(enum hpd_pin pin) | |
1487 | { | |
1488 | switch (pin) { | |
1489 | case HPD_PORT_B: | |
1490 | return PORT_B; | |
1491 | case HPD_PORT_C: | |
1492 | return PORT_C; | |
1493 | case HPD_PORT_D: | |
1494 | return PORT_D; | |
1495 | default: | |
1496 | return PORT_A; /* no hpd */ | |
1497 | } | |
1498 | } | |
1499 | ||
10a504de | 1500 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba | 1501 | u32 hotplug_trigger, |
13cf5504 | 1502 | u32 dig_hotplug_reg, |
22062dba | 1503 | const u32 *hpd) |
b543fb04 | 1504 | { |
2d1013dd | 1505 | struct drm_i915_private *dev_priv = dev->dev_private; |
b543fb04 | 1506 | int i; |
13cf5504 | 1507 | enum port port; |
10a504de | 1508 | bool storm_detected = false; |
13cf5504 DA |
1509 | bool queue_dig = false, queue_hp = false; |
1510 | u32 dig_shift; | |
1511 | u32 dig_port_mask = 0; | |
b543fb04 | 1512 | |
91d131d2 DV |
1513 | if (!hotplug_trigger) |
1514 | return; | |
1515 | ||
13cf5504 DA |
1516 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n", |
1517 | hotplug_trigger, dig_hotplug_reg); | |
cc9bd499 | 1518 | |
b5ea2d56 | 1519 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1520 | for (i = 1; i < HPD_NUM_PINS; i++) { |
13cf5504 DA |
1521 | if (!(hpd[i] & hotplug_trigger)) |
1522 | continue; | |
1523 | ||
1524 | port = get_port_from_pin(i); | |
1525 | if (port && dev_priv->hpd_irq_port[port]) { | |
1526 | bool long_hpd; | |
1527 | ||
07c338ce JN |
1528 | if (HAS_PCH_SPLIT(dev)) { |
1529 | dig_shift = pch_port_to_hotplug_shift(port); | |
13cf5504 | 1530 | long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; |
07c338ce JN |
1531 | } else { |
1532 | dig_shift = i915_port_to_hotplug_shift(port); | |
1533 | long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; | |
13cf5504 DA |
1534 | } |
1535 | ||
26fbb774 VS |
1536 | DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", |
1537 | port_name(port), | |
1538 | long_hpd ? "long" : "short"); | |
13cf5504 DA |
1539 | /* for long HPD pulses we want to have the digital queue happen, |
1540 | but we still want HPD storm detection to function. */ | |
1541 | if (long_hpd) { | |
1542 | dev_priv->long_hpd_port_mask |= (1 << port); | |
1543 | dig_port_mask |= hpd[i]; | |
1544 | } else { | |
1545 | /* for short HPD just trigger the digital queue */ | |
1546 | dev_priv->short_hpd_port_mask |= (1 << port); | |
1547 | hotplug_trigger &= ~hpd[i]; | |
1548 | } | |
1549 | queue_dig = true; | |
1550 | } | |
1551 | } | |
821450c6 | 1552 | |
13cf5504 | 1553 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3ff04a16 DV |
1554 | if (hpd[i] & hotplug_trigger && |
1555 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { | |
1556 | /* | |
1557 | * On GMCH platforms the interrupt mask bits only | |
1558 | * prevent irq generation, not the setting of the | |
1559 | * hotplug bits itself. So only WARN about unexpected | |
1560 | * interrupts on saner platforms. | |
1561 | */ | |
1562 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), | |
1563 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | |
1564 | hotplug_trigger, i, hpd[i]); | |
1565 | ||
1566 | continue; | |
1567 | } | |
b8f102e8 | 1568 | |
b543fb04 EE |
1569 | if (!(hpd[i] & hotplug_trigger) || |
1570 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1571 | continue; | |
1572 | ||
13cf5504 DA |
1573 | if (!(dig_port_mask & hpd[i])) { |
1574 | dev_priv->hpd_event_bits |= (1 << i); | |
1575 | queue_hp = true; | |
1576 | } | |
1577 | ||
b543fb04 EE |
1578 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1579 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1580 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1581 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1582 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1583 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1584 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1585 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1586 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1587 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1588 | storm_detected = true; |
b543fb04 EE |
1589 | } else { |
1590 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1591 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1592 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1593 | } |
1594 | } | |
1595 | ||
10a504de DV |
1596 | if (storm_detected) |
1597 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1598 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1599 | |
645416f5 DV |
1600 | /* |
1601 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1602 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1603 | * queue for otherwise the flush_work in the pageflip code will | |
1604 | * deadlock. | |
1605 | */ | |
13cf5504 | 1606 | if (queue_dig) |
0e32b39c | 1607 | queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work); |
13cf5504 DA |
1608 | if (queue_hp) |
1609 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1610 | } |
1611 | ||
515ac2bb DV |
1612 | static void gmbus_irq_handler(struct drm_device *dev) |
1613 | { | |
2d1013dd | 1614 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1615 | |
28c70f16 | 1616 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1617 | } |
1618 | ||
ce99c256 DV |
1619 | static void dp_aux_irq_handler(struct drm_device *dev) |
1620 | { | |
2d1013dd | 1621 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1622 | |
9ee32fea | 1623 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1624 | } |
1625 | ||
8bf1e9f1 | 1626 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1627 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1628 | uint32_t crc0, uint32_t crc1, | |
1629 | uint32_t crc2, uint32_t crc3, | |
1630 | uint32_t crc4) | |
8bf1e9f1 SH |
1631 | { |
1632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1633 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1634 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1635 | int head, tail; |
b2c88f5b | 1636 | |
d538bbdf DL |
1637 | spin_lock(&pipe_crc->lock); |
1638 | ||
0c912c79 | 1639 | if (!pipe_crc->entries) { |
d538bbdf | 1640 | spin_unlock(&pipe_crc->lock); |
34273620 | 1641 | DRM_DEBUG_KMS("spurious interrupt\n"); |
0c912c79 DL |
1642 | return; |
1643 | } | |
1644 | ||
d538bbdf DL |
1645 | head = pipe_crc->head; |
1646 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1647 | |
1648 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1649 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1650 | DRM_ERROR("CRC buffer overflowing\n"); |
1651 | return; | |
1652 | } | |
1653 | ||
1654 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1655 | |
8bc5e955 | 1656 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1657 | entry->crc[0] = crc0; |
1658 | entry->crc[1] = crc1; | |
1659 | entry->crc[2] = crc2; | |
1660 | entry->crc[3] = crc3; | |
1661 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1662 | |
1663 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1664 | pipe_crc->head = head; |
1665 | ||
1666 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1667 | |
1668 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1669 | } |
277de95e DV |
1670 | #else |
1671 | static inline void | |
1672 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1673 | uint32_t crc0, uint32_t crc1, | |
1674 | uint32_t crc2, uint32_t crc3, | |
1675 | uint32_t crc4) {} | |
1676 | #endif | |
1677 | ||
eba94eb9 | 1678 | |
277de95e | 1679 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1680 | { |
1681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1682 | ||
277de95e DV |
1683 | display_pipe_crc_irq_handler(dev, pipe, |
1684 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1685 | 0, 0, 0, 0); | |
5a69b89f DV |
1686 | } |
1687 | ||
277de95e | 1688 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1689 | { |
1690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1691 | ||
277de95e DV |
1692 | display_pipe_crc_irq_handler(dev, pipe, |
1693 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1694 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1695 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1696 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1697 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1698 | } |
5b3a856b | 1699 | |
277de95e | 1700 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1701 | { |
1702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1703 | uint32_t res1, res2; |
1704 | ||
1705 | if (INTEL_INFO(dev)->gen >= 3) | |
1706 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1707 | else | |
1708 | res1 = 0; | |
1709 | ||
1710 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1711 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1712 | else | |
1713 | res2 = 0; | |
5b3a856b | 1714 | |
277de95e DV |
1715 | display_pipe_crc_irq_handler(dev, pipe, |
1716 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1717 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1718 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1719 | res1, res2); | |
5b3a856b | 1720 | } |
8bf1e9f1 | 1721 | |
1403c0d4 PZ |
1722 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1723 | * IMR bits until the work is done. Other interrupts can be processed without | |
1724 | * the work queue. */ | |
1725 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1726 | { |
4a74de82 ID |
1727 | /* TODO: RPS on GEN9+ is not supported yet. */ |
1728 | if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9, | |
1729 | "GEN9+: unexpected RPS IRQ\n")) | |
132f3f17 ID |
1730 | return; |
1731 | ||
a6706b45 | 1732 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1733 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1734 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1735 | if (dev_priv->rps.interrupts_enabled) { |
1736 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1737 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1738 | } | |
59cdb63d | 1739 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1740 | } |
baf02a1f | 1741 | |
c9a9a268 ID |
1742 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1743 | return; | |
1744 | ||
1403c0d4 PZ |
1745 | if (HAS_VEBOX(dev_priv->dev)) { |
1746 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1747 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1748 | |
aaecdf61 DV |
1749 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1750 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1751 | } |
baf02a1f BW |
1752 | } |
1753 | ||
8d7849db VS |
1754 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1755 | { | |
8d7849db VS |
1756 | if (!drm_handle_vblank(dev, pipe)) |
1757 | return false; | |
1758 | ||
8d7849db VS |
1759 | return true; |
1760 | } | |
1761 | ||
c1874ed7 ID |
1762 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1763 | { | |
1764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1765 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1766 | int pipe; |
1767 | ||
58ead0d7 | 1768 | spin_lock(&dev_priv->irq_lock); |
055e393f | 1769 | for_each_pipe(dev_priv, pipe) { |
91d181dd | 1770 | int reg; |
bbb5eebf | 1771 | u32 mask, iir_bit = 0; |
91d181dd | 1772 | |
bbb5eebf DV |
1773 | /* |
1774 | * PIPESTAT bits get signalled even when the interrupt is | |
1775 | * disabled with the mask bits, and some of the status bits do | |
1776 | * not generate interrupts at all (like the underrun bit). Hence | |
1777 | * we need to be careful that we only handle what we want to | |
1778 | * handle. | |
1779 | */ | |
0f239f4c DV |
1780 | |
1781 | /* fifo underruns are filterered in the underrun handler. */ | |
1782 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1783 | |
1784 | switch (pipe) { | |
1785 | case PIPE_A: | |
1786 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1787 | break; | |
1788 | case PIPE_B: | |
1789 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1790 | break; | |
3278f67f VS |
1791 | case PIPE_C: |
1792 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1793 | break; | |
bbb5eebf DV |
1794 | } |
1795 | if (iir & iir_bit) | |
1796 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1797 | ||
1798 | if (!mask) | |
91d181dd ID |
1799 | continue; |
1800 | ||
1801 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1802 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1803 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1804 | |
1805 | /* | |
1806 | * Clear the PIPE*STAT regs before the IIR | |
1807 | */ | |
91d181dd ID |
1808 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1809 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1810 | I915_WRITE(reg, pipe_stats[pipe]); |
1811 | } | |
58ead0d7 | 1812 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 | 1813 | |
055e393f | 1814 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1815 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1816 | intel_pipe_handle_vblank(dev, pipe)) | |
1817 | intel_check_page_flip(dev, pipe); | |
c1874ed7 | 1818 | |
579a9b0e | 1819 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1820 | intel_prepare_page_flip(dev, pipe); |
1821 | intel_finish_page_flip(dev, pipe); | |
1822 | } | |
1823 | ||
1824 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1825 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1826 | ||
1f7247c0 DV |
1827 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1828 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1829 | } |
1830 | ||
1831 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1832 | gmbus_irq_handler(dev); | |
1833 | } | |
1834 | ||
16c6c56b VS |
1835 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1836 | { | |
1837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1838 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1839 | ||
3ff60f89 OM |
1840 | if (hotplug_status) { |
1841 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1842 | /* | |
1843 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1844 | * may miss hotplug events. | |
1845 | */ | |
1846 | POSTING_READ(PORT_HOTPLUG_STAT); | |
16c6c56b | 1847 | |
3ff60f89 OM |
1848 | if (IS_G4X(dev)) { |
1849 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
16c6c56b | 1850 | |
13cf5504 | 1851 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x); |
3ff60f89 OM |
1852 | } else { |
1853 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1854 | |
13cf5504 | 1855 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915); |
3ff60f89 | 1856 | } |
16c6c56b | 1857 | |
3ff60f89 OM |
1858 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && |
1859 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1860 | dp_aux_irq_handler(dev); | |
1861 | } | |
16c6c56b VS |
1862 | } |
1863 | ||
ff1f525e | 1864 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1865 | { |
45a83f84 | 1866 | struct drm_device *dev = arg; |
2d1013dd | 1867 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1868 | u32 iir, gt_iir, pm_iir; |
1869 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1870 | |
7e231dbe | 1871 | while (true) { |
3ff60f89 OM |
1872 | /* Find, clear, then process each source of interrupt */ |
1873 | ||
7e231dbe | 1874 | gt_iir = I915_READ(GTIIR); |
3ff60f89 OM |
1875 | if (gt_iir) |
1876 | I915_WRITE(GTIIR, gt_iir); | |
1877 | ||
7e231dbe | 1878 | pm_iir = I915_READ(GEN6_PMIIR); |
3ff60f89 OM |
1879 | if (pm_iir) |
1880 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1881 | ||
1882 | iir = I915_READ(VLV_IIR); | |
1883 | if (iir) { | |
1884 | /* Consume port before clearing IIR or we'll miss events */ | |
1885 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1886 | i9xx_hpd_irq_handler(dev); | |
1887 | I915_WRITE(VLV_IIR, iir); | |
1888 | } | |
7e231dbe JB |
1889 | |
1890 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1891 | goto out; | |
1892 | ||
1893 | ret = IRQ_HANDLED; | |
1894 | ||
3ff60f89 OM |
1895 | if (gt_iir) |
1896 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
60611c13 | 1897 | if (pm_iir) |
d0ecd7e2 | 1898 | gen6_rps_irq_handler(dev_priv, pm_iir); |
3ff60f89 OM |
1899 | /* Call regardless, as some status bits might not be |
1900 | * signalled in iir */ | |
1901 | valleyview_pipestat_irq_handler(dev, iir); | |
7e231dbe JB |
1902 | } |
1903 | ||
1904 | out: | |
1905 | return ret; | |
1906 | } | |
1907 | ||
43f328d7 VS |
1908 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1909 | { | |
45a83f84 | 1910 | struct drm_device *dev = arg; |
43f328d7 VS |
1911 | struct drm_i915_private *dev_priv = dev->dev_private; |
1912 | u32 master_ctl, iir; | |
1913 | irqreturn_t ret = IRQ_NONE; | |
43f328d7 | 1914 | |
8e5fd599 VS |
1915 | for (;;) { |
1916 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; | |
1917 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1918 | |
8e5fd599 VS |
1919 | if (master_ctl == 0 && iir == 0) |
1920 | break; | |
43f328d7 | 1921 | |
27b6c122 OM |
1922 | ret = IRQ_HANDLED; |
1923 | ||
8e5fd599 | 1924 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
43f328d7 | 1925 | |
27b6c122 | 1926 | /* Find, clear, then process each source of interrupt */ |
43f328d7 | 1927 | |
27b6c122 OM |
1928 | if (iir) { |
1929 | /* Consume port before clearing IIR or we'll miss events */ | |
1930 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1931 | i9xx_hpd_irq_handler(dev); | |
1932 | I915_WRITE(VLV_IIR, iir); | |
1933 | } | |
43f328d7 | 1934 | |
27b6c122 | 1935 | gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
43f328d7 | 1936 | |
27b6c122 OM |
1937 | /* Call regardless, as some status bits might not be |
1938 | * signalled in iir */ | |
1939 | valleyview_pipestat_irq_handler(dev, iir); | |
43f328d7 | 1940 | |
8e5fd599 VS |
1941 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
1942 | POSTING_READ(GEN8_MASTER_IRQ); | |
8e5fd599 | 1943 | } |
3278f67f | 1944 | |
43f328d7 VS |
1945 | return ret; |
1946 | } | |
1947 | ||
23e81d69 | 1948 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1949 | { |
2d1013dd | 1950 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1951 | int pipe; |
b543fb04 | 1952 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 DA |
1953 | u32 dig_hotplug_reg; |
1954 | ||
1955 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1956 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
776ad806 | 1957 | |
13cf5504 | 1958 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx); |
91d131d2 | 1959 | |
cfc33bf7 VS |
1960 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1961 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1962 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1963 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1964 | port_name(port)); |
1965 | } | |
776ad806 | 1966 | |
ce99c256 DV |
1967 | if (pch_iir & SDE_AUX_MASK) |
1968 | dp_aux_irq_handler(dev); | |
1969 | ||
776ad806 | 1970 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1971 | gmbus_irq_handler(dev); |
776ad806 JB |
1972 | |
1973 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1974 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1975 | ||
1976 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1977 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1978 | ||
1979 | if (pch_iir & SDE_POISON) | |
1980 | DRM_ERROR("PCH poison interrupt\n"); | |
1981 | ||
9db4a9c7 | 1982 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 1983 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
1984 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1985 | pipe_name(pipe), | |
1986 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1987 | |
1988 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1989 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1990 | ||
1991 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1992 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1993 | ||
776ad806 | 1994 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 1995 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1996 | |
1997 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 1998 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1999 | } |
2000 | ||
2001 | static void ivb_err_int_handler(struct drm_device *dev) | |
2002 | { | |
2003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2004 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 2005 | enum pipe pipe; |
8664281b | 2006 | |
de032bf4 PZ |
2007 | if (err_int & ERR_INT_POISON) |
2008 | DRM_ERROR("Poison interrupt\n"); | |
2009 | ||
055e393f | 2010 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
2011 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
2012 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 2013 | |
5a69b89f DV |
2014 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
2015 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 2016 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 2017 | else |
277de95e | 2018 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
2019 | } |
2020 | } | |
8bf1e9f1 | 2021 | |
8664281b PZ |
2022 | I915_WRITE(GEN7_ERR_INT, err_int); |
2023 | } | |
2024 | ||
2025 | static void cpt_serr_int_handler(struct drm_device *dev) | |
2026 | { | |
2027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2028 | u32 serr_int = I915_READ(SERR_INT); | |
2029 | ||
de032bf4 PZ |
2030 | if (serr_int & SERR_INT_POISON) |
2031 | DRM_ERROR("PCH poison interrupt\n"); | |
2032 | ||
8664281b | 2033 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 2034 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2035 | |
2036 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 2037 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2038 | |
2039 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 2040 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
2041 | |
2042 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
2043 | } |
2044 | ||
23e81d69 AJ |
2045 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
2046 | { | |
2d1013dd | 2047 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 2048 | int pipe; |
b543fb04 | 2049 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 DA |
2050 | u32 dig_hotplug_reg; |
2051 | ||
2052 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
2053 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
23e81d69 | 2054 | |
13cf5504 | 2055 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt); |
91d131d2 | 2056 | |
cfc33bf7 VS |
2057 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
2058 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
2059 | SDE_AUDIO_POWER_SHIFT_CPT); | |
2060 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
2061 | port_name(port)); | |
2062 | } | |
23e81d69 AJ |
2063 | |
2064 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 2065 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
2066 | |
2067 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 2068 | gmbus_irq_handler(dev); |
23e81d69 AJ |
2069 | |
2070 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
2071 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
2072 | ||
2073 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
2074 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
2075 | ||
2076 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 2077 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
2078 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2079 | pipe_name(pipe), | |
2080 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
2081 | |
2082 | if (pch_iir & SDE_ERROR_CPT) | |
2083 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
2084 | } |
2085 | ||
c008bc6e PZ |
2086 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2087 | { | |
2088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 2089 | enum pipe pipe; |
c008bc6e PZ |
2090 | |
2091 | if (de_iir & DE_AUX_CHANNEL_A) | |
2092 | dp_aux_irq_handler(dev); | |
2093 | ||
2094 | if (de_iir & DE_GSE) | |
2095 | intel_opregion_asle_intr(dev); | |
2096 | ||
c008bc6e PZ |
2097 | if (de_iir & DE_POISON) |
2098 | DRM_ERROR("Poison interrupt\n"); | |
2099 | ||
055e393f | 2100 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2101 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2102 | intel_pipe_handle_vblank(dev, pipe)) | |
2103 | intel_check_page_flip(dev, pipe); | |
5b3a856b | 2104 | |
40da17c2 | 2105 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2106 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2107 | |
40da17c2 DV |
2108 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
2109 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 2110 | |
40da17c2 DV |
2111 | /* plane/pipes map 1:1 on ilk+ */ |
2112 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
2113 | intel_prepare_page_flip(dev, pipe); | |
2114 | intel_finish_page_flip_plane(dev, pipe); | |
2115 | } | |
c008bc6e PZ |
2116 | } |
2117 | ||
2118 | /* check event from PCH */ | |
2119 | if (de_iir & DE_PCH_EVENT) { | |
2120 | u32 pch_iir = I915_READ(SDEIIR); | |
2121 | ||
2122 | if (HAS_PCH_CPT(dev)) | |
2123 | cpt_irq_handler(dev, pch_iir); | |
2124 | else | |
2125 | ibx_irq_handler(dev, pch_iir); | |
2126 | ||
2127 | /* should clear PCH hotplug event before clear CPU irq */ | |
2128 | I915_WRITE(SDEIIR, pch_iir); | |
2129 | } | |
2130 | ||
2131 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
2132 | ironlake_rps_change_irq_handler(dev); | |
2133 | } | |
2134 | ||
9719fb98 PZ |
2135 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2136 | { | |
2137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 2138 | enum pipe pipe; |
9719fb98 PZ |
2139 | |
2140 | if (de_iir & DE_ERR_INT_IVB) | |
2141 | ivb_err_int_handler(dev); | |
2142 | ||
2143 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2144 | dp_aux_irq_handler(dev); | |
2145 | ||
2146 | if (de_iir & DE_GSE_IVB) | |
2147 | intel_opregion_asle_intr(dev); | |
2148 | ||
055e393f | 2149 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2150 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2151 | intel_pipe_handle_vblank(dev, pipe)) | |
2152 | intel_check_page_flip(dev, pipe); | |
40da17c2 DV |
2153 | |
2154 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2155 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2156 | intel_prepare_page_flip(dev, pipe); | |
2157 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2158 | } |
2159 | } | |
2160 | ||
2161 | /* check event from PCH */ | |
2162 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2163 | u32 pch_iir = I915_READ(SDEIIR); | |
2164 | ||
2165 | cpt_irq_handler(dev, pch_iir); | |
2166 | ||
2167 | /* clear PCH hotplug event before clear CPU irq */ | |
2168 | I915_WRITE(SDEIIR, pch_iir); | |
2169 | } | |
2170 | } | |
2171 | ||
72c90f62 OM |
2172 | /* |
2173 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2174 | * 1 - Disable Master Interrupt Control. | |
2175 | * 2 - Find the source(s) of the interrupt. | |
2176 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2177 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2178 | * 5 - Re-enable Master Interrupt Control. | |
2179 | */ | |
f1af8fc1 | 2180 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2181 | { |
45a83f84 | 2182 | struct drm_device *dev = arg; |
2d1013dd | 2183 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2184 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2185 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2186 | |
8664281b PZ |
2187 | /* We get interrupts on unclaimed registers, so check for this before we |
2188 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 2189 | intel_uncore_check_errors(dev); |
8664281b | 2190 | |
b1f14ad0 JB |
2191 | /* disable master interrupt before clearing iir */ |
2192 | de_ier = I915_READ(DEIER); | |
2193 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2194 | POSTING_READ(DEIER); |
b1f14ad0 | 2195 | |
44498aea PZ |
2196 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2197 | * interrupts will will be stored on its back queue, and then we'll be | |
2198 | * able to process them after we restore SDEIER (as soon as we restore | |
2199 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2200 | * due to its back queue). */ | |
ab5c608b BW |
2201 | if (!HAS_PCH_NOP(dev)) { |
2202 | sde_ier = I915_READ(SDEIER); | |
2203 | I915_WRITE(SDEIER, 0); | |
2204 | POSTING_READ(SDEIER); | |
2205 | } | |
44498aea | 2206 | |
72c90f62 OM |
2207 | /* Find, clear, then process each source of interrupt */ |
2208 | ||
b1f14ad0 | 2209 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2210 | if (gt_iir) { |
72c90f62 OM |
2211 | I915_WRITE(GTIIR, gt_iir); |
2212 | ret = IRQ_HANDLED; | |
d8fc8a47 | 2213 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 2214 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
2215 | else |
2216 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
b1f14ad0 JB |
2217 | } |
2218 | ||
0e43406b CW |
2219 | de_iir = I915_READ(DEIIR); |
2220 | if (de_iir) { | |
72c90f62 OM |
2221 | I915_WRITE(DEIIR, de_iir); |
2222 | ret = IRQ_HANDLED; | |
f1af8fc1 PZ |
2223 | if (INTEL_INFO(dev)->gen >= 7) |
2224 | ivb_display_irq_handler(dev, de_iir); | |
2225 | else | |
2226 | ilk_display_irq_handler(dev, de_iir); | |
b1f14ad0 JB |
2227 | } |
2228 | ||
f1af8fc1 PZ |
2229 | if (INTEL_INFO(dev)->gen >= 6) { |
2230 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2231 | if (pm_iir) { | |
f1af8fc1 PZ |
2232 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2233 | ret = IRQ_HANDLED; | |
72c90f62 | 2234 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2235 | } |
0e43406b | 2236 | } |
b1f14ad0 | 2237 | |
b1f14ad0 JB |
2238 | I915_WRITE(DEIER, de_ier); |
2239 | POSTING_READ(DEIER); | |
ab5c608b BW |
2240 | if (!HAS_PCH_NOP(dev)) { |
2241 | I915_WRITE(SDEIER, sde_ier); | |
2242 | POSTING_READ(SDEIER); | |
2243 | } | |
b1f14ad0 JB |
2244 | |
2245 | return ret; | |
2246 | } | |
2247 | ||
abd58f01 BW |
2248 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2249 | { | |
2250 | struct drm_device *dev = arg; | |
2251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2252 | u32 master_ctl; | |
2253 | irqreturn_t ret = IRQ_NONE; | |
2254 | uint32_t tmp = 0; | |
c42664cc | 2255 | enum pipe pipe; |
88e04703 JB |
2256 | u32 aux_mask = GEN8_AUX_CHANNEL_A; |
2257 | ||
2258 | if (IS_GEN9(dev)) | |
2259 | aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | | |
2260 | GEN9_AUX_CHANNEL_D; | |
abd58f01 | 2261 | |
abd58f01 BW |
2262 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
2263 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2264 | if (!master_ctl) | |
2265 | return IRQ_NONE; | |
2266 | ||
2267 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
2268 | POSTING_READ(GEN8_MASTER_IRQ); | |
2269 | ||
38cc46d7 OM |
2270 | /* Find, clear, then process each source of interrupt */ |
2271 | ||
abd58f01 BW |
2272 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
2273 | ||
2274 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2275 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
abd58f01 BW |
2276 | if (tmp) { |
2277 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2278 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2279 | if (tmp & GEN8_DE_MISC_GSE) |
2280 | intel_opregion_asle_intr(dev); | |
2281 | else | |
2282 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2283 | } |
38cc46d7 OM |
2284 | else |
2285 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2286 | } |
2287 | ||
6d766f02 DV |
2288 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2289 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
6d766f02 DV |
2290 | if (tmp) { |
2291 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
2292 | ret = IRQ_HANDLED; | |
88e04703 JB |
2293 | |
2294 | if (tmp & aux_mask) | |
38cc46d7 OM |
2295 | dp_aux_irq_handler(dev); |
2296 | else | |
2297 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
6d766f02 | 2298 | } |
38cc46d7 OM |
2299 | else |
2300 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2301 | } |
2302 | ||
055e393f | 2303 | for_each_pipe(dev_priv, pipe) { |
770de83d | 2304 | uint32_t pipe_iir, flip_done = 0, fault_errors = 0; |
abd58f01 | 2305 | |
c42664cc DV |
2306 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2307 | continue; | |
abd58f01 | 2308 | |
c42664cc | 2309 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
c42664cc DV |
2310 | if (pipe_iir) { |
2311 | ret = IRQ_HANDLED; | |
2312 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
770de83d | 2313 | |
d6bbafa1 CW |
2314 | if (pipe_iir & GEN8_PIPE_VBLANK && |
2315 | intel_pipe_handle_vblank(dev, pipe)) | |
2316 | intel_check_page_flip(dev, pipe); | |
38cc46d7 | 2317 | |
770de83d DL |
2318 | if (IS_GEN9(dev)) |
2319 | flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; | |
2320 | else | |
2321 | flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; | |
2322 | ||
2323 | if (flip_done) { | |
38cc46d7 OM |
2324 | intel_prepare_page_flip(dev, pipe); |
2325 | intel_finish_page_flip_plane(dev, pipe); | |
2326 | } | |
2327 | ||
2328 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) | |
2329 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2330 | ||
1f7247c0 DV |
2331 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) |
2332 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
2333 | pipe); | |
38cc46d7 | 2334 | |
770de83d DL |
2335 | |
2336 | if (IS_GEN9(dev)) | |
2337 | fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2338 | else | |
2339 | fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2340 | ||
2341 | if (fault_errors) | |
38cc46d7 OM |
2342 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
2343 | pipe_name(pipe), | |
2344 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
c42664cc | 2345 | } else |
abd58f01 BW |
2346 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2347 | } | |
2348 | ||
92d03a80 DV |
2349 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2350 | /* | |
2351 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2352 | * scheme also closed the SDE interrupt handling race we've seen | |
2353 | * on older pch-split platforms. But this needs testing. | |
2354 | */ | |
2355 | u32 pch_iir = I915_READ(SDEIIR); | |
92d03a80 DV |
2356 | if (pch_iir) { |
2357 | I915_WRITE(SDEIIR, pch_iir); | |
2358 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2359 | cpt_irq_handler(dev, pch_iir); |
2360 | } else | |
2361 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); | |
2362 | ||
92d03a80 DV |
2363 | } |
2364 | ||
abd58f01 BW |
2365 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2366 | POSTING_READ(GEN8_MASTER_IRQ); | |
2367 | ||
2368 | return ret; | |
2369 | } | |
2370 | ||
17e1df07 DV |
2371 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2372 | bool reset_completed) | |
2373 | { | |
a4872ba6 | 2374 | struct intel_engine_cs *ring; |
17e1df07 DV |
2375 | int i; |
2376 | ||
2377 | /* | |
2378 | * Notify all waiters for GPU completion events that reset state has | |
2379 | * been changed, and that they need to restart their wait after | |
2380 | * checking for potential errors (and bail out to drop locks if there is | |
2381 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2382 | */ | |
2383 | ||
2384 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2385 | for_each_ring(ring, dev_priv, i) | |
2386 | wake_up_all(&ring->irq_queue); | |
2387 | ||
2388 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2389 | wake_up_all(&dev_priv->pending_flip_queue); | |
2390 | ||
2391 | /* | |
2392 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2393 | * reset state is cleared. | |
2394 | */ | |
2395 | if (reset_completed) | |
2396 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2397 | } | |
2398 | ||
8a905236 JB |
2399 | /** |
2400 | * i915_error_work_func - do process context error handling work | |
2401 | * @work: work struct | |
2402 | * | |
2403 | * Fire an error uevent so userspace can see that a hang or error | |
2404 | * was detected. | |
2405 | */ | |
2406 | static void i915_error_work_func(struct work_struct *work) | |
2407 | { | |
1f83fee0 DV |
2408 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
2409 | work); | |
2d1013dd JN |
2410 | struct drm_i915_private *dev_priv = |
2411 | container_of(error, struct drm_i915_private, gpu_error); | |
8a905236 | 2412 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
2413 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2414 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2415 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2416 | int ret; |
8a905236 | 2417 | |
5bdebb18 | 2418 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2419 | |
7db0ba24 DV |
2420 | /* |
2421 | * Note that there's only one work item which does gpu resets, so we | |
2422 | * need not worry about concurrent gpu resets potentially incrementing | |
2423 | * error->reset_counter twice. We only need to take care of another | |
2424 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2425 | * quick check for that is good enough: schedule_work ensures the | |
2426 | * correct ordering between hang detection and this work item, and since | |
2427 | * the reset in-progress bit is only ever set by code outside of this | |
2428 | * work we don't need to worry about any other races. | |
2429 | */ | |
2430 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2431 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2432 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2433 | reset_event); |
1f83fee0 | 2434 | |
f454c694 ID |
2435 | /* |
2436 | * In most cases it's guaranteed that we get here with an RPM | |
2437 | * reference held, for example because there is a pending GPU | |
2438 | * request that won't finish until the reset is done. This | |
2439 | * isn't the case at least when we get here by doing a | |
2440 | * simulated reset via debugs, so get an RPM reference. | |
2441 | */ | |
2442 | intel_runtime_pm_get(dev_priv); | |
7514747d VS |
2443 | |
2444 | intel_prepare_reset(dev); | |
2445 | ||
17e1df07 DV |
2446 | /* |
2447 | * All state reset _must_ be completed before we update the | |
2448 | * reset counter, for otherwise waiters might miss the reset | |
2449 | * pending state and not properly drop locks, resulting in | |
2450 | * deadlocks with the reset work. | |
2451 | */ | |
f69061be DV |
2452 | ret = i915_reset(dev); |
2453 | ||
7514747d | 2454 | intel_finish_reset(dev); |
17e1df07 | 2455 | |
f454c694 ID |
2456 | intel_runtime_pm_put(dev_priv); |
2457 | ||
f69061be DV |
2458 | if (ret == 0) { |
2459 | /* | |
2460 | * After all the gem state is reset, increment the reset | |
2461 | * counter and wake up everyone waiting for the reset to | |
2462 | * complete. | |
2463 | * | |
2464 | * Since unlock operations are a one-sided barrier only, | |
2465 | * we need to insert a barrier here to order any seqno | |
2466 | * updates before | |
2467 | * the counter increment. | |
2468 | */ | |
4e857c58 | 2469 | smp_mb__before_atomic(); |
f69061be DV |
2470 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
2471 | ||
5bdebb18 | 2472 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2473 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2474 | } else { |
2ac0f450 | 2475 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2476 | } |
1f83fee0 | 2477 | |
17e1df07 DV |
2478 | /* |
2479 | * Note: The wake_up also serves as a memory barrier so that | |
2480 | * waiters see the update value of the reset counter atomic_t. | |
2481 | */ | |
2482 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2483 | } |
8a905236 JB |
2484 | } |
2485 | ||
35aed2e6 | 2486 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2487 | { |
2488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2489 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2490 | u32 eir = I915_READ(EIR); |
050ee91f | 2491 | int pipe, i; |
8a905236 | 2492 | |
35aed2e6 CW |
2493 | if (!eir) |
2494 | return; | |
8a905236 | 2495 | |
a70491cc | 2496 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2497 | |
bd9854f9 BW |
2498 | i915_get_extra_instdone(dev, instdone); |
2499 | ||
8a905236 JB |
2500 | if (IS_G4X(dev)) { |
2501 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2502 | u32 ipeir = I915_READ(IPEIR_I965); | |
2503 | ||
a70491cc JP |
2504 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2505 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2506 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2507 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2508 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2509 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2510 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2511 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2512 | } |
2513 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2514 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2515 | pr_err("page table error\n"); |
2516 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2517 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2518 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2519 | } |
2520 | } | |
2521 | ||
a6c45cf0 | 2522 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2523 | if (eir & I915_ERROR_PAGE_TABLE) { |
2524 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2525 | pr_err("page table error\n"); |
2526 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2527 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2528 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2529 | } |
2530 | } | |
2531 | ||
2532 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2533 | pr_err("memory refresh error:\n"); |
055e393f | 2534 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2535 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2536 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2537 | /* pipestat has already been acked */ |
2538 | } | |
2539 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2540 | pr_err("instruction error\n"); |
2541 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2542 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2543 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2544 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2545 | u32 ipeir = I915_READ(IPEIR); |
2546 | ||
a70491cc JP |
2547 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2548 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2549 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2550 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2551 | POSTING_READ(IPEIR); |
8a905236 JB |
2552 | } else { |
2553 | u32 ipeir = I915_READ(IPEIR_I965); | |
2554 | ||
a70491cc JP |
2555 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2556 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2557 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2558 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2559 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2560 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2561 | } |
2562 | } | |
2563 | ||
2564 | I915_WRITE(EIR, eir); | |
3143a2bf | 2565 | POSTING_READ(EIR); |
8a905236 JB |
2566 | eir = I915_READ(EIR); |
2567 | if (eir) { | |
2568 | /* | |
2569 | * some errors might have become stuck, | |
2570 | * mask them. | |
2571 | */ | |
2572 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2573 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2574 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2575 | } | |
35aed2e6 CW |
2576 | } |
2577 | ||
2578 | /** | |
2579 | * i915_handle_error - handle an error interrupt | |
2580 | * @dev: drm device | |
2581 | * | |
2582 | * Do some basic checking of regsiter state at error interrupt time and | |
2583 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2584 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2585 | * so userspace knows something bad happened (should trigger collection | |
2586 | * of a ring dump etc.). | |
2587 | */ | |
58174462 MK |
2588 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2589 | const char *fmt, ...) | |
35aed2e6 CW |
2590 | { |
2591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2592 | va_list args; |
2593 | char error_msg[80]; | |
35aed2e6 | 2594 | |
58174462 MK |
2595 | va_start(args, fmt); |
2596 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2597 | va_end(args); | |
2598 | ||
2599 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2600 | i915_report_and_clear_eir(dev); |
8a905236 | 2601 | |
ba1234d1 | 2602 | if (wedged) { |
f69061be DV |
2603 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2604 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2605 | |
11ed50ec | 2606 | /* |
17e1df07 DV |
2607 | * Wakeup waiting processes so that the reset work function |
2608 | * i915_error_work_func doesn't deadlock trying to grab various | |
2609 | * locks. By bumping the reset counter first, the woken | |
2610 | * processes will see a reset in progress and back off, | |
2611 | * releasing their locks and then wait for the reset completion. | |
2612 | * We must do this for _all_ gpu waiters that might hold locks | |
2613 | * that the reset work needs to acquire. | |
2614 | * | |
2615 | * Note: The wake_up serves as the required memory barrier to | |
2616 | * ensure that the waiters see the updated value of the reset | |
2617 | * counter atomic_t. | |
11ed50ec | 2618 | */ |
17e1df07 | 2619 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2620 | } |
2621 | ||
122f46ba DV |
2622 | /* |
2623 | * Our reset work can grab modeset locks (since it needs to reset the | |
2624 | * state of outstanding pagelips). Hence it must not be run on our own | |
2625 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2626 | * code will deadlock. | |
2627 | */ | |
2628 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2629 | } |
2630 | ||
42f52ef8 KP |
2631 | /* Called from drm generic code, passed 'crtc' which |
2632 | * we use as a pipe index | |
2633 | */ | |
f71d4af4 | 2634 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2635 | { |
2d1013dd | 2636 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2637 | unsigned long irqflags; |
71e0ffa5 | 2638 | |
5eddb70b | 2639 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2640 | return -EINVAL; |
0a3e67a4 | 2641 | |
1ec14ad3 | 2642 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2643 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2644 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2645 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2646 | else |
7c463586 | 2647 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2648 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2649 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2650 | |
0a3e67a4 JB |
2651 | return 0; |
2652 | } | |
2653 | ||
f71d4af4 | 2654 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2655 | { |
2d1013dd | 2656 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2657 | unsigned long irqflags; |
b518421f | 2658 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2659 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2660 | |
2661 | if (!i915_pipe_enabled(dev, pipe)) | |
2662 | return -EINVAL; | |
2663 | ||
2664 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2665 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2666 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2667 | ||
2668 | return 0; | |
2669 | } | |
2670 | ||
7e231dbe JB |
2671 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2672 | { | |
2d1013dd | 2673 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2674 | unsigned long irqflags; |
7e231dbe JB |
2675 | |
2676 | if (!i915_pipe_enabled(dev, pipe)) | |
2677 | return -EINVAL; | |
2678 | ||
2679 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2680 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2681 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2682 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2683 | ||
2684 | return 0; | |
2685 | } | |
2686 | ||
abd58f01 BW |
2687 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2688 | { | |
2689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2690 | unsigned long irqflags; | |
abd58f01 BW |
2691 | |
2692 | if (!i915_pipe_enabled(dev, pipe)) | |
2693 | return -EINVAL; | |
2694 | ||
2695 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2696 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2697 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2698 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2699 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2700 | return 0; | |
2701 | } | |
2702 | ||
42f52ef8 KP |
2703 | /* Called from drm generic code, passed 'crtc' which |
2704 | * we use as a pipe index | |
2705 | */ | |
f71d4af4 | 2706 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2707 | { |
2d1013dd | 2708 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2709 | unsigned long irqflags; |
0a3e67a4 | 2710 | |
1ec14ad3 | 2711 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2712 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2713 | PIPE_VBLANK_INTERRUPT_STATUS | |
2714 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2715 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2716 | } | |
2717 | ||
f71d4af4 | 2718 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2719 | { |
2d1013dd | 2720 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2721 | unsigned long irqflags; |
b518421f | 2722 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2723 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2724 | |
2725 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2726 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2727 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2728 | } | |
2729 | ||
7e231dbe JB |
2730 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2731 | { | |
2d1013dd | 2732 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2733 | unsigned long irqflags; |
7e231dbe JB |
2734 | |
2735 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2736 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2737 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2738 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2739 | } | |
2740 | ||
abd58f01 BW |
2741 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2742 | { | |
2743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2744 | unsigned long irqflags; | |
abd58f01 BW |
2745 | |
2746 | if (!i915_pipe_enabled(dev, pipe)) | |
2747 | return; | |
2748 | ||
2749 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2750 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2751 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2752 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2753 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2754 | } | |
2755 | ||
893eead0 | 2756 | static u32 |
a4872ba6 | 2757 | ring_last_seqno(struct intel_engine_cs *ring) |
852835f3 | 2758 | { |
893eead0 CW |
2759 | return list_entry(ring->request_list.prev, |
2760 | struct drm_i915_gem_request, list)->seqno; | |
2761 | } | |
2762 | ||
9107e9d2 | 2763 | static bool |
a4872ba6 | 2764 | ring_idle(struct intel_engine_cs *ring, u32 seqno) |
9107e9d2 CW |
2765 | { |
2766 | return (list_empty(&ring->request_list) || | |
2767 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2768 | } |
2769 | ||
a028c4b0 DV |
2770 | static bool |
2771 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2772 | { | |
2773 | if (INTEL_INFO(dev)->gen >= 8) { | |
a6cdb93a | 2774 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2775 | } else { |
2776 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2777 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2778 | MI_SEMAPHORE_REGISTER); | |
2779 | } | |
2780 | } | |
2781 | ||
a4872ba6 | 2782 | static struct intel_engine_cs * |
a6cdb93a | 2783 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
921d42ea DV |
2784 | { |
2785 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2786 | struct intel_engine_cs *signaller; |
921d42ea DV |
2787 | int i; |
2788 | ||
2789 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
a6cdb93a RV |
2790 | for_each_ring(signaller, dev_priv, i) { |
2791 | if (ring == signaller) | |
2792 | continue; | |
2793 | ||
2794 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) | |
2795 | return signaller; | |
2796 | } | |
921d42ea DV |
2797 | } else { |
2798 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2799 | ||
2800 | for_each_ring(signaller, dev_priv, i) { | |
2801 | if(ring == signaller) | |
2802 | continue; | |
2803 | ||
ebc348b2 | 2804 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2805 | return signaller; |
2806 | } | |
2807 | } | |
2808 | ||
a6cdb93a RV |
2809 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
2810 | ring->id, ipehr, offset); | |
921d42ea DV |
2811 | |
2812 | return NULL; | |
2813 | } | |
2814 | ||
a4872ba6 OM |
2815 | static struct intel_engine_cs * |
2816 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) | |
a24a11e6 CW |
2817 | { |
2818 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d | 2819 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2820 | u64 offset = 0; |
2821 | int i, backwards; | |
a24a11e6 CW |
2822 | |
2823 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2824 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2825 | return NULL; |
a24a11e6 | 2826 | |
88fe429d DV |
2827 | /* |
2828 | * HEAD is likely pointing to the dword after the actual command, | |
2829 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2830 | * or 4 dwords depending on the semaphore wait command size. |
2831 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2832 | * point at at batch, and semaphores are always emitted into the |
2833 | * ringbuffer itself. | |
a24a11e6 | 2834 | */ |
88fe429d | 2835 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
a6cdb93a | 2836 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
88fe429d | 2837 | |
a6cdb93a | 2838 | for (i = backwards; i; --i) { |
88fe429d DV |
2839 | /* |
2840 | * Be paranoid and presume the hw has gone off into the wild - | |
2841 | * our ring is smaller than what the hardware (and hence | |
2842 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2843 | */ | |
ee1b1e5e | 2844 | head &= ring->buffer->size - 1; |
88fe429d DV |
2845 | |
2846 | /* This here seems to blow up */ | |
ee1b1e5e | 2847 | cmd = ioread32(ring->buffer->virtual_start + head); |
a24a11e6 CW |
2848 | if (cmd == ipehr) |
2849 | break; | |
2850 | ||
88fe429d DV |
2851 | head -= 4; |
2852 | } | |
a24a11e6 | 2853 | |
88fe429d DV |
2854 | if (!i) |
2855 | return NULL; | |
a24a11e6 | 2856 | |
ee1b1e5e | 2857 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
a6cdb93a RV |
2858 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2859 | offset = ioread32(ring->buffer->virtual_start + head + 12); | |
2860 | offset <<= 32; | |
2861 | offset = ioread32(ring->buffer->virtual_start + head + 8); | |
2862 | } | |
2863 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); | |
a24a11e6 CW |
2864 | } |
2865 | ||
a4872ba6 | 2866 | static int semaphore_passed(struct intel_engine_cs *ring) |
6274f212 CW |
2867 | { |
2868 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2869 | struct intel_engine_cs *signaller; |
a0d036b0 | 2870 | u32 seqno; |
6274f212 | 2871 | |
4be17381 | 2872 | ring->hangcheck.deadlock++; |
6274f212 CW |
2873 | |
2874 | signaller = semaphore_waits_for(ring, &seqno); | |
4be17381 CW |
2875 | if (signaller == NULL) |
2876 | return -1; | |
2877 | ||
2878 | /* Prevent pathological recursion due to driver bugs */ | |
2879 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) | |
6274f212 CW |
2880 | return -1; |
2881 | ||
4be17381 CW |
2882 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
2883 | return 1; | |
2884 | ||
a0d036b0 CW |
2885 | /* cursory check for an unkickable deadlock */ |
2886 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
2887 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
2888 | return -1; |
2889 | ||
2890 | return 0; | |
6274f212 CW |
2891 | } |
2892 | ||
2893 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2894 | { | |
a4872ba6 | 2895 | struct intel_engine_cs *ring; |
6274f212 CW |
2896 | int i; |
2897 | ||
2898 | for_each_ring(ring, dev_priv, i) | |
4be17381 | 2899 | ring->hangcheck.deadlock = 0; |
6274f212 CW |
2900 | } |
2901 | ||
ad8beaea | 2902 | static enum intel_ring_hangcheck_action |
a4872ba6 | 2903 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
1ec14ad3 CW |
2904 | { |
2905 | struct drm_device *dev = ring->dev; | |
2906 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2907 | u32 tmp; |
2908 | ||
f260fe7b MK |
2909 | if (acthd != ring->hangcheck.acthd) { |
2910 | if (acthd > ring->hangcheck.max_acthd) { | |
2911 | ring->hangcheck.max_acthd = acthd; | |
2912 | return HANGCHECK_ACTIVE; | |
2913 | } | |
2914 | ||
2915 | return HANGCHECK_ACTIVE_LOOP; | |
2916 | } | |
6274f212 | 2917 | |
9107e9d2 | 2918 | if (IS_GEN2(dev)) |
f2f4d82f | 2919 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2920 | |
2921 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2922 | * If so we can simply poke the RB_WAIT bit | |
2923 | * and break the hang. This should work on | |
2924 | * all but the second generation chipsets. | |
2925 | */ | |
2926 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2927 | if (tmp & RING_WAIT) { |
58174462 MK |
2928 | i915_handle_error(dev, false, |
2929 | "Kicking stuck wait on %s", | |
2930 | ring->name); | |
1ec14ad3 | 2931 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2932 | return HANGCHECK_KICK; |
6274f212 CW |
2933 | } |
2934 | ||
2935 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2936 | switch (semaphore_passed(ring)) { | |
2937 | default: | |
f2f4d82f | 2938 | return HANGCHECK_HUNG; |
6274f212 | 2939 | case 1: |
58174462 MK |
2940 | i915_handle_error(dev, false, |
2941 | "Kicking stuck semaphore on %s", | |
2942 | ring->name); | |
6274f212 | 2943 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2944 | return HANGCHECK_KICK; |
6274f212 | 2945 | case 0: |
f2f4d82f | 2946 | return HANGCHECK_WAIT; |
6274f212 | 2947 | } |
9107e9d2 | 2948 | } |
ed5cbb03 | 2949 | |
f2f4d82f | 2950 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2951 | } |
2952 | ||
f65d9421 BG |
2953 | /** |
2954 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2955 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2956 | * if there are no progress, hangcheck score for that ring is increased. | |
2957 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2958 | * we kick the ring. If we see no progress on three subsequent calls | |
2959 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2960 | */ |
a658b5d2 | 2961 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2962 | { |
2963 | struct drm_device *dev = (struct drm_device *)data; | |
2d1013dd | 2964 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2965 | struct intel_engine_cs *ring; |
b4519513 | 2966 | int i; |
05407ff8 | 2967 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2968 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2969 | #define BUSY 1 | |
2970 | #define KICK 5 | |
2971 | #define HUNG 20 | |
893eead0 | 2972 | |
d330a953 | 2973 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2974 | return; |
2975 | ||
b4519513 | 2976 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2977 | u64 acthd; |
2978 | u32 seqno; | |
9107e9d2 | 2979 | bool busy = true; |
05407ff8 | 2980 | |
6274f212 CW |
2981 | semaphore_clear_deadlocks(dev_priv); |
2982 | ||
05407ff8 MK |
2983 | seqno = ring->get_seqno(ring, false); |
2984 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2985 | |
9107e9d2 CW |
2986 | if (ring->hangcheck.seqno == seqno) { |
2987 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2988 | ring->hangcheck.action = HANGCHECK_IDLE; |
2989 | ||
9107e9d2 CW |
2990 | if (waitqueue_active(&ring->irq_queue)) { |
2991 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2992 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2993 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2994 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2995 | ring->name); | |
2996 | else | |
2997 | DRM_INFO("Fake missed irq on %s\n", | |
2998 | ring->name); | |
094f9a54 CW |
2999 | wake_up_all(&ring->irq_queue); |
3000 | } | |
3001 | /* Safeguard against driver failure */ | |
3002 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
3003 | } else |
3004 | busy = false; | |
05407ff8 | 3005 | } else { |
6274f212 CW |
3006 | /* We always increment the hangcheck score |
3007 | * if the ring is busy and still processing | |
3008 | * the same request, so that no single request | |
3009 | * can run indefinitely (such as a chain of | |
3010 | * batches). The only time we do not increment | |
3011 | * the hangcheck score on this ring, if this | |
3012 | * ring is in a legitimate wait for another | |
3013 | * ring. In that case the waiting ring is a | |
3014 | * victim and we want to be sure we catch the | |
3015 | * right culprit. Then every time we do kick | |
3016 | * the ring, add a small increment to the | |
3017 | * score so that we can catch a batch that is | |
3018 | * being repeatedly kicked and so responsible | |
3019 | * for stalling the machine. | |
3020 | */ | |
ad8beaea MK |
3021 | ring->hangcheck.action = ring_stuck(ring, |
3022 | acthd); | |
3023 | ||
3024 | switch (ring->hangcheck.action) { | |
da661464 | 3025 | case HANGCHECK_IDLE: |
f2f4d82f | 3026 | case HANGCHECK_WAIT: |
f2f4d82f | 3027 | case HANGCHECK_ACTIVE: |
f260fe7b MK |
3028 | break; |
3029 | case HANGCHECK_ACTIVE_LOOP: | |
ea04cb31 | 3030 | ring->hangcheck.score += BUSY; |
6274f212 | 3031 | break; |
f2f4d82f | 3032 | case HANGCHECK_KICK: |
ea04cb31 | 3033 | ring->hangcheck.score += KICK; |
6274f212 | 3034 | break; |
f2f4d82f | 3035 | case HANGCHECK_HUNG: |
ea04cb31 | 3036 | ring->hangcheck.score += HUNG; |
6274f212 CW |
3037 | stuck[i] = true; |
3038 | break; | |
3039 | } | |
05407ff8 | 3040 | } |
9107e9d2 | 3041 | } else { |
da661464 MK |
3042 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
3043 | ||
9107e9d2 CW |
3044 | /* Gradually reduce the count so that we catch DoS |
3045 | * attempts across multiple batches. | |
3046 | */ | |
3047 | if (ring->hangcheck.score > 0) | |
3048 | ring->hangcheck.score--; | |
f260fe7b MK |
3049 | |
3050 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; | |
d1e61e7f CW |
3051 | } |
3052 | ||
05407ff8 MK |
3053 | ring->hangcheck.seqno = seqno; |
3054 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 3055 | busy_count += busy; |
893eead0 | 3056 | } |
b9201c14 | 3057 | |
92cab734 | 3058 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 3059 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
3060 | DRM_INFO("%s on %s\n", |
3061 | stuck[i] ? "stuck" : "no progress", | |
3062 | ring->name); | |
a43adf07 | 3063 | rings_hung++; |
92cab734 MK |
3064 | } |
3065 | } | |
3066 | ||
05407ff8 | 3067 | if (rings_hung) |
58174462 | 3068 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 3069 | |
05407ff8 MK |
3070 | if (busy_count) |
3071 | /* Reset timer case chip hangs without another request | |
3072 | * being added */ | |
10cd45b6 MK |
3073 | i915_queue_hangcheck(dev); |
3074 | } | |
3075 | ||
3076 | void i915_queue_hangcheck(struct drm_device *dev) | |
3077 | { | |
3078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
672e7b7c CW |
3079 | struct timer_list *timer = &dev_priv->gpu_error.hangcheck_timer; |
3080 | ||
d330a953 | 3081 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
3082 | return; |
3083 | ||
672e7b7c | 3084 | /* Don't continually defer the hangcheck, but make sure it is active */ |
d9e600b2 CW |
3085 | if (timer_pending(timer)) |
3086 | return; | |
3087 | mod_timer(timer, | |
3088 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
3089 | } |
3090 | ||
1c69eb42 | 3091 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
3092 | { |
3093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3094 | ||
3095 | if (HAS_PCH_NOP(dev)) | |
3096 | return; | |
3097 | ||
f86f3fb0 | 3098 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3099 | |
3100 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3101 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3102 | } |
105b122e | 3103 | |
622364b6 PZ |
3104 | /* |
3105 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3106 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3107 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3108 | * only unmask them as needed with SDEIMR. | |
3109 | * | |
3110 | * This function needs to be called before interrupts are enabled. | |
3111 | */ | |
3112 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3113 | { | |
3114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3115 | ||
3116 | if (HAS_PCH_NOP(dev)) | |
3117 | return; | |
3118 | ||
3119 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3120 | I915_WRITE(SDEIER, 0xffffffff); |
3121 | POSTING_READ(SDEIER); | |
3122 | } | |
3123 | ||
7c4d664e | 3124 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3125 | { |
3126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3127 | ||
f86f3fb0 | 3128 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3129 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3130 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3131 | } |
3132 | ||
1da177e4 LT |
3133 | /* drm_dma.h hooks |
3134 | */ | |
be30b29f | 3135 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 3136 | { |
2d1013dd | 3137 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 3138 | |
0c841212 | 3139 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 3140 | |
f86f3fb0 | 3141 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
3142 | if (IS_GEN7(dev)) |
3143 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 3144 | |
7c4d664e | 3145 | gen5_gt_irq_reset(dev); |
c650156a | 3146 | |
1c69eb42 | 3147 | ibx_irq_reset(dev); |
7d99163d | 3148 | } |
c650156a | 3149 | |
70591a41 VS |
3150 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
3151 | { | |
3152 | enum pipe pipe; | |
3153 | ||
3154 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3155 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3156 | ||
3157 | for_each_pipe(dev_priv, pipe) | |
3158 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3159 | ||
3160 | GEN5_IRQ_RESET(VLV_); | |
3161 | } | |
3162 | ||
7e231dbe JB |
3163 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3164 | { | |
2d1013dd | 3165 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3166 | |
7e231dbe JB |
3167 | /* VLV magic */ |
3168 | I915_WRITE(VLV_IMR, 0); | |
3169 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
3170 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
3171 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
3172 | ||
7c4d664e | 3173 | gen5_gt_irq_reset(dev); |
7e231dbe | 3174 | |
7c4cde39 | 3175 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
7e231dbe | 3176 | |
70591a41 | 3177 | vlv_display_irq_reset(dev_priv); |
7e231dbe JB |
3178 | } |
3179 | ||
d6e3cca3 DV |
3180 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3181 | { | |
3182 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3183 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3184 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3185 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3186 | } | |
3187 | ||
823f6b38 | 3188 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3189 | { |
3190 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3191 | int pipe; | |
3192 | ||
abd58f01 BW |
3193 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3194 | POSTING_READ(GEN8_MASTER_IRQ); | |
3195 | ||
d6e3cca3 | 3196 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3197 | |
055e393f | 3198 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3199 | if (intel_display_power_is_enabled(dev_priv, |
3200 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3201 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3202 | |
f86f3fb0 PZ |
3203 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3204 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3205 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3206 | |
1c69eb42 | 3207 | ibx_irq_reset(dev); |
abd58f01 | 3208 | } |
09f2344d | 3209 | |
d49bdb0e PZ |
3210 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) |
3211 | { | |
1180e206 | 3212 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
d49bdb0e | 3213 | |
13321786 | 3214 | spin_lock_irq(&dev_priv->irq_lock); |
d49bdb0e | 3215 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], |
1180e206 | 3216 | ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); |
d49bdb0e | 3217 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], |
1180e206 | 3218 | ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); |
13321786 | 3219 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3220 | } |
3221 | ||
43f328d7 VS |
3222 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3223 | { | |
3224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3225 | |
3226 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3227 | POSTING_READ(GEN8_MASTER_IRQ); | |
3228 | ||
d6e3cca3 | 3229 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3230 | |
3231 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3232 | ||
43f328d7 VS |
3233 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
3234 | ||
70591a41 | 3235 | vlv_display_irq_reset(dev_priv); |
43f328d7 VS |
3236 | } |
3237 | ||
82a28bcf | 3238 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3239 | { |
2d1013dd | 3240 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3241 | struct intel_encoder *intel_encoder; |
fee884ed | 3242 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
3243 | |
3244 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3245 | hotplug_irqs = SDE_HOTPLUG_MASK; |
b2784e15 | 3246 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3247 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3248 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 3249 | } else { |
fee884ed | 3250 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
b2784e15 | 3251 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3252 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3253 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 3254 | } |
7fe0b973 | 3255 | |
fee884ed | 3256 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3257 | |
3258 | /* | |
3259 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
3260 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3261 | * | |
3262 | * This register is the same on all known PCH chips. | |
3263 | */ | |
7fe0b973 KP |
3264 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3265 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3266 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3267 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3268 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
3269 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
3270 | } | |
3271 | ||
d46da437 PZ |
3272 | static void ibx_irq_postinstall(struct drm_device *dev) |
3273 | { | |
2d1013dd | 3274 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3275 | u32 mask; |
e5868a31 | 3276 | |
692a04cf DV |
3277 | if (HAS_PCH_NOP(dev)) |
3278 | return; | |
3279 | ||
105b122e | 3280 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3281 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3282 | else |
5c673b60 | 3283 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3284 | |
337ba017 | 3285 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3286 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3287 | } |
3288 | ||
0a9a8c91 DV |
3289 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3290 | { | |
3291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3292 | u32 pm_irqs, gt_irqs; | |
3293 | ||
3294 | pm_irqs = gt_irqs = 0; | |
3295 | ||
3296 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3297 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3298 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3299 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3300 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3301 | } |
3302 | ||
3303 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3304 | if (IS_GEN5(dev)) { | |
3305 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3306 | ILK_BSD_USER_INTERRUPT; | |
3307 | } else { | |
3308 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3309 | } | |
3310 | ||
35079899 | 3311 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3312 | |
3313 | if (INTEL_INFO(dev)->gen >= 6) { | |
78e68d36 ID |
3314 | /* |
3315 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3316 | * itself is enabled/disabled. | |
3317 | */ | |
0a9a8c91 DV |
3318 | if (HAS_VEBOX(dev)) |
3319 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3320 | ||
605cd25b | 3321 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3322 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3323 | } |
3324 | } | |
3325 | ||
f71d4af4 | 3326 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3327 | { |
2d1013dd | 3328 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3329 | u32 display_mask, extra_mask; |
3330 | ||
3331 | if (INTEL_INFO(dev)->gen >= 7) { | |
3332 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3333 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3334 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3335 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3336 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 3337 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
3338 | } else { |
3339 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3340 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3341 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3342 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3343 | DE_POISON); | |
5c673b60 DV |
3344 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3345 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3346 | } |
036a4a7d | 3347 | |
1ec14ad3 | 3348 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3349 | |
0c841212 PZ |
3350 | I915_WRITE(HWSTAM, 0xeffe); |
3351 | ||
622364b6 PZ |
3352 | ibx_irq_pre_postinstall(dev); |
3353 | ||
35079899 | 3354 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3355 | |
0a9a8c91 | 3356 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3357 | |
d46da437 | 3358 | ibx_irq_postinstall(dev); |
7fe0b973 | 3359 | |
f97108d1 | 3360 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3361 | /* Enable PCU event interrupts |
3362 | * | |
3363 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3364 | * setup is guaranteed to run in single-threaded context. But we |
3365 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3366 | spin_lock_irq(&dev_priv->irq_lock); |
f97108d1 | 3367 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3368 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3369 | } |
3370 | ||
036a4a7d ZW |
3371 | return 0; |
3372 | } | |
3373 | ||
f8b79e58 ID |
3374 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3375 | { | |
3376 | u32 pipestat_mask; | |
3377 | u32 iir_mask; | |
120dda4f | 3378 | enum pipe pipe; |
f8b79e58 ID |
3379 | |
3380 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3381 | PIPE_FIFO_UNDERRUN_STATUS; | |
3382 | ||
120dda4f VS |
3383 | for_each_pipe(dev_priv, pipe) |
3384 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3385 | POSTING_READ(PIPESTAT(PIPE_A)); |
3386 | ||
3387 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3388 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3389 | ||
120dda4f VS |
3390 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3391 | for_each_pipe(dev_priv, pipe) | |
3392 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3393 | |
3394 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3395 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3396 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
120dda4f VS |
3397 | if (IS_CHERRYVIEW(dev_priv)) |
3398 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3399 | dev_priv->irq_mask &= ~iir_mask; |
3400 | ||
3401 | I915_WRITE(VLV_IIR, iir_mask); | |
3402 | I915_WRITE(VLV_IIR, iir_mask); | |
f8b79e58 | 3403 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
76e41860 VS |
3404 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3405 | POSTING_READ(VLV_IMR); | |
f8b79e58 ID |
3406 | } |
3407 | ||
3408 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3409 | { | |
3410 | u32 pipestat_mask; | |
3411 | u32 iir_mask; | |
120dda4f | 3412 | enum pipe pipe; |
f8b79e58 ID |
3413 | |
3414 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3415 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3416 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
120dda4f VS |
3417 | if (IS_CHERRYVIEW(dev_priv)) |
3418 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3419 | |
3420 | dev_priv->irq_mask |= iir_mask; | |
f8b79e58 | 3421 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
76e41860 | 3422 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
f8b79e58 ID |
3423 | I915_WRITE(VLV_IIR, iir_mask); |
3424 | I915_WRITE(VLV_IIR, iir_mask); | |
3425 | POSTING_READ(VLV_IIR); | |
3426 | ||
3427 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3428 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3429 | ||
120dda4f VS |
3430 | i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3431 | for_each_pipe(dev_priv, pipe) | |
3432 | i915_disable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3433 | |
3434 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3435 | PIPE_FIFO_UNDERRUN_STATUS; | |
120dda4f VS |
3436 | |
3437 | for_each_pipe(dev_priv, pipe) | |
3438 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3439 | POSTING_READ(PIPESTAT(PIPE_A)); |
3440 | } | |
3441 | ||
3442 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3443 | { | |
3444 | assert_spin_locked(&dev_priv->irq_lock); | |
3445 | ||
3446 | if (dev_priv->display_irqs_enabled) | |
3447 | return; | |
3448 | ||
3449 | dev_priv->display_irqs_enabled = true; | |
3450 | ||
950eabaf | 3451 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3452 | valleyview_display_irqs_install(dev_priv); |
3453 | } | |
3454 | ||
3455 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3456 | { | |
3457 | assert_spin_locked(&dev_priv->irq_lock); | |
3458 | ||
3459 | if (!dev_priv->display_irqs_enabled) | |
3460 | return; | |
3461 | ||
3462 | dev_priv->display_irqs_enabled = false; | |
3463 | ||
950eabaf | 3464 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3465 | valleyview_display_irqs_uninstall(dev_priv); |
3466 | } | |
3467 | ||
0e6c9a9e | 3468 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
7e231dbe | 3469 | { |
f8b79e58 | 3470 | dev_priv->irq_mask = ~0; |
7e231dbe | 3471 | |
20afbda2 DV |
3472 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3473 | POSTING_READ(PORT_HOTPLUG_EN); | |
3474 | ||
7e231dbe | 3475 | I915_WRITE(VLV_IIR, 0xffffffff); |
76e41860 VS |
3476 | I915_WRITE(VLV_IIR, 0xffffffff); |
3477 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3478 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3479 | POSTING_READ(VLV_IMR); | |
7e231dbe | 3480 | |
b79480ba DV |
3481 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3482 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3483 | spin_lock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3484 | if (dev_priv->display_irqs_enabled) |
3485 | valleyview_display_irqs_install(dev_priv); | |
d6207435 | 3486 | spin_unlock_irq(&dev_priv->irq_lock); |
0e6c9a9e VS |
3487 | } |
3488 | ||
3489 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3490 | { | |
3491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3492 | ||
3493 | vlv_display_irq_postinstall(dev_priv); | |
7e231dbe | 3494 | |
0a9a8c91 | 3495 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3496 | |
3497 | /* ack & enable invalid PTE error interrupts */ | |
3498 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3499 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3500 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3501 | #endif | |
3502 | ||
3503 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3504 | |
3505 | return 0; | |
3506 | } | |
3507 | ||
abd58f01 BW |
3508 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3509 | { | |
abd58f01 BW |
3510 | /* These are interrupts we'll toggle with the ring mask register */ |
3511 | uint32_t gt_interrupts[] = { | |
3512 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3513 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
abd58f01 | 3514 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
73d477f6 OM |
3515 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3516 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3517 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3518 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3519 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3520 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3521 | 0, |
73d477f6 OM |
3522 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3523 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3524 | }; |
3525 | ||
0961021a | 3526 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3527 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3528 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3529 | /* |
3530 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
3531 | * is enabled/disabled. | |
3532 | */ | |
3533 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0); | |
9a2d2d87 | 3534 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3535 | } |
3536 | ||
3537 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3538 | { | |
770de83d DL |
3539 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3540 | uint32_t de_pipe_enables; | |
abd58f01 | 3541 | int pipe; |
88e04703 | 3542 | u32 aux_en = GEN8_AUX_CHANNEL_A; |
770de83d | 3543 | |
88e04703 | 3544 | if (IS_GEN9(dev_priv)) { |
770de83d DL |
3545 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3546 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
88e04703 JB |
3547 | aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3548 | GEN9_AUX_CHANNEL_D; | |
3549 | } else | |
770de83d DL |
3550 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3551 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3552 | ||
3553 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3554 | GEN8_PIPE_FIFO_UNDERRUN; | |
3555 | ||
13b3a0a7 DV |
3556 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3557 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3558 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3559 | |
055e393f | 3560 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3561 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3562 | POWER_DOMAIN_PIPE(pipe))) |
3563 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3564 | dev_priv->de_irq_mask[pipe], | |
3565 | de_pipe_enables); | |
abd58f01 | 3566 | |
88e04703 | 3567 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en); |
abd58f01 BW |
3568 | } |
3569 | ||
3570 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3571 | { | |
3572 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3573 | ||
622364b6 PZ |
3574 | ibx_irq_pre_postinstall(dev); |
3575 | ||
abd58f01 BW |
3576 | gen8_gt_irq_postinstall(dev_priv); |
3577 | gen8_de_irq_postinstall(dev_priv); | |
3578 | ||
3579 | ibx_irq_postinstall(dev); | |
3580 | ||
3581 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3582 | POSTING_READ(GEN8_MASTER_IRQ); | |
3583 | ||
3584 | return 0; | |
3585 | } | |
3586 | ||
43f328d7 VS |
3587 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3588 | { | |
3589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 | 3590 | |
c2b66797 | 3591 | vlv_display_irq_postinstall(dev_priv); |
43f328d7 VS |
3592 | |
3593 | gen8_gt_irq_postinstall(dev_priv); | |
3594 | ||
3595 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3596 | POSTING_READ(GEN8_MASTER_IRQ); | |
3597 | ||
3598 | return 0; | |
3599 | } | |
3600 | ||
abd58f01 BW |
3601 | static void gen8_irq_uninstall(struct drm_device *dev) |
3602 | { | |
3603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3604 | |
3605 | if (!dev_priv) | |
3606 | return; | |
3607 | ||
823f6b38 | 3608 | gen8_irq_reset(dev); |
abd58f01 BW |
3609 | } |
3610 | ||
8ea0be4f VS |
3611 | static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv) |
3612 | { | |
3613 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3614 | * just to make the assert_spin_locked check happy. */ | |
3615 | spin_lock_irq(&dev_priv->irq_lock); | |
3616 | if (dev_priv->display_irqs_enabled) | |
3617 | valleyview_display_irqs_uninstall(dev_priv); | |
3618 | spin_unlock_irq(&dev_priv->irq_lock); | |
3619 | ||
3620 | vlv_display_irq_reset(dev_priv); | |
3621 | ||
c352d1ba | 3622 | dev_priv->irq_mask = ~0; |
8ea0be4f VS |
3623 | } |
3624 | ||
7e231dbe JB |
3625 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3626 | { | |
2d1013dd | 3627 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3628 | |
3629 | if (!dev_priv) | |
3630 | return; | |
3631 | ||
843d0e7d ID |
3632 | I915_WRITE(VLV_MASTER_IER, 0); |
3633 | ||
893fce8e VS |
3634 | gen5_gt_irq_reset(dev); |
3635 | ||
7e231dbe | 3636 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3637 | |
8ea0be4f | 3638 | vlv_display_irq_uninstall(dev_priv); |
7e231dbe JB |
3639 | } |
3640 | ||
43f328d7 VS |
3641 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3642 | { | |
3643 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3644 | |
3645 | if (!dev_priv) | |
3646 | return; | |
3647 | ||
3648 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3649 | POSTING_READ(GEN8_MASTER_IRQ); | |
3650 | ||
a2c30fba | 3651 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3652 | |
a2c30fba | 3653 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3654 | |
c2b66797 | 3655 | vlv_display_irq_uninstall(dev_priv); |
43f328d7 VS |
3656 | } |
3657 | ||
f71d4af4 | 3658 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3659 | { |
2d1013dd | 3660 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3661 | |
3662 | if (!dev_priv) | |
3663 | return; | |
3664 | ||
be30b29f | 3665 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3666 | } |
3667 | ||
a266c7d5 | 3668 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3669 | { |
2d1013dd | 3670 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3671 | int pipe; |
91e3738e | 3672 | |
055e393f | 3673 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3674 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3675 | I915_WRITE16(IMR, 0xffff); |
3676 | I915_WRITE16(IER, 0x0); | |
3677 | POSTING_READ16(IER); | |
c2798b19 CW |
3678 | } |
3679 | ||
3680 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3681 | { | |
2d1013dd | 3682 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3683 | |
c2798b19 CW |
3684 | I915_WRITE16(EMR, |
3685 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3686 | ||
3687 | /* Unmask the interrupts that we always want on. */ | |
3688 | dev_priv->irq_mask = | |
3689 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3690 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3691 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3692 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3693 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3694 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3695 | ||
3696 | I915_WRITE16(IER, | |
3697 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3698 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3699 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3700 | I915_USER_INTERRUPT); | |
3701 | POSTING_READ16(IER); | |
3702 | ||
379ef82d DV |
3703 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3704 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3705 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3706 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3707 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3708 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3709 | |
c2798b19 CW |
3710 | return 0; |
3711 | } | |
3712 | ||
90a72f87 VS |
3713 | /* |
3714 | * Returns true when a page flip has completed. | |
3715 | */ | |
3716 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3717 | int plane, int pipe, u32 iir) |
90a72f87 | 3718 | { |
2d1013dd | 3719 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3720 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3721 | |
8d7849db | 3722 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3723 | return false; |
3724 | ||
3725 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3726 | goto check_page_flip; |
90a72f87 | 3727 | |
90a72f87 VS |
3728 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3729 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3730 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3731 | * the flip is completed (no longer pending). Since this doesn't raise | |
3732 | * an interrupt per se, we watch for the change at vblank. | |
3733 | */ | |
3734 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 3735 | goto check_page_flip; |
90a72f87 | 3736 | |
7d47559e | 3737 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3738 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3739 | return true; |
d6bbafa1 CW |
3740 | |
3741 | check_page_flip: | |
3742 | intel_check_page_flip(dev, pipe); | |
3743 | return false; | |
90a72f87 VS |
3744 | } |
3745 | ||
ff1f525e | 3746 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3747 | { |
45a83f84 | 3748 | struct drm_device *dev = arg; |
2d1013dd | 3749 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3750 | u16 iir, new_iir; |
3751 | u32 pipe_stats[2]; | |
c2798b19 CW |
3752 | int pipe; |
3753 | u16 flip_mask = | |
3754 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3755 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3756 | ||
c2798b19 CW |
3757 | iir = I915_READ16(IIR); |
3758 | if (iir == 0) | |
3759 | return IRQ_NONE; | |
3760 | ||
3761 | while (iir & ~flip_mask) { | |
3762 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3763 | * have been cleared after the pipestat interrupt was received. | |
3764 | * It doesn't set the bit in iir again, but it still produces | |
3765 | * interrupts (for non-MSI). | |
3766 | */ | |
222c7f51 | 3767 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3768 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3769 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 3770 | |
055e393f | 3771 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3772 | int reg = PIPESTAT(pipe); |
3773 | pipe_stats[pipe] = I915_READ(reg); | |
3774 | ||
3775 | /* | |
3776 | * Clear the PIPE*STAT regs before the IIR | |
3777 | */ | |
2d9d2b0b | 3778 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3779 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3780 | } |
222c7f51 | 3781 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3782 | |
3783 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3784 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3785 | ||
c2798b19 CW |
3786 | if (iir & I915_USER_INTERRUPT) |
3787 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3788 | ||
055e393f | 3789 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 3790 | int plane = pipe; |
3a77c4c4 | 3791 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3792 | plane = !plane; |
3793 | ||
4356d586 | 3794 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3795 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3796 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3797 | |
4356d586 | 3798 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3799 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3800 | |
1f7247c0 DV |
3801 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3802 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3803 | pipe); | |
4356d586 | 3804 | } |
c2798b19 CW |
3805 | |
3806 | iir = new_iir; | |
3807 | } | |
3808 | ||
3809 | return IRQ_HANDLED; | |
3810 | } | |
3811 | ||
3812 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3813 | { | |
2d1013dd | 3814 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3815 | int pipe; |
3816 | ||
055e393f | 3817 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3818 | /* Clear enable bits; then clear status bits */ |
3819 | I915_WRITE(PIPESTAT(pipe), 0); | |
3820 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3821 | } | |
3822 | I915_WRITE16(IMR, 0xffff); | |
3823 | I915_WRITE16(IER, 0x0); | |
3824 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3825 | } | |
3826 | ||
a266c7d5 CW |
3827 | static void i915_irq_preinstall(struct drm_device * dev) |
3828 | { | |
2d1013dd | 3829 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3830 | int pipe; |
3831 | ||
a266c7d5 CW |
3832 | if (I915_HAS_HOTPLUG(dev)) { |
3833 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3834 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3835 | } | |
3836 | ||
00d98ebd | 3837 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3838 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3839 | I915_WRITE(PIPESTAT(pipe), 0); |
3840 | I915_WRITE(IMR, 0xffffffff); | |
3841 | I915_WRITE(IER, 0x0); | |
3842 | POSTING_READ(IER); | |
3843 | } | |
3844 | ||
3845 | static int i915_irq_postinstall(struct drm_device *dev) | |
3846 | { | |
2d1013dd | 3847 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3848 | u32 enable_mask; |
a266c7d5 | 3849 | |
38bde180 CW |
3850 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3851 | ||
3852 | /* Unmask the interrupts that we always want on. */ | |
3853 | dev_priv->irq_mask = | |
3854 | ~(I915_ASLE_INTERRUPT | | |
3855 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3856 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3857 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3858 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3859 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3860 | ||
3861 | enable_mask = | |
3862 | I915_ASLE_INTERRUPT | | |
3863 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3864 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3865 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3866 | I915_USER_INTERRUPT; | |
3867 | ||
a266c7d5 | 3868 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3869 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3870 | POSTING_READ(PORT_HOTPLUG_EN); | |
3871 | ||
a266c7d5 CW |
3872 | /* Enable in IER... */ |
3873 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3874 | /* and unmask in IMR */ | |
3875 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3876 | } | |
3877 | ||
a266c7d5 CW |
3878 | I915_WRITE(IMR, dev_priv->irq_mask); |
3879 | I915_WRITE(IER, enable_mask); | |
3880 | POSTING_READ(IER); | |
3881 | ||
f49e38dd | 3882 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3883 | |
379ef82d DV |
3884 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3885 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3886 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3887 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3888 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3889 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3890 | |
20afbda2 DV |
3891 | return 0; |
3892 | } | |
3893 | ||
90a72f87 VS |
3894 | /* |
3895 | * Returns true when a page flip has completed. | |
3896 | */ | |
3897 | static bool i915_handle_vblank(struct drm_device *dev, | |
3898 | int plane, int pipe, u32 iir) | |
3899 | { | |
2d1013dd | 3900 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3901 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3902 | ||
8d7849db | 3903 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3904 | return false; |
3905 | ||
3906 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3907 | goto check_page_flip; |
90a72f87 | 3908 | |
90a72f87 VS |
3909 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3910 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3911 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3912 | * the flip is completed (no longer pending). Since this doesn't raise | |
3913 | * an interrupt per se, we watch for the change at vblank. | |
3914 | */ | |
3915 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 3916 | goto check_page_flip; |
90a72f87 | 3917 | |
7d47559e | 3918 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3919 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3920 | return true; |
d6bbafa1 CW |
3921 | |
3922 | check_page_flip: | |
3923 | intel_check_page_flip(dev, pipe); | |
3924 | return false; | |
90a72f87 VS |
3925 | } |
3926 | ||
ff1f525e | 3927 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3928 | { |
45a83f84 | 3929 | struct drm_device *dev = arg; |
2d1013dd | 3930 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3931 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
3932 | u32 flip_mask = |
3933 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3934 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3935 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3936 | |
a266c7d5 | 3937 | iir = I915_READ(IIR); |
38bde180 CW |
3938 | do { |
3939 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3940 | bool blc_event = false; |
a266c7d5 CW |
3941 | |
3942 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3943 | * have been cleared after the pipestat interrupt was received. | |
3944 | * It doesn't set the bit in iir again, but it still produces | |
3945 | * interrupts (for non-MSI). | |
3946 | */ | |
222c7f51 | 3947 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3948 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3949 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 3950 | |
055e393f | 3951 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
3952 | int reg = PIPESTAT(pipe); |
3953 | pipe_stats[pipe] = I915_READ(reg); | |
3954 | ||
38bde180 | 3955 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3956 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3957 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3958 | irq_received = true; |
a266c7d5 CW |
3959 | } |
3960 | } | |
222c7f51 | 3961 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
3962 | |
3963 | if (!irq_received) | |
3964 | break; | |
3965 | ||
a266c7d5 | 3966 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
3967 | if (I915_HAS_HOTPLUG(dev) && |
3968 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
3969 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3970 | |
38bde180 | 3971 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3972 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3973 | ||
a266c7d5 CW |
3974 | if (iir & I915_USER_INTERRUPT) |
3975 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3976 | |
055e393f | 3977 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 3978 | int plane = pipe; |
3a77c4c4 | 3979 | if (HAS_FBC(dev)) |
38bde180 | 3980 | plane = !plane; |
90a72f87 | 3981 | |
8291ee90 | 3982 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3983 | i915_handle_vblank(dev, plane, pipe, iir)) |
3984 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3985 | |
3986 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3987 | blc_event = true; | |
4356d586 DV |
3988 | |
3989 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3990 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3991 | |
1f7247c0 DV |
3992 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3993 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3994 | pipe); | |
a266c7d5 CW |
3995 | } |
3996 | ||
a266c7d5 CW |
3997 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3998 | intel_opregion_asle_intr(dev); | |
3999 | ||
4000 | /* With MSI, interrupts are only generated when iir | |
4001 | * transitions from zero to nonzero. If another bit got | |
4002 | * set while we were handling the existing iir bits, then | |
4003 | * we would never get another interrupt. | |
4004 | * | |
4005 | * This is fine on non-MSI as well, as if we hit this path | |
4006 | * we avoid exiting the interrupt handler only to generate | |
4007 | * another one. | |
4008 | * | |
4009 | * Note that for MSI this could cause a stray interrupt report | |
4010 | * if an interrupt landed in the time between writing IIR and | |
4011 | * the posting read. This should be rare enough to never | |
4012 | * trigger the 99% of 100,000 interrupts test for disabling | |
4013 | * stray interrupts. | |
4014 | */ | |
38bde180 | 4015 | ret = IRQ_HANDLED; |
a266c7d5 | 4016 | iir = new_iir; |
38bde180 | 4017 | } while (iir & ~flip_mask); |
a266c7d5 CW |
4018 | |
4019 | return ret; | |
4020 | } | |
4021 | ||
4022 | static void i915_irq_uninstall(struct drm_device * dev) | |
4023 | { | |
2d1013dd | 4024 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4025 | int pipe; |
4026 | ||
a266c7d5 CW |
4027 | if (I915_HAS_HOTPLUG(dev)) { |
4028 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
4029 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
4030 | } | |
4031 | ||
00d98ebd | 4032 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 4033 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 4034 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 4035 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4036 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4037 | } | |
a266c7d5 CW |
4038 | I915_WRITE(IMR, 0xffffffff); |
4039 | I915_WRITE(IER, 0x0); | |
4040 | ||
a266c7d5 CW |
4041 | I915_WRITE(IIR, I915_READ(IIR)); |
4042 | } | |
4043 | ||
4044 | static void i965_irq_preinstall(struct drm_device * dev) | |
4045 | { | |
2d1013dd | 4046 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4047 | int pipe; |
4048 | ||
adca4730 CW |
4049 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4050 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4051 | |
4052 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4053 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4054 | I915_WRITE(PIPESTAT(pipe), 0); |
4055 | I915_WRITE(IMR, 0xffffffff); | |
4056 | I915_WRITE(IER, 0x0); | |
4057 | POSTING_READ(IER); | |
4058 | } | |
4059 | ||
4060 | static int i965_irq_postinstall(struct drm_device *dev) | |
4061 | { | |
2d1013dd | 4062 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4063 | u32 enable_mask; |
a266c7d5 CW |
4064 | u32 error_mask; |
4065 | ||
a266c7d5 | 4066 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4067 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4068 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4069 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4070 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4071 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4072 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4073 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4074 | ||
4075 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4076 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4077 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4078 | enable_mask |= I915_USER_INTERRUPT; |
4079 | ||
4080 | if (IS_G4X(dev)) | |
4081 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 4082 | |
b79480ba DV |
4083 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4084 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4085 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4086 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4087 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4088 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4089 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4090 | |
a266c7d5 CW |
4091 | /* |
4092 | * Enable some error detection, note the instruction error mask | |
4093 | * bit is reserved, so we leave it masked. | |
4094 | */ | |
4095 | if (IS_G4X(dev)) { | |
4096 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4097 | GM45_ERROR_MEM_PRIV | | |
4098 | GM45_ERROR_CP_PRIV | | |
4099 | I915_ERROR_MEMORY_REFRESH); | |
4100 | } else { | |
4101 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4102 | I915_ERROR_MEMORY_REFRESH); | |
4103 | } | |
4104 | I915_WRITE(EMR, error_mask); | |
4105 | ||
4106 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4107 | I915_WRITE(IER, enable_mask); | |
4108 | POSTING_READ(IER); | |
4109 | ||
20afbda2 DV |
4110 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4111 | POSTING_READ(PORT_HOTPLUG_EN); | |
4112 | ||
f49e38dd | 4113 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4114 | |
4115 | return 0; | |
4116 | } | |
4117 | ||
bac56d5b | 4118 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4119 | { |
2d1013dd | 4120 | struct drm_i915_private *dev_priv = dev->dev_private; |
cd569aed | 4121 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
4122 | u32 hotplug_en; |
4123 | ||
b5ea2d56 DV |
4124 | assert_spin_locked(&dev_priv->irq_lock); |
4125 | ||
bac56d5b EE |
4126 | if (I915_HAS_HOTPLUG(dev)) { |
4127 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
4128 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
4129 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 4130 | /* enable bits are the same for all generations */ |
b2784e15 | 4131 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed EE |
4132 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
4133 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
4134 | /* Programming the CRT detection parameters tends |
4135 | to generate a spurious hotplug event about three | |
4136 | seconds later. So just do it once. | |
4137 | */ | |
4138 | if (IS_G4X(dev)) | |
4139 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 4140 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 4141 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 4142 | |
bac56d5b EE |
4143 | /* Ignore TV since it's buggy */ |
4144 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
4145 | } | |
a266c7d5 CW |
4146 | } |
4147 | ||
ff1f525e | 4148 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4149 | { |
45a83f84 | 4150 | struct drm_device *dev = arg; |
2d1013dd | 4151 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4152 | u32 iir, new_iir; |
4153 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4154 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4155 | u32 flip_mask = |
4156 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4157 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4158 | |
a266c7d5 CW |
4159 | iir = I915_READ(IIR); |
4160 | ||
a266c7d5 | 4161 | for (;;) { |
501e01d7 | 4162 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4163 | bool blc_event = false; |
4164 | ||
a266c7d5 CW |
4165 | /* Can't rely on pipestat interrupt bit in iir as it might |
4166 | * have been cleared after the pipestat interrupt was received. | |
4167 | * It doesn't set the bit in iir again, but it still produces | |
4168 | * interrupts (for non-MSI). | |
4169 | */ | |
222c7f51 | 4170 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4171 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4172 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4173 | |
055e393f | 4174 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4175 | int reg = PIPESTAT(pipe); |
4176 | pipe_stats[pipe] = I915_READ(reg); | |
4177 | ||
4178 | /* | |
4179 | * Clear the PIPE*STAT regs before the IIR | |
4180 | */ | |
4181 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4182 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4183 | irq_received = true; |
a266c7d5 CW |
4184 | } |
4185 | } | |
222c7f51 | 4186 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4187 | |
4188 | if (!irq_received) | |
4189 | break; | |
4190 | ||
4191 | ret = IRQ_HANDLED; | |
4192 | ||
4193 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
4194 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
4195 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4196 | |
21ad8330 | 4197 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4198 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4199 | ||
a266c7d5 CW |
4200 | if (iir & I915_USER_INTERRUPT) |
4201 | notify_ring(dev, &dev_priv->ring[RCS]); | |
4202 | if (iir & I915_BSD_USER_INTERRUPT) | |
4203 | notify_ring(dev, &dev_priv->ring[VCS]); | |
4204 | ||
055e393f | 4205 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 4206 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4207 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4208 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4209 | |
4210 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4211 | blc_event = true; | |
4356d586 DV |
4212 | |
4213 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4214 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4215 | |
1f7247c0 DV |
4216 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4217 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4218 | } |
a266c7d5 CW |
4219 | |
4220 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4221 | intel_opregion_asle_intr(dev); | |
4222 | ||
515ac2bb DV |
4223 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4224 | gmbus_irq_handler(dev); | |
4225 | ||
a266c7d5 CW |
4226 | /* With MSI, interrupts are only generated when iir |
4227 | * transitions from zero to nonzero. If another bit got | |
4228 | * set while we were handling the existing iir bits, then | |
4229 | * we would never get another interrupt. | |
4230 | * | |
4231 | * This is fine on non-MSI as well, as if we hit this path | |
4232 | * we avoid exiting the interrupt handler only to generate | |
4233 | * another one. | |
4234 | * | |
4235 | * Note that for MSI this could cause a stray interrupt report | |
4236 | * if an interrupt landed in the time between writing IIR and | |
4237 | * the posting read. This should be rare enough to never | |
4238 | * trigger the 99% of 100,000 interrupts test for disabling | |
4239 | * stray interrupts. | |
4240 | */ | |
4241 | iir = new_iir; | |
4242 | } | |
4243 | ||
4244 | return ret; | |
4245 | } | |
4246 | ||
4247 | static void i965_irq_uninstall(struct drm_device * dev) | |
4248 | { | |
2d1013dd | 4249 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4250 | int pipe; |
4251 | ||
4252 | if (!dev_priv) | |
4253 | return; | |
4254 | ||
adca4730 CW |
4255 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4256 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4257 | |
4258 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4259 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4260 | I915_WRITE(PIPESTAT(pipe), 0); |
4261 | I915_WRITE(IMR, 0xffffffff); | |
4262 | I915_WRITE(IER, 0x0); | |
4263 | ||
055e393f | 4264 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4265 | I915_WRITE(PIPESTAT(pipe), |
4266 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4267 | I915_WRITE(IIR, I915_READ(IIR)); | |
4268 | } | |
4269 | ||
4cb21832 | 4270 | static void intel_hpd_irq_reenable_work(struct work_struct *work) |
ac4c16c5 | 4271 | { |
6323751d ID |
4272 | struct drm_i915_private *dev_priv = |
4273 | container_of(work, typeof(*dev_priv), | |
4274 | hotplug_reenable_work.work); | |
ac4c16c5 EE |
4275 | struct drm_device *dev = dev_priv->dev; |
4276 | struct drm_mode_config *mode_config = &dev->mode_config; | |
ac4c16c5 EE |
4277 | int i; |
4278 | ||
6323751d ID |
4279 | intel_runtime_pm_get(dev_priv); |
4280 | ||
4cb21832 | 4281 | spin_lock_irq(&dev_priv->irq_lock); |
ac4c16c5 EE |
4282 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
4283 | struct drm_connector *connector; | |
4284 | ||
4285 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
4286 | continue; | |
4287 | ||
4288 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4289 | ||
4290 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4291 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4292 | ||
4293 | if (intel_connector->encoder->hpd_pin == i) { | |
4294 | if (connector->polled != intel_connector->polled) | |
4295 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
c23cc417 | 4296 | connector->name); |
ac4c16c5 EE |
4297 | connector->polled = intel_connector->polled; |
4298 | if (!connector->polled) | |
4299 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4300 | } | |
4301 | } | |
4302 | } | |
4303 | if (dev_priv->display.hpd_irq_setup) | |
4304 | dev_priv->display.hpd_irq_setup(dev); | |
4cb21832 | 4305 | spin_unlock_irq(&dev_priv->irq_lock); |
6323751d ID |
4306 | |
4307 | intel_runtime_pm_put(dev_priv); | |
ac4c16c5 EE |
4308 | } |
4309 | ||
fca52a55 DV |
4310 | /** |
4311 | * intel_irq_init - initializes irq support | |
4312 | * @dev_priv: i915 device instance | |
4313 | * | |
4314 | * This function initializes all the irq support including work items, timers | |
4315 | * and all the vtables. It does not setup the interrupt itself though. | |
4316 | */ | |
b963291c | 4317 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4318 | { |
b963291c | 4319 | struct drm_device *dev = dev_priv->dev; |
8b2e326d CW |
4320 | |
4321 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
13cf5504 | 4322 | INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func); |
99584db3 | 4323 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 4324 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4325 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4326 | |
a6706b45 | 4327 | /* Let's track the enabled rps events */ |
b963291c | 4328 | if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6c65a587 | 4329 | /* WaGsvRC0ResidencyMethod:vlv */ |
31685c25 D |
4330 | dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; |
4331 | else | |
4332 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4333 | |
99584db3 DV |
4334 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
4335 | i915_hangcheck_elapsed, | |
61bac78e | 4336 | (unsigned long) dev); |
6323751d | 4337 | INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, |
4cb21832 | 4338 | intel_hpd_irq_reenable_work); |
61bac78e | 4339 | |
97a19a24 | 4340 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4341 | |
b963291c | 4342 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4343 | dev->max_vblank_count = 0; |
4344 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4345 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 JB |
4346 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4347 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4348 | } else { |
4349 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4350 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4351 | } |
4352 | ||
21da2700 VS |
4353 | /* |
4354 | * Opt out of the vblank disable timer on everything except gen2. | |
4355 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4356 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4357 | */ | |
b963291c | 4358 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4359 | dev->vblank_disable_immediate = true; |
4360 | ||
c2baf4b7 | 4361 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 4362 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
4363 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
4364 | } | |
f71d4af4 | 4365 | |
b963291c | 4366 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4367 | dev->driver->irq_handler = cherryview_irq_handler; |
4368 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4369 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4370 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4371 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4372 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4373 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4374 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4375 | dev->driver->irq_handler = valleyview_irq_handler; |
4376 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4377 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4378 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4379 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4380 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4381 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4382 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4383 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4384 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4385 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4386 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4387 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4388 | dev->driver->disable_vblank = gen8_disable_vblank; | |
4389 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
4390 | } else if (HAS_PCH_SPLIT(dev)) { |
4391 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4392 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4393 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4394 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4395 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4396 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4397 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4398 | } else { |
b963291c | 4399 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4400 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4401 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4402 | dev->driver->irq_handler = i8xx_irq_handler; | |
4403 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4404 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4405 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4406 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4407 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4408 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 4409 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4410 | } else { |
a266c7d5 CW |
4411 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4412 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4413 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4414 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 4415 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4416 | } |
f71d4af4 JB |
4417 | dev->driver->enable_vblank = i915_enable_vblank; |
4418 | dev->driver->disable_vblank = i915_disable_vblank; | |
4419 | } | |
4420 | } | |
20afbda2 | 4421 | |
fca52a55 DV |
4422 | /** |
4423 | * intel_hpd_init - initializes and enables hpd support | |
4424 | * @dev_priv: i915 device instance | |
4425 | * | |
4426 | * This function enables the hotplug support. It requires that interrupts have | |
4427 | * already been enabled with intel_irq_init_hw(). From this point on hotplug and | |
4428 | * poll request can run concurrently to other code, so locking rules must be | |
4429 | * obeyed. | |
4430 | * | |
4431 | * This is a separate step from interrupt enabling to simplify the locking rules | |
4432 | * in the driver load and resume code. | |
4433 | */ | |
b963291c | 4434 | void intel_hpd_init(struct drm_i915_private *dev_priv) |
20afbda2 | 4435 | { |
b963291c | 4436 | struct drm_device *dev = dev_priv->dev; |
821450c6 EE |
4437 | struct drm_mode_config *mode_config = &dev->mode_config; |
4438 | struct drm_connector *connector; | |
4439 | int i; | |
20afbda2 | 4440 | |
821450c6 EE |
4441 | for (i = 1; i < HPD_NUM_PINS; i++) { |
4442 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
4443 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4444 | } | |
4445 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4446 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4447 | connector->polled = intel_connector->polled; | |
0e32b39c DA |
4448 | if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) |
4449 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4450 | if (intel_connector->mst_port) | |
821450c6 EE |
4451 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
4452 | } | |
b5ea2d56 DV |
4453 | |
4454 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
4455 | * just to make the assert_spin_locked checks happy. */ | |
d6207435 | 4456 | spin_lock_irq(&dev_priv->irq_lock); |
20afbda2 DV |
4457 | if (dev_priv->display.hpd_irq_setup) |
4458 | dev_priv->display.hpd_irq_setup(dev); | |
d6207435 | 4459 | spin_unlock_irq(&dev_priv->irq_lock); |
20afbda2 | 4460 | } |
c67a470b | 4461 | |
fca52a55 DV |
4462 | /** |
4463 | * intel_irq_install - enables the hardware interrupt | |
4464 | * @dev_priv: i915 device instance | |
4465 | * | |
4466 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4467 | * handling still disabled. It is called after intel_irq_init(). | |
4468 | * | |
4469 | * In the driver load and resume code we need working interrupts in a few places | |
4470 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4471 | * workers. Hence the split into this two-stage approach. | |
4472 | */ | |
2aeb7d3a DV |
4473 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4474 | { | |
4475 | /* | |
4476 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4477 | * interrupts as enabled _before_ actually enabling them to avoid | |
4478 | * special cases in our ordering checks. | |
4479 | */ | |
4480 | dev_priv->pm.irqs_enabled = true; | |
4481 | ||
4482 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4483 | } | |
4484 | ||
fca52a55 DV |
4485 | /** |
4486 | * intel_irq_uninstall - finilizes all irq handling | |
4487 | * @dev_priv: i915 device instance | |
4488 | * | |
4489 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4490 | * resources acquired in the init functions. | |
4491 | */ | |
2aeb7d3a DV |
4492 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4493 | { | |
4494 | drm_irq_uninstall(dev_priv->dev); | |
4495 | intel_hpd_cancel_work(dev_priv); | |
4496 | dev_priv->pm.irqs_enabled = false; | |
4497 | } | |
4498 | ||
fca52a55 DV |
4499 | /** |
4500 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4501 | * @dev_priv: i915 device instance | |
4502 | * | |
4503 | * This function is used to disable interrupts at runtime, both in the runtime | |
4504 | * pm and the system suspend/resume code. | |
4505 | */ | |
b963291c | 4506 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4507 | { |
b963291c | 4508 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4509 | dev_priv->pm.irqs_enabled = false; |
c67a470b PZ |
4510 | } |
4511 | ||
fca52a55 DV |
4512 | /** |
4513 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4514 | * @dev_priv: i915 device instance | |
4515 | * | |
4516 | * This function is used to enable interrupts at runtime, both in the runtime | |
4517 | * pm and the system suspend/resume code. | |
4518 | */ | |
b963291c | 4519 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4520 | { |
2aeb7d3a | 4521 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4522 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4523 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4524 | } |