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drm/i915: Error checks in gen6_set_rps
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
9270388e
DV		 299/* defined intel_pm.c */
300extern spinlock_t mchdev_lock;
301
73edd18f 302static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 303{
304 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 305 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 306 u8 new_delay;
307 unsigned long flags;
308
309 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 310
73edd18f
DV		 311 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
312
20e4d407 313 new_delay = dev_priv->ips.cur_delay;
9270388e 314
7648fa99 315 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 316 busy_up = I915_READ(RCPREVBSYTUPAVG);
317 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 318 max_avg = I915_READ(RCBMAXAVG);
319 min_avg = I915_READ(RCBMINAVG);
320
321 /* Handle RCS change request from hw */
b5b72e89 322 if (busy_up > max_avg) {
20e4d407
DV		 323 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
324 new_delay = dev_priv->ips.cur_delay - 1;
325 if (new_delay < dev_priv->ips.max_delay)
326 new_delay = dev_priv->ips.max_delay;
b5b72e89 327 } else if (busy_down < min_avg) {
20e4d407
DV		 328 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
329 new_delay = dev_priv->ips.cur_delay + 1;
330 if (new_delay > dev_priv->ips.min_delay)
331 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 332 }
333
7648fa99 334 if (ironlake_set_drps(dev, new_delay))
20e4d407 335 dev_priv->ips.cur_delay = new_delay;
f97108d1 336
9270388e
DV		 337 spin_unlock_irqrestore(&mchdev_lock, flags);
338
f97108d1
JB		 339 return;
340}
341
549f7365
CW		 342static void notify_ring(struct drm_device *dev,
343 struct intel_ring_buffer *ring)
344{
345 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 346
475553de
CW		 347 if (ring->obj == NULL)
348 return;
349
b2eadbc8 350 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 351
549f7365 352 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 353 if (i915_enable_hangcheck) {
354 dev_priv->hangcheck_count = 0;
355 mod_timer(&dev_priv->hangcheck_timer,
356 jiffies +
357 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
358 }
549f7365
CW		 359}
360
4912d041 361static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 362{
4912d041 363 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 364 rps.work);
4912d041 365 u32 pm_iir, pm_imr;
7b9e0ae6 366 u8 new_delay;
4912d041 367
c6a828d3
DV		 368 spin_lock_irq(&dev_priv->rps.lock);
369 pm_iir = dev_priv->rps.pm_iir;
370 dev_priv->rps.pm_iir = 0;
4912d041 371 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 372 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 373 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 374
7b9e0ae6 375 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 376 return;
377
4912d041 378 mutex_lock(&dev_priv->dev->struct_mutex);
7b9e0ae6
CW		 379
380 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 381 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 382 else
c6a828d3 383 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 384
79249636
BW		 385 /* sysfs frequency interfaces may have snuck in while servicing the
386 * interrupt
387 */
388 if (!(new_delay > dev_priv->rps.max_delay ||
389 new_delay < dev_priv->rps.min_delay)) {
390 gen6_set_rps(dev_priv->dev, new_delay);
391 }
3b8d8d91 392
4912d041 393 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 394}
395
e3689190
BW		 396
397/**
398 * ivybridge_parity_work - Workqueue called when a parity error interrupt
399 * occurred.
400 * @work: workqueue struct
401 *
402 * Doesn't actually do anything except notify userspace. As a consequence of
403 * this event, userspace should try to remap the bad rows since statistically
404 * it is likely the same row is more likely to go bad again.
405 */
406static void ivybridge_parity_work(struct work_struct *work)
407{
408 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
409 parity_error_work);
410 u32 error_status, row, bank, subbank;
411 char *parity_event[5];
412 uint32_t misccpctl;
413 unsigned long flags;
414
415 /* We must turn off DOP level clock gating to access the L3 registers.
416 * In order to prevent a get/put style interface, acquire struct mutex
417 * any time we access those registers.
418 */
419 mutex_lock(&dev_priv->dev->struct_mutex);
420
421 misccpctl = I915_READ(GEN7_MISCCPCTL);
422 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
423 POSTING_READ(GEN7_MISCCPCTL);
424
425 error_status = I915_READ(GEN7_L3CDERRST1);
426 row = GEN7_PARITY_ERROR_ROW(error_status);
427 bank = GEN7_PARITY_ERROR_BANK(error_status);
428 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
429
430 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
431 GEN7_L3CDERRST1_ENABLE);
432 POSTING_READ(GEN7_L3CDERRST1);
433
434 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
435
436 spin_lock_irqsave(&dev_priv->irq_lock, flags);
437 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
438 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
439 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
440
441 mutex_unlock(&dev_priv->dev->struct_mutex);
442
443 parity_event[0] = "L3_PARITY_ERROR=1";
444 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
445 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
446 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
447 parity_event[4] = NULL;
448
449 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
450 KOBJ_CHANGE, parity_event);
451
452 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
453 row, bank, subbank);
454
455 kfree(parity_event[3]);
456 kfree(parity_event[2]);
457 kfree(parity_event[1]);
458}
459
d2ba8470 460static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 461{
462 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
463 unsigned long flags;
464
e1ef7cc2 465 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 466 return;
467
468 spin_lock_irqsave(&dev_priv->irq_lock, flags);
469 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
470 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
471 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
472
473 queue_work(dev_priv->wq, &dev_priv->parity_error_work);
474}
475
e7b4c6b1
DV		 476static void snb_gt_irq_handler(struct drm_device *dev,
477 struct drm_i915_private *dev_priv,
478 u32 gt_iir)
479{
480
481 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
482 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
483 notify_ring(dev, &dev_priv->ring[RCS]);
484 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
485 notify_ring(dev, &dev_priv->ring[VCS]);
486 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
487 notify_ring(dev, &dev_priv->ring[BCS]);
488
489 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
490 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
491 GT_RENDER_CS_ERROR_INTERRUPT)) {
492 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
493 i915_handle_error(dev, false);
494 }
e3689190
BW		 495
496 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
497 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 498}
499
fc6826d1
CW		 500static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
501 u32 pm_iir)
502{
503 unsigned long flags;
504
505 /*
506 * IIR bits should never already be set because IMR should
507 * prevent an interrupt from being shown in IIR. The warning
508 * displays a case where we've unsafely cleared
c6a828d3 509 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 510 * type is not a problem, it displays a problem in the logic.
511 *
c6a828d3 512 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 513 */
514
c6a828d3 515 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 516 dev_priv->rps.pm_iir |= pm_iir;
517 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 518 POSTING_READ(GEN6_PMIMR);
c6a828d3 519 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 520
c6a828d3 521 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 522}
523
7e231dbe
JB		 524static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
525{
526 struct drm_device *dev = (struct drm_device *) arg;
527 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
528 u32 iir, gt_iir, pm_iir;
529 irqreturn_t ret = IRQ_NONE;
530 unsigned long irqflags;
531 int pipe;
532 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 533 bool blc_event;
534
535 atomic_inc(&dev_priv->irq_received);
536
7e231dbe
JB		 537 while (true) {
538 iir = I915_READ(VLV_IIR);
539 gt_iir = I915_READ(GTIIR);
540 pm_iir = I915_READ(GEN6_PMIIR);
541
542 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
543 goto out;
544
545 ret = IRQ_HANDLED;
546
e7b4c6b1 547 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 548
549 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
550 for_each_pipe(pipe) {
551 int reg = PIPESTAT(pipe);
552 pipe_stats[pipe] = I915_READ(reg);
553
554 /*
555 * Clear the PIPE*STAT regs before the IIR
556 */
557 if (pipe_stats[pipe] & 0x8000ffff) {
558 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
559 DRM_DEBUG_DRIVER("pipe %c underrun\n",
560 pipe_name(pipe));
561 I915_WRITE(reg, pipe_stats[pipe]);
562 }
563 }
564 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
565
31acc7f5
JB		 566 for_each_pipe(pipe) {
567 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
568 drm_handle_vblank(dev, pipe);
569
570 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
571 intel_prepare_page_flip(dev, pipe);
572 intel_finish_page_flip(dev, pipe);
573 }
574 }
575
7e231dbe
JB		 576 /* Consume port. Then clear IIR or we'll miss events */
577 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
578 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
579
580 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
581 hotplug_status);
582 if (hotplug_status & dev_priv->hotplug_supported_mask)
583 queue_work(dev_priv->wq,
584 &dev_priv->hotplug_work);
585
586 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
587 I915_READ(PORT_HOTPLUG_STAT);
588 }
589
7e231dbe
JB		 590 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
591 blc_event = true;
592
fc6826d1
CW		 593 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
594 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 595
596 I915_WRITE(GTIIR, gt_iir);
597 I915_WRITE(GEN6_PMIIR, pm_iir);
598 I915_WRITE(VLV_IIR, iir);
599 }
600
601out:
602 return ret;
603}
604
23e81d69 605static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 606{
607 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 608 int pipe;
776ad806 609
776ad806
JB		 610 if (pch_iir & SDE_AUDIO_POWER_MASK)
611 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
612 (pch_iir & SDE_AUDIO_POWER_MASK) >>
613 SDE_AUDIO_POWER_SHIFT);
614
615 if (pch_iir & SDE_GMBUS)
616 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
617
618 if (pch_iir & SDE_AUDIO_HDCP_MASK)
619 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
620
621 if (pch_iir & SDE_AUDIO_TRANS_MASK)
622 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
623
624 if (pch_iir & SDE_POISON)
625 DRM_ERROR("PCH poison interrupt\n");
626
9db4a9c7
JB		 627 if (pch_iir & SDE_FDI_MASK)
628 for_each_pipe(pipe)
629 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
630 pipe_name(pipe),
631 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 632
633 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
634 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
635
636 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
637 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
638
639 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
640 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
641 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
642 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
643}
644
23e81d69
AJ		 645static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
646{
647 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
648 int pipe;
649
650 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
651 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
652 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
653 SDE_AUDIO_POWER_SHIFT_CPT);
654
655 if (pch_iir & SDE_AUX_MASK_CPT)
656 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
657
658 if (pch_iir & SDE_GMBUS_CPT)
659 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
660
661 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
662 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
663
664 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
665 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
666
667 if (pch_iir & SDE_FDI_MASK_CPT)
668 for_each_pipe(pipe)
669 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
670 pipe_name(pipe),
671 I915_READ(FDI_RX_IIR(pipe)));
672}
673
f71d4af4 674static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 675{
676 struct drm_device *dev = (struct drm_device *) arg;
677 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 678 u32 de_iir, gt_iir, de_ier, pm_iir;
679 irqreturn_t ret = IRQ_NONE;
680 int i;
b1f14ad0
JB		 681
682 atomic_inc(&dev_priv->irq_received);
683
684 /* disable master interrupt before clearing iir */
685 de_ier = I915_READ(DEIER);
686 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 687
b1f14ad0 688 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 689 if (gt_iir) {
690 snb_gt_irq_handler(dev, dev_priv, gt_iir);
691 I915_WRITE(GTIIR, gt_iir);
692 ret = IRQ_HANDLED;
b1f14ad0
JB		 693 }
694
0e43406b
CW		 695 de_iir = I915_READ(DEIIR);
696 if (de_iir) {
697 if (de_iir & DE_GSE_IVB)
698 intel_opregion_gse_intr(dev);
699
700 for (i = 0; i < 3; i++) {
701 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
702 intel_prepare_page_flip(dev, i);
703 intel_finish_page_flip_plane(dev, i);
704 }
705 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
706 drm_handle_vblank(dev, i);
707 }
b615b57a 708
0e43406b
CW		 709 /* check event from PCH */
710 if (de_iir & DE_PCH_EVENT_IVB) {
711 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 712
0e43406b
CW		 713 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
714 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
23e81d69 715 cpt_irq_handler(dev, pch_iir);
b1f14ad0 716
0e43406b
CW		 717 /* clear PCH hotplug event before clear CPU irq */
718 I915_WRITE(SDEIIR, pch_iir);
719 }
b615b57a 720
0e43406b
CW		 721 I915_WRITE(DEIIR, de_iir);
722 ret = IRQ_HANDLED;
b1f14ad0
JB		 723 }
724
0e43406b
CW		 725 pm_iir = I915_READ(GEN6_PMIIR);
726 if (pm_iir) {
727 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
728 gen6_queue_rps_work(dev_priv, pm_iir);
729 I915_WRITE(GEN6_PMIIR, pm_iir);
730 ret = IRQ_HANDLED;
731 }
b1f14ad0 732
b1f14ad0
JB		 733 I915_WRITE(DEIER, de_ier);
734 POSTING_READ(DEIER);
735
736 return ret;
737}
738
e7b4c6b1
DV		 739static void ilk_gt_irq_handler(struct drm_device *dev,
740 struct drm_i915_private *dev_priv,
741 u32 gt_iir)
742{
743 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
744 notify_ring(dev, &dev_priv->ring[RCS]);
745 if (gt_iir & GT_BSD_USER_INTERRUPT)
746 notify_ring(dev, &dev_priv->ring[VCS]);
747}
748
f71d4af4 749static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 750{
4697995b 751 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 752 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
753 int ret = IRQ_NONE;
3b8d8d91 754 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 755 u32 hotplug_mask;
881f47b6 756
4697995b
JB		 757 atomic_inc(&dev_priv->irq_received);
758
2d109a84
ZN		 759 /* disable master interrupt before clearing iir */
760 de_ier = I915_READ(DEIER);
761 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 762 POSTING_READ(DEIER);
2d109a84 763
036a4a7d
ZW		 764 de_iir = I915_READ(DEIIR);
765 gt_iir = I915_READ(GTIIR);
c650156a 766 pch_iir = I915_READ(SDEIIR);
3b8d8d91 767 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 768
3b8d8d91
JB		 769 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
770 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 771 goto done;
036a4a7d 772
2d7b8366
YL		 773 if (HAS_PCH_CPT(dev))
774 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
775 else
776 hotplug_mask = SDE_HOTPLUG_MASK;
777
c7c85101 778 ret = IRQ_HANDLED;
036a4a7d 779
e7b4c6b1
DV		 780 if (IS_GEN5(dev))
781 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
782 else
783 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 784
c7c85101 785 if (de_iir & DE_GSE)
3b617967 786 intel_opregion_gse_intr(dev);
c650156a 787
f072d2e7 788 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 789 intel_prepare_page_flip(dev, 0);
2bbda389 790 intel_finish_page_flip_plane(dev, 0);
f072d2e7 791 }
013d5aa2 792
f072d2e7 793 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 794 intel_prepare_page_flip(dev, 1);
2bbda389 795 intel_finish_page_flip_plane(dev, 1);
f072d2e7 796 }
013d5aa2 797
f072d2e7 798 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 799 drm_handle_vblank(dev, 0);
800
f072d2e7 801 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 802 drm_handle_vblank(dev, 1);
803
c7c85101 804 /* check event from PCH */
776ad806
JB		 805 if (de_iir & DE_PCH_EVENT) {
806 if (pch_iir & hotplug_mask)
807 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
23e81d69
AJ		 808 if (HAS_PCH_CPT(dev))
809 cpt_irq_handler(dev, pch_iir);
810 else
811 ibx_irq_handler(dev, pch_iir);
776ad806 812 }
036a4a7d 813
73edd18f
DV		 814 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
815 ironlake_handle_rps_change(dev);
f97108d1 816
fc6826d1
CW		 817 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
818 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 819
c7c85101
ZN		 820 /* should clear PCH hotplug event before clear CPU irq */
821 I915_WRITE(SDEIIR, pch_iir);
822 I915_WRITE(GTIIR, gt_iir);
823 I915_WRITE(DEIIR, de_iir);
4912d041 824 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 825
826done:
2d109a84 827 I915_WRITE(DEIER, de_ier);
3143a2bf 828 POSTING_READ(DEIER);
2d109a84 829
036a4a7d
ZW		 830 return ret;
831}
832
8a905236
JB		 833/**
834 * i915_error_work_func - do process context error handling work
835 * @work: work struct
836 *
837 * Fire an error uevent so userspace can see that a hang or error
838 * was detected.
839 */
840static void i915_error_work_func(struct work_struct *work)
841{
842 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
843 error_work);
844 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 845 char *error_event[] = { "ERROR=1", NULL };
846 char *reset_event[] = { "RESET=1", NULL };
847 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 848
f316a42c
BG		 849 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
850
ba1234d1 851 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 852 DRM_DEBUG_DRIVER("resetting chip\n");
853 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 854 if (!i915_reset(dev)) {
f803aa55
CW		 855 atomic_set(&dev_priv->mm.wedged, 0);
856 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 857 }
30dbf0c0 858 complete_all(&dev_priv->error_completion);
f316a42c 859 }
8a905236
JB		 860}
861
85f9e50d
DV		 862/* NB: please notice the memset */
863static void i915_get_extra_instdone(struct drm_device *dev,
864 uint32_t *instdone)
865{
866 struct drm_i915_private *dev_priv = dev->dev_private;
867 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
868
869 switch(INTEL_INFO(dev)->gen) {
870 case 2:
871 case 3:
872 instdone[0] = I915_READ(INSTDONE);
873 break;
874 case 4:
875 case 5:
876 case 6:
877 instdone[0] = I915_READ(INSTDONE_I965);
878 instdone[1] = I915_READ(INSTDONE1);
879 break;
880 default:
881 WARN_ONCE(1, "Unsupported platform\n");
882 case 7:
883 instdone[0] = I915_READ(GEN7_INSTDONE_1);
884 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
885 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
886 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
887 break;
888 }
889}
890
3bd3c932 891#ifdef CONFIG_DEBUG_FS
9df30794 892static struct drm_i915_error_object *
bcfb2e28 893i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 894 struct drm_i915_gem_object *src)
9df30794
CW		 895{
896 struct drm_i915_error_object *dst;
9da3da66 897 int i, count;
e56660dd 898 u32 reloc_offset;
9df30794 899
05394f39 900 if (src == NULL || src->pages == NULL)
9df30794
CW		 901 return NULL;
902
9da3da66 903 count = src->base.size / PAGE_SIZE;
9df30794 904
9da3da66 905 dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 906 if (dst == NULL)
907 return NULL;
908
05394f39 909 reloc_offset = src->gtt_offset;
9da3da66 910 for (i = 0; i < count; i++) {
788885ae 911 unsigned long flags;
e56660dd 912 void *d;
788885ae 913
e56660dd 914 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 915 if (d == NULL)
916 goto unwind;
e56660dd 917
788885ae 918 local_irq_save(flags);
74898d7e
DV		 919 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
920 src->has_global_gtt_mapping) {
172975aa
CW		 921 void __iomem *s;
922
923 /* Simply ignore tiling or any overlapping fence.
924 * It's part of the error state, and this hopefully
925 * captures what the GPU read.
926 */
927
928 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
929 reloc_offset);
930 memcpy_fromio(d, s, PAGE_SIZE);
931 io_mapping_unmap_atomic(s);
932 } else {
9da3da66 933 struct page *page;
172975aa
CW		 934 void *s;
935
9da3da66 936 page = i915_gem_object_get_page(src, i);
172975aa 937
9da3da66
CW		 938 drm_clflush_pages(&page, 1);
939
940 s = kmap_atomic(page);
172975aa
CW		 941 memcpy(d, s, PAGE_SIZE);
942 kunmap_atomic(s);
943
9da3da66 944 drm_clflush_pages(&page, 1);
172975aa 945 }
788885ae 946 local_irq_restore(flags);
e56660dd 947
9da3da66 948 dst->pages[i] = d;
e56660dd
CW		 949
950 reloc_offset += PAGE_SIZE;
9df30794 951 }
9da3da66 952 dst->page_count = count;
05394f39 953 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 954
955 return dst;
956
957unwind:
9da3da66
CW		 958 while (i--)
959 kfree(dst->pages[i]);
9df30794
CW		 960 kfree(dst);
961 return NULL;
962}
963
964static void
965i915_error_object_free(struct drm_i915_error_object *obj)
966{
967 int page;
968
969 if (obj == NULL)
970 return;
971
972 for (page = 0; page < obj->page_count; page++)
973 kfree(obj->pages[page]);
974
975 kfree(obj);
976}
977
742cbee8
DV		 978void
979i915_error_state_free(struct kref *error_ref)
9df30794 980{
742cbee8
DV		 981 struct drm_i915_error_state *error = container_of(error_ref,
982 typeof(*error), ref);
e2f973d5
CW		 983 int i;
984
52d39a21
CW		 985 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
986 i915_error_object_free(error->ring[i].batchbuffer);
987 i915_error_object_free(error->ring[i].ringbuffer);
988 kfree(error->ring[i].requests);
989 }
e2f973d5 990
9df30794 991 kfree(error->active_bo);
6ef3d427 992 kfree(error->overlay);
9df30794
CW		 993 kfree(error);
994}
1b50247a
CW		 995static void capture_bo(struct drm_i915_error_buffer *err,
996 struct drm_i915_gem_object *obj)
997{
998 err->size = obj->base.size;
999 err->name = obj->base.name;
0201f1ec
CW		 1000 err->rseqno = obj->last_read_seqno;
1001 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1002 err->gtt_offset = obj->gtt_offset;
1003 err->read_domains = obj->base.read_domains;
1004 err->write_domain = obj->base.write_domain;
1005 err->fence_reg = obj->fence_reg;
1006 err->pinned = 0;
1007 if (obj->pin_count > 0)
1008 err->pinned = 1;
1009 if (obj->user_pin_count > 0)
1010 err->pinned = -1;
1011 err->tiling = obj->tiling_mode;
1012 err->dirty = obj->dirty;
1013 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1014 err->ring = obj->ring ? obj->ring->id : -1;
1015 err->cache_level = obj->cache_level;
1016}
9df30794 1017
1b50247a
CW		 1018static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1019 int count, struct list_head *head)
c724e8a9
CW		 1020{
1021 struct drm_i915_gem_object *obj;
1022 int i = 0;
1023
1024 list_for_each_entry(obj, head, mm_list) {
1b50247a 1025 capture_bo(err++, obj);
c724e8a9
CW		 1026 if (++i == count)
1027 break;
1b50247a
CW		 1028 }
1029
1030 return i;
1031}
1032
1033static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1034 int count, struct list_head *head)
1035{
1036 struct drm_i915_gem_object *obj;
1037 int i = 0;
1038
1039 list_for_each_entry(obj, head, gtt_list) {
1040 if (obj->pin_count == 0)
1041 continue;
c724e8a9 1042
1b50247a
CW		 1043 capture_bo(err++, obj);
1044 if (++i == count)
1045 break;
c724e8a9
CW		 1046 }
1047
1048 return i;
1049}
1050
748ebc60
CW		 1051static void i915_gem_record_fences(struct drm_device *dev,
1052 struct drm_i915_error_state *error)
1053{
1054 struct drm_i915_private *dev_priv = dev->dev_private;
1055 int i;
1056
1057 /* Fences */
1058 switch (INTEL_INFO(dev)->gen) {
775d17b6 1059 case 7:
748ebc60
CW		 1060 case 6:
1061 for (i = 0; i < 16; i++)
1062 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1063 break;
1064 case 5:
1065 case 4:
1066 for (i = 0; i < 16; i++)
1067 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1068 break;
1069 case 3:
1070 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1071 for (i = 0; i < 8; i++)
1072 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1073 case 2:
1074 for (i = 0; i < 8; i++)
1075 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1076 break;
1077
1078 }
1079}
1080
bcfb2e28
CW		 1081static struct drm_i915_error_object *
1082i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1083 struct intel_ring_buffer *ring)
1084{
1085 struct drm_i915_gem_object *obj;
1086 u32 seqno;
1087
1088 if (!ring->get_seqno)
1089 return NULL;
1090
b2eadbc8 1091 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1092 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1093 if (obj->ring != ring)
1094 continue;
1095
0201f1ec 1096 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1097 continue;
1098
1099 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1100 continue;
1101
1102 /* We need to copy these to an anonymous buffer as the simplest
1103 * method to avoid being overwritten by userspace.
1104 */
1105 return i915_error_object_create(dev_priv, obj);
1106 }
1107
1108 return NULL;
1109}
1110
d27b1e0e
DV		 1111static void i915_record_ring_state(struct drm_device *dev,
1112 struct drm_i915_error_state *error,
1113 struct intel_ring_buffer *ring)
1114{
1115 struct drm_i915_private *dev_priv = dev->dev_private;
1116
33f3f518 1117 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1118 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1119 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1120 error->semaphore_mboxes[ring->id][0]
1121 = I915_READ(RING_SYNC_0(ring->mmio_base));
1122 error->semaphore_mboxes[ring->id][1]
1123 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1124 }
c1cd90ed 1125
d27b1e0e 1126 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1127 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1128 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1129 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1130 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1131 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1132 if (ring->id == RCS)
d27b1e0e 1133 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1134 } else {
9d2f41fa 1135 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1136 error->ipeir[ring->id] = I915_READ(IPEIR);
1137 error->ipehr[ring->id] = I915_READ(IPEHR);
1138 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1139 }
1140
9574b3fe 1141 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1142 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1143 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1144 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1145 error->head[ring->id] = I915_READ_HEAD(ring);
1146 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1147
1148 error->cpu_ring_head[ring->id] = ring->head;
1149 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1150}
1151
52d39a21
CW		 1152static void i915_gem_record_rings(struct drm_device *dev,
1153 struct drm_i915_error_state *error)
1154{
1155 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1156 struct intel_ring_buffer *ring;
52d39a21
CW		 1157 struct drm_i915_gem_request *request;
1158 int i, count;
1159
b4519513 1160 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1161 i915_record_ring_state(dev, error, ring);
1162
1163 error->ring[i].batchbuffer =
1164 i915_error_first_batchbuffer(dev_priv, ring);
1165
1166 error->ring[i].ringbuffer =
1167 i915_error_object_create(dev_priv, ring->obj);
1168
1169 count = 0;
1170 list_for_each_entry(request, &ring->request_list, list)
1171 count++;
1172
1173 error->ring[i].num_requests = count;
1174 error->ring[i].requests =
1175 kmalloc(count*sizeof(struct drm_i915_error_request),
1176 GFP_ATOMIC);
1177 if (error->ring[i].requests == NULL) {
1178 error->ring[i].num_requests = 0;
1179 continue;
1180 }
1181
1182 count = 0;
1183 list_for_each_entry(request, &ring->request_list, list) {
1184 struct drm_i915_error_request *erq;
1185
1186 erq = &error->ring[i].requests[count++];
1187 erq->seqno = request->seqno;
1188 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1189 erq->tail = request->tail;
52d39a21
CW		 1190 }
1191 }
1192}
1193
8a905236
JB		 1194/**
1195 * i915_capture_error_state - capture an error record for later analysis
1196 * @dev: drm device
1197 *
1198 * Should be called when an error is detected (either a hang or an error
1199 * interrupt) to capture error state from the time of the error. Fills
1200 * out a structure which becomes available in debugfs for user level tools
1201 * to pick up.
1202 */
63eeaf38
JB		 1203static void i915_capture_error_state(struct drm_device *dev)
1204{
1205 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1206 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1207 struct drm_i915_error_state *error;
1208 unsigned long flags;
9db4a9c7 1209 int i, pipe;
63eeaf38
JB		 1210
1211 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1212 error = dev_priv->first_error;
1213 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1214 if (error)
1215 return;
63eeaf38 1216
9db4a9c7 1217 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1218 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1219 if (!error) {
9df30794
CW		 1220 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1221 return;
63eeaf38
JB		 1222 }
1223
b6f7833b
CW		 1224 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1225 dev->primary->index);
2fa772f3 1226
742cbee8 1227 kref_init(&error->ref);
63eeaf38
JB		 1228 error->eir = I915_READ(EIR);
1229 error->pgtbl_er = I915_READ(PGTBL_ER);
b9a3906b 1230 error->ccid = I915_READ(CCID);
be998e2e
BW		 1231
1232 if (HAS_PCH_SPLIT(dev))
1233 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1234 else if (IS_VALLEYVIEW(dev))
1235 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1236 else if (IS_GEN2(dev))
1237 error->ier = I915_READ16(IER);
1238 else
1239 error->ier = I915_READ(IER);
1240
9db4a9c7
JB		 1241 for_each_pipe(pipe)
1242 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1243
33f3f518 1244 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1245 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1246 error->done_reg = I915_READ(DONE_REG);
1247 }
d27b1e0e 1248
71e172e8
BW		 1249 if (INTEL_INFO(dev)->gen == 7)
1250 error->err_int = I915_READ(GEN7_ERR_INT);
1251
050ee91f
BW		 1252 i915_get_extra_instdone(dev, error->extra_instdone);
1253
748ebc60 1254 i915_gem_record_fences(dev, error);
52d39a21 1255 i915_gem_record_rings(dev, error);
9df30794 1256
c724e8a9 1257 /* Record buffers on the active and pinned lists. */
9df30794 1258 error->active_bo = NULL;
c724e8a9 1259 error->pinned_bo = NULL;
9df30794 1260
bcfb2e28
CW		 1261 i = 0;
1262 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1263 i++;
1264 error->active_bo_count = i;
6c085a72 1265 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1266 if (obj->pin_count)
1267 i++;
bcfb2e28 1268 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1269
8e934dbf
CW		 1270 error->active_bo = NULL;
1271 error->pinned_bo = NULL;
bcfb2e28
CW		 1272 if (i) {
1273 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1274 GFP_ATOMIC);
c724e8a9
CW		 1275 if (error->active_bo)
1276 error->pinned_bo =
1277 error->active_bo + error->active_bo_count;
9df30794
CW		 1278 }
1279
c724e8a9
CW		 1280 if (error->active_bo)
1281 error->active_bo_count =
1b50247a
CW		 1282 capture_active_bo(error->active_bo,
1283 error->active_bo_count,
1284 &dev_priv->mm.active_list);
c724e8a9
CW		 1285
1286 if (error->pinned_bo)
1287 error->pinned_bo_count =
1b50247a
CW		 1288 capture_pinned_bo(error->pinned_bo,
1289 error->pinned_bo_count,
6c085a72 1290 &dev_priv->mm.bound_list);
c724e8a9 1291
9df30794
CW		 1292 do_gettimeofday(&error->time);
1293
6ef3d427 1294 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1295 error->display = intel_display_capture_error_state(dev);
6ef3d427 1296
9df30794
CW		 1297 spin_lock_irqsave(&dev_priv->error_lock, flags);
1298 if (dev_priv->first_error == NULL) {
1299 dev_priv->first_error = error;
1300 error = NULL;
1301 }
63eeaf38 1302 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1303
1304 if (error)
742cbee8 1305 i915_error_state_free(&error->ref);
9df30794
CW		 1306}
1307
1308void i915_destroy_error_state(struct drm_device *dev)
1309{
1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 struct drm_i915_error_state *error;
6dc0e816 1312 unsigned long flags;
9df30794 1313
6dc0e816 1314 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1315 error = dev_priv->first_error;
1316 dev_priv->first_error = NULL;
6dc0e816 1317 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1318
1319 if (error)
742cbee8 1320 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1321}
3bd3c932
CW		 1322#else
1323#define i915_capture_error_state(x)
1324#endif
63eeaf38 1325
35aed2e6 1326static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1327{
1328 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1329 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1330 u32 eir = I915_READ(EIR);
050ee91f 1331 int pipe, i;
8a905236 1332
35aed2e6
CW		 1333 if (!eir)
1334 return;
8a905236 1335
a70491cc 1336 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1337
bd9854f9
BW		 1338 i915_get_extra_instdone(dev, instdone);
1339
8a905236
JB		 1340 if (IS_G4X(dev)) {
1341 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1342 u32 ipeir = I915_READ(IPEIR_I965);
1343
a70491cc
JP		 1344 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1345 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1346 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1347 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1348 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1349 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1350 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1351 POSTING_READ(IPEIR_I965);
8a905236
JB		 1352 }
1353 if (eir & GM45_ERROR_PAGE_TABLE) {
1354 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1355 pr_err("page table error\n");
1356 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1357 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1358 POSTING_READ(PGTBL_ER);
8a905236
JB		 1359 }
1360 }
1361
a6c45cf0 1362 if (!IS_GEN2(dev)) {
8a905236
JB		 1363 if (eir & I915_ERROR_PAGE_TABLE) {
1364 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1365 pr_err("page table error\n");
1366 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1367 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1368 POSTING_READ(PGTBL_ER);
8a905236
JB		 1369 }
1370 }
1371
1372 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1373 pr_err("memory refresh error:\n");
9db4a9c7 1374 for_each_pipe(pipe)
a70491cc 1375 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1376 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1377 /* pipestat has already been acked */
1378 }
1379 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1380 pr_err("instruction error\n");
1381 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1382 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1383 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1384 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1385 u32 ipeir = I915_READ(IPEIR);
1386
a70491cc
JP		 1387 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1388 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1389 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1390 I915_WRITE(IPEIR, ipeir);
3143a2bf 1391 POSTING_READ(IPEIR);
8a905236
JB		 1392 } else {
1393 u32 ipeir = I915_READ(IPEIR_I965);
1394
a70491cc
JP		 1395 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1396 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1397 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1398 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1399 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1400 POSTING_READ(IPEIR_I965);
8a905236
JB		 1401 }
1402 }
1403
1404 I915_WRITE(EIR, eir);
3143a2bf 1405 POSTING_READ(EIR);
8a905236
JB		 1406 eir = I915_READ(EIR);
1407 if (eir) {
1408 /*
1409 * some errors might have become stuck,
1410 * mask them.
1411 */
1412 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1413 I915_WRITE(EMR, I915_READ(EMR) | eir);
1414 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1415 }
35aed2e6
CW		 1416}
1417
1418/**
1419 * i915_handle_error - handle an error interrupt
1420 * @dev: drm device
1421 *
1422 * Do some basic checking of regsiter state at error interrupt time and
1423 * dump it to the syslog. Also call i915_capture_error_state() to make
1424 * sure we get a record and make it available in debugfs. Fire a uevent
1425 * so userspace knows something bad happened (should trigger collection
1426 * of a ring dump etc.).
1427 */
527f9e90 1428void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1429{
1430 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1431 struct intel_ring_buffer *ring;
1432 int i;
35aed2e6
CW		 1433
1434 i915_capture_error_state(dev);
1435 i915_report_and_clear_eir(dev);
8a905236 1436
ba1234d1 1437 if (wedged) {
30dbf0c0 1438 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1439 atomic_set(&dev_priv->mm.wedged, 1);
1440
11ed50ec
BG		 1441 /*
1442 * Wakeup waiting processes so they don't hang
1443 */
b4519513
CW		 1444 for_each_ring(ring, dev_priv, i)
1445 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1446 }
1447
9c9fe1f8 1448 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1449}
1450
4e5359cd
SF		 1451static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1452{
1453 drm_i915_private_t *dev_priv = dev->dev_private;
1454 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1456 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1457 struct intel_unpin_work *work;
1458 unsigned long flags;
1459 bool stall_detected;
1460
1461 /* Ignore early vblank irqs */
1462 if (intel_crtc == NULL)
1463 return;
1464
1465 spin_lock_irqsave(&dev->event_lock, flags);
1466 work = intel_crtc->unpin_work;
1467
1468 if (work == NULL || work->pending || !work->enable_stall_check) {
1469 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1470 spin_unlock_irqrestore(&dev->event_lock, flags);
1471 return;
1472 }
1473
1474 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1475 obj = work->pending_flip_obj;
a6c45cf0 1476 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1477 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1478 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1479 obj->gtt_offset;
4e5359cd 1480 } else {
9db4a9c7 1481 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1482 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1483 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1484 crtc->x * crtc->fb->bits_per_pixel/8);
1485 }
1486
1487 spin_unlock_irqrestore(&dev->event_lock, flags);
1488
1489 if (stall_detected) {
1490 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1491 intel_prepare_page_flip(dev, intel_crtc->plane);
1492 }
1493}
1494
42f52ef8
KP		 1495/* Called from drm generic code, passed 'crtc' which
1496 * we use as a pipe index
1497 */
f71d4af4 1498static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1499{
1500 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1501 unsigned long irqflags;
71e0ffa5 1502
5eddb70b 1503 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1504 return -EINVAL;
0a3e67a4 1505
1ec14ad3 1506 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1507 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1508 i915_enable_pipestat(dev_priv, pipe,
1509 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1510 else
7c463586
KP		 1511 i915_enable_pipestat(dev_priv, pipe,
1512 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1513
1514 /* maintain vblank delivery even in deep C-states */
1515 if (dev_priv->info->gen == 3)
6b26c86d 1516 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1517 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1518
0a3e67a4
JB		 1519 return 0;
1520}
1521
f71d4af4 1522static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1523{
1524 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1525 unsigned long irqflags;
1526
1527 if (!i915_pipe_enabled(dev, pipe))
1528 return -EINVAL;
1529
1530 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1531 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1532 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1533 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1534
1535 return 0;
1536}
1537
f71d4af4 1538static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1539{
1540 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1541 unsigned long irqflags;
1542
1543 if (!i915_pipe_enabled(dev, pipe))
1544 return -EINVAL;
1545
1546 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1547 ironlake_enable_display_irq(dev_priv,
1548 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1549 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1550
1551 return 0;
1552}
1553
7e231dbe
JB		 1554static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1555{
1556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1557 unsigned long irqflags;
31acc7f5 1558 u32 imr;
7e231dbe
JB		 1559
1560 if (!i915_pipe_enabled(dev, pipe))
1561 return -EINVAL;
1562
1563 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1564 imr = I915_READ(VLV_IMR);
31acc7f5 1565 if (pipe == 0)
7e231dbe 1566 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1567 else
7e231dbe 1568 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1569 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1570 i915_enable_pipestat(dev_priv, pipe,
1571 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1572 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1573
1574 return 0;
1575}
1576
42f52ef8
KP		 1577/* Called from drm generic code, passed 'crtc' which
1578 * we use as a pipe index
1579 */
f71d4af4 1580static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1581{
1582 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1583 unsigned long irqflags;
0a3e67a4 1584
1ec14ad3 1585 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1586 if (dev_priv->info->gen == 3)
6b26c86d 1587 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1588
f796cf8f
JB		 1589 i915_disable_pipestat(dev_priv, pipe,
1590 PIPE_VBLANK_INTERRUPT_ENABLE |
1591 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1592 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1593}
1594
f71d4af4 1595static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1596{
1597 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1598 unsigned long irqflags;
1599
1600 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1601 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1602 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1603 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1604}
1605
f71d4af4 1606static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1607{
1608 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1609 unsigned long irqflags;
1610
1611 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1612 ironlake_disable_display_irq(dev_priv,
1613 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1614 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1615}
1616
7e231dbe
JB		 1617static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1618{
1619 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1620 unsigned long irqflags;
31acc7f5 1621 u32 imr;
7e231dbe
JB		 1622
1623 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1624 i915_disable_pipestat(dev_priv, pipe,
1625 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1626 imr = I915_READ(VLV_IMR);
31acc7f5 1627 if (pipe == 0)
7e231dbe 1628 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1629 else
7e231dbe 1630 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1631 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1632 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1633}
1634
893eead0
CW		 1635static u32
1636ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1637{
893eead0
CW		 1638 return list_entry(ring->request_list.prev,
1639 struct drm_i915_gem_request, list)->seqno;
1640}
1641
1642static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1643{
1644 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1645 i915_seqno_passed(ring->get_seqno(ring, false),
1646 ring_last_seqno(ring))) {
893eead0 1647 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1648 if (waitqueue_active(&ring->irq_queue)) {
1649 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1650 ring->name);
893eead0
CW		 1651 wake_up_all(&ring->irq_queue);
1652 *err = true;
1653 }
1654 return true;
1655 }
1656 return false;
f65d9421
BG		 1657}
1658
1ec14ad3
CW		 1659static bool kick_ring(struct intel_ring_buffer *ring)
1660{
1661 struct drm_device *dev = ring->dev;
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663 u32 tmp = I915_READ_CTL(ring);
1664 if (tmp & RING_WAIT) {
1665 DRM_ERROR("Kicking stuck wait on %s\n",
1666 ring->name);
1667 I915_WRITE_CTL(ring, tmp);
1668 return true;
1669 }
1ec14ad3
CW		 1670 return false;
1671}
1672
d1e61e7f
CW		 1673static bool i915_hangcheck_hung(struct drm_device *dev)
1674{
1675 drm_i915_private_t *dev_priv = dev->dev_private;
1676
1677 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1678 bool hung = true;
1679
d1e61e7f
CW		 1680 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1681 i915_handle_error(dev, true);
1682
1683 if (!IS_GEN2(dev)) {
b4519513
CW		 1684 struct intel_ring_buffer *ring;
1685 int i;
1686
d1e61e7f
CW		 1687 /* Is the chip hanging on a WAIT_FOR_EVENT?
1688 * If so we can simply poke the RB_WAIT bit
1689 * and break the hang. This should work on
1690 * all but the second generation chipsets.
1691 */
b4519513
CW		 1692 for_each_ring(ring, dev_priv, i)
1693 hung &= !kick_ring(ring);
d1e61e7f
CW		 1694 }
1695
b4519513 1696 return hung;
d1e61e7f
CW		 1697 }
1698
1699 return false;
1700}
1701
f65d9421
BG		 1702/**
1703 * This is called when the chip hasn't reported back with completed
1704 * batchbuffers in a long time. The first time this is called we simply record
1705 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1706 * again, we assume the chip is wedged and try to fix it.
1707 */
1708void i915_hangcheck_elapsed(unsigned long data)
1709{
1710 struct drm_device *dev = (struct drm_device *)data;
1711 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 1712 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 1713 struct intel_ring_buffer *ring;
1714 bool err = false, idle;
1715 int i;
893eead0 1716
3e0dc6b0
BW		 1717 if (!i915_enable_hangcheck)
1718 return;
1719
b4519513
CW		 1720 memset(acthd, 0, sizeof(acthd));
1721 idle = true;
1722 for_each_ring(ring, dev_priv, i) {
1723 idle &= i915_hangcheck_ring_idle(ring, &err);
1724 acthd[i] = intel_ring_get_active_head(ring);
1725 }
1726
893eead0 1727 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1728 if (idle) {
d1e61e7f
CW		 1729 if (err) {
1730 if (i915_hangcheck_hung(dev))
1731 return;
1732
893eead0 1733 goto repeat;
d1e61e7f
CW		 1734 }
1735
1736 dev_priv->hangcheck_count = 0;
893eead0
CW		 1737 return;
1738 }
b9201c14 1739
bd9854f9 1740 i915_get_extra_instdone(dev, instdone);
b4519513 1741 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
050ee91f 1742 memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
d1e61e7f 1743 if (i915_hangcheck_hung(dev))
cbb465e7 1744 return;
cbb465e7
CW		 1745 } else {
1746 dev_priv->hangcheck_count = 0;
1747
b4519513 1748 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
050ee91f 1749 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
cbb465e7 1750 }
f65d9421 1751
893eead0 1752repeat:
f65d9421 1753 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1754 mod_timer(&dev_priv->hangcheck_timer,
1755 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1756}
1757
1da177e4
LT		 1758/* drm_dma.h hooks
1759*/
f71d4af4 1760static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1761{
1762 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1763
4697995b
JB		 1764 atomic_set(&dev_priv->irq_received, 0);
1765
036a4a7d 1766 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1767
036a4a7d
ZW		 1768 /* XXX hotplug from PCH */
1769
1770 I915_WRITE(DEIMR, 0xffffffff);
1771 I915_WRITE(DEIER, 0x0);
3143a2bf 1772 POSTING_READ(DEIER);
036a4a7d
ZW		 1773
1774 /* and GT */
1775 I915_WRITE(GTIMR, 0xffffffff);
1776 I915_WRITE(GTIER, 0x0);
3143a2bf 1777 POSTING_READ(GTIER);
c650156a
ZW		 1778
1779 /* south display irq */
1780 I915_WRITE(SDEIMR, 0xffffffff);
1781 I915_WRITE(SDEIER, 0x0);
3143a2bf 1782 POSTING_READ(SDEIER);
036a4a7d
ZW		 1783}
1784
7e231dbe
JB		 1785static void valleyview_irq_preinstall(struct drm_device *dev)
1786{
1787 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1788 int pipe;
1789
1790 atomic_set(&dev_priv->irq_received, 0);
1791
7e231dbe
JB		 1792 /* VLV magic */
1793 I915_WRITE(VLV_IMR, 0);
1794 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1795 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1796 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1797
7e231dbe
JB		 1798 /* and GT */
1799 I915_WRITE(GTIIR, I915_READ(GTIIR));
1800 I915_WRITE(GTIIR, I915_READ(GTIIR));
1801 I915_WRITE(GTIMR, 0xffffffff);
1802 I915_WRITE(GTIER, 0x0);
1803 POSTING_READ(GTIER);
1804
1805 I915_WRITE(DPINVGTT, 0xff);
1806
1807 I915_WRITE(PORT_HOTPLUG_EN, 0);
1808 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1809 for_each_pipe(pipe)
1810 I915_WRITE(PIPESTAT(pipe), 0xffff);
1811 I915_WRITE(VLV_IIR, 0xffffffff);
1812 I915_WRITE(VLV_IMR, 0xffffffff);
1813 I915_WRITE(VLV_IER, 0x0);
1814 POSTING_READ(VLV_IER);
1815}
1816
7fe0b973
KP		 1817/*
1818 * Enable digital hotplug on the PCH, and configure the DP short pulse
1819 * duration to 2ms (which is the minimum in the Display Port spec)
1820 *
1821 * This register is the same on all known PCH chips.
1822 */
1823
1824static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1825{
1826 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1827 u32 hotplug;
1828
1829 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1830 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1831 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1832 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1833 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1834 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1835}
1836
f71d4af4 1837static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1838{
1839 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1840 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1841 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1842 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1843 u32 render_irqs;
2d7b8366 1844 u32 hotplug_mask;
036a4a7d 1845
1ec14ad3 1846 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1847
1848 /* should always can generate irq */
1849 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1850 I915_WRITE(DEIMR, dev_priv->irq_mask);
1851 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1852 POSTING_READ(DEIER);
036a4a7d 1853
1ec14ad3 1854 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1855
1856 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1857 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1858
1ec14ad3
CW		 1859 if (IS_GEN6(dev))
1860 render_irqs =
1861 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1862 GEN6_BSD_USER_INTERRUPT |
1863 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1864 else
1865 render_irqs =
88f23b8f 1866 GT_USER_INTERRUPT |
c6df541c 1867 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1868 GT_BSD_USER_INTERRUPT;
1869 I915_WRITE(GTIER, render_irqs);
3143a2bf 1870 POSTING_READ(GTIER);
036a4a7d 1871
2d7b8366 1872 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1873 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1874 SDE_PORTB_HOTPLUG_CPT |
1875 SDE_PORTC_HOTPLUG_CPT |
1876 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1877 } else {
9035a97a
CW		 1878 hotplug_mask = (SDE_CRT_HOTPLUG |
1879 SDE_PORTB_HOTPLUG |
1880 SDE_PORTC_HOTPLUG |
1881 SDE_PORTD_HOTPLUG |
1882 SDE_AUX_MASK);
2d7b8366
YL		 1883 }
1884
1ec14ad3 1885 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1886
1887 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1888 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1889 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1890 POSTING_READ(SDEIER);
c650156a 1891
7fe0b973
KP		 1892 ironlake_enable_pch_hotplug(dev);
1893
f97108d1
JB		 1894 if (IS_IRONLAKE_M(dev)) {
1895 /* Clear & enable PCU event interrupts */
1896 I915_WRITE(DEIIR, DE_PCU_EVENT);
1897 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1898 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1899 }
1900
036a4a7d
ZW		 1901 return 0;
1902}
1903
f71d4af4 1904static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1905{
1906 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1907 /* enable kind of interrupts always enabled */
b615b57a
CW		 1908 u32 display_mask =
1909 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1910 DE_PLANEC_FLIP_DONE_IVB |
1911 DE_PLANEB_FLIP_DONE_IVB |
1912 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1913 u32 render_irqs;
1914 u32 hotplug_mask;
1915
b1f14ad0
JB		 1916 dev_priv->irq_mask = ~display_mask;
1917
1918 /* should always can generate irq */
1919 I915_WRITE(DEIIR, I915_READ(DEIIR));
1920 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1921 I915_WRITE(DEIER,
1922 display_mask |
1923 DE_PIPEC_VBLANK_IVB |
1924 DE_PIPEB_VBLANK_IVB |
1925 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1926 POSTING_READ(DEIER);
1927
15b9f80e 1928 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1929
1930 I915_WRITE(GTIIR, I915_READ(GTIIR));
1931 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1932
e2a1e2f0 1933 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 1934 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1935 I915_WRITE(GTIER, render_irqs);
1936 POSTING_READ(GTIER);
1937
1938 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1939 SDE_PORTB_HOTPLUG_CPT |
1940 SDE_PORTC_HOTPLUG_CPT |
1941 SDE_PORTD_HOTPLUG_CPT);
1942 dev_priv->pch_irq_mask = ~hotplug_mask;
1943
1944 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1945 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1946 I915_WRITE(SDEIER, hotplug_mask);
1947 POSTING_READ(SDEIER);
1948
7fe0b973
KP		 1949 ironlake_enable_pch_hotplug(dev);
1950
b1f14ad0
JB		 1951 return 0;
1952}
1953
7e231dbe
JB		 1954static int valleyview_irq_postinstall(struct drm_device *dev)
1955{
1956 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe
JB		 1957 u32 enable_mask;
1958 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
31acc7f5 1959 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
7e231dbe
JB		 1960 u16 msid;
1961
1962 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 1963 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1964 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1965 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 1966 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1967
31acc7f5
JB		 1968 /*
1969 *Leave vblank interrupts masked initially. enable/disable will
1970 * toggle them based on usage.
1971 */
1972 dev_priv->irq_mask = (~enable_mask) |
1973 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1974 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1975
7e231dbe
JB		 1976 dev_priv->pipestat[0] = 0;
1977 dev_priv->pipestat[1] = 0;
1978
7e231dbe
JB		 1979 /* Hack for broken MSIs on VLV */
1980 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1981 pci_read_config_word(dev->pdev, 0x98, &msid);
1982 msid &= 0xff; /* mask out delivery bits */
1983 msid |= (1<<14);
1984 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1985
1986 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1987 I915_WRITE(VLV_IER, enable_mask);
1988 I915_WRITE(VLV_IIR, 0xffffffff);
1989 I915_WRITE(PIPESTAT(0), 0xffff);
1990 I915_WRITE(PIPESTAT(1), 0xffff);
1991 POSTING_READ(VLV_IER);
1992
31acc7f5
JB		 1993 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1994 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1995
7e231dbe
JB		 1996 I915_WRITE(VLV_IIR, 0xffffffff);
1997 I915_WRITE(VLV_IIR, 0xffffffff);
1998
31acc7f5 1999 dev_priv->gt_irq_mask = ~0;
7e231dbe
JB		 2000
2001 I915_WRITE(GTIIR, I915_READ(GTIIR));
2002 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5
JB		 2003 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2004 I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
2005 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
2006 GT_GEN6_BLT_USER_INTERRUPT |
2007 GT_GEN6_BSD_USER_INTERRUPT |
2008 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
2009 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
2010 GT_PIPE_NOTIFY |
2011 GT_RENDER_CS_ERROR_INTERRUPT |
2012 GT_SYNC_STATUS |
2013 GT_USER_INTERRUPT);
7e231dbe
JB		 2014 POSTING_READ(GTIER);
2015
2016 /* ack & enable invalid PTE error interrupts */
2017#if 0 /* FIXME: add support to irq handler for checking these bits */
2018 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2019 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2020#endif
2021
2022 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2023#if 0 /* FIXME: check register definitions; some have moved */
2024 /* Note HDMI and DP share bits */
2025 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2026 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2027 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2028 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2029 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2030 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2031 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2032 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2033 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2034 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2035 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2036 hotplug_en |= CRT_HOTPLUG_INT_EN;
2037 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2038 }
2039#endif
2040
2041 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2042
2043 return 0;
2044}
2045
7e231dbe
JB		 2046static void valleyview_irq_uninstall(struct drm_device *dev)
2047{
2048 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2049 int pipe;
2050
2051 if (!dev_priv)
2052 return;
2053
7e231dbe
JB		 2054 for_each_pipe(pipe)
2055 I915_WRITE(PIPESTAT(pipe), 0xffff);
2056
2057 I915_WRITE(HWSTAM, 0xffffffff);
2058 I915_WRITE(PORT_HOTPLUG_EN, 0);
2059 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2060 for_each_pipe(pipe)
2061 I915_WRITE(PIPESTAT(pipe), 0xffff);
2062 I915_WRITE(VLV_IIR, 0xffffffff);
2063 I915_WRITE(VLV_IMR, 0xffffffff);
2064 I915_WRITE(VLV_IER, 0x0);
2065 POSTING_READ(VLV_IER);
2066}
2067
f71d4af4 2068static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2069{
2070 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2071
2072 if (!dev_priv)
2073 return;
2074
036a4a7d
ZW		 2075 I915_WRITE(HWSTAM, 0xffffffff);
2076
2077 I915_WRITE(DEIMR, 0xffffffff);
2078 I915_WRITE(DEIER, 0x0);
2079 I915_WRITE(DEIIR, I915_READ(DEIIR));
2080
2081 I915_WRITE(GTIMR, 0xffffffff);
2082 I915_WRITE(GTIER, 0x0);
2083 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2084
2085 I915_WRITE(SDEIMR, 0xffffffff);
2086 I915_WRITE(SDEIER, 0x0);
2087 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2088}
2089
a266c7d5 2090static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2091{
2092 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2093 int pipe;
91e3738e 2094
a266c7d5 2095 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2096
9db4a9c7
JB		 2097 for_each_pipe(pipe)
2098 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2099 I915_WRITE16(IMR, 0xffff);
2100 I915_WRITE16(IER, 0x0);
2101 POSTING_READ16(IER);
c2798b19
CW		 2102}
2103
2104static int i8xx_irq_postinstall(struct drm_device *dev)
2105{
2106 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2107
c2798b19
CW		 2108 dev_priv->pipestat[0] = 0;
2109 dev_priv->pipestat[1] = 0;
2110
2111 I915_WRITE16(EMR,
2112 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2113
2114 /* Unmask the interrupts that we always want on. */
2115 dev_priv->irq_mask =
2116 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2117 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2118 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2119 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2120 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2121 I915_WRITE16(IMR, dev_priv->irq_mask);
2122
2123 I915_WRITE16(IER,
2124 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2125 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2126 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2127 I915_USER_INTERRUPT);
2128 POSTING_READ16(IER);
2129
2130 return 0;
2131}
2132
2133static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2134{
2135 struct drm_device *dev = (struct drm_device *) arg;
2136 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2137 u16 iir, new_iir;
2138 u32 pipe_stats[2];
2139 unsigned long irqflags;
2140 int irq_received;
2141 int pipe;
2142 u16 flip_mask =
2143 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2144 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2145
2146 atomic_inc(&dev_priv->irq_received);
2147
2148 iir = I915_READ16(IIR);
2149 if (iir == 0)
2150 return IRQ_NONE;
2151
2152 while (iir & ~flip_mask) {
2153 /* Can't rely on pipestat interrupt bit in iir as it might
2154 * have been cleared after the pipestat interrupt was received.
2155 * It doesn't set the bit in iir again, but it still produces
2156 * interrupts (for non-MSI).
2157 */
2158 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2159 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2160 i915_handle_error(dev, false);
2161
2162 for_each_pipe(pipe) {
2163 int reg = PIPESTAT(pipe);
2164 pipe_stats[pipe] = I915_READ(reg);
2165
2166 /*
2167 * Clear the PIPE*STAT regs before the IIR
2168 */
2169 if (pipe_stats[pipe] & 0x8000ffff) {
2170 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2171 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2172 pipe_name(pipe));
2173 I915_WRITE(reg, pipe_stats[pipe]);
2174 irq_received = 1;
2175 }
2176 }
2177 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2178
2179 I915_WRITE16(IIR, iir & ~flip_mask);
2180 new_iir = I915_READ16(IIR); /* Flush posted writes */
2181
d05c617e 2182 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2183
2184 if (iir & I915_USER_INTERRUPT)
2185 notify_ring(dev, &dev_priv->ring[RCS]);
2186
2187 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2188 drm_handle_vblank(dev, 0)) {
2189 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2190 intel_prepare_page_flip(dev, 0);
2191 intel_finish_page_flip(dev, 0);
2192 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2193 }
2194 }
2195
2196 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2197 drm_handle_vblank(dev, 1)) {
2198 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2199 intel_prepare_page_flip(dev, 1);
2200 intel_finish_page_flip(dev, 1);
2201 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2202 }
2203 }
2204
2205 iir = new_iir;
2206 }
2207
2208 return IRQ_HANDLED;
2209}
2210
2211static void i8xx_irq_uninstall(struct drm_device * dev)
2212{
2213 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2214 int pipe;
2215
c2798b19
CW		 2216 for_each_pipe(pipe) {
2217 /* Clear enable bits; then clear status bits */
2218 I915_WRITE(PIPESTAT(pipe), 0);
2219 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2220 }
2221 I915_WRITE16(IMR, 0xffff);
2222 I915_WRITE16(IER, 0x0);
2223 I915_WRITE16(IIR, I915_READ16(IIR));
2224}
2225
a266c7d5
CW		 2226static void i915_irq_preinstall(struct drm_device * dev)
2227{
2228 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2229 int pipe;
2230
2231 atomic_set(&dev_priv->irq_received, 0);
2232
2233 if (I915_HAS_HOTPLUG(dev)) {
2234 I915_WRITE(PORT_HOTPLUG_EN, 0);
2235 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2236 }
2237
00d98ebd 2238 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2239 for_each_pipe(pipe)
2240 I915_WRITE(PIPESTAT(pipe), 0);
2241 I915_WRITE(IMR, 0xffffffff);
2242 I915_WRITE(IER, 0x0);
2243 POSTING_READ(IER);
2244}
2245
2246static int i915_irq_postinstall(struct drm_device *dev)
2247{
2248 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2249 u32 enable_mask;
a266c7d5 2250
a266c7d5
CW		 2251 dev_priv->pipestat[0] = 0;
2252 dev_priv->pipestat[1] = 0;
2253
38bde180
CW		 2254 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2255
2256 /* Unmask the interrupts that we always want on. */
2257 dev_priv->irq_mask =
2258 ~(I915_ASLE_INTERRUPT |
2259 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2260 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2261 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2262 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2263 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2264
2265 enable_mask =
2266 I915_ASLE_INTERRUPT |
2267 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2268 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2269 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2270 I915_USER_INTERRUPT;
2271
a266c7d5
CW		 2272 if (I915_HAS_HOTPLUG(dev)) {
2273 /* Enable in IER... */
2274 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2275 /* and unmask in IMR */
2276 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2277 }
2278
a266c7d5
CW		 2279 I915_WRITE(IMR, dev_priv->irq_mask);
2280 I915_WRITE(IER, enable_mask);
2281 POSTING_READ(IER);
2282
2283 if (I915_HAS_HOTPLUG(dev)) {
2284 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2285
a266c7d5
CW		 2286 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2287 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2288 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2289 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2290 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2291 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2292 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2293 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2294 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2295 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2296 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2297 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2298 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2299 }
2300
2301 /* Ignore TV since it's buggy */
2302
2303 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2304 }
2305
2306 intel_opregion_enable_asle(dev);
2307
2308 return 0;
2309}
2310
2311static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2312{
2313 struct drm_device *dev = (struct drm_device *) arg;
2314 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2315 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2316 unsigned long irqflags;
38bde180
CW		 2317 u32 flip_mask =
2318 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2319 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2320 u32 flip[2] = {
2321 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2322 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2323 };
2324 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2325
2326 atomic_inc(&dev_priv->irq_received);
2327
2328 iir = I915_READ(IIR);
38bde180
CW		 2329 do {
2330 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2331 bool blc_event = false;
a266c7d5
CW		 2332
2333 /* Can't rely on pipestat interrupt bit in iir as it might
2334 * have been cleared after the pipestat interrupt was received.
2335 * It doesn't set the bit in iir again, but it still produces
2336 * interrupts (for non-MSI).
2337 */
2338 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2339 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2340 i915_handle_error(dev, false);
2341
2342 for_each_pipe(pipe) {
2343 int reg = PIPESTAT(pipe);
2344 pipe_stats[pipe] = I915_READ(reg);
2345
38bde180 2346 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2347 if (pipe_stats[pipe] & 0x8000ffff) {
2348 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2349 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2350 pipe_name(pipe));
2351 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2352 irq_received = true;
a266c7d5
CW		 2353 }
2354 }
2355 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2356
2357 if (!irq_received)
2358 break;
2359
a266c7d5
CW		 2360 /* Consume port. Then clear IIR or we'll miss events */
2361 if ((I915_HAS_HOTPLUG(dev)) &&
2362 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2363 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2364
2365 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2366 hotplug_status);
2367 if (hotplug_status & dev_priv->hotplug_supported_mask)
2368 queue_work(dev_priv->wq,
2369 &dev_priv->hotplug_work);
2370
2371 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2372 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2373 }
2374
38bde180 2375 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2376 new_iir = I915_READ(IIR); /* Flush posted writes */
2377
a266c7d5
CW		 2378 if (iir & I915_USER_INTERRUPT)
2379 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2380
a266c7d5 2381 for_each_pipe(pipe) {
38bde180
CW		 2382 int plane = pipe;
2383 if (IS_MOBILE(dev))
2384 plane = !plane;
8291ee90 2385 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2386 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2387 if (iir & flip[plane]) {
2388 intel_prepare_page_flip(dev, plane);
2389 intel_finish_page_flip(dev, pipe);
2390 flip_mask &= ~flip[plane];
2391 }
a266c7d5
CW		 2392 }
2393
2394 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2395 blc_event = true;
2396 }
2397
a266c7d5
CW		 2398 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2399 intel_opregion_asle_intr(dev);
2400
2401 /* With MSI, interrupts are only generated when iir
2402 * transitions from zero to nonzero. If another bit got
2403 * set while we were handling the existing iir bits, then
2404 * we would never get another interrupt.
2405 *
2406 * This is fine on non-MSI as well, as if we hit this path
2407 * we avoid exiting the interrupt handler only to generate
2408 * another one.
2409 *
2410 * Note that for MSI this could cause a stray interrupt report
2411 * if an interrupt landed in the time between writing IIR and
2412 * the posting read. This should be rare enough to never
2413 * trigger the 99% of 100,000 interrupts test for disabling
2414 * stray interrupts.
2415 */
38bde180 2416 ret = IRQ_HANDLED;
a266c7d5 2417 iir = new_iir;
38bde180 2418 } while (iir & ~flip_mask);
a266c7d5 2419
d05c617e 2420 i915_update_dri1_breadcrumb(dev);
8291ee90 2421
a266c7d5
CW		 2422 return ret;
2423}
2424
2425static void i915_irq_uninstall(struct drm_device * dev)
2426{
2427 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2428 int pipe;
2429
a266c7d5
CW		 2430 if (I915_HAS_HOTPLUG(dev)) {
2431 I915_WRITE(PORT_HOTPLUG_EN, 0);
2432 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2433 }
2434
00d98ebd 2435 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2436 for_each_pipe(pipe) {
2437 /* Clear enable bits; then clear status bits */
a266c7d5 2438 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2439 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2440 }
a266c7d5
CW		 2441 I915_WRITE(IMR, 0xffffffff);
2442 I915_WRITE(IER, 0x0);
2443
a266c7d5
CW		 2444 I915_WRITE(IIR, I915_READ(IIR));
2445}
2446
2447static void i965_irq_preinstall(struct drm_device * dev)
2448{
2449 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2450 int pipe;
2451
2452 atomic_set(&dev_priv->irq_received, 0);
2453
adca4730
CW		 2454 I915_WRITE(PORT_HOTPLUG_EN, 0);
2455 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2456
2457 I915_WRITE(HWSTAM, 0xeffe);
2458 for_each_pipe(pipe)
2459 I915_WRITE(PIPESTAT(pipe), 0);
2460 I915_WRITE(IMR, 0xffffffff);
2461 I915_WRITE(IER, 0x0);
2462 POSTING_READ(IER);
2463}
2464
2465static int i965_irq_postinstall(struct drm_device *dev)
2466{
2467 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2468 u32 hotplug_en;
bbba0a97 2469 u32 enable_mask;
a266c7d5
CW		 2470 u32 error_mask;
2471
a266c7d5 2472 /* Unmask the interrupts that we always want on. */
bbba0a97 2473 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2474 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2475 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2476 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2477 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2478 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2479 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2480
2481 enable_mask = ~dev_priv->irq_mask;
2482 enable_mask |= I915_USER_INTERRUPT;
2483
2484 if (IS_G4X(dev))
2485 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2486
2487 dev_priv->pipestat[0] = 0;
2488 dev_priv->pipestat[1] = 0;
2489
a266c7d5
CW		 2490 /*
2491 * Enable some error detection, note the instruction error mask
2492 * bit is reserved, so we leave it masked.
2493 */
2494 if (IS_G4X(dev)) {
2495 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2496 GM45_ERROR_MEM_PRIV |
2497 GM45_ERROR_CP_PRIV |
2498 I915_ERROR_MEMORY_REFRESH);
2499 } else {
2500 error_mask = ~(I915_ERROR_PAGE_TABLE |
2501 I915_ERROR_MEMORY_REFRESH);
2502 }
2503 I915_WRITE(EMR, error_mask);
2504
2505 I915_WRITE(IMR, dev_priv->irq_mask);
2506 I915_WRITE(IER, enable_mask);
2507 POSTING_READ(IER);
2508
adca4730
CW		 2509 /* Note HDMI and DP share hotplug bits */
2510 hotplug_en = 0;
2511 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2512 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2513 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2514 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2515 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2516 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2517 if (IS_G4X(dev)) {
2518 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2519 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2520 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2521 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2522 } else {
2523 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2524 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2525 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2526 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2527 }
adca4730
CW		 2528 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2529 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2530
adca4730
CW		 2531 /* Programming the CRT detection parameters tends
2532 to generate a spurious hotplug event about three
2533 seconds later. So just do it once.
2534 */
2535 if (IS_G4X(dev))
2536 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2537 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2538 }
a266c7d5 2539
adca4730 2540 /* Ignore TV since it's buggy */
a266c7d5 2541
adca4730 2542 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2543
2544 intel_opregion_enable_asle(dev);
2545
2546 return 0;
2547}
2548
2549static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2550{
2551 struct drm_device *dev = (struct drm_device *) arg;
2552 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2553 u32 iir, new_iir;
2554 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2555 unsigned long irqflags;
2556 int irq_received;
2557 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2558
2559 atomic_inc(&dev_priv->irq_received);
2560
2561 iir = I915_READ(IIR);
2562
a266c7d5 2563 for (;;) {
2c8ba29f
CW		 2564 bool blc_event = false;
2565
a266c7d5
CW		 2566 irq_received = iir != 0;
2567
2568 /* Can't rely on pipestat interrupt bit in iir as it might
2569 * have been cleared after the pipestat interrupt was received.
2570 * It doesn't set the bit in iir again, but it still produces
2571 * interrupts (for non-MSI).
2572 */
2573 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2574 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2575 i915_handle_error(dev, false);
2576
2577 for_each_pipe(pipe) {
2578 int reg = PIPESTAT(pipe);
2579 pipe_stats[pipe] = I915_READ(reg);
2580
2581 /*
2582 * Clear the PIPE*STAT regs before the IIR
2583 */
2584 if (pipe_stats[pipe] & 0x8000ffff) {
2585 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2586 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2587 pipe_name(pipe));
2588 I915_WRITE(reg, pipe_stats[pipe]);
2589 irq_received = 1;
2590 }
2591 }
2592 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2593
2594 if (!irq_received)
2595 break;
2596
2597 ret = IRQ_HANDLED;
2598
2599 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2600 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2601 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2602
2603 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2604 hotplug_status);
2605 if (hotplug_status & dev_priv->hotplug_supported_mask)
2606 queue_work(dev_priv->wq,
2607 &dev_priv->hotplug_work);
2608
2609 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2610 I915_READ(PORT_HOTPLUG_STAT);
2611 }
2612
2613 I915_WRITE(IIR, iir);
2614 new_iir = I915_READ(IIR); /* Flush posted writes */
2615
a266c7d5
CW		 2616 if (iir & I915_USER_INTERRUPT)
2617 notify_ring(dev, &dev_priv->ring[RCS]);
2618 if (iir & I915_BSD_USER_INTERRUPT)
2619 notify_ring(dev, &dev_priv->ring[VCS]);
2620
4f7d1e79 2621 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2622 intel_prepare_page_flip(dev, 0);
a266c7d5 2623
4f7d1e79 2624 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2625 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2626
2627 for_each_pipe(pipe) {
2c8ba29f 2628 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2629 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2630 i915_pageflip_stall_check(dev, pipe);
2631 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2632 }
2633
2634 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2635 blc_event = true;
2636 }
2637
2638
2639 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2640 intel_opregion_asle_intr(dev);
2641
2642 /* With MSI, interrupts are only generated when iir
2643 * transitions from zero to nonzero. If another bit got
2644 * set while we were handling the existing iir bits, then
2645 * we would never get another interrupt.
2646 *
2647 * This is fine on non-MSI as well, as if we hit this path
2648 * we avoid exiting the interrupt handler only to generate
2649 * another one.
2650 *
2651 * Note that for MSI this could cause a stray interrupt report
2652 * if an interrupt landed in the time between writing IIR and
2653 * the posting read. This should be rare enough to never
2654 * trigger the 99% of 100,000 interrupts test for disabling
2655 * stray interrupts.
2656 */
2657 iir = new_iir;
2658 }
2659
d05c617e 2660 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2661
a266c7d5
CW		 2662 return ret;
2663}
2664
2665static void i965_irq_uninstall(struct drm_device * dev)
2666{
2667 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2668 int pipe;
2669
2670 if (!dev_priv)
2671 return;
2672
adca4730
CW		 2673 I915_WRITE(PORT_HOTPLUG_EN, 0);
2674 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2675
2676 I915_WRITE(HWSTAM, 0xffffffff);
2677 for_each_pipe(pipe)
2678 I915_WRITE(PIPESTAT(pipe), 0);
2679 I915_WRITE(IMR, 0xffffffff);
2680 I915_WRITE(IER, 0x0);
2681
2682 for_each_pipe(pipe)
2683 I915_WRITE(PIPESTAT(pipe),
2684 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2685 I915_WRITE(IIR, I915_READ(IIR));
2686}
2687
f71d4af4
JB		 2688void intel_irq_init(struct drm_device *dev)
2689{
8b2e326d
CW		 2690 struct drm_i915_private *dev_priv = dev->dev_private;
2691
2692 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2693 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
c6a828d3 2694 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
98fd81cd 2695 INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
8b2e326d 2696
f71d4af4
JB		 2697 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2698 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2699 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2700 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2701 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2702 }
2703
c3613de9
KP		 2704 if (drm_core_check_feature(dev, DRIVER_MODESET))
2705 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2706 else
2707 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2708 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2709
7e231dbe
JB		 2710 if (IS_VALLEYVIEW(dev)) {
2711 dev->driver->irq_handler = valleyview_irq_handler;
2712 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2713 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2714 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2715 dev->driver->enable_vblank = valleyview_enable_vblank;
2716 dev->driver->disable_vblank = valleyview_disable_vblank;
2717 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2718 /* Share pre & uninstall handlers with ILK/SNB */
2719 dev->driver->irq_handler = ivybridge_irq_handler;
2720 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2721 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2722 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2723 dev->driver->enable_vblank = ivybridge_enable_vblank;
2724 dev->driver->disable_vblank = ivybridge_disable_vblank;
7d4e146f
ED		 2725 } else if (IS_HASWELL(dev)) {
2726 /* Share interrupts handling with IVB */
2727 dev->driver->irq_handler = ivybridge_irq_handler;
2728 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2729 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2730 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2731 dev->driver->enable_vblank = ivybridge_enable_vblank;
2732 dev->driver->disable_vblank = ivybridge_disable_vblank;
f71d4af4
JB		 2733 } else if (HAS_PCH_SPLIT(dev)) {
2734 dev->driver->irq_handler = ironlake_irq_handler;
2735 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2736 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2737 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2738 dev->driver->enable_vblank = ironlake_enable_vblank;
2739 dev->driver->disable_vblank = ironlake_disable_vblank;
2740 } else {
c2798b19
CW		 2741 if (INTEL_INFO(dev)->gen == 2) {
2742 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2743 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2744 dev->driver->irq_handler = i8xx_irq_handler;
2745 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2746 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2747 /* IIR "flip pending" means done if this bit is set */
2748 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2749
a266c7d5
CW		 2750 dev->driver->irq_preinstall = i915_irq_preinstall;
2751 dev->driver->irq_postinstall = i915_irq_postinstall;
2752 dev->driver->irq_uninstall = i915_irq_uninstall;
2753 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2754 } else {
a266c7d5
CW		 2755 dev->driver->irq_preinstall = i965_irq_preinstall;
2756 dev->driver->irq_postinstall = i965_irq_postinstall;
2757 dev->driver->irq_uninstall = i965_irq_uninstall;
2758 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2759 }
f71d4af4
JB		 2760 dev->driver->enable_vblank = i915_enable_vblank;
2761 dev->driver->disable_vblank = i915_disable_vblank;
2762 }
2763}
Linux kernel - Deliverables
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