Commit | Line | Data |
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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/i915_drm.h> | |
1da177e4 | 35 | #include "i915_drv.h" |
1c5d22f7 | 36 | #include "i915_trace.h" |
79e53945 | 37 | #include "intel_drv.h" |
1da177e4 | 38 | |
036a4a7d | 39 | /* For display hotplug interrupt */ |
995b6762 | 40 | static void |
f2b115e6 | 41 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 42 | { |
1ec14ad3 CW |
43 | if ((dev_priv->irq_mask & mask) != 0) { |
44 | dev_priv->irq_mask &= ~mask; | |
45 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 46 | POSTING_READ(DEIMR); |
036a4a7d ZW |
47 | } |
48 | } | |
49 | ||
50 | static inline void | |
f2b115e6 | 51 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 52 | { |
1ec14ad3 CW |
53 | if ((dev_priv->irq_mask & mask) != mask) { |
54 | dev_priv->irq_mask |= mask; | |
55 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 56 | POSTING_READ(DEIMR); |
036a4a7d ZW |
57 | } |
58 | } | |
59 | ||
7c463586 KP |
60 | void |
61 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
62 | { | |
46c06a30 VS |
63 | u32 reg = PIPESTAT(pipe); |
64 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
7c463586 | 65 | |
46c06a30 VS |
66 | if ((pipestat & mask) == mask) |
67 | return; | |
68 | ||
69 | /* Enable the interrupt, clear any pending status */ | |
70 | pipestat |= mask | (mask >> 16); | |
71 | I915_WRITE(reg, pipestat); | |
72 | POSTING_READ(reg); | |
7c463586 KP |
73 | } |
74 | ||
75 | void | |
76 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
77 | { | |
46c06a30 VS |
78 | u32 reg = PIPESTAT(pipe); |
79 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
7c463586 | 80 | |
46c06a30 VS |
81 | if ((pipestat & mask) == 0) |
82 | return; | |
83 | ||
84 | pipestat &= ~mask; | |
85 | I915_WRITE(reg, pipestat); | |
86 | POSTING_READ(reg); | |
7c463586 KP |
87 | } |
88 | ||
01c66889 ZY |
89 | /** |
90 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
91 | */ | |
1ec14ad3 | 92 | void intel_enable_asle(struct drm_device *dev) |
01c66889 | 93 | { |
1ec14ad3 CW |
94 | drm_i915_private_t *dev_priv = dev->dev_private; |
95 | unsigned long irqflags; | |
96 | ||
7e231dbe JB |
97 | /* FIXME: opregion/asle for VLV */ |
98 | if (IS_VALLEYVIEW(dev)) | |
99 | return; | |
100 | ||
1ec14ad3 | 101 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 102 | |
c619eed4 | 103 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 104 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 105 | else { |
01c66889 | 106 | i915_enable_pipestat(dev_priv, 1, |
d874bcff | 107 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
a6c45cf0 | 108 | if (INTEL_INFO(dev)->gen >= 4) |
edcb49ca | 109 | i915_enable_pipestat(dev_priv, 0, |
d874bcff | 110 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca | 111 | } |
1ec14ad3 CW |
112 | |
113 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
114 | } |
115 | ||
0a3e67a4 JB |
116 | /** |
117 | * i915_pipe_enabled - check if a pipe is enabled | |
118 | * @dev: DRM device | |
119 | * @pipe: pipe to check | |
120 | * | |
121 | * Reading certain registers when the pipe is disabled can hang the chip. | |
122 | * Use this routine to make sure the PLL is running and the pipe is active | |
123 | * before reading such registers if unsure. | |
124 | */ | |
125 | static int | |
126 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
127 | { | |
128 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
702e7a56 PZ |
129 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
130 | pipe); | |
131 | ||
132 | return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE; | |
0a3e67a4 JB |
133 | } |
134 | ||
42f52ef8 KP |
135 | /* Called from drm generic code, passed a 'crtc', which |
136 | * we use as a pipe index | |
137 | */ | |
f71d4af4 | 138 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
139 | { |
140 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
141 | unsigned long high_frame; | |
142 | unsigned long low_frame; | |
5eddb70b | 143 | u32 high1, high2, low; |
0a3e67a4 JB |
144 | |
145 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 146 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 147 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
148 | return 0; |
149 | } | |
150 | ||
9db4a9c7 JB |
151 | high_frame = PIPEFRAME(pipe); |
152 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 153 | |
0a3e67a4 JB |
154 | /* |
155 | * High & low register fields aren't synchronized, so make sure | |
156 | * we get a low value that's stable across two reads of the high | |
157 | * register. | |
158 | */ | |
159 | do { | |
5eddb70b CW |
160 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
161 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; | |
162 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
163 | } while (high1 != high2); |
164 | ||
5eddb70b CW |
165 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
166 | low >>= PIPE_FRAME_LOW_SHIFT; | |
167 | return (high1 << 8) | low; | |
0a3e67a4 JB |
168 | } |
169 | ||
f71d4af4 | 170 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 JB |
171 | { |
172 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 173 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
174 | |
175 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 176 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 177 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
178 | return 0; |
179 | } | |
180 | ||
181 | return I915_READ(reg); | |
182 | } | |
183 | ||
f71d4af4 | 184 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
0af7e4df MK |
185 | int *vpos, int *hpos) |
186 | { | |
187 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
188 | u32 vbl = 0, position = 0; | |
189 | int vbl_start, vbl_end, htotal, vtotal; | |
190 | bool in_vbl = true; | |
191 | int ret = 0; | |
fe2b8f9d PZ |
192 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
193 | pipe); | |
0af7e4df MK |
194 | |
195 | if (!i915_pipe_enabled(dev, pipe)) { | |
196 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " | |
9db4a9c7 | 197 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
198 | return 0; |
199 | } | |
200 | ||
201 | /* Get vtotal. */ | |
fe2b8f9d | 202 | vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff); |
0af7e4df MK |
203 | |
204 | if (INTEL_INFO(dev)->gen >= 4) { | |
205 | /* No obvious pixelcount register. Only query vertical | |
206 | * scanout position from Display scan line register. | |
207 | */ | |
208 | position = I915_READ(PIPEDSL(pipe)); | |
209 | ||
210 | /* Decode into vertical scanout position. Don't have | |
211 | * horizontal scanout position. | |
212 | */ | |
213 | *vpos = position & 0x1fff; | |
214 | *hpos = 0; | |
215 | } else { | |
216 | /* Have access to pixelcount since start of frame. | |
217 | * We can split this into vertical and horizontal | |
218 | * scanout position. | |
219 | */ | |
220 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; | |
221 | ||
fe2b8f9d | 222 | htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff); |
0af7e4df MK |
223 | *vpos = position / htotal; |
224 | *hpos = position - (*vpos * htotal); | |
225 | } | |
226 | ||
227 | /* Query vblank area. */ | |
fe2b8f9d | 228 | vbl = I915_READ(VBLANK(cpu_transcoder)); |
0af7e4df MK |
229 | |
230 | /* Test position against vblank region. */ | |
231 | vbl_start = vbl & 0x1fff; | |
232 | vbl_end = (vbl >> 16) & 0x1fff; | |
233 | ||
234 | if ((*vpos < vbl_start) || (*vpos > vbl_end)) | |
235 | in_vbl = false; | |
236 | ||
237 | /* Inside "upper part" of vblank area? Apply corrective offset: */ | |
238 | if (in_vbl && (*vpos >= vbl_start)) | |
239 | *vpos = *vpos - vtotal; | |
240 | ||
241 | /* Readouts valid? */ | |
242 | if (vbl > 0) | |
243 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; | |
244 | ||
245 | /* In vblank? */ | |
246 | if (in_vbl) | |
247 | ret |= DRM_SCANOUTPOS_INVBL; | |
248 | ||
249 | return ret; | |
250 | } | |
251 | ||
f71d4af4 | 252 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
253 | int *max_error, |
254 | struct timeval *vblank_time, | |
255 | unsigned flags) | |
256 | { | |
4041b853 | 257 | struct drm_crtc *crtc; |
0af7e4df | 258 | |
7eb552ae | 259 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 260 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
261 | return -EINVAL; |
262 | } | |
263 | ||
264 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
265 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
266 | if (crtc == NULL) { | |
267 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
268 | return -EINVAL; | |
269 | } | |
270 | ||
271 | if (!crtc->enabled) { | |
272 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
273 | return -EBUSY; | |
274 | } | |
0af7e4df MK |
275 | |
276 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
277 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
278 | vblank_time, flags, | |
279 | crtc); | |
0af7e4df MK |
280 | } |
281 | ||
5ca58282 JB |
282 | /* |
283 | * Handle hotplug events outside the interrupt handler proper. | |
284 | */ | |
285 | static void i915_hotplug_work_func(struct work_struct *work) | |
286 | { | |
287 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
288 | hotplug_work); | |
289 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 290 | struct drm_mode_config *mode_config = &dev->mode_config; |
4ef69c7a CW |
291 | struct intel_encoder *encoder; |
292 | ||
52d7eced DV |
293 | /* HPD irq before everything is fully set up. */ |
294 | if (!dev_priv->enable_hotplug_processing) | |
295 | return; | |
296 | ||
a65e34c7 | 297 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
298 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
299 | ||
4ef69c7a CW |
300 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) |
301 | if (encoder->hot_plug) | |
302 | encoder->hot_plug(encoder); | |
303 | ||
40ee3381 KP |
304 | mutex_unlock(&mode_config->mutex); |
305 | ||
5ca58282 | 306 | /* Just fire off a uevent and let userspace tell us what to do */ |
eb1f8e4f | 307 | drm_helper_hpd_irq_event(dev); |
5ca58282 JB |
308 | } |
309 | ||
73edd18f | 310 | static void ironlake_handle_rps_change(struct drm_device *dev) |
f97108d1 JB |
311 | { |
312 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 313 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e DV |
314 | u8 new_delay; |
315 | unsigned long flags; | |
316 | ||
317 | spin_lock_irqsave(&mchdev_lock, flags); | |
f97108d1 | 318 | |
73edd18f DV |
319 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
320 | ||
20e4d407 | 321 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 322 | |
7648fa99 | 323 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
324 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
325 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
326 | max_avg = I915_READ(RCBMAXAVG); |
327 | min_avg = I915_READ(RCBMINAVG); | |
328 | ||
329 | /* Handle RCS change request from hw */ | |
b5b72e89 | 330 | if (busy_up > max_avg) { |
20e4d407 DV |
331 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
332 | new_delay = dev_priv->ips.cur_delay - 1; | |
333 | if (new_delay < dev_priv->ips.max_delay) | |
334 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 335 | } else if (busy_down < min_avg) { |
20e4d407 DV |
336 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
337 | new_delay = dev_priv->ips.cur_delay + 1; | |
338 | if (new_delay > dev_priv->ips.min_delay) | |
339 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
340 | } |
341 | ||
7648fa99 | 342 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 343 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 344 | |
9270388e DV |
345 | spin_unlock_irqrestore(&mchdev_lock, flags); |
346 | ||
f97108d1 JB |
347 | return; |
348 | } | |
349 | ||
549f7365 CW |
350 | static void notify_ring(struct drm_device *dev, |
351 | struct intel_ring_buffer *ring) | |
352 | { | |
353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9862e600 | 354 | |
475553de CW |
355 | if (ring->obj == NULL) |
356 | return; | |
357 | ||
b2eadbc8 | 358 | trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false)); |
9862e600 | 359 | |
549f7365 | 360 | wake_up_all(&ring->irq_queue); |
3e0dc6b0 | 361 | if (i915_enable_hangcheck) { |
99584db3 DV |
362 | dev_priv->gpu_error.hangcheck_count = 0; |
363 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
cecc21fe | 364 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
3e0dc6b0 | 365 | } |
549f7365 CW |
366 | } |
367 | ||
4912d041 | 368 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 369 | { |
4912d041 | 370 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
c6a828d3 | 371 | rps.work); |
4912d041 | 372 | u32 pm_iir, pm_imr; |
7b9e0ae6 | 373 | u8 new_delay; |
4912d041 | 374 | |
c6a828d3 DV |
375 | spin_lock_irq(&dev_priv->rps.lock); |
376 | pm_iir = dev_priv->rps.pm_iir; | |
377 | dev_priv->rps.pm_iir = 0; | |
4912d041 | 378 | pm_imr = I915_READ(GEN6_PMIMR); |
a9e2641d | 379 | I915_WRITE(GEN6_PMIMR, 0); |
c6a828d3 | 380 | spin_unlock_irq(&dev_priv->rps.lock); |
3b8d8d91 | 381 | |
7b9e0ae6 | 382 | if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0) |
3b8d8d91 JB |
383 | return; |
384 | ||
4fc688ce | 385 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 CW |
386 | |
387 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) | |
c6a828d3 | 388 | new_delay = dev_priv->rps.cur_delay + 1; |
7b9e0ae6 | 389 | else |
c6a828d3 | 390 | new_delay = dev_priv->rps.cur_delay - 1; |
3b8d8d91 | 391 | |
79249636 BW |
392 | /* sysfs frequency interfaces may have snuck in while servicing the |
393 | * interrupt | |
394 | */ | |
395 | if (!(new_delay > dev_priv->rps.max_delay || | |
396 | new_delay < dev_priv->rps.min_delay)) { | |
397 | gen6_set_rps(dev_priv->dev, new_delay); | |
398 | } | |
3b8d8d91 | 399 | |
4fc688ce | 400 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
401 | } |
402 | ||
e3689190 BW |
403 | |
404 | /** | |
405 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
406 | * occurred. | |
407 | * @work: workqueue struct | |
408 | * | |
409 | * Doesn't actually do anything except notify userspace. As a consequence of | |
410 | * this event, userspace should try to remap the bad rows since statistically | |
411 | * it is likely the same row is more likely to go bad again. | |
412 | */ | |
413 | static void ivybridge_parity_work(struct work_struct *work) | |
414 | { | |
415 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
a4da4fa4 | 416 | l3_parity.error_work); |
e3689190 BW |
417 | u32 error_status, row, bank, subbank; |
418 | char *parity_event[5]; | |
419 | uint32_t misccpctl; | |
420 | unsigned long flags; | |
421 | ||
422 | /* We must turn off DOP level clock gating to access the L3 registers. | |
423 | * In order to prevent a get/put style interface, acquire struct mutex | |
424 | * any time we access those registers. | |
425 | */ | |
426 | mutex_lock(&dev_priv->dev->struct_mutex); | |
427 | ||
428 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
429 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
430 | POSTING_READ(GEN7_MISCCPCTL); | |
431 | ||
432 | error_status = I915_READ(GEN7_L3CDERRST1); | |
433 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
434 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
435 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
436 | ||
437 | I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID | | |
438 | GEN7_L3CDERRST1_ENABLE); | |
439 | POSTING_READ(GEN7_L3CDERRST1); | |
440 | ||
441 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
442 | ||
443 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
444 | dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT; | |
445 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
446 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
447 | ||
448 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
449 | ||
450 | parity_event[0] = "L3_PARITY_ERROR=1"; | |
451 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
452 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
453 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
454 | parity_event[4] = NULL; | |
455 | ||
456 | kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj, | |
457 | KOBJ_CHANGE, parity_event); | |
458 | ||
459 | DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n", | |
460 | row, bank, subbank); | |
461 | ||
462 | kfree(parity_event[3]); | |
463 | kfree(parity_event[2]); | |
464 | kfree(parity_event[1]); | |
465 | } | |
466 | ||
d2ba8470 | 467 | static void ivybridge_handle_parity_error(struct drm_device *dev) |
e3689190 BW |
468 | { |
469 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
470 | unsigned long flags; | |
471 | ||
e1ef7cc2 | 472 | if (!HAS_L3_GPU_CACHE(dev)) |
e3689190 BW |
473 | return; |
474 | ||
475 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
476 | dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT; | |
477 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
478 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
479 | ||
a4da4fa4 | 480 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
481 | } |
482 | ||
e7b4c6b1 DV |
483 | static void snb_gt_irq_handler(struct drm_device *dev, |
484 | struct drm_i915_private *dev_priv, | |
485 | u32 gt_iir) | |
486 | { | |
487 | ||
488 | if (gt_iir & (GEN6_RENDER_USER_INTERRUPT | | |
489 | GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT)) | |
490 | notify_ring(dev, &dev_priv->ring[RCS]); | |
491 | if (gt_iir & GEN6_BSD_USER_INTERRUPT) | |
492 | notify_ring(dev, &dev_priv->ring[VCS]); | |
493 | if (gt_iir & GEN6_BLITTER_USER_INTERRUPT) | |
494 | notify_ring(dev, &dev_priv->ring[BCS]); | |
495 | ||
496 | if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT | | |
497 | GT_GEN6_BSD_CS_ERROR_INTERRUPT | | |
498 | GT_RENDER_CS_ERROR_INTERRUPT)) { | |
499 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); | |
500 | i915_handle_error(dev, false); | |
501 | } | |
e3689190 BW |
502 | |
503 | if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT) | |
504 | ivybridge_handle_parity_error(dev); | |
e7b4c6b1 DV |
505 | } |
506 | ||
fc6826d1 CW |
507 | static void gen6_queue_rps_work(struct drm_i915_private *dev_priv, |
508 | u32 pm_iir) | |
509 | { | |
510 | unsigned long flags; | |
511 | ||
512 | /* | |
513 | * IIR bits should never already be set because IMR should | |
514 | * prevent an interrupt from being shown in IIR. The warning | |
515 | * displays a case where we've unsafely cleared | |
c6a828d3 | 516 | * dev_priv->rps.pm_iir. Although missing an interrupt of the same |
fc6826d1 CW |
517 | * type is not a problem, it displays a problem in the logic. |
518 | * | |
c6a828d3 | 519 | * The mask bit in IMR is cleared by dev_priv->rps.work. |
fc6826d1 CW |
520 | */ |
521 | ||
c6a828d3 | 522 | spin_lock_irqsave(&dev_priv->rps.lock, flags); |
c6a828d3 DV |
523 | dev_priv->rps.pm_iir |= pm_iir; |
524 | I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir); | |
fc6826d1 | 525 | POSTING_READ(GEN6_PMIMR); |
c6a828d3 | 526 | spin_unlock_irqrestore(&dev_priv->rps.lock, flags); |
fc6826d1 | 527 | |
c6a828d3 | 528 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
fc6826d1 CW |
529 | } |
530 | ||
515ac2bb DV |
531 | static void gmbus_irq_handler(struct drm_device *dev) |
532 | { | |
28c70f16 DV |
533 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
534 | ||
28c70f16 | 535 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
536 | } |
537 | ||
ce99c256 DV |
538 | static void dp_aux_irq_handler(struct drm_device *dev) |
539 | { | |
9ee32fea DV |
540 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
541 | ||
9ee32fea | 542 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
543 | } |
544 | ||
ff1f525e | 545 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe JB |
546 | { |
547 | struct drm_device *dev = (struct drm_device *) arg; | |
548 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
549 | u32 iir, gt_iir, pm_iir; | |
550 | irqreturn_t ret = IRQ_NONE; | |
551 | unsigned long irqflags; | |
552 | int pipe; | |
553 | u32 pipe_stats[I915_MAX_PIPES]; | |
7e231dbe JB |
554 | |
555 | atomic_inc(&dev_priv->irq_received); | |
556 | ||
7e231dbe JB |
557 | while (true) { |
558 | iir = I915_READ(VLV_IIR); | |
559 | gt_iir = I915_READ(GTIIR); | |
560 | pm_iir = I915_READ(GEN6_PMIIR); | |
561 | ||
562 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
563 | goto out; | |
564 | ||
565 | ret = IRQ_HANDLED; | |
566 | ||
e7b4c6b1 | 567 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe JB |
568 | |
569 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
570 | for_each_pipe(pipe) { | |
571 | int reg = PIPESTAT(pipe); | |
572 | pipe_stats[pipe] = I915_READ(reg); | |
573 | ||
574 | /* | |
575 | * Clear the PIPE*STAT regs before the IIR | |
576 | */ | |
577 | if (pipe_stats[pipe] & 0x8000ffff) { | |
578 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
579 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
580 | pipe_name(pipe)); | |
581 | I915_WRITE(reg, pipe_stats[pipe]); | |
582 | } | |
583 | } | |
584 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
585 | ||
31acc7f5 JB |
586 | for_each_pipe(pipe) { |
587 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) | |
588 | drm_handle_vblank(dev, pipe); | |
589 | ||
590 | if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { | |
591 | intel_prepare_page_flip(dev, pipe); | |
592 | intel_finish_page_flip(dev, pipe); | |
593 | } | |
594 | } | |
595 | ||
7e231dbe JB |
596 | /* Consume port. Then clear IIR or we'll miss events */ |
597 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { | |
598 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
599 | ||
600 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
601 | hotplug_status); | |
602 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
603 | queue_work(dev_priv->wq, | |
604 | &dev_priv->hotplug_work); | |
605 | ||
606 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
607 | I915_READ(PORT_HOTPLUG_STAT); | |
608 | } | |
609 | ||
515ac2bb DV |
610 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
611 | gmbus_irq_handler(dev); | |
7e231dbe | 612 | |
fc6826d1 CW |
613 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) |
614 | gen6_queue_rps_work(dev_priv, pm_iir); | |
7e231dbe JB |
615 | |
616 | I915_WRITE(GTIIR, gt_iir); | |
617 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
618 | I915_WRITE(VLV_IIR, iir); | |
619 | } | |
620 | ||
621 | out: | |
622 | return ret; | |
623 | } | |
624 | ||
23e81d69 | 625 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 JB |
626 | { |
627 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 628 | int pipe; |
776ad806 | 629 | |
76e43830 DV |
630 | if (pch_iir & SDE_HOTPLUG_MASK) |
631 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
632 | ||
776ad806 JB |
633 | if (pch_iir & SDE_AUDIO_POWER_MASK) |
634 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", | |
635 | (pch_iir & SDE_AUDIO_POWER_MASK) >> | |
636 | SDE_AUDIO_POWER_SHIFT); | |
637 | ||
ce99c256 DV |
638 | if (pch_iir & SDE_AUX_MASK) |
639 | dp_aux_irq_handler(dev); | |
640 | ||
776ad806 | 641 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 642 | gmbus_irq_handler(dev); |
776ad806 JB |
643 | |
644 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
645 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
646 | ||
647 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
648 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
649 | ||
650 | if (pch_iir & SDE_POISON) | |
651 | DRM_ERROR("PCH poison interrupt\n"); | |
652 | ||
9db4a9c7 JB |
653 | if (pch_iir & SDE_FDI_MASK) |
654 | for_each_pipe(pipe) | |
655 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
656 | pipe_name(pipe), | |
657 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
658 | |
659 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
660 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
661 | ||
662 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
663 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
664 | ||
665 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
666 | DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); | |
667 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) | |
668 | DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); | |
669 | } | |
670 | ||
23e81d69 AJ |
671 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
672 | { | |
673 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
674 | int pipe; | |
675 | ||
76e43830 DV |
676 | if (pch_iir & SDE_HOTPLUG_MASK_CPT) |
677 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
678 | ||
23e81d69 AJ |
679 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) |
680 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", | |
681 | (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
682 | SDE_AUDIO_POWER_SHIFT_CPT); | |
683 | ||
684 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 685 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
686 | |
687 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 688 | gmbus_irq_handler(dev); |
23e81d69 AJ |
689 | |
690 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
691 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
692 | ||
693 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
694 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
695 | ||
696 | if (pch_iir & SDE_FDI_MASK_CPT) | |
697 | for_each_pipe(pipe) | |
698 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
699 | pipe_name(pipe), | |
700 | I915_READ(FDI_RX_IIR(pipe))); | |
701 | } | |
702 | ||
ff1f525e | 703 | static irqreturn_t ivybridge_irq_handler(int irq, void *arg) |
b1f14ad0 JB |
704 | { |
705 | struct drm_device *dev = (struct drm_device *) arg; | |
706 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
44498aea | 707 | u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier; |
0e43406b CW |
708 | irqreturn_t ret = IRQ_NONE; |
709 | int i; | |
b1f14ad0 JB |
710 | |
711 | atomic_inc(&dev_priv->irq_received); | |
712 | ||
713 | /* disable master interrupt before clearing iir */ | |
714 | de_ier = I915_READ(DEIER); | |
715 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
b1f14ad0 | 716 | |
44498aea PZ |
717 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
718 | * interrupts will will be stored on its back queue, and then we'll be | |
719 | * able to process them after we restore SDEIER (as soon as we restore | |
720 | * it, we'll get an interrupt if SDEIIR still has something to process | |
721 | * due to its back queue). */ | |
722 | sde_ier = I915_READ(SDEIER); | |
723 | I915_WRITE(SDEIER, 0); | |
724 | POSTING_READ(SDEIER); | |
725 | ||
b1f14ad0 | 726 | gt_iir = I915_READ(GTIIR); |
0e43406b CW |
727 | if (gt_iir) { |
728 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
729 | I915_WRITE(GTIIR, gt_iir); | |
730 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
731 | } |
732 | ||
0e43406b CW |
733 | de_iir = I915_READ(DEIIR); |
734 | if (de_iir) { | |
ce99c256 DV |
735 | if (de_iir & DE_AUX_CHANNEL_A_IVB) |
736 | dp_aux_irq_handler(dev); | |
737 | ||
0e43406b CW |
738 | if (de_iir & DE_GSE_IVB) |
739 | intel_opregion_gse_intr(dev); | |
740 | ||
741 | for (i = 0; i < 3; i++) { | |
74d44445 DV |
742 | if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i))) |
743 | drm_handle_vblank(dev, i); | |
0e43406b CW |
744 | if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) { |
745 | intel_prepare_page_flip(dev, i); | |
746 | intel_finish_page_flip_plane(dev, i); | |
747 | } | |
0e43406b | 748 | } |
b615b57a | 749 | |
0e43406b CW |
750 | /* check event from PCH */ |
751 | if (de_iir & DE_PCH_EVENT_IVB) { | |
752 | u32 pch_iir = I915_READ(SDEIIR); | |
b1f14ad0 | 753 | |
23e81d69 | 754 | cpt_irq_handler(dev, pch_iir); |
b1f14ad0 | 755 | |
0e43406b CW |
756 | /* clear PCH hotplug event before clear CPU irq */ |
757 | I915_WRITE(SDEIIR, pch_iir); | |
758 | } | |
b615b57a | 759 | |
0e43406b CW |
760 | I915_WRITE(DEIIR, de_iir); |
761 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
762 | } |
763 | ||
0e43406b CW |
764 | pm_iir = I915_READ(GEN6_PMIIR); |
765 | if (pm_iir) { | |
766 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) | |
767 | gen6_queue_rps_work(dev_priv, pm_iir); | |
768 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
769 | ret = IRQ_HANDLED; | |
770 | } | |
b1f14ad0 | 771 | |
b1f14ad0 JB |
772 | I915_WRITE(DEIER, de_ier); |
773 | POSTING_READ(DEIER); | |
44498aea PZ |
774 | I915_WRITE(SDEIER, sde_ier); |
775 | POSTING_READ(SDEIER); | |
b1f14ad0 JB |
776 | |
777 | return ret; | |
778 | } | |
779 | ||
e7b4c6b1 DV |
780 | static void ilk_gt_irq_handler(struct drm_device *dev, |
781 | struct drm_i915_private *dev_priv, | |
782 | u32 gt_iir) | |
783 | { | |
784 | if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) | |
785 | notify_ring(dev, &dev_priv->ring[RCS]); | |
786 | if (gt_iir & GT_BSD_USER_INTERRUPT) | |
787 | notify_ring(dev, &dev_priv->ring[VCS]); | |
788 | } | |
789 | ||
ff1f525e | 790 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
036a4a7d | 791 | { |
4697995b | 792 | struct drm_device *dev = (struct drm_device *) arg; |
036a4a7d ZW |
793 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
794 | int ret = IRQ_NONE; | |
44498aea | 795 | u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier; |
881f47b6 | 796 | |
4697995b JB |
797 | atomic_inc(&dev_priv->irq_received); |
798 | ||
2d109a84 ZN |
799 | /* disable master interrupt before clearing iir */ |
800 | de_ier = I915_READ(DEIER); | |
801 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
3143a2bf | 802 | POSTING_READ(DEIER); |
2d109a84 | 803 | |
44498aea PZ |
804 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
805 | * interrupts will will be stored on its back queue, and then we'll be | |
806 | * able to process them after we restore SDEIER (as soon as we restore | |
807 | * it, we'll get an interrupt if SDEIIR still has something to process | |
808 | * due to its back queue). */ | |
809 | sde_ier = I915_READ(SDEIER); | |
810 | I915_WRITE(SDEIER, 0); | |
811 | POSTING_READ(SDEIER); | |
812 | ||
036a4a7d ZW |
813 | de_iir = I915_READ(DEIIR); |
814 | gt_iir = I915_READ(GTIIR); | |
3b8d8d91 | 815 | pm_iir = I915_READ(GEN6_PMIIR); |
036a4a7d | 816 | |
acd15b6c | 817 | if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0)) |
c7c85101 | 818 | goto done; |
036a4a7d | 819 | |
c7c85101 | 820 | ret = IRQ_HANDLED; |
036a4a7d | 821 | |
e7b4c6b1 DV |
822 | if (IS_GEN5(dev)) |
823 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
824 | else | |
825 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
01c66889 | 826 | |
ce99c256 DV |
827 | if (de_iir & DE_AUX_CHANNEL_A) |
828 | dp_aux_irq_handler(dev); | |
829 | ||
c7c85101 | 830 | if (de_iir & DE_GSE) |
3b617967 | 831 | intel_opregion_gse_intr(dev); |
c650156a | 832 | |
74d44445 DV |
833 | if (de_iir & DE_PIPEA_VBLANK) |
834 | drm_handle_vblank(dev, 0); | |
835 | ||
836 | if (de_iir & DE_PIPEB_VBLANK) | |
837 | drm_handle_vblank(dev, 1); | |
838 | ||
f072d2e7 | 839 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 840 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 841 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 842 | } |
013d5aa2 | 843 | |
f072d2e7 | 844 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 845 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 846 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 847 | } |
013d5aa2 | 848 | |
c7c85101 | 849 | /* check event from PCH */ |
776ad806 | 850 | if (de_iir & DE_PCH_EVENT) { |
acd15b6c DV |
851 | u32 pch_iir = I915_READ(SDEIIR); |
852 | ||
23e81d69 AJ |
853 | if (HAS_PCH_CPT(dev)) |
854 | cpt_irq_handler(dev, pch_iir); | |
855 | else | |
856 | ibx_irq_handler(dev, pch_iir); | |
acd15b6c DV |
857 | |
858 | /* should clear PCH hotplug event before clear CPU irq */ | |
859 | I915_WRITE(SDEIIR, pch_iir); | |
776ad806 | 860 | } |
036a4a7d | 861 | |
73edd18f DV |
862 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) |
863 | ironlake_handle_rps_change(dev); | |
f97108d1 | 864 | |
fc6826d1 CW |
865 | if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) |
866 | gen6_queue_rps_work(dev_priv, pm_iir); | |
3b8d8d91 | 867 | |
c7c85101 ZN |
868 | I915_WRITE(GTIIR, gt_iir); |
869 | I915_WRITE(DEIIR, de_iir); | |
4912d041 | 870 | I915_WRITE(GEN6_PMIIR, pm_iir); |
c7c85101 ZN |
871 | |
872 | done: | |
2d109a84 | 873 | I915_WRITE(DEIER, de_ier); |
3143a2bf | 874 | POSTING_READ(DEIER); |
44498aea PZ |
875 | I915_WRITE(SDEIER, sde_ier); |
876 | POSTING_READ(SDEIER); | |
2d109a84 | 877 | |
036a4a7d ZW |
878 | return ret; |
879 | } | |
880 | ||
8a905236 JB |
881 | /** |
882 | * i915_error_work_func - do process context error handling work | |
883 | * @work: work struct | |
884 | * | |
885 | * Fire an error uevent so userspace can see that a hang or error | |
886 | * was detected. | |
887 | */ | |
888 | static void i915_error_work_func(struct work_struct *work) | |
889 | { | |
1f83fee0 DV |
890 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
891 | work); | |
892 | drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, | |
893 | gpu_error); | |
8a905236 | 894 | struct drm_device *dev = dev_priv->dev; |
f69061be | 895 | struct intel_ring_buffer *ring; |
f316a42c BG |
896 | char *error_event[] = { "ERROR=1", NULL }; |
897 | char *reset_event[] = { "RESET=1", NULL }; | |
898 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
f69061be | 899 | int i, ret; |
8a905236 | 900 | |
f316a42c BG |
901 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
902 | ||
7db0ba24 DV |
903 | /* |
904 | * Note that there's only one work item which does gpu resets, so we | |
905 | * need not worry about concurrent gpu resets potentially incrementing | |
906 | * error->reset_counter twice. We only need to take care of another | |
907 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
908 | * quick check for that is good enough: schedule_work ensures the | |
909 | * correct ordering between hang detection and this work item, and since | |
910 | * the reset in-progress bit is only ever set by code outside of this | |
911 | * work we don't need to worry about any other races. | |
912 | */ | |
913 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 914 | DRM_DEBUG_DRIVER("resetting chip\n"); |
7db0ba24 DV |
915 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, |
916 | reset_event); | |
1f83fee0 | 917 | |
f69061be DV |
918 | ret = i915_reset(dev); |
919 | ||
920 | if (ret == 0) { | |
921 | /* | |
922 | * After all the gem state is reset, increment the reset | |
923 | * counter and wake up everyone waiting for the reset to | |
924 | * complete. | |
925 | * | |
926 | * Since unlock operations are a one-sided barrier only, | |
927 | * we need to insert a barrier here to order any seqno | |
928 | * updates before | |
929 | * the counter increment. | |
930 | */ | |
931 | smp_mb__before_atomic_inc(); | |
932 | atomic_inc(&dev_priv->gpu_error.reset_counter); | |
933 | ||
934 | kobject_uevent_env(&dev->primary->kdev.kobj, | |
935 | KOBJ_CHANGE, reset_done_event); | |
1f83fee0 DV |
936 | } else { |
937 | atomic_set(&error->reset_counter, I915_WEDGED); | |
f316a42c | 938 | } |
1f83fee0 | 939 | |
f69061be DV |
940 | for_each_ring(ring, dev_priv, i) |
941 | wake_up_all(&ring->irq_queue); | |
942 | ||
96a02917 VS |
943 | intel_display_handle_reset(dev); |
944 | ||
1f83fee0 | 945 | wake_up_all(&dev_priv->gpu_error.reset_queue); |
f316a42c | 946 | } |
8a905236 JB |
947 | } |
948 | ||
85f9e50d DV |
949 | /* NB: please notice the memset */ |
950 | static void i915_get_extra_instdone(struct drm_device *dev, | |
951 | uint32_t *instdone) | |
952 | { | |
953 | struct drm_i915_private *dev_priv = dev->dev_private; | |
954 | memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); | |
955 | ||
956 | switch(INTEL_INFO(dev)->gen) { | |
957 | case 2: | |
958 | case 3: | |
959 | instdone[0] = I915_READ(INSTDONE); | |
960 | break; | |
961 | case 4: | |
962 | case 5: | |
963 | case 6: | |
964 | instdone[0] = I915_READ(INSTDONE_I965); | |
965 | instdone[1] = I915_READ(INSTDONE1); | |
966 | break; | |
967 | default: | |
968 | WARN_ONCE(1, "Unsupported platform\n"); | |
969 | case 7: | |
970 | instdone[0] = I915_READ(GEN7_INSTDONE_1); | |
971 | instdone[1] = I915_READ(GEN7_SC_INSTDONE); | |
972 | instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); | |
973 | instdone[3] = I915_READ(GEN7_ROW_INSTDONE); | |
974 | break; | |
975 | } | |
976 | } | |
977 | ||
3bd3c932 | 978 | #ifdef CONFIG_DEBUG_FS |
9df30794 | 979 | static struct drm_i915_error_object * |
d0d045e8 BW |
980 | i915_error_object_create_sized(struct drm_i915_private *dev_priv, |
981 | struct drm_i915_gem_object *src, | |
982 | const int num_pages) | |
9df30794 CW |
983 | { |
984 | struct drm_i915_error_object *dst; | |
d0d045e8 | 985 | int i; |
e56660dd | 986 | u32 reloc_offset; |
9df30794 | 987 | |
05394f39 | 988 | if (src == NULL || src->pages == NULL) |
9df30794 CW |
989 | return NULL; |
990 | ||
d0d045e8 | 991 | dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); |
9df30794 CW |
992 | if (dst == NULL) |
993 | return NULL; | |
994 | ||
05394f39 | 995 | reloc_offset = src->gtt_offset; |
d0d045e8 | 996 | for (i = 0; i < num_pages; i++) { |
788885ae | 997 | unsigned long flags; |
e56660dd | 998 | void *d; |
788885ae | 999 | |
e56660dd | 1000 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
1001 | if (d == NULL) |
1002 | goto unwind; | |
e56660dd | 1003 | |
788885ae | 1004 | local_irq_save(flags); |
5d4545ae | 1005 | if (reloc_offset < dev_priv->gtt.mappable_end && |
74898d7e | 1006 | src->has_global_gtt_mapping) { |
172975aa CW |
1007 | void __iomem *s; |
1008 | ||
1009 | /* Simply ignore tiling or any overlapping fence. | |
1010 | * It's part of the error state, and this hopefully | |
1011 | * captures what the GPU read. | |
1012 | */ | |
1013 | ||
5d4545ae | 1014 | s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
172975aa CW |
1015 | reloc_offset); |
1016 | memcpy_fromio(d, s, PAGE_SIZE); | |
1017 | io_mapping_unmap_atomic(s); | |
960e3564 CW |
1018 | } else if (src->stolen) { |
1019 | unsigned long offset; | |
1020 | ||
1021 | offset = dev_priv->mm.stolen_base; | |
1022 | offset += src->stolen->start; | |
1023 | offset += i << PAGE_SHIFT; | |
1024 | ||
1a240d4d | 1025 | memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE); |
172975aa | 1026 | } else { |
9da3da66 | 1027 | struct page *page; |
172975aa CW |
1028 | void *s; |
1029 | ||
9da3da66 | 1030 | page = i915_gem_object_get_page(src, i); |
172975aa | 1031 | |
9da3da66 CW |
1032 | drm_clflush_pages(&page, 1); |
1033 | ||
1034 | s = kmap_atomic(page); | |
172975aa CW |
1035 | memcpy(d, s, PAGE_SIZE); |
1036 | kunmap_atomic(s); | |
1037 | ||
9da3da66 | 1038 | drm_clflush_pages(&page, 1); |
172975aa | 1039 | } |
788885ae | 1040 | local_irq_restore(flags); |
e56660dd | 1041 | |
9da3da66 | 1042 | dst->pages[i] = d; |
e56660dd CW |
1043 | |
1044 | reloc_offset += PAGE_SIZE; | |
9df30794 | 1045 | } |
d0d045e8 | 1046 | dst->page_count = num_pages; |
05394f39 | 1047 | dst->gtt_offset = src->gtt_offset; |
9df30794 CW |
1048 | |
1049 | return dst; | |
1050 | ||
1051 | unwind: | |
9da3da66 CW |
1052 | while (i--) |
1053 | kfree(dst->pages[i]); | |
9df30794 CW |
1054 | kfree(dst); |
1055 | return NULL; | |
1056 | } | |
d0d045e8 BW |
1057 | #define i915_error_object_create(dev_priv, src) \ |
1058 | i915_error_object_create_sized((dev_priv), (src), \ | |
1059 | (src)->base.size>>PAGE_SHIFT) | |
9df30794 CW |
1060 | |
1061 | static void | |
1062 | i915_error_object_free(struct drm_i915_error_object *obj) | |
1063 | { | |
1064 | int page; | |
1065 | ||
1066 | if (obj == NULL) | |
1067 | return; | |
1068 | ||
1069 | for (page = 0; page < obj->page_count; page++) | |
1070 | kfree(obj->pages[page]); | |
1071 | ||
1072 | kfree(obj); | |
1073 | } | |
1074 | ||
742cbee8 DV |
1075 | void |
1076 | i915_error_state_free(struct kref *error_ref) | |
9df30794 | 1077 | { |
742cbee8 DV |
1078 | struct drm_i915_error_state *error = container_of(error_ref, |
1079 | typeof(*error), ref); | |
e2f973d5 CW |
1080 | int i; |
1081 | ||
52d39a21 CW |
1082 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
1083 | i915_error_object_free(error->ring[i].batchbuffer); | |
1084 | i915_error_object_free(error->ring[i].ringbuffer); | |
1085 | kfree(error->ring[i].requests); | |
1086 | } | |
e2f973d5 | 1087 | |
9df30794 | 1088 | kfree(error->active_bo); |
6ef3d427 | 1089 | kfree(error->overlay); |
9df30794 CW |
1090 | kfree(error); |
1091 | } | |
1b50247a CW |
1092 | static void capture_bo(struct drm_i915_error_buffer *err, |
1093 | struct drm_i915_gem_object *obj) | |
1094 | { | |
1095 | err->size = obj->base.size; | |
1096 | err->name = obj->base.name; | |
0201f1ec CW |
1097 | err->rseqno = obj->last_read_seqno; |
1098 | err->wseqno = obj->last_write_seqno; | |
1b50247a CW |
1099 | err->gtt_offset = obj->gtt_offset; |
1100 | err->read_domains = obj->base.read_domains; | |
1101 | err->write_domain = obj->base.write_domain; | |
1102 | err->fence_reg = obj->fence_reg; | |
1103 | err->pinned = 0; | |
1104 | if (obj->pin_count > 0) | |
1105 | err->pinned = 1; | |
1106 | if (obj->user_pin_count > 0) | |
1107 | err->pinned = -1; | |
1108 | err->tiling = obj->tiling_mode; | |
1109 | err->dirty = obj->dirty; | |
1110 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
1111 | err->ring = obj->ring ? obj->ring->id : -1; | |
1112 | err->cache_level = obj->cache_level; | |
1113 | } | |
9df30794 | 1114 | |
1b50247a CW |
1115 | static u32 capture_active_bo(struct drm_i915_error_buffer *err, |
1116 | int count, struct list_head *head) | |
c724e8a9 CW |
1117 | { |
1118 | struct drm_i915_gem_object *obj; | |
1119 | int i = 0; | |
1120 | ||
1121 | list_for_each_entry(obj, head, mm_list) { | |
1b50247a | 1122 | capture_bo(err++, obj); |
c724e8a9 CW |
1123 | if (++i == count) |
1124 | break; | |
1b50247a CW |
1125 | } |
1126 | ||
1127 | return i; | |
1128 | } | |
1129 | ||
1130 | static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, | |
1131 | int count, struct list_head *head) | |
1132 | { | |
1133 | struct drm_i915_gem_object *obj; | |
1134 | int i = 0; | |
1135 | ||
1136 | list_for_each_entry(obj, head, gtt_list) { | |
1137 | if (obj->pin_count == 0) | |
1138 | continue; | |
c724e8a9 | 1139 | |
1b50247a CW |
1140 | capture_bo(err++, obj); |
1141 | if (++i == count) | |
1142 | break; | |
c724e8a9 CW |
1143 | } |
1144 | ||
1145 | return i; | |
1146 | } | |
1147 | ||
748ebc60 CW |
1148 | static void i915_gem_record_fences(struct drm_device *dev, |
1149 | struct drm_i915_error_state *error) | |
1150 | { | |
1151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1152 | int i; | |
1153 | ||
1154 | /* Fences */ | |
1155 | switch (INTEL_INFO(dev)->gen) { | |
775d17b6 | 1156 | case 7: |
748ebc60 CW |
1157 | case 6: |
1158 | for (i = 0; i < 16; i++) | |
1159 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); | |
1160 | break; | |
1161 | case 5: | |
1162 | case 4: | |
1163 | for (i = 0; i < 16; i++) | |
1164 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
1165 | break; | |
1166 | case 3: | |
1167 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
1168 | for (i = 0; i < 8; i++) | |
1169 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
1170 | case 2: | |
1171 | for (i = 0; i < 8; i++) | |
1172 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
1173 | break; | |
1174 | ||
7dbf9d6e BW |
1175 | default: |
1176 | BUG(); | |
748ebc60 CW |
1177 | } |
1178 | } | |
1179 | ||
bcfb2e28 CW |
1180 | static struct drm_i915_error_object * |
1181 | i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, | |
1182 | struct intel_ring_buffer *ring) | |
1183 | { | |
1184 | struct drm_i915_gem_object *obj; | |
1185 | u32 seqno; | |
1186 | ||
1187 | if (!ring->get_seqno) | |
1188 | return NULL; | |
1189 | ||
b45305fc DV |
1190 | if (HAS_BROKEN_CS_TLB(dev_priv->dev)) { |
1191 | u32 acthd = I915_READ(ACTHD); | |
1192 | ||
1193 | if (WARN_ON(ring->id != RCS)) | |
1194 | return NULL; | |
1195 | ||
1196 | obj = ring->private; | |
1197 | if (acthd >= obj->gtt_offset && | |
1198 | acthd < obj->gtt_offset + obj->base.size) | |
1199 | return i915_error_object_create(dev_priv, obj); | |
1200 | } | |
1201 | ||
b2eadbc8 | 1202 | seqno = ring->get_seqno(ring, false); |
bcfb2e28 CW |
1203 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { |
1204 | if (obj->ring != ring) | |
1205 | continue; | |
1206 | ||
0201f1ec | 1207 | if (i915_seqno_passed(seqno, obj->last_read_seqno)) |
bcfb2e28 CW |
1208 | continue; |
1209 | ||
1210 | if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) | |
1211 | continue; | |
1212 | ||
1213 | /* We need to copy these to an anonymous buffer as the simplest | |
1214 | * method to avoid being overwritten by userspace. | |
1215 | */ | |
1216 | return i915_error_object_create(dev_priv, obj); | |
1217 | } | |
1218 | ||
1219 | return NULL; | |
1220 | } | |
1221 | ||
d27b1e0e DV |
1222 | static void i915_record_ring_state(struct drm_device *dev, |
1223 | struct drm_i915_error_state *error, | |
1224 | struct intel_ring_buffer *ring) | |
1225 | { | |
1226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1227 | ||
33f3f518 | 1228 | if (INTEL_INFO(dev)->gen >= 6) { |
12f55818 | 1229 | error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50); |
33f3f518 | 1230 | error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); |
7e3b8737 DV |
1231 | error->semaphore_mboxes[ring->id][0] |
1232 | = I915_READ(RING_SYNC_0(ring->mmio_base)); | |
1233 | error->semaphore_mboxes[ring->id][1] | |
1234 | = I915_READ(RING_SYNC_1(ring->mmio_base)); | |
df2b23d9 CW |
1235 | error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0]; |
1236 | error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1]; | |
33f3f518 | 1237 | } |
c1cd90ed | 1238 | |
d27b1e0e | 1239 | if (INTEL_INFO(dev)->gen >= 4) { |
9d2f41fa | 1240 | error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); |
d27b1e0e DV |
1241 | error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); |
1242 | error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); | |
1243 | error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); | |
c1cd90ed | 1244 | error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); |
050ee91f | 1245 | if (ring->id == RCS) |
d27b1e0e | 1246 | error->bbaddr = I915_READ64(BB_ADDR); |
d27b1e0e | 1247 | } else { |
9d2f41fa | 1248 | error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX); |
d27b1e0e DV |
1249 | error->ipeir[ring->id] = I915_READ(IPEIR); |
1250 | error->ipehr[ring->id] = I915_READ(IPEHR); | |
1251 | error->instdone[ring->id] = I915_READ(INSTDONE); | |
d27b1e0e DV |
1252 | } |
1253 | ||
9574b3fe | 1254 | error->waiting[ring->id] = waitqueue_active(&ring->irq_queue); |
c1cd90ed | 1255 | error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); |
b2eadbc8 | 1256 | error->seqno[ring->id] = ring->get_seqno(ring, false); |
d27b1e0e | 1257 | error->acthd[ring->id] = intel_ring_get_active_head(ring); |
c1cd90ed DV |
1258 | error->head[ring->id] = I915_READ_HEAD(ring); |
1259 | error->tail[ring->id] = I915_READ_TAIL(ring); | |
0f3b6849 | 1260 | error->ctl[ring->id] = I915_READ_CTL(ring); |
7e3b8737 DV |
1261 | |
1262 | error->cpu_ring_head[ring->id] = ring->head; | |
1263 | error->cpu_ring_tail[ring->id] = ring->tail; | |
d27b1e0e DV |
1264 | } |
1265 | ||
8c123e54 BW |
1266 | |
1267 | static void i915_gem_record_active_context(struct intel_ring_buffer *ring, | |
1268 | struct drm_i915_error_state *error, | |
1269 | struct drm_i915_error_ring *ering) | |
1270 | { | |
1271 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1272 | struct drm_i915_gem_object *obj; | |
1273 | ||
1274 | /* Currently render ring is the only HW context user */ | |
1275 | if (ring->id != RCS || !error->ccid) | |
1276 | return; | |
1277 | ||
1278 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { | |
1279 | if ((error->ccid & PAGE_MASK) == obj->gtt_offset) { | |
1280 | ering->ctx = i915_error_object_create_sized(dev_priv, | |
1281 | obj, 1); | |
1282 | } | |
1283 | } | |
1284 | } | |
1285 | ||
52d39a21 CW |
1286 | static void i915_gem_record_rings(struct drm_device *dev, |
1287 | struct drm_i915_error_state *error) | |
1288 | { | |
1289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b4519513 | 1290 | struct intel_ring_buffer *ring; |
52d39a21 CW |
1291 | struct drm_i915_gem_request *request; |
1292 | int i, count; | |
1293 | ||
b4519513 | 1294 | for_each_ring(ring, dev_priv, i) { |
52d39a21 CW |
1295 | i915_record_ring_state(dev, error, ring); |
1296 | ||
1297 | error->ring[i].batchbuffer = | |
1298 | i915_error_first_batchbuffer(dev_priv, ring); | |
1299 | ||
1300 | error->ring[i].ringbuffer = | |
1301 | i915_error_object_create(dev_priv, ring->obj); | |
1302 | ||
8c123e54 BW |
1303 | |
1304 | i915_gem_record_active_context(ring, error, &error->ring[i]); | |
1305 | ||
52d39a21 CW |
1306 | count = 0; |
1307 | list_for_each_entry(request, &ring->request_list, list) | |
1308 | count++; | |
1309 | ||
1310 | error->ring[i].num_requests = count; | |
1311 | error->ring[i].requests = | |
1312 | kmalloc(count*sizeof(struct drm_i915_error_request), | |
1313 | GFP_ATOMIC); | |
1314 | if (error->ring[i].requests == NULL) { | |
1315 | error->ring[i].num_requests = 0; | |
1316 | continue; | |
1317 | } | |
1318 | ||
1319 | count = 0; | |
1320 | list_for_each_entry(request, &ring->request_list, list) { | |
1321 | struct drm_i915_error_request *erq; | |
1322 | ||
1323 | erq = &error->ring[i].requests[count++]; | |
1324 | erq->seqno = request->seqno; | |
1325 | erq->jiffies = request->emitted_jiffies; | |
ee4f42b1 | 1326 | erq->tail = request->tail; |
52d39a21 CW |
1327 | } |
1328 | } | |
1329 | } | |
1330 | ||
8a905236 JB |
1331 | /** |
1332 | * i915_capture_error_state - capture an error record for later analysis | |
1333 | * @dev: drm device | |
1334 | * | |
1335 | * Should be called when an error is detected (either a hang or an error | |
1336 | * interrupt) to capture error state from the time of the error. Fills | |
1337 | * out a structure which becomes available in debugfs for user level tools | |
1338 | * to pick up. | |
1339 | */ | |
63eeaf38 JB |
1340 | static void i915_capture_error_state(struct drm_device *dev) |
1341 | { | |
1342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1343 | struct drm_i915_gem_object *obj; |
63eeaf38 JB |
1344 | struct drm_i915_error_state *error; |
1345 | unsigned long flags; | |
9db4a9c7 | 1346 | int i, pipe; |
63eeaf38 | 1347 | |
99584db3 DV |
1348 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
1349 | error = dev_priv->gpu_error.first_error; | |
1350 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); | |
9df30794 CW |
1351 | if (error) |
1352 | return; | |
63eeaf38 | 1353 | |
9db4a9c7 | 1354 | /* Account for pipe specific data like PIPE*STAT */ |
33f3f518 | 1355 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
63eeaf38 | 1356 | if (!error) { |
9df30794 CW |
1357 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
1358 | return; | |
63eeaf38 JB |
1359 | } |
1360 | ||
5d83d294 | 1361 | DRM_INFO("capturing error event; look for more information in " |
2f86f191 | 1362 | "/sys/kernel/debug/dri/%d/i915_error_state\n", |
b6f7833b | 1363 | dev->primary->index); |
2fa772f3 | 1364 | |
742cbee8 | 1365 | kref_init(&error->ref); |
63eeaf38 JB |
1366 | error->eir = I915_READ(EIR); |
1367 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
211816ec BW |
1368 | if (HAS_HW_CONTEXTS(dev)) |
1369 | error->ccid = I915_READ(CCID); | |
be998e2e BW |
1370 | |
1371 | if (HAS_PCH_SPLIT(dev)) | |
1372 | error->ier = I915_READ(DEIER) | I915_READ(GTIER); | |
1373 | else if (IS_VALLEYVIEW(dev)) | |
1374 | error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); | |
1375 | else if (IS_GEN2(dev)) | |
1376 | error->ier = I915_READ16(IER); | |
1377 | else | |
1378 | error->ier = I915_READ(IER); | |
1379 | ||
0f3b6849 CW |
1380 | if (INTEL_INFO(dev)->gen >= 6) |
1381 | error->derrmr = I915_READ(DERRMR); | |
1382 | ||
1383 | if (IS_VALLEYVIEW(dev)) | |
1384 | error->forcewake = I915_READ(FORCEWAKE_VLV); | |
1385 | else if (INTEL_INFO(dev)->gen >= 7) | |
1386 | error->forcewake = I915_READ(FORCEWAKE_MT); | |
1387 | else if (INTEL_INFO(dev)->gen == 6) | |
1388 | error->forcewake = I915_READ(FORCEWAKE); | |
1389 | ||
9db4a9c7 JB |
1390 | for_each_pipe(pipe) |
1391 | error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); | |
d27b1e0e | 1392 | |
33f3f518 | 1393 | if (INTEL_INFO(dev)->gen >= 6) { |
f406839f | 1394 | error->error = I915_READ(ERROR_GEN6); |
33f3f518 DV |
1395 | error->done_reg = I915_READ(DONE_REG); |
1396 | } | |
d27b1e0e | 1397 | |
71e172e8 BW |
1398 | if (INTEL_INFO(dev)->gen == 7) |
1399 | error->err_int = I915_READ(GEN7_ERR_INT); | |
1400 | ||
050ee91f BW |
1401 | i915_get_extra_instdone(dev, error->extra_instdone); |
1402 | ||
748ebc60 | 1403 | i915_gem_record_fences(dev, error); |
52d39a21 | 1404 | i915_gem_record_rings(dev, error); |
9df30794 | 1405 | |
c724e8a9 | 1406 | /* Record buffers on the active and pinned lists. */ |
9df30794 | 1407 | error->active_bo = NULL; |
c724e8a9 | 1408 | error->pinned_bo = NULL; |
9df30794 | 1409 | |
bcfb2e28 CW |
1410 | i = 0; |
1411 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) | |
1412 | i++; | |
1413 | error->active_bo_count = i; | |
6c085a72 | 1414 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
1415 | if (obj->pin_count) |
1416 | i++; | |
bcfb2e28 | 1417 | error->pinned_bo_count = i - error->active_bo_count; |
c724e8a9 | 1418 | |
8e934dbf CW |
1419 | error->active_bo = NULL; |
1420 | error->pinned_bo = NULL; | |
bcfb2e28 CW |
1421 | if (i) { |
1422 | error->active_bo = kmalloc(sizeof(*error->active_bo)*i, | |
9df30794 | 1423 | GFP_ATOMIC); |
c724e8a9 CW |
1424 | if (error->active_bo) |
1425 | error->pinned_bo = | |
1426 | error->active_bo + error->active_bo_count; | |
9df30794 CW |
1427 | } |
1428 | ||
c724e8a9 CW |
1429 | if (error->active_bo) |
1430 | error->active_bo_count = | |
1b50247a CW |
1431 | capture_active_bo(error->active_bo, |
1432 | error->active_bo_count, | |
1433 | &dev_priv->mm.active_list); | |
c724e8a9 CW |
1434 | |
1435 | if (error->pinned_bo) | |
1436 | error->pinned_bo_count = | |
1b50247a CW |
1437 | capture_pinned_bo(error->pinned_bo, |
1438 | error->pinned_bo_count, | |
6c085a72 | 1439 | &dev_priv->mm.bound_list); |
c724e8a9 | 1440 | |
9df30794 CW |
1441 | do_gettimeofday(&error->time); |
1442 | ||
6ef3d427 | 1443 | error->overlay = intel_overlay_capture_error_state(dev); |
c4a1d9e4 | 1444 | error->display = intel_display_capture_error_state(dev); |
6ef3d427 | 1445 | |
99584db3 DV |
1446 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
1447 | if (dev_priv->gpu_error.first_error == NULL) { | |
1448 | dev_priv->gpu_error.first_error = error; | |
9df30794 CW |
1449 | error = NULL; |
1450 | } | |
99584db3 | 1451 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); |
9df30794 CW |
1452 | |
1453 | if (error) | |
742cbee8 | 1454 | i915_error_state_free(&error->ref); |
9df30794 CW |
1455 | } |
1456 | ||
1457 | void i915_destroy_error_state(struct drm_device *dev) | |
1458 | { | |
1459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1460 | struct drm_i915_error_state *error; | |
6dc0e816 | 1461 | unsigned long flags; |
9df30794 | 1462 | |
99584db3 DV |
1463 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
1464 | error = dev_priv->gpu_error.first_error; | |
1465 | dev_priv->gpu_error.first_error = NULL; | |
1466 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); | |
9df30794 CW |
1467 | |
1468 | if (error) | |
742cbee8 | 1469 | kref_put(&error->ref, i915_error_state_free); |
63eeaf38 | 1470 | } |
3bd3c932 CW |
1471 | #else |
1472 | #define i915_capture_error_state(x) | |
1473 | #endif | |
63eeaf38 | 1474 | |
35aed2e6 | 1475 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
1476 | { |
1477 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 1478 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 1479 | u32 eir = I915_READ(EIR); |
050ee91f | 1480 | int pipe, i; |
8a905236 | 1481 | |
35aed2e6 CW |
1482 | if (!eir) |
1483 | return; | |
8a905236 | 1484 | |
a70491cc | 1485 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 1486 | |
bd9854f9 BW |
1487 | i915_get_extra_instdone(dev, instdone); |
1488 | ||
8a905236 JB |
1489 | if (IS_G4X(dev)) { |
1490 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
1491 | u32 ipeir = I915_READ(IPEIR_I965); | |
1492 | ||
a70491cc JP |
1493 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
1494 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
1495 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
1496 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 1497 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 1498 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 1499 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 1500 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1501 | } |
1502 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
1503 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
1504 | pr_err("page table error\n"); |
1505 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 1506 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 1507 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1508 | } |
1509 | } | |
1510 | ||
a6c45cf0 | 1511 | if (!IS_GEN2(dev)) { |
8a905236 JB |
1512 | if (eir & I915_ERROR_PAGE_TABLE) { |
1513 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
1514 | pr_err("page table error\n"); |
1515 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 1516 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 1517 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1518 | } |
1519 | } | |
1520 | ||
1521 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 1522 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 1523 | for_each_pipe(pipe) |
a70491cc | 1524 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 1525 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
1526 | /* pipestat has already been acked */ |
1527 | } | |
1528 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
1529 | pr_err("instruction error\n"); |
1530 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
1531 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
1532 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 1533 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
1534 | u32 ipeir = I915_READ(IPEIR); |
1535 | ||
a70491cc JP |
1536 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
1537 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 1538 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 1539 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 1540 | POSTING_READ(IPEIR); |
8a905236 JB |
1541 | } else { |
1542 | u32 ipeir = I915_READ(IPEIR_I965); | |
1543 | ||
a70491cc JP |
1544 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
1545 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 1546 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 1547 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 1548 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 1549 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1550 | } |
1551 | } | |
1552 | ||
1553 | I915_WRITE(EIR, eir); | |
3143a2bf | 1554 | POSTING_READ(EIR); |
8a905236 JB |
1555 | eir = I915_READ(EIR); |
1556 | if (eir) { | |
1557 | /* | |
1558 | * some errors might have become stuck, | |
1559 | * mask them. | |
1560 | */ | |
1561 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
1562 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
1563 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
1564 | } | |
35aed2e6 CW |
1565 | } |
1566 | ||
1567 | /** | |
1568 | * i915_handle_error - handle an error interrupt | |
1569 | * @dev: drm device | |
1570 | * | |
1571 | * Do some basic checking of regsiter state at error interrupt time and | |
1572 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
1573 | * sure we get a record and make it available in debugfs. Fire a uevent | |
1574 | * so userspace knows something bad happened (should trigger collection | |
1575 | * of a ring dump etc.). | |
1576 | */ | |
527f9e90 | 1577 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
1578 | { |
1579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b4519513 CW |
1580 | struct intel_ring_buffer *ring; |
1581 | int i; | |
35aed2e6 CW |
1582 | |
1583 | i915_capture_error_state(dev); | |
1584 | i915_report_and_clear_eir(dev); | |
8a905236 | 1585 | |
ba1234d1 | 1586 | if (wedged) { |
f69061be DV |
1587 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
1588 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 1589 | |
11ed50ec | 1590 | /* |
1f83fee0 DV |
1591 | * Wakeup waiting processes so that the reset work item |
1592 | * doesn't deadlock trying to grab various locks. | |
11ed50ec | 1593 | */ |
b4519513 CW |
1594 | for_each_ring(ring, dev_priv, i) |
1595 | wake_up_all(&ring->irq_queue); | |
11ed50ec BG |
1596 | } |
1597 | ||
99584db3 | 1598 | queue_work(dev_priv->wq, &dev_priv->gpu_error.work); |
8a905236 JB |
1599 | } |
1600 | ||
21ad8330 | 1601 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
4e5359cd SF |
1602 | { |
1603 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1604 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1605 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 1606 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
1607 | struct intel_unpin_work *work; |
1608 | unsigned long flags; | |
1609 | bool stall_detected; | |
1610 | ||
1611 | /* Ignore early vblank irqs */ | |
1612 | if (intel_crtc == NULL) | |
1613 | return; | |
1614 | ||
1615 | spin_lock_irqsave(&dev->event_lock, flags); | |
1616 | work = intel_crtc->unpin_work; | |
1617 | ||
e7d841ca CW |
1618 | if (work == NULL || |
1619 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || | |
1620 | !work->enable_stall_check) { | |
4e5359cd SF |
1621 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
1622 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1623 | return; | |
1624 | } | |
1625 | ||
1626 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 1627 | obj = work->pending_flip_obj; |
a6c45cf0 | 1628 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 1629 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 AR |
1630 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
1631 | obj->gtt_offset; | |
4e5359cd | 1632 | } else { |
9db4a9c7 | 1633 | int dspaddr = DSPADDR(intel_crtc->plane); |
05394f39 | 1634 | stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |
01f2c773 | 1635 | crtc->y * crtc->fb->pitches[0] + |
4e5359cd SF |
1636 | crtc->x * crtc->fb->bits_per_pixel/8); |
1637 | } | |
1638 | ||
1639 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1640 | ||
1641 | if (stall_detected) { | |
1642 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
1643 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
1644 | } | |
1645 | } | |
1646 | ||
42f52ef8 KP |
1647 | /* Called from drm generic code, passed 'crtc' which |
1648 | * we use as a pipe index | |
1649 | */ | |
f71d4af4 | 1650 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1651 | { |
1652 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1653 | unsigned long irqflags; |
71e0ffa5 | 1654 | |
5eddb70b | 1655 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1656 | return -EINVAL; |
0a3e67a4 | 1657 | |
1ec14ad3 | 1658 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 1659 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1660 | i915_enable_pipestat(dev_priv, pipe, |
1661 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1662 | else |
7c463586 KP |
1663 | i915_enable_pipestat(dev_priv, pipe, |
1664 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
8692d00e CW |
1665 | |
1666 | /* maintain vblank delivery even in deep C-states */ | |
1667 | if (dev_priv->info->gen == 3) | |
6b26c86d | 1668 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 1669 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 1670 | |
0a3e67a4 JB |
1671 | return 0; |
1672 | } | |
1673 | ||
f71d4af4 | 1674 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1675 | { |
1676 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1677 | unsigned long irqflags; | |
1678 | ||
1679 | if (!i915_pipe_enabled(dev, pipe)) | |
1680 | return -EINVAL; | |
1681 | ||
1682 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1683 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | |
0206e353 | 1684 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
f796cf8f JB |
1685 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1686 | ||
1687 | return 0; | |
1688 | } | |
1689 | ||
f71d4af4 | 1690 | static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) |
b1f14ad0 JB |
1691 | { |
1692 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1693 | unsigned long irqflags; | |
1694 | ||
1695 | if (!i915_pipe_enabled(dev, pipe)) | |
1696 | return -EINVAL; | |
1697 | ||
1698 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b615b57a CW |
1699 | ironlake_enable_display_irq(dev_priv, |
1700 | DE_PIPEA_VBLANK_IVB << (5 * pipe)); | |
b1f14ad0 JB |
1701 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1702 | ||
1703 | return 0; | |
1704 | } | |
1705 | ||
7e231dbe JB |
1706 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
1707 | { | |
1708 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1709 | unsigned long irqflags; | |
31acc7f5 | 1710 | u32 imr; |
7e231dbe JB |
1711 | |
1712 | if (!i915_pipe_enabled(dev, pipe)) | |
1713 | return -EINVAL; | |
1714 | ||
1715 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7e231dbe | 1716 | imr = I915_READ(VLV_IMR); |
31acc7f5 | 1717 | if (pipe == 0) |
7e231dbe | 1718 | imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 1719 | else |
7e231dbe | 1720 | imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 1721 | I915_WRITE(VLV_IMR, imr); |
31acc7f5 JB |
1722 | i915_enable_pipestat(dev_priv, pipe, |
1723 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe JB |
1724 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1725 | ||
1726 | return 0; | |
1727 | } | |
1728 | ||
42f52ef8 KP |
1729 | /* Called from drm generic code, passed 'crtc' which |
1730 | * we use as a pipe index | |
1731 | */ | |
f71d4af4 | 1732 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1733 | { |
1734 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1735 | unsigned long irqflags; |
0a3e67a4 | 1736 | |
1ec14ad3 | 1737 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8692d00e | 1738 | if (dev_priv->info->gen == 3) |
6b26c86d | 1739 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 1740 | |
f796cf8f JB |
1741 | i915_disable_pipestat(dev_priv, pipe, |
1742 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1743 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
1744 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1745 | } | |
1746 | ||
f71d4af4 | 1747 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1748 | { |
1749 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1750 | unsigned long irqflags; | |
1751 | ||
1752 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1753 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? | |
0206e353 | 1754 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
1ec14ad3 | 1755 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
0a3e67a4 JB |
1756 | } |
1757 | ||
f71d4af4 | 1758 | static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) |
b1f14ad0 JB |
1759 | { |
1760 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1761 | unsigned long irqflags; | |
1762 | ||
1763 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b615b57a CW |
1764 | ironlake_disable_display_irq(dev_priv, |
1765 | DE_PIPEA_VBLANK_IVB << (pipe * 5)); | |
b1f14ad0 JB |
1766 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1767 | } | |
1768 | ||
7e231dbe JB |
1769 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
1770 | { | |
1771 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1772 | unsigned long irqflags; | |
31acc7f5 | 1773 | u32 imr; |
7e231dbe JB |
1774 | |
1775 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 JB |
1776 | i915_disable_pipestat(dev_priv, pipe, |
1777 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe | 1778 | imr = I915_READ(VLV_IMR); |
31acc7f5 | 1779 | if (pipe == 0) |
7e231dbe | 1780 | imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 1781 | else |
7e231dbe | 1782 | imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 1783 | I915_WRITE(VLV_IMR, imr); |
7e231dbe JB |
1784 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1785 | } | |
1786 | ||
893eead0 CW |
1787 | static u32 |
1788 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 1789 | { |
893eead0 CW |
1790 | return list_entry(ring->request_list.prev, |
1791 | struct drm_i915_gem_request, list)->seqno; | |
1792 | } | |
1793 | ||
1794 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) | |
1795 | { | |
1796 | if (list_empty(&ring->request_list) || | |
b2eadbc8 CW |
1797 | i915_seqno_passed(ring->get_seqno(ring, false), |
1798 | ring_last_seqno(ring))) { | |
893eead0 | 1799 | /* Issue a wake-up to catch stuck h/w. */ |
9574b3fe BW |
1800 | if (waitqueue_active(&ring->irq_queue)) { |
1801 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
1802 | ring->name); | |
893eead0 CW |
1803 | wake_up_all(&ring->irq_queue); |
1804 | *err = true; | |
1805 | } | |
1806 | return true; | |
1807 | } | |
1808 | return false; | |
f65d9421 BG |
1809 | } |
1810 | ||
a24a11e6 CW |
1811 | static bool semaphore_passed(struct intel_ring_buffer *ring) |
1812 | { | |
1813 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1814 | u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; | |
1815 | struct intel_ring_buffer *signaller; | |
1816 | u32 cmd, ipehr, acthd_min; | |
1817 | ||
1818 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
1819 | if ((ipehr & ~(0x3 << 16)) != | |
1820 | (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) | |
1821 | return false; | |
1822 | ||
1823 | /* ACTHD is likely pointing to the dword after the actual command, | |
1824 | * so scan backwards until we find the MBOX. | |
1825 | */ | |
1826 | acthd_min = max((int)acthd - 3 * 4, 0); | |
1827 | do { | |
1828 | cmd = ioread32(ring->virtual_start + acthd); | |
1829 | if (cmd == ipehr) | |
1830 | break; | |
1831 | ||
1832 | acthd -= 4; | |
1833 | if (acthd < acthd_min) | |
1834 | return false; | |
1835 | } while (1); | |
1836 | ||
1837 | signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; | |
1838 | return i915_seqno_passed(signaller->get_seqno(signaller, false), | |
1839 | ioread32(ring->virtual_start+acthd+4)+1); | |
1840 | } | |
1841 | ||
1ec14ad3 CW |
1842 | static bool kick_ring(struct intel_ring_buffer *ring) |
1843 | { | |
1844 | struct drm_device *dev = ring->dev; | |
1845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1846 | u32 tmp = I915_READ_CTL(ring); | |
1847 | if (tmp & RING_WAIT) { | |
1848 | DRM_ERROR("Kicking stuck wait on %s\n", | |
1849 | ring->name); | |
1850 | I915_WRITE_CTL(ring, tmp); | |
1851 | return true; | |
1852 | } | |
a24a11e6 CW |
1853 | |
1854 | if (INTEL_INFO(dev)->gen >= 6 && | |
1855 | tmp & RING_WAIT_SEMAPHORE && | |
1856 | semaphore_passed(ring)) { | |
1857 | DRM_ERROR("Kicking stuck semaphore on %s\n", | |
1858 | ring->name); | |
1859 | I915_WRITE_CTL(ring, tmp); | |
1860 | return true; | |
1861 | } | |
1ec14ad3 CW |
1862 | return false; |
1863 | } | |
1864 | ||
d1e61e7f CW |
1865 | static bool i915_hangcheck_hung(struct drm_device *dev) |
1866 | { | |
1867 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1868 | ||
99584db3 | 1869 | if (dev_priv->gpu_error.hangcheck_count++ > 1) { |
b4519513 CW |
1870 | bool hung = true; |
1871 | ||
d1e61e7f CW |
1872 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); |
1873 | i915_handle_error(dev, true); | |
1874 | ||
1875 | if (!IS_GEN2(dev)) { | |
b4519513 CW |
1876 | struct intel_ring_buffer *ring; |
1877 | int i; | |
1878 | ||
d1e61e7f CW |
1879 | /* Is the chip hanging on a WAIT_FOR_EVENT? |
1880 | * If so we can simply poke the RB_WAIT bit | |
1881 | * and break the hang. This should work on | |
1882 | * all but the second generation chipsets. | |
1883 | */ | |
b4519513 CW |
1884 | for_each_ring(ring, dev_priv, i) |
1885 | hung &= !kick_ring(ring); | |
d1e61e7f CW |
1886 | } |
1887 | ||
b4519513 | 1888 | return hung; |
d1e61e7f CW |
1889 | } |
1890 | ||
1891 | return false; | |
1892 | } | |
1893 | ||
f65d9421 BG |
1894 | /** |
1895 | * This is called when the chip hasn't reported back with completed | |
1896 | * batchbuffers in a long time. The first time this is called we simply record | |
1897 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1898 | * again, we assume the chip is wedged and try to fix it. | |
1899 | */ | |
1900 | void i915_hangcheck_elapsed(unsigned long data) | |
1901 | { | |
1902 | struct drm_device *dev = (struct drm_device *)data; | |
1903 | drm_i915_private_t *dev_priv = dev->dev_private; | |
bd9854f9 | 1904 | uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG]; |
b4519513 CW |
1905 | struct intel_ring_buffer *ring; |
1906 | bool err = false, idle; | |
1907 | int i; | |
893eead0 | 1908 | |
3e0dc6b0 BW |
1909 | if (!i915_enable_hangcheck) |
1910 | return; | |
1911 | ||
b4519513 CW |
1912 | memset(acthd, 0, sizeof(acthd)); |
1913 | idle = true; | |
1914 | for_each_ring(ring, dev_priv, i) { | |
1915 | idle &= i915_hangcheck_ring_idle(ring, &err); | |
1916 | acthd[i] = intel_ring_get_active_head(ring); | |
1917 | } | |
1918 | ||
893eead0 | 1919 | /* If all work is done then ACTHD clearly hasn't advanced. */ |
b4519513 | 1920 | if (idle) { |
d1e61e7f CW |
1921 | if (err) { |
1922 | if (i915_hangcheck_hung(dev)) | |
1923 | return; | |
1924 | ||
893eead0 | 1925 | goto repeat; |
d1e61e7f CW |
1926 | } |
1927 | ||
99584db3 | 1928 | dev_priv->gpu_error.hangcheck_count = 0; |
893eead0 CW |
1929 | return; |
1930 | } | |
b9201c14 | 1931 | |
bd9854f9 | 1932 | i915_get_extra_instdone(dev, instdone); |
99584db3 DV |
1933 | if (memcmp(dev_priv->gpu_error.last_acthd, acthd, |
1934 | sizeof(acthd)) == 0 && | |
1935 | memcmp(dev_priv->gpu_error.prev_instdone, instdone, | |
1936 | sizeof(instdone)) == 0) { | |
d1e61e7f | 1937 | if (i915_hangcheck_hung(dev)) |
cbb465e7 | 1938 | return; |
cbb465e7 | 1939 | } else { |
99584db3 | 1940 | dev_priv->gpu_error.hangcheck_count = 0; |
cbb465e7 | 1941 | |
99584db3 DV |
1942 | memcpy(dev_priv->gpu_error.last_acthd, acthd, |
1943 | sizeof(acthd)); | |
1944 | memcpy(dev_priv->gpu_error.prev_instdone, instdone, | |
1945 | sizeof(instdone)); | |
cbb465e7 | 1946 | } |
f65d9421 | 1947 | |
893eead0 | 1948 | repeat: |
f65d9421 | 1949 | /* Reset timer case chip hangs without another request being added */ |
99584db3 | 1950 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
cecc21fe | 1951 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
f65d9421 BG |
1952 | } |
1953 | ||
1da177e4 LT |
1954 | /* drm_dma.h hooks |
1955 | */ | |
f71d4af4 | 1956 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1957 | { |
1958 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1959 | ||
4697995b JB |
1960 | atomic_set(&dev_priv->irq_received, 0); |
1961 | ||
036a4a7d | 1962 | I915_WRITE(HWSTAM, 0xeffe); |
bdfcdb63 | 1963 | |
036a4a7d ZW |
1964 | /* XXX hotplug from PCH */ |
1965 | ||
1966 | I915_WRITE(DEIMR, 0xffffffff); | |
1967 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 1968 | POSTING_READ(DEIER); |
036a4a7d ZW |
1969 | |
1970 | /* and GT */ | |
1971 | I915_WRITE(GTIMR, 0xffffffff); | |
1972 | I915_WRITE(GTIER, 0x0); | |
3143a2bf | 1973 | POSTING_READ(GTIER); |
c650156a ZW |
1974 | |
1975 | /* south display irq */ | |
1976 | I915_WRITE(SDEIMR, 0xffffffff); | |
1977 | I915_WRITE(SDEIER, 0x0); | |
3143a2bf | 1978 | POSTING_READ(SDEIER); |
036a4a7d ZW |
1979 | } |
1980 | ||
7e231dbe JB |
1981 | static void valleyview_irq_preinstall(struct drm_device *dev) |
1982 | { | |
1983 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1984 | int pipe; | |
1985 | ||
1986 | atomic_set(&dev_priv->irq_received, 0); | |
1987 | ||
7e231dbe JB |
1988 | /* VLV magic */ |
1989 | I915_WRITE(VLV_IMR, 0); | |
1990 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
1991 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
1992 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
1993 | ||
7e231dbe JB |
1994 | /* and GT */ |
1995 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1996 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1997 | I915_WRITE(GTIMR, 0xffffffff); | |
1998 | I915_WRITE(GTIER, 0x0); | |
1999 | POSTING_READ(GTIER); | |
2000 | ||
2001 | I915_WRITE(DPINVGTT, 0xff); | |
2002 | ||
2003 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2004 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2005 | for_each_pipe(pipe) | |
2006 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2007 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2008 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2009 | I915_WRITE(VLV_IER, 0x0); | |
2010 | POSTING_READ(VLV_IER); | |
2011 | } | |
2012 | ||
7fe0b973 KP |
2013 | /* |
2014 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
2015 | * duration to 2ms (which is the minimum in the Display Port spec) | |
2016 | * | |
2017 | * This register is the same on all known PCH chips. | |
2018 | */ | |
2019 | ||
d46da437 | 2020 | static void ibx_enable_hotplug(struct drm_device *dev) |
7fe0b973 KP |
2021 | { |
2022 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2023 | u32 hotplug; | |
2024 | ||
2025 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
2026 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
2027 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
2028 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
2029 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
2030 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
2031 | } | |
2032 | ||
d46da437 PZ |
2033 | static void ibx_irq_postinstall(struct drm_device *dev) |
2034 | { | |
2035 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2036 | u32 mask; | |
2037 | ||
2038 | if (HAS_PCH_IBX(dev)) | |
2039 | mask = SDE_HOTPLUG_MASK | | |
2040 | SDE_GMBUS | | |
2041 | SDE_AUX_MASK; | |
2042 | else | |
2043 | mask = SDE_HOTPLUG_MASK_CPT | | |
2044 | SDE_GMBUS_CPT | | |
2045 | SDE_AUX_MASK_CPT; | |
2046 | ||
2047 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
2048 | I915_WRITE(SDEIMR, ~mask); | |
2049 | I915_WRITE(SDEIER, mask); | |
2050 | POSTING_READ(SDEIER); | |
2051 | ||
2052 | ibx_enable_hotplug(dev); | |
2053 | } | |
2054 | ||
f71d4af4 | 2055 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
2056 | { |
2057 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2058 | /* enable kind of interrupts always enabled */ | |
013d5aa2 | 2059 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
ce99c256 DV |
2060 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | |
2061 | DE_AUX_CHANNEL_A; | |
1ec14ad3 | 2062 | u32 render_irqs; |
036a4a7d | 2063 | |
1ec14ad3 | 2064 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
2065 | |
2066 | /* should always can generate irq */ | |
2067 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 CW |
2068 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
2069 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); | |
3143a2bf | 2070 | POSTING_READ(DEIER); |
036a4a7d | 2071 | |
1ec14ad3 | 2072 | dev_priv->gt_irq_mask = ~0; |
036a4a7d ZW |
2073 | |
2074 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1ec14ad3 | 2075 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
881f47b6 | 2076 | |
1ec14ad3 CW |
2077 | if (IS_GEN6(dev)) |
2078 | render_irqs = | |
2079 | GT_USER_INTERRUPT | | |
e2a1e2f0 BW |
2080 | GEN6_BSD_USER_INTERRUPT | |
2081 | GEN6_BLITTER_USER_INTERRUPT; | |
1ec14ad3 CW |
2082 | else |
2083 | render_irqs = | |
88f23b8f | 2084 | GT_USER_INTERRUPT | |
c6df541c | 2085 | GT_PIPE_NOTIFY | |
1ec14ad3 CW |
2086 | GT_BSD_USER_INTERRUPT; |
2087 | I915_WRITE(GTIER, render_irqs); | |
3143a2bf | 2088 | POSTING_READ(GTIER); |
036a4a7d | 2089 | |
d46da437 | 2090 | ibx_irq_postinstall(dev); |
7fe0b973 | 2091 | |
f97108d1 JB |
2092 | if (IS_IRONLAKE_M(dev)) { |
2093 | /* Clear & enable PCU event interrupts */ | |
2094 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
2095 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
2096 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
2097 | } | |
2098 | ||
036a4a7d ZW |
2099 | return 0; |
2100 | } | |
2101 | ||
f71d4af4 | 2102 | static int ivybridge_irq_postinstall(struct drm_device *dev) |
b1f14ad0 JB |
2103 | { |
2104 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2105 | /* enable kind of interrupts always enabled */ | |
b615b57a CW |
2106 | u32 display_mask = |
2107 | DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | | |
2108 | DE_PLANEC_FLIP_DONE_IVB | | |
2109 | DE_PLANEB_FLIP_DONE_IVB | | |
ce99c256 DV |
2110 | DE_PLANEA_FLIP_DONE_IVB | |
2111 | DE_AUX_CHANNEL_A_IVB; | |
b1f14ad0 | 2112 | u32 render_irqs; |
b1f14ad0 | 2113 | |
b1f14ad0 JB |
2114 | dev_priv->irq_mask = ~display_mask; |
2115 | ||
2116 | /* should always can generate irq */ | |
2117 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
2118 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
b615b57a CW |
2119 | I915_WRITE(DEIER, |
2120 | display_mask | | |
2121 | DE_PIPEC_VBLANK_IVB | | |
2122 | DE_PIPEB_VBLANK_IVB | | |
2123 | DE_PIPEA_VBLANK_IVB); | |
b1f14ad0 JB |
2124 | POSTING_READ(DEIER); |
2125 | ||
15b9f80e | 2126 | dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT; |
b1f14ad0 JB |
2127 | |
2128 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2129 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
2130 | ||
e2a1e2f0 | 2131 | render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | |
15b9f80e | 2132 | GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT; |
b1f14ad0 JB |
2133 | I915_WRITE(GTIER, render_irqs); |
2134 | POSTING_READ(GTIER); | |
2135 | ||
d46da437 | 2136 | ibx_irq_postinstall(dev); |
7fe0b973 | 2137 | |
b1f14ad0 JB |
2138 | return 0; |
2139 | } | |
2140 | ||
7e231dbe JB |
2141 | static int valleyview_irq_postinstall(struct drm_device *dev) |
2142 | { | |
2143 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7e231dbe | 2144 | u32 enable_mask; |
31acc7f5 | 2145 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; |
3bcedbe5 | 2146 | u32 render_irqs; |
7e231dbe JB |
2147 | u16 msid; |
2148 | ||
2149 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; | |
31acc7f5 JB |
2150 | enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
2151 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2152 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
7e231dbe JB |
2153 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
2154 | ||
31acc7f5 JB |
2155 | /* |
2156 | *Leave vblank interrupts masked initially. enable/disable will | |
2157 | * toggle them based on usage. | |
2158 | */ | |
2159 | dev_priv->irq_mask = (~enable_mask) | | |
2160 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2161 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
7e231dbe | 2162 | |
7e231dbe JB |
2163 | /* Hack for broken MSIs on VLV */ |
2164 | pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000); | |
2165 | pci_read_config_word(dev->pdev, 0x98, &msid); | |
2166 | msid &= 0xff; /* mask out delivery bits */ | |
2167 | msid |= (1<<14); | |
2168 | pci_write_config_word(dev_priv->dev->pdev, 0x98, msid); | |
2169 | ||
20afbda2 DV |
2170 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2171 | POSTING_READ(PORT_HOTPLUG_EN); | |
2172 | ||
7e231dbe JB |
2173 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
2174 | I915_WRITE(VLV_IER, enable_mask); | |
2175 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2176 | I915_WRITE(PIPESTAT(0), 0xffff); | |
2177 | I915_WRITE(PIPESTAT(1), 0xffff); | |
2178 | POSTING_READ(VLV_IER); | |
2179 | ||
31acc7f5 | 2180 | i915_enable_pipestat(dev_priv, 0, pipestat_enable); |
515ac2bb | 2181 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); |
31acc7f5 JB |
2182 | i915_enable_pipestat(dev_priv, 1, pipestat_enable); |
2183 | ||
7e231dbe JB |
2184 | I915_WRITE(VLV_IIR, 0xffffffff); |
2185 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2186 | ||
7e231dbe | 2187 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
31acc7f5 | 2188 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
3bcedbe5 JB |
2189 | |
2190 | render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | | |
2191 | GEN6_BLITTER_USER_INTERRUPT; | |
2192 | I915_WRITE(GTIER, render_irqs); | |
7e231dbe JB |
2193 | POSTING_READ(GTIER); |
2194 | ||
2195 | /* ack & enable invalid PTE error interrupts */ | |
2196 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
2197 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
2198 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
2199 | #endif | |
2200 | ||
2201 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
2202 | |
2203 | return 0; | |
2204 | } | |
2205 | ||
2206 | static void valleyview_hpd_irq_setup(struct drm_device *dev) | |
2207 | { | |
2208 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2209 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
2210 | ||
7e231dbe | 2211 | /* Note HDMI and DP share bits */ |
26739f12 DV |
2212 | if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS) |
2213 | hotplug_en |= PORTB_HOTPLUG_INT_EN; | |
2214 | if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS) | |
2215 | hotplug_en |= PORTC_HOTPLUG_INT_EN; | |
2216 | if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS) | |
2217 | hotplug_en |= PORTD_HOTPLUG_INT_EN; | |
ae33cdcf | 2218 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) |
7e231dbe | 2219 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
ae33cdcf | 2220 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) |
7e231dbe JB |
2221 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; |
2222 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { | |
2223 | hotplug_en |= CRT_HOTPLUG_INT_EN; | |
2224 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
2225 | } | |
7e231dbe JB |
2226 | |
2227 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
7e231dbe JB |
2228 | } |
2229 | ||
7e231dbe JB |
2230 | static void valleyview_irq_uninstall(struct drm_device *dev) |
2231 | { | |
2232 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2233 | int pipe; | |
2234 | ||
2235 | if (!dev_priv) | |
2236 | return; | |
2237 | ||
7e231dbe JB |
2238 | for_each_pipe(pipe) |
2239 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2240 | ||
2241 | I915_WRITE(HWSTAM, 0xffffffff); | |
2242 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2243 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2244 | for_each_pipe(pipe) | |
2245 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2246 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2247 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2248 | I915_WRITE(VLV_IER, 0x0); | |
2249 | POSTING_READ(VLV_IER); | |
2250 | } | |
2251 | ||
f71d4af4 | 2252 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
2253 | { |
2254 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
4697995b JB |
2255 | |
2256 | if (!dev_priv) | |
2257 | return; | |
2258 | ||
036a4a7d ZW |
2259 | I915_WRITE(HWSTAM, 0xffffffff); |
2260 | ||
2261 | I915_WRITE(DEIMR, 0xffffffff); | |
2262 | I915_WRITE(DEIER, 0x0); | |
2263 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
2264 | ||
2265 | I915_WRITE(GTIMR, 0xffffffff); | |
2266 | I915_WRITE(GTIER, 0x0); | |
2267 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
192aac1f KP |
2268 | |
2269 | I915_WRITE(SDEIMR, 0xffffffff); | |
2270 | I915_WRITE(SDEIER, 0x0); | |
2271 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
036a4a7d ZW |
2272 | } |
2273 | ||
a266c7d5 | 2274 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
2275 | { |
2276 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 2277 | int pipe; |
91e3738e | 2278 | |
a266c7d5 | 2279 | atomic_set(&dev_priv->irq_received, 0); |
5ca58282 | 2280 | |
9db4a9c7 JB |
2281 | for_each_pipe(pipe) |
2282 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
2283 | I915_WRITE16(IMR, 0xffff); |
2284 | I915_WRITE16(IER, 0x0); | |
2285 | POSTING_READ16(IER); | |
c2798b19 CW |
2286 | } |
2287 | ||
2288 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
2289 | { | |
2290 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2291 | ||
c2798b19 CW |
2292 | I915_WRITE16(EMR, |
2293 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
2294 | ||
2295 | /* Unmask the interrupts that we always want on. */ | |
2296 | dev_priv->irq_mask = | |
2297 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2298 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2299 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2300 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
2301 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2302 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
2303 | ||
2304 | I915_WRITE16(IER, | |
2305 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2306 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2307 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
2308 | I915_USER_INTERRUPT); | |
2309 | POSTING_READ16(IER); | |
2310 | ||
2311 | return 0; | |
2312 | } | |
2313 | ||
90a72f87 VS |
2314 | /* |
2315 | * Returns true when a page flip has completed. | |
2316 | */ | |
2317 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
2318 | int pipe, u16 iir) | |
2319 | { | |
2320 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2321 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe); | |
2322 | ||
2323 | if (!drm_handle_vblank(dev, pipe)) | |
2324 | return false; | |
2325 | ||
2326 | if ((iir & flip_pending) == 0) | |
2327 | return false; | |
2328 | ||
2329 | intel_prepare_page_flip(dev, pipe); | |
2330 | ||
2331 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
2332 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
2333 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
2334 | * the flip is completed (no longer pending). Since this doesn't raise | |
2335 | * an interrupt per se, we watch for the change at vblank. | |
2336 | */ | |
2337 | if (I915_READ16(ISR) & flip_pending) | |
2338 | return false; | |
2339 | ||
2340 | intel_finish_page_flip(dev, pipe); | |
2341 | ||
2342 | return true; | |
2343 | } | |
2344 | ||
ff1f525e | 2345 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 CW |
2346 | { |
2347 | struct drm_device *dev = (struct drm_device *) arg; | |
2348 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
c2798b19 CW |
2349 | u16 iir, new_iir; |
2350 | u32 pipe_stats[2]; | |
2351 | unsigned long irqflags; | |
2352 | int irq_received; | |
2353 | int pipe; | |
2354 | u16 flip_mask = | |
2355 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2356 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
2357 | ||
2358 | atomic_inc(&dev_priv->irq_received); | |
2359 | ||
2360 | iir = I915_READ16(IIR); | |
2361 | if (iir == 0) | |
2362 | return IRQ_NONE; | |
2363 | ||
2364 | while (iir & ~flip_mask) { | |
2365 | /* Can't rely on pipestat interrupt bit in iir as it might | |
2366 | * have been cleared after the pipestat interrupt was received. | |
2367 | * It doesn't set the bit in iir again, but it still produces | |
2368 | * interrupts (for non-MSI). | |
2369 | */ | |
2370 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
2371 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
2372 | i915_handle_error(dev, false); | |
2373 | ||
2374 | for_each_pipe(pipe) { | |
2375 | int reg = PIPESTAT(pipe); | |
2376 | pipe_stats[pipe] = I915_READ(reg); | |
2377 | ||
2378 | /* | |
2379 | * Clear the PIPE*STAT regs before the IIR | |
2380 | */ | |
2381 | if (pipe_stats[pipe] & 0x8000ffff) { | |
2382 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
2383 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
2384 | pipe_name(pipe)); | |
2385 | I915_WRITE(reg, pipe_stats[pipe]); | |
2386 | irq_received = 1; | |
2387 | } | |
2388 | } | |
2389 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2390 | ||
2391 | I915_WRITE16(IIR, iir & ~flip_mask); | |
2392 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
2393 | ||
d05c617e | 2394 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
2395 | |
2396 | if (iir & I915_USER_INTERRUPT) | |
2397 | notify_ring(dev, &dev_priv->ring[RCS]); | |
2398 | ||
2399 | if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && | |
90a72f87 VS |
2400 | i8xx_handle_vblank(dev, 0, iir)) |
2401 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0); | |
c2798b19 CW |
2402 | |
2403 | if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && | |
90a72f87 VS |
2404 | i8xx_handle_vblank(dev, 1, iir)) |
2405 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1); | |
c2798b19 CW |
2406 | |
2407 | iir = new_iir; | |
2408 | } | |
2409 | ||
2410 | return IRQ_HANDLED; | |
2411 | } | |
2412 | ||
2413 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
2414 | { | |
2415 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2416 | int pipe; | |
2417 | ||
c2798b19 CW |
2418 | for_each_pipe(pipe) { |
2419 | /* Clear enable bits; then clear status bits */ | |
2420 | I915_WRITE(PIPESTAT(pipe), 0); | |
2421 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
2422 | } | |
2423 | I915_WRITE16(IMR, 0xffff); | |
2424 | I915_WRITE16(IER, 0x0); | |
2425 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
2426 | } | |
2427 | ||
a266c7d5 CW |
2428 | static void i915_irq_preinstall(struct drm_device * dev) |
2429 | { | |
2430 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2431 | int pipe; | |
2432 | ||
2433 | atomic_set(&dev_priv->irq_received, 0); | |
2434 | ||
2435 | if (I915_HAS_HOTPLUG(dev)) { | |
2436 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2437 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2438 | } | |
2439 | ||
00d98ebd | 2440 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
2441 | for_each_pipe(pipe) |
2442 | I915_WRITE(PIPESTAT(pipe), 0); | |
2443 | I915_WRITE(IMR, 0xffffffff); | |
2444 | I915_WRITE(IER, 0x0); | |
2445 | POSTING_READ(IER); | |
2446 | } | |
2447 | ||
2448 | static int i915_irq_postinstall(struct drm_device *dev) | |
2449 | { | |
2450 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
38bde180 | 2451 | u32 enable_mask; |
a266c7d5 | 2452 | |
38bde180 CW |
2453 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
2454 | ||
2455 | /* Unmask the interrupts that we always want on. */ | |
2456 | dev_priv->irq_mask = | |
2457 | ~(I915_ASLE_INTERRUPT | | |
2458 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2459 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2460 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2461 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
2462 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2463 | ||
2464 | enable_mask = | |
2465 | I915_ASLE_INTERRUPT | | |
2466 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2467 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2468 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
2469 | I915_USER_INTERRUPT; | |
2470 | ||
a266c7d5 | 2471 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
2472 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2473 | POSTING_READ(PORT_HOTPLUG_EN); | |
2474 | ||
a266c7d5 CW |
2475 | /* Enable in IER... */ |
2476 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
2477 | /* and unmask in IMR */ | |
2478 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
2479 | } | |
2480 | ||
a266c7d5 CW |
2481 | I915_WRITE(IMR, dev_priv->irq_mask); |
2482 | I915_WRITE(IER, enable_mask); | |
2483 | POSTING_READ(IER); | |
2484 | ||
20afbda2 DV |
2485 | intel_opregion_enable_asle(dev); |
2486 | ||
2487 | return 0; | |
2488 | } | |
2489 | ||
2490 | static void i915_hpd_irq_setup(struct drm_device *dev) | |
2491 | { | |
2492 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2493 | u32 hotplug_en; | |
2494 | ||
a266c7d5 | 2495 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 | 2496 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
a266c7d5 | 2497 | |
26739f12 DV |
2498 | if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS) |
2499 | hotplug_en |= PORTB_HOTPLUG_INT_EN; | |
2500 | if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS) | |
2501 | hotplug_en |= PORTC_HOTPLUG_INT_EN; | |
2502 | if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS) | |
2503 | hotplug_en |= PORTD_HOTPLUG_INT_EN; | |
084b612e | 2504 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) |
a266c7d5 | 2505 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
084b612e | 2506 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) |
a266c7d5 CW |
2507 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; |
2508 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { | |
2509 | hotplug_en |= CRT_HOTPLUG_INT_EN; | |
a266c7d5 CW |
2510 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
2511 | } | |
2512 | ||
2513 | /* Ignore TV since it's buggy */ | |
2514 | ||
2515 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
2516 | } | |
a266c7d5 CW |
2517 | } |
2518 | ||
90a72f87 VS |
2519 | /* |
2520 | * Returns true when a page flip has completed. | |
2521 | */ | |
2522 | static bool i915_handle_vblank(struct drm_device *dev, | |
2523 | int plane, int pipe, u32 iir) | |
2524 | { | |
2525 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2526 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
2527 | ||
2528 | if (!drm_handle_vblank(dev, pipe)) | |
2529 | return false; | |
2530 | ||
2531 | if ((iir & flip_pending) == 0) | |
2532 | return false; | |
2533 | ||
2534 | intel_prepare_page_flip(dev, plane); | |
2535 | ||
2536 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
2537 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
2538 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
2539 | * the flip is completed (no longer pending). Since this doesn't raise | |
2540 | * an interrupt per se, we watch for the change at vblank. | |
2541 | */ | |
2542 | if (I915_READ(ISR) & flip_pending) | |
2543 | return false; | |
2544 | ||
2545 | intel_finish_page_flip(dev, pipe); | |
2546 | ||
2547 | return true; | |
2548 | } | |
2549 | ||
ff1f525e | 2550 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 CW |
2551 | { |
2552 | struct drm_device *dev = (struct drm_device *) arg; | |
2553 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8291ee90 | 2554 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 2555 | unsigned long irqflags; |
38bde180 CW |
2556 | u32 flip_mask = |
2557 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2558 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 2559 | int pipe, ret = IRQ_NONE; |
a266c7d5 CW |
2560 | |
2561 | atomic_inc(&dev_priv->irq_received); | |
2562 | ||
2563 | iir = I915_READ(IIR); | |
38bde180 CW |
2564 | do { |
2565 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 2566 | bool blc_event = false; |
a266c7d5 CW |
2567 | |
2568 | /* Can't rely on pipestat interrupt bit in iir as it might | |
2569 | * have been cleared after the pipestat interrupt was received. | |
2570 | * It doesn't set the bit in iir again, but it still produces | |
2571 | * interrupts (for non-MSI). | |
2572 | */ | |
2573 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
2574 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
2575 | i915_handle_error(dev, false); | |
2576 | ||
2577 | for_each_pipe(pipe) { | |
2578 | int reg = PIPESTAT(pipe); | |
2579 | pipe_stats[pipe] = I915_READ(reg); | |
2580 | ||
38bde180 | 2581 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 CW |
2582 | if (pipe_stats[pipe] & 0x8000ffff) { |
2583 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
2584 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
2585 | pipe_name(pipe)); | |
2586 | I915_WRITE(reg, pipe_stats[pipe]); | |
38bde180 | 2587 | irq_received = true; |
a266c7d5 CW |
2588 | } |
2589 | } | |
2590 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2591 | ||
2592 | if (!irq_received) | |
2593 | break; | |
2594 | ||
a266c7d5 CW |
2595 | /* Consume port. Then clear IIR or we'll miss events */ |
2596 | if ((I915_HAS_HOTPLUG(dev)) && | |
2597 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
2598 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
2599 | ||
2600 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
2601 | hotplug_status); | |
2602 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
2603 | queue_work(dev_priv->wq, | |
2604 | &dev_priv->hotplug_work); | |
2605 | ||
2606 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
38bde180 | 2607 | POSTING_READ(PORT_HOTPLUG_STAT); |
a266c7d5 CW |
2608 | } |
2609 | ||
38bde180 | 2610 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
2611 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
2612 | ||
a266c7d5 CW |
2613 | if (iir & I915_USER_INTERRUPT) |
2614 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 2615 | |
a266c7d5 | 2616 | for_each_pipe(pipe) { |
38bde180 CW |
2617 | int plane = pipe; |
2618 | if (IS_MOBILE(dev)) | |
2619 | plane = !plane; | |
90a72f87 | 2620 | |
8291ee90 | 2621 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
2622 | i915_handle_vblank(dev, plane, pipe, iir)) |
2623 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
2624 | |
2625 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
2626 | blc_event = true; | |
2627 | } | |
2628 | ||
a266c7d5 CW |
2629 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
2630 | intel_opregion_asle_intr(dev); | |
2631 | ||
2632 | /* With MSI, interrupts are only generated when iir | |
2633 | * transitions from zero to nonzero. If another bit got | |
2634 | * set while we were handling the existing iir bits, then | |
2635 | * we would never get another interrupt. | |
2636 | * | |
2637 | * This is fine on non-MSI as well, as if we hit this path | |
2638 | * we avoid exiting the interrupt handler only to generate | |
2639 | * another one. | |
2640 | * | |
2641 | * Note that for MSI this could cause a stray interrupt report | |
2642 | * if an interrupt landed in the time between writing IIR and | |
2643 | * the posting read. This should be rare enough to never | |
2644 | * trigger the 99% of 100,000 interrupts test for disabling | |
2645 | * stray interrupts. | |
2646 | */ | |
38bde180 | 2647 | ret = IRQ_HANDLED; |
a266c7d5 | 2648 | iir = new_iir; |
38bde180 | 2649 | } while (iir & ~flip_mask); |
a266c7d5 | 2650 | |
d05c617e | 2651 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 2652 | |
a266c7d5 CW |
2653 | return ret; |
2654 | } | |
2655 | ||
2656 | static void i915_irq_uninstall(struct drm_device * dev) | |
2657 | { | |
2658 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2659 | int pipe; | |
2660 | ||
a266c7d5 CW |
2661 | if (I915_HAS_HOTPLUG(dev)) { |
2662 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2663 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2664 | } | |
2665 | ||
00d98ebd | 2666 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
2667 | for_each_pipe(pipe) { |
2668 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 2669 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
2670 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
2671 | } | |
a266c7d5 CW |
2672 | I915_WRITE(IMR, 0xffffffff); |
2673 | I915_WRITE(IER, 0x0); | |
2674 | ||
a266c7d5 CW |
2675 | I915_WRITE(IIR, I915_READ(IIR)); |
2676 | } | |
2677 | ||
2678 | static void i965_irq_preinstall(struct drm_device * dev) | |
2679 | { | |
2680 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2681 | int pipe; | |
2682 | ||
2683 | atomic_set(&dev_priv->irq_received, 0); | |
2684 | ||
adca4730 CW |
2685 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2686 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
2687 | |
2688 | I915_WRITE(HWSTAM, 0xeffe); | |
2689 | for_each_pipe(pipe) | |
2690 | I915_WRITE(PIPESTAT(pipe), 0); | |
2691 | I915_WRITE(IMR, 0xffffffff); | |
2692 | I915_WRITE(IER, 0x0); | |
2693 | POSTING_READ(IER); | |
2694 | } | |
2695 | ||
2696 | static int i965_irq_postinstall(struct drm_device *dev) | |
2697 | { | |
2698 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
bbba0a97 | 2699 | u32 enable_mask; |
a266c7d5 CW |
2700 | u32 error_mask; |
2701 | ||
a266c7d5 | 2702 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 2703 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 2704 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
2705 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
2706 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2707 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2708 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
2709 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2710 | ||
2711 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
2712 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
2713 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
2714 | enable_mask |= I915_USER_INTERRUPT; |
2715 | ||
2716 | if (IS_G4X(dev)) | |
2717 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 2718 | |
515ac2bb | 2719 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); |
a266c7d5 | 2720 | |
a266c7d5 CW |
2721 | /* |
2722 | * Enable some error detection, note the instruction error mask | |
2723 | * bit is reserved, so we leave it masked. | |
2724 | */ | |
2725 | if (IS_G4X(dev)) { | |
2726 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
2727 | GM45_ERROR_MEM_PRIV | | |
2728 | GM45_ERROR_CP_PRIV | | |
2729 | I915_ERROR_MEMORY_REFRESH); | |
2730 | } else { | |
2731 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
2732 | I915_ERROR_MEMORY_REFRESH); | |
2733 | } | |
2734 | I915_WRITE(EMR, error_mask); | |
2735 | ||
2736 | I915_WRITE(IMR, dev_priv->irq_mask); | |
2737 | I915_WRITE(IER, enable_mask); | |
2738 | POSTING_READ(IER); | |
2739 | ||
20afbda2 DV |
2740 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2741 | POSTING_READ(PORT_HOTPLUG_EN); | |
2742 | ||
2743 | intel_opregion_enable_asle(dev); | |
2744 | ||
2745 | return 0; | |
2746 | } | |
2747 | ||
2748 | static void i965_hpd_irq_setup(struct drm_device *dev) | |
2749 | { | |
2750 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2751 | u32 hotplug_en; | |
2752 | ||
adca4730 CW |
2753 | /* Note HDMI and DP share hotplug bits */ |
2754 | hotplug_en = 0; | |
26739f12 DV |
2755 | if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS) |
2756 | hotplug_en |= PORTB_HOTPLUG_INT_EN; | |
2757 | if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS) | |
2758 | hotplug_en |= PORTC_HOTPLUG_INT_EN; | |
2759 | if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS) | |
2760 | hotplug_en |= PORTD_HOTPLUG_INT_EN; | |
084b612e CW |
2761 | if (IS_G4X(dev)) { |
2762 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X) | |
2763 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
2764 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X) | |
2765 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2766 | } else { | |
2767 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965) | |
2768 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
2769 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965) | |
2770 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2771 | } | |
adca4730 CW |
2772 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
2773 | hotplug_en |= CRT_HOTPLUG_INT_EN; | |
a266c7d5 | 2774 | |
adca4730 CW |
2775 | /* Programming the CRT detection parameters tends |
2776 | to generate a spurious hotplug event about three | |
2777 | seconds later. So just do it once. | |
2778 | */ | |
2779 | if (IS_G4X(dev)) | |
2780 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
2781 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
2782 | } | |
a266c7d5 | 2783 | |
adca4730 | 2784 | /* Ignore TV since it's buggy */ |
a266c7d5 | 2785 | |
adca4730 | 2786 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
a266c7d5 CW |
2787 | } |
2788 | ||
ff1f525e | 2789 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 CW |
2790 | { |
2791 | struct drm_device *dev = (struct drm_device *) arg; | |
2792 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
a266c7d5 CW |
2793 | u32 iir, new_iir; |
2794 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 CW |
2795 | unsigned long irqflags; |
2796 | int irq_received; | |
2797 | int ret = IRQ_NONE, pipe; | |
21ad8330 VS |
2798 | u32 flip_mask = |
2799 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2800 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 CW |
2801 | |
2802 | atomic_inc(&dev_priv->irq_received); | |
2803 | ||
2804 | iir = I915_READ(IIR); | |
2805 | ||
a266c7d5 | 2806 | for (;;) { |
2c8ba29f CW |
2807 | bool blc_event = false; |
2808 | ||
21ad8330 | 2809 | irq_received = (iir & ~flip_mask) != 0; |
a266c7d5 CW |
2810 | |
2811 | /* Can't rely on pipestat interrupt bit in iir as it might | |
2812 | * have been cleared after the pipestat interrupt was received. | |
2813 | * It doesn't set the bit in iir again, but it still produces | |
2814 | * interrupts (for non-MSI). | |
2815 | */ | |
2816 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
2817 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
2818 | i915_handle_error(dev, false); | |
2819 | ||
2820 | for_each_pipe(pipe) { | |
2821 | int reg = PIPESTAT(pipe); | |
2822 | pipe_stats[pipe] = I915_READ(reg); | |
2823 | ||
2824 | /* | |
2825 | * Clear the PIPE*STAT regs before the IIR | |
2826 | */ | |
2827 | if (pipe_stats[pipe] & 0x8000ffff) { | |
2828 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
2829 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
2830 | pipe_name(pipe)); | |
2831 | I915_WRITE(reg, pipe_stats[pipe]); | |
2832 | irq_received = 1; | |
2833 | } | |
2834 | } | |
2835 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2836 | ||
2837 | if (!irq_received) | |
2838 | break; | |
2839 | ||
2840 | ret = IRQ_HANDLED; | |
2841 | ||
2842 | /* Consume port. Then clear IIR or we'll miss events */ | |
adca4730 | 2843 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
a266c7d5 CW |
2844 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
2845 | ||
2846 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
2847 | hotplug_status); | |
2848 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
2849 | queue_work(dev_priv->wq, | |
2850 | &dev_priv->hotplug_work); | |
2851 | ||
2852 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
2853 | I915_READ(PORT_HOTPLUG_STAT); | |
2854 | } | |
2855 | ||
21ad8330 | 2856 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
2857 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
2858 | ||
a266c7d5 CW |
2859 | if (iir & I915_USER_INTERRUPT) |
2860 | notify_ring(dev, &dev_priv->ring[RCS]); | |
2861 | if (iir & I915_BSD_USER_INTERRUPT) | |
2862 | notify_ring(dev, &dev_priv->ring[VCS]); | |
2863 | ||
a266c7d5 | 2864 | for_each_pipe(pipe) { |
2c8ba29f | 2865 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
2866 | i915_handle_vblank(dev, pipe, pipe, iir)) |
2867 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
2868 | |
2869 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
2870 | blc_event = true; | |
2871 | } | |
2872 | ||
2873 | ||
2874 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
2875 | intel_opregion_asle_intr(dev); | |
2876 | ||
515ac2bb DV |
2877 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
2878 | gmbus_irq_handler(dev); | |
2879 | ||
a266c7d5 CW |
2880 | /* With MSI, interrupts are only generated when iir |
2881 | * transitions from zero to nonzero. If another bit got | |
2882 | * set while we were handling the existing iir bits, then | |
2883 | * we would never get another interrupt. | |
2884 | * | |
2885 | * This is fine on non-MSI as well, as if we hit this path | |
2886 | * we avoid exiting the interrupt handler only to generate | |
2887 | * another one. | |
2888 | * | |
2889 | * Note that for MSI this could cause a stray interrupt report | |
2890 | * if an interrupt landed in the time between writing IIR and | |
2891 | * the posting read. This should be rare enough to never | |
2892 | * trigger the 99% of 100,000 interrupts test for disabling | |
2893 | * stray interrupts. | |
2894 | */ | |
2895 | iir = new_iir; | |
2896 | } | |
2897 | ||
d05c617e | 2898 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 2899 | |
a266c7d5 CW |
2900 | return ret; |
2901 | } | |
2902 | ||
2903 | static void i965_irq_uninstall(struct drm_device * dev) | |
2904 | { | |
2905 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2906 | int pipe; | |
2907 | ||
2908 | if (!dev_priv) | |
2909 | return; | |
2910 | ||
adca4730 CW |
2911 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2912 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
2913 | |
2914 | I915_WRITE(HWSTAM, 0xffffffff); | |
2915 | for_each_pipe(pipe) | |
2916 | I915_WRITE(PIPESTAT(pipe), 0); | |
2917 | I915_WRITE(IMR, 0xffffffff); | |
2918 | I915_WRITE(IER, 0x0); | |
2919 | ||
2920 | for_each_pipe(pipe) | |
2921 | I915_WRITE(PIPESTAT(pipe), | |
2922 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
2923 | I915_WRITE(IIR, I915_READ(IIR)); | |
2924 | } | |
2925 | ||
f71d4af4 JB |
2926 | void intel_irq_init(struct drm_device *dev) |
2927 | { | |
8b2e326d CW |
2928 | struct drm_i915_private *dev_priv = dev->dev_private; |
2929 | ||
2930 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
99584db3 | 2931 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 2932 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 2933 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 2934 | |
99584db3 DV |
2935 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
2936 | i915_hangcheck_elapsed, | |
61bac78e DV |
2937 | (unsigned long) dev); |
2938 | ||
97a19a24 | 2939 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 2940 | |
f71d4af4 JB |
2941 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
2942 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
7d4e146f | 2943 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
f71d4af4 JB |
2944 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
2945 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
2946 | } | |
2947 | ||
c3613de9 KP |
2948 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
2949 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; | |
2950 | else | |
2951 | dev->driver->get_vblank_timestamp = NULL; | |
f71d4af4 JB |
2952 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
2953 | ||
7e231dbe JB |
2954 | if (IS_VALLEYVIEW(dev)) { |
2955 | dev->driver->irq_handler = valleyview_irq_handler; | |
2956 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
2957 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
2958 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
2959 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
2960 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
20afbda2 | 2961 | dev_priv->display.hpd_irq_setup = valleyview_hpd_irq_setup; |
4a06e201 | 2962 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
f71d4af4 JB |
2963 | /* Share pre & uninstall handlers with ILK/SNB */ |
2964 | dev->driver->irq_handler = ivybridge_irq_handler; | |
2965 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
2966 | dev->driver->irq_postinstall = ivybridge_irq_postinstall; | |
2967 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
2968 | dev->driver->enable_vblank = ivybridge_enable_vblank; | |
2969 | dev->driver->disable_vblank = ivybridge_disable_vblank; | |
2970 | } else if (HAS_PCH_SPLIT(dev)) { | |
2971 | dev->driver->irq_handler = ironlake_irq_handler; | |
2972 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
2973 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
2974 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
2975 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
2976 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
2977 | } else { | |
c2798b19 CW |
2978 | if (INTEL_INFO(dev)->gen == 2) { |
2979 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
2980 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
2981 | dev->driver->irq_handler = i8xx_irq_handler; | |
2982 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 CW |
2983 | } else if (INTEL_INFO(dev)->gen == 3) { |
2984 | dev->driver->irq_preinstall = i915_irq_preinstall; | |
2985 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
2986 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
2987 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 2988 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 2989 | } else { |
a266c7d5 CW |
2990 | dev->driver->irq_preinstall = i965_irq_preinstall; |
2991 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
2992 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
2993 | dev->driver->irq_handler = i965_irq_handler; | |
20afbda2 | 2994 | dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup; |
c2798b19 | 2995 | } |
f71d4af4 JB |
2996 | dev->driver->enable_vblank = i915_enable_vblank; |
2997 | dev->driver->disable_vblank = i915_disable_vblank; | |
2998 | } | |
2999 | } | |
20afbda2 DV |
3000 | |
3001 | void intel_hpd_init(struct drm_device *dev) | |
3002 | { | |
3003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3004 | ||
3005 | if (dev_priv->display.hpd_irq_setup) | |
3006 | dev_priv->display.hpd_irq_setup(dev); | |
3007 | } |