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Merge tag 'v3.10' into drm-intel-fixes
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
e5868a31
EE		 73static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
036a4a7d 82/* For display hotplug interrupt */
995b6762 83static void
f2b115e6 84ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 85{
4bc9d430
DV		 86 assert_spin_locked(&dev_priv->irq_lock);
87
1ec14ad3
CW		 88 if ((dev_priv->irq_mask & mask) != 0) {
89 dev_priv->irq_mask &= ~mask;
90 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 91 POSTING_READ(DEIMR);
036a4a7d
ZW		 92 }
93}
94
0ff9800a 95static void
f2b115e6 96ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 97{
4bc9d430
DV		 98 assert_spin_locked(&dev_priv->irq_lock);
99
1ec14ad3
CW		 100 if ((dev_priv->irq_mask & mask) != mask) {
101 dev_priv->irq_mask |= mask;
102 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 103 POSTING_READ(DEIMR);
036a4a7d
ZW		 104 }
105}
106
8664281b
PZ		 107static bool ivb_can_enable_err_int(struct drm_device *dev)
108{
109 struct drm_i915_private *dev_priv = dev->dev_private;
110 struct intel_crtc *crtc;
111 enum pipe pipe;
112
4bc9d430
DV		 113 assert_spin_locked(&dev_priv->irq_lock);
114
8664281b
PZ		 115 for_each_pipe(pipe) {
116 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
117
118 if (crtc->cpu_fifo_underrun_disabled)
119 return false;
120 }
121
122 return true;
123}
124
125static bool cpt_can_enable_serr_int(struct drm_device *dev)
126{
127 struct drm_i915_private *dev_priv = dev->dev_private;
128 enum pipe pipe;
129 struct intel_crtc *crtc;
130
131 for_each_pipe(pipe) {
132 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
133
134 if (crtc->pch_fifo_underrun_disabled)
135 return false;
136 }
137
138 return true;
139}
140
141static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
142 enum pipe pipe, bool enable)
143{
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
146 DE_PIPEB_FIFO_UNDERRUN;
147
148 if (enable)
149 ironlake_enable_display_irq(dev_priv, bit);
150 else
151 ironlake_disable_display_irq(dev_priv, bit);
152}
153
154static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
155 bool enable)
156{
157 struct drm_i915_private *dev_priv = dev->dev_private;
158
159 if (enable) {
160 if (!ivb_can_enable_err_int(dev))
161 return;
162
163 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
164 ERR_INT_FIFO_UNDERRUN_B |
165 ERR_INT_FIFO_UNDERRUN_C);
166
167 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
168 } else {
169 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
170 }
171}
172
173static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
174 bool enable)
175{
176 struct drm_device *dev = crtc->base.dev;
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
179 SDE_TRANSB_FIFO_UNDER;
180
181 if (enable)
182 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
183 else
184 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
185
186 POSTING_READ(SDEIMR);
187}
188
189static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
190 enum transcoder pch_transcoder,
191 bool enable)
192{
193 struct drm_i915_private *dev_priv = dev->dev_private;
194
195 if (enable) {
196 if (!cpt_can_enable_serr_int(dev))
197 return;
198
199 I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
200 SERR_INT_TRANS_B_FIFO_UNDERRUN |
201 SERR_INT_TRANS_C_FIFO_UNDERRUN);
202
203 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
204 } else {
205 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
206 }
207
208 POSTING_READ(SDEIMR);
209}
210
211/**
212 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
213 * @dev: drm device
214 * @pipe: pipe
215 * @enable: true if we want to report FIFO underrun errors, false otherwise
216 *
217 * This function makes us disable or enable CPU fifo underruns for a specific
218 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
219 * reporting for one pipe may also disable all the other CPU error interruts for
220 * the other pipes, due to the fact that there's just one interrupt mask/enable
221 * bit for all the pipes.
222 *
223 * Returns the previous state of underrun reporting.
224 */
225bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
226 enum pipe pipe, bool enable)
227{
228 struct drm_i915_private *dev_priv = dev->dev_private;
229 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
231 unsigned long flags;
232 bool ret;
233
234 spin_lock_irqsave(&dev_priv->irq_lock, flags);
235
236 ret = !intel_crtc->cpu_fifo_underrun_disabled;
237
238 if (enable == ret)
239 goto done;
240
241 intel_crtc->cpu_fifo_underrun_disabled = !enable;
242
243 if (IS_GEN5(dev) || IS_GEN6(dev))
244 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
245 else if (IS_GEN7(dev))
246 ivybridge_set_fifo_underrun_reporting(dev, enable);
247
248done:
249 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
250 return ret;
251}
252
253/**
254 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
255 * @dev: drm device
256 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
257 * @enable: true if we want to report FIFO underrun errors, false otherwise
258 *
259 * This function makes us disable or enable PCH fifo underruns for a specific
260 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
261 * underrun reporting for one transcoder may also disable all the other PCH
262 * error interruts for the other transcoders, due to the fact that there's just
263 * one interrupt mask/enable bit for all the transcoders.
264 *
265 * Returns the previous state of underrun reporting.
266 */
267bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
268 enum transcoder pch_transcoder,
269 bool enable)
270{
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 enum pipe p;
273 struct drm_crtc *crtc;
274 struct intel_crtc *intel_crtc;
275 unsigned long flags;
276 bool ret;
277
278 if (HAS_PCH_LPT(dev)) {
279 crtc = NULL;
280 for_each_pipe(p) {
281 struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
282 if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
283 crtc = c;
284 break;
285 }
286 }
287 if (!crtc) {
288 DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
289 return false;
290 }
291 } else {
292 crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
293 }
294 intel_crtc = to_intel_crtc(crtc);
295
296 spin_lock_irqsave(&dev_priv->irq_lock, flags);
297
298 ret = !intel_crtc->pch_fifo_underrun_disabled;
299
300 if (enable == ret)
301 goto done;
302
303 intel_crtc->pch_fifo_underrun_disabled = !enable;
304
305 if (HAS_PCH_IBX(dev))
306 ibx_set_fifo_underrun_reporting(intel_crtc, enable);
307 else
308 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
309
310done:
311 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
312 return ret;
313}
314
315
7c463586
KP		 316void
317i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
318{
46c06a30
VS		 319 u32 reg = PIPESTAT(pipe);
320 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 321
46c06a30
VS		 322 if ((pipestat & mask) == mask)
323 return;
324
325 /* Enable the interrupt, clear any pending status */
326 pipestat |= mask | (mask >> 16);
327 I915_WRITE(reg, pipestat);
328 POSTING_READ(reg);
7c463586
KP		 329}
330
331void
332i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
333{
46c06a30
VS		 334 u32 reg = PIPESTAT(pipe);
335 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 336
46c06a30
VS		 337 if ((pipestat & mask) == 0)
338 return;
339
340 pipestat &= ~mask;
341 I915_WRITE(reg, pipestat);
342 POSTING_READ(reg);
7c463586
KP		 343}
344
01c66889 345/**
f49e38dd 346 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 347 */
f49e38dd 348static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 349{
1ec14ad3
CW		 350 drm_i915_private_t *dev_priv = dev->dev_private;
351 unsigned long irqflags;
352
f49e38dd
JN		 353 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
354 return;
355
1ec14ad3 356 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 357
f898780b
JN		 358 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
359 if (INTEL_INFO(dev)->gen >= 4)
360 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 361
362 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 363}
364
0a3e67a4
JB		 365/**
366 * i915_pipe_enabled - check if a pipe is enabled
367 * @dev: DRM device
368 * @pipe: pipe to check
369 *
370 * Reading certain registers when the pipe is disabled can hang the chip.
371 * Use this routine to make sure the PLL is running and the pipe is active
372 * before reading such registers if unsure.
373 */
374static int
375i915_pipe_enabled(struct drm_device *dev, int pipe)
376{
377 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 378
a01025af
DV		 379 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
380 /* Locking is horribly broken here, but whatever. */
381 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 383
a01025af
DV		 384 return intel_crtc->active;
385 } else {
386 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
387 }
0a3e67a4
JB		 388}
389
42f52ef8
KP		 390/* Called from drm generic code, passed a 'crtc', which
391 * we use as a pipe index
392 */
f71d4af4 393static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 394{
395 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
396 unsigned long high_frame;
397 unsigned long low_frame;
5eddb70b 398 u32 high1, high2, low;
0a3e67a4
JB		 399
400 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 401 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 402 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 403 return 0;
404 }
405
9db4a9c7
JB		 406 high_frame = PIPEFRAME(pipe);
407 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 408
0a3e67a4
JB		 409 /*
410 * High & low register fields aren't synchronized, so make sure
411 * we get a low value that's stable across two reads of the high
412 * register.
413 */
414 do {
5eddb70b
CW		 415 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
416 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
417 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 418 } while (high1 != high2);
419
5eddb70b
CW		 420 high1 >>= PIPE_FRAME_HIGH_SHIFT;
421 low >>= PIPE_FRAME_LOW_SHIFT;
422 return (high1 << 8) | low;
0a3e67a4
JB		 423}
424
f71d4af4 425static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 426{
427 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 428 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 429
430 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 431 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 432 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 433 return 0;
434 }
435
436 return I915_READ(reg);
437}
438
f71d4af4 439static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 440 int *vpos, int *hpos)
441{
442 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
443 u32 vbl = 0, position = 0;
444 int vbl_start, vbl_end, htotal, vtotal;
445 bool in_vbl = true;
446 int ret = 0;
fe2b8f9d
PZ		 447 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
448 pipe);
0af7e4df
MK		 449
450 if (!i915_pipe_enabled(dev, pipe)) {
451 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 452 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 453 return 0;
454 }
455
456 /* Get vtotal. */
fe2b8f9d 457 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 458
459 if (INTEL_INFO(dev)->gen >= 4) {
460 /* No obvious pixelcount register. Only query vertical
461 * scanout position from Display scan line register.
462 */
463 position = I915_READ(PIPEDSL(pipe));
464
465 /* Decode into vertical scanout position. Don't have
466 * horizontal scanout position.
467 */
468 *vpos = position & 0x1fff;
469 *hpos = 0;
470 } else {
471 /* Have access to pixelcount since start of frame.
472 * We can split this into vertical and horizontal
473 * scanout position.
474 */
475 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
476
fe2b8f9d 477 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 478 *vpos = position / htotal;
479 *hpos = position - (*vpos * htotal);
480 }
481
482 /* Query vblank area. */
fe2b8f9d 483 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 484
485 /* Test position against vblank region. */
486 vbl_start = vbl & 0x1fff;
487 vbl_end = (vbl >> 16) & 0x1fff;
488
489 if ((*vpos < vbl_start) || (*vpos > vbl_end))
490 in_vbl = false;
491
492 /* Inside "upper part" of vblank area? Apply corrective offset: */
493 if (in_vbl && (*vpos >= vbl_start))
494 *vpos = *vpos - vtotal;
495
496 /* Readouts valid? */
497 if (vbl > 0)
498 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
499
500 /* In vblank? */
501 if (in_vbl)
502 ret |= DRM_SCANOUTPOS_INVBL;
503
504 return ret;
505}
506
f71d4af4 507static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 508 int *max_error,
509 struct timeval *vblank_time,
510 unsigned flags)
511{
4041b853 512 struct drm_crtc *crtc;
0af7e4df 513
7eb552ae 514 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 515 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 516 return -EINVAL;
517 }
518
519 /* Get drm_crtc to timestamp: */
4041b853
CW		 520 crtc = intel_get_crtc_for_pipe(dev, pipe);
521 if (crtc == NULL) {
522 DRM_ERROR("Invalid crtc %d\n", pipe);
523 return -EINVAL;
524 }
525
526 if (!crtc->enabled) {
527 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
528 return -EBUSY;
529 }
0af7e4df
MK		 530
531 /* Helper routine in DRM core does all the work: */
4041b853
CW		 532 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
533 vblank_time, flags,
534 crtc);
0af7e4df
MK		 535}
536
321a1b30
EE		 537static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
538{
539 enum drm_connector_status old_status;
540
541 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
542 old_status = connector->status;
543
544 connector->status = connector->funcs->detect(connector, false);
545 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
546 connector->base.id,
547 drm_get_connector_name(connector),
548 old_status, connector->status);
549 return (old_status != connector->status);
550}
551
5ca58282
JB		 552/*
553 * Handle hotplug events outside the interrupt handler proper.
554 */
ac4c16c5
EE		 555#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
556
5ca58282
JB		 557static void i915_hotplug_work_func(struct work_struct *work)
558{
559 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
560 hotplug_work);
561 struct drm_device *dev = dev_priv->dev;
c31c4ba3 562 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 563 struct intel_connector *intel_connector;
564 struct intel_encoder *intel_encoder;
565 struct drm_connector *connector;
566 unsigned long irqflags;
567 bool hpd_disabled = false;
321a1b30 568 bool changed = false;
142e2398 569 u32 hpd_event_bits;
4ef69c7a 570
52d7eced
DV		 571 /* HPD irq before everything is fully set up. */
572 if (!dev_priv->enable_hotplug_processing)
573 return;
574
a65e34c7 575 mutex_lock(&mode_config->mutex);
e67189ab
JB		 576 DRM_DEBUG_KMS("running encoder hotplug functions\n");
577
cd569aed 578 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 579
580 hpd_event_bits = dev_priv->hpd_event_bits;
581 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 582 list_for_each_entry(connector, &mode_config->connector_list, head) {
583 intel_connector = to_intel_connector(connector);
584 intel_encoder = intel_connector->encoder;
585 if (intel_encoder->hpd_pin > HPD_NONE &&
586 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
587 connector->polled == DRM_CONNECTOR_POLL_HPD) {
588 DRM_INFO("HPD interrupt storm detected on connector %s: "
589 "switching from hotplug detection to polling\n",
590 drm_get_connector_name(connector));
591 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
592 connector->polled = DRM_CONNECTOR_POLL_CONNECT
593 | DRM_CONNECTOR_POLL_DISCONNECT;
594 hpd_disabled = true;
595 }
142e2398
EE		 596 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
597 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
598 drm_get_connector_name(connector), intel_encoder->hpd_pin);
599 }
cd569aed
EE		 600 }
601 /* if there were no outputs to poll, poll was disabled,
602 * therefore make sure it's enabled when disabling HPD on
603 * some connectors */
ac4c16c5 604 if (hpd_disabled) {
cd569aed 605 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 606 mod_timer(&dev_priv->hotplug_reenable_timer,
607 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
608 }
cd569aed
EE		 609
610 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
611
321a1b30
EE		 612 list_for_each_entry(connector, &mode_config->connector_list, head) {
613 intel_connector = to_intel_connector(connector);
614 intel_encoder = intel_connector->encoder;
615 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
616 if (intel_encoder->hot_plug)
617 intel_encoder->hot_plug(intel_encoder);
618 if (intel_hpd_irq_event(dev, connector))
619 changed = true;
620 }
621 }
40ee3381
KP		 622 mutex_unlock(&mode_config->mutex);
623
321a1b30
EE		 624 if (changed)
625 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 626}
627
73edd18f 628static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 629{
630 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 631 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 632 u8 new_delay;
633 unsigned long flags;
634
635 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 636
73edd18f
DV		 637 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
638
20e4d407 639 new_delay = dev_priv->ips.cur_delay;
9270388e 640
7648fa99 641 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 642 busy_up = I915_READ(RCPREVBSYTUPAVG);
643 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 644 max_avg = I915_READ(RCBMAXAVG);
645 min_avg = I915_READ(RCBMINAVG);
646
647 /* Handle RCS change request from hw */
b5b72e89 648 if (busy_up > max_avg) {
20e4d407
DV		 649 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
650 new_delay = dev_priv->ips.cur_delay - 1;
651 if (new_delay < dev_priv->ips.max_delay)
652 new_delay = dev_priv->ips.max_delay;
b5b72e89 653 } else if (busy_down < min_avg) {
20e4d407
DV		 654 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
655 new_delay = dev_priv->ips.cur_delay + 1;
656 if (new_delay > dev_priv->ips.min_delay)
657 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 658 }
659
7648fa99 660 if (ironlake_set_drps(dev, new_delay))
20e4d407 661 dev_priv->ips.cur_delay = new_delay;
f97108d1 662
9270388e
DV		 663 spin_unlock_irqrestore(&mchdev_lock, flags);
664
f97108d1
JB		 665 return;
666}
667
549f7365
CW		 668static void notify_ring(struct drm_device *dev,
669 struct intel_ring_buffer *ring)
670{
671 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 672
475553de
CW		 673 if (ring->obj == NULL)
674 return;
675
b2eadbc8 676 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 677
549f7365 678 wake_up_all(&ring->irq_queue);
3e0dc6b0 679 if (i915_enable_hangcheck) {
99584db3 680 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 681 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 682 }
549f7365
CW		 683}
684
4912d041 685static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 686{
4912d041 687 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 688 rps.work);
4912d041 689 u32 pm_iir, pm_imr;
7b9e0ae6 690 u8 new_delay;
4912d041 691
c6a828d3
DV		 692 spin_lock_irq(&dev_priv->rps.lock);
693 pm_iir = dev_priv->rps.pm_iir;
694 dev_priv->rps.pm_iir = 0;
4912d041 695 pm_imr = I915_READ(GEN6_PMIMR);
4848405c
BW		 696 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
697 I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
c6a828d3 698 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 699
4848405c 700 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 701 return;
702
4fc688ce 703 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 704
7425034a 705 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
c6a828d3 706 new_delay = dev_priv->rps.cur_delay + 1;
7425034a
VS		 707
708 /*
709 * For better performance, jump directly
710 * to RPe if we're below it.
711 */
712 if (IS_VALLEYVIEW(dev_priv->dev) &&
713 dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
714 new_delay = dev_priv->rps.rpe_delay;
715 } else
c6a828d3 716 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 717
79249636
BW		 718 /* sysfs frequency interfaces may have snuck in while servicing the
719 * interrupt
720 */
d8289c9e
VS		 721 if (new_delay >= dev_priv->rps.min_delay &&
722 new_delay <= dev_priv->rps.max_delay) {
0a073b84
JB		 723 if (IS_VALLEYVIEW(dev_priv->dev))
724 valleyview_set_rps(dev_priv->dev, new_delay);
725 else
726 gen6_set_rps(dev_priv->dev, new_delay);
79249636 727 }
3b8d8d91 728
52ceb908
JB		 729 if (IS_VALLEYVIEW(dev_priv->dev)) {
730 /*
731 * On VLV, when we enter RC6 we may not be at the minimum
732 * voltage level, so arm a timer to check. It should only
733 * fire when there's activity or once after we've entered
734 * RC6, and then won't be re-armed until the next RPS interrupt.
735 */
736 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
737 msecs_to_jiffies(100));
738 }
739
4fc688ce 740 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 741}
742
e3689190
BW		 743
744/**
745 * ivybridge_parity_work - Workqueue called when a parity error interrupt
746 * occurred.
747 * @work: workqueue struct
748 *
749 * Doesn't actually do anything except notify userspace. As a consequence of
750 * this event, userspace should try to remap the bad rows since statistically
751 * it is likely the same row is more likely to go bad again.
752 */
753static void ivybridge_parity_work(struct work_struct *work)
754{
755 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 756 l3_parity.error_work);
e3689190
BW		 757 u32 error_status, row, bank, subbank;
758 char *parity_event[5];
759 uint32_t misccpctl;
760 unsigned long flags;
761
762 /* We must turn off DOP level clock gating to access the L3 registers.
763 * In order to prevent a get/put style interface, acquire struct mutex
764 * any time we access those registers.
765 */
766 mutex_lock(&dev_priv->dev->struct_mutex);
767
768 misccpctl = I915_READ(GEN7_MISCCPCTL);
769 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
770 POSTING_READ(GEN7_MISCCPCTL);
771
772 error_status = I915_READ(GEN7_L3CDERRST1);
773 row = GEN7_PARITY_ERROR_ROW(error_status);
774 bank = GEN7_PARITY_ERROR_BANK(error_status);
775 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
776
777 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
778 GEN7_L3CDERRST1_ENABLE);
779 POSTING_READ(GEN7_L3CDERRST1);
780
781 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
782
783 spin_lock_irqsave(&dev_priv->irq_lock, flags);
cc609d5d 784 dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
e3689190
BW		 785 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
786 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
787
788 mutex_unlock(&dev_priv->dev->struct_mutex);
789
790 parity_event[0] = "L3_PARITY_ERROR=1";
791 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
792 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
793 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
794 parity_event[4] = NULL;
795
796 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
797 KOBJ_CHANGE, parity_event);
798
799 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
800 row, bank, subbank);
801
802 kfree(parity_event[3]);
803 kfree(parity_event[2]);
804 kfree(parity_event[1]);
805}
806
d2ba8470 807static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 808{
809 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
810 unsigned long flags;
811
e1ef7cc2 812 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 813 return;
814
815 spin_lock_irqsave(&dev_priv->irq_lock, flags);
cc609d5d 816 dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
e3689190
BW		 817 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
818 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
819
a4da4fa4 820 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 821}
822
e7b4c6b1
DV		 823static void snb_gt_irq_handler(struct drm_device *dev,
824 struct drm_i915_private *dev_priv,
825 u32 gt_iir)
826{
827
cc609d5d
BW		 828 if (gt_iir &
829 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 830 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 831 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 832 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 833 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 834 notify_ring(dev, &dev_priv->ring[BCS]);
835
cc609d5d
BW		 836 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
837 GT_BSD_CS_ERROR_INTERRUPT |
838 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 839 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
840 i915_handle_error(dev, false);
841 }
e3689190 842
cc609d5d 843 if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
e3689190 844 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 845}
846
baf02a1f 847/* Legacy way of handling PM interrupts */
fc6826d1
CW		 848static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
849 u32 pm_iir)
850{
851 unsigned long flags;
852
853 /*
854 * IIR bits should never already be set because IMR should
855 * prevent an interrupt from being shown in IIR. The warning
856 * displays a case where we've unsafely cleared
c6a828d3 857 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 858 * type is not a problem, it displays a problem in the logic.
859 *
c6a828d3 860 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 861 */
862
c6a828d3 863 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 864 dev_priv->rps.pm_iir |= pm_iir;
865 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 866 POSTING_READ(GEN6_PMIMR);
c6a828d3 867 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 868
c6a828d3 869 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 870}
871
b543fb04
EE		 872#define HPD_STORM_DETECT_PERIOD 1000
873#define HPD_STORM_THRESHOLD 5
874
10a504de 875static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 876 u32 hotplug_trigger,
877 const u32 *hpd)
b543fb04
EE		 878{
879 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 880 int i;
10a504de 881 bool storm_detected = false;
b543fb04 882
91d131d2
DV		 883 if (!hotplug_trigger)
884 return;
885
b5ea2d56 886 spin_lock(&dev_priv->irq_lock);
b543fb04 887 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 888
b543fb04
EE		 889 if (!(hpd[i] & hotplug_trigger) ||
890 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
891 continue;
892
bc5ead8c 893 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 894 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
895 dev_priv->hpd_stats[i].hpd_last_jiffies
896 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
897 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
898 dev_priv->hpd_stats[i].hpd_cnt = 0;
899 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
900 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 901 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 902 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 903 storm_detected = true;
b543fb04
EE		 904 } else {
905 dev_priv->hpd_stats[i].hpd_cnt++;
906 }
907 }
908
10a504de
DV		 909 if (storm_detected)
910 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 911 spin_unlock(&dev_priv->irq_lock);
5876fa0d
DV		 912
913 queue_work(dev_priv->wq,
914 &dev_priv->hotplug_work);
b543fb04
EE		 915}
916
515ac2bb
DV		 917static void gmbus_irq_handler(struct drm_device *dev)
918{
28c70f16
DV		 919 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
920
28c70f16 921 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 922}
923
ce99c256
DV		 924static void dp_aux_irq_handler(struct drm_device *dev)
925{
9ee32fea
DV		 926 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
927
9ee32fea 928 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 929}
930
baf02a1f
BW		 931/* Unlike gen6_queue_rps_work() from which this function is originally derived,
932 * we must be able to deal with other PM interrupts. This is complicated because
933 * of the way in which we use the masks to defer the RPS work (which for
934 * posterity is necessary because of forcewake).
935 */
936static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
937 u32 pm_iir)
938{
939 unsigned long flags;
940
941 spin_lock_irqsave(&dev_priv->rps.lock, flags);
4848405c 942 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
baf02a1f
BW		 943 if (dev_priv->rps.pm_iir) {
944 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
945 /* never want to mask useful interrupts. (also posting read) */
4848405c 946 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
baf02a1f
BW		 947 /* TODO: if queue_work is slow, move it out of the spinlock */
948 queue_work(dev_priv->wq, &dev_priv->rps.work);
949 }
950 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
951
12638c57
BW		 952 if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
953 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
954 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
955
956 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
957 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
958 i915_handle_error(dev_priv->dev, false);
959 }
960 }
baf02a1f
BW		 961}
962
ff1f525e 963static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 964{
965 struct drm_device *dev = (struct drm_device *) arg;
966 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
967 u32 iir, gt_iir, pm_iir;
968 irqreturn_t ret = IRQ_NONE;
969 unsigned long irqflags;
970 int pipe;
971 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 972
973 atomic_inc(&dev_priv->irq_received);
974
7e231dbe
JB		 975 while (true) {
976 iir = I915_READ(VLV_IIR);
977 gt_iir = I915_READ(GTIIR);
978 pm_iir = I915_READ(GEN6_PMIIR);
979
980 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
981 goto out;
982
983 ret = IRQ_HANDLED;
984
e7b4c6b1 985 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 986
987 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
988 for_each_pipe(pipe) {
989 int reg = PIPESTAT(pipe);
990 pipe_stats[pipe] = I915_READ(reg);
991
992 /*
993 * Clear the PIPE*STAT regs before the IIR
994 */
995 if (pipe_stats[pipe] & 0x8000ffff) {
996 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
997 DRM_DEBUG_DRIVER("pipe %c underrun\n",
998 pipe_name(pipe));
999 I915_WRITE(reg, pipe_stats[pipe]);
1000 }
1001 }
1002 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1003
31acc7f5
JB		 1004 for_each_pipe(pipe) {
1005 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1006 drm_handle_vblank(dev, pipe);
1007
1008 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1009 intel_prepare_page_flip(dev, pipe);
1010 intel_finish_page_flip(dev, pipe);
1011 }
1012 }
1013
7e231dbe
JB		 1014 /* Consume port. Then clear IIR or we'll miss events */
1015 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1016 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1017 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 1018
1019 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1020 hotplug_status);
91d131d2
DV		 1021
1022 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1023
7e231dbe
JB		 1024 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1025 I915_READ(PORT_HOTPLUG_STAT);
1026 }
1027
515ac2bb
DV		 1028 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1029 gmbus_irq_handler(dev);
7e231dbe 1030
4848405c 1031 if (pm_iir & GEN6_PM_RPS_EVENTS)
fc6826d1 1032 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 1033
1034 I915_WRITE(GTIIR, gt_iir);
1035 I915_WRITE(GEN6_PMIIR, pm_iir);
1036 I915_WRITE(VLV_IIR, iir);
1037 }
1038
1039out:
1040 return ret;
1041}
1042
23e81d69 1043static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1044{
1045 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1046 int pipe;
b543fb04 1047 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1048
91d131d2
DV		 1049 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1050
cfc33bf7
VS		 1051 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1052 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1053 SDE_AUDIO_POWER_SHIFT);
776ad806 1054 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1055 port_name(port));
1056 }
776ad806 1057
ce99c256
DV		 1058 if (pch_iir & SDE_AUX_MASK)
1059 dp_aux_irq_handler(dev);
1060
776ad806 1061 if (pch_iir & SDE_GMBUS)
515ac2bb 1062 gmbus_irq_handler(dev);
776ad806
JB		 1063
1064 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1065 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1066
1067 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1068 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1069
1070 if (pch_iir & SDE_POISON)
1071 DRM_ERROR("PCH poison interrupt\n");
1072
9db4a9c7
JB		 1073 if (pch_iir & SDE_FDI_MASK)
1074 for_each_pipe(pipe)
1075 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1076 pipe_name(pipe),
1077 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1078
1079 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1080 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1081
1082 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1083 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1084
776ad806 1085 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1086 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1087 false))
1088 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1089
1090 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1091 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1092 false))
1093 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1094}
1095
1096static void ivb_err_int_handler(struct drm_device *dev)
1097{
1098 struct drm_i915_private *dev_priv = dev->dev_private;
1099 u32 err_int = I915_READ(GEN7_ERR_INT);
1100
de032bf4
PZ		 1101 if (err_int & ERR_INT_POISON)
1102 DRM_ERROR("Poison interrupt\n");
1103
8664281b
PZ		 1104 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1105 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1106 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1107
1108 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1109 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1110 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1111
1112 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1113 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1114 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1115
1116 I915_WRITE(GEN7_ERR_INT, err_int);
1117}
1118
1119static void cpt_serr_int_handler(struct drm_device *dev)
1120{
1121 struct drm_i915_private *dev_priv = dev->dev_private;
1122 u32 serr_int = I915_READ(SERR_INT);
1123
de032bf4
PZ		 1124 if (serr_int & SERR_INT_POISON)
1125 DRM_ERROR("PCH poison interrupt\n");
1126
8664281b
PZ		 1127 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1128 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1129 false))
1130 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1131
1132 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1133 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1134 false))
1135 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1136
1137 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1138 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1139 false))
1140 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1141
1142 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1143}
1144
23e81d69
AJ		 1145static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1146{
1147 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1148 int pipe;
b543fb04 1149 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1150
91d131d2
DV		 1151 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1152
cfc33bf7
VS		 1153 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1154 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1155 SDE_AUDIO_POWER_SHIFT_CPT);
1156 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1157 port_name(port));
1158 }
23e81d69
AJ		 1159
1160 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1161 dp_aux_irq_handler(dev);
23e81d69
AJ		 1162
1163 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1164 gmbus_irq_handler(dev);
23e81d69
AJ		 1165
1166 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1167 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1168
1169 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1170 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1171
1172 if (pch_iir & SDE_FDI_MASK_CPT)
1173 for_each_pipe(pipe)
1174 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1175 pipe_name(pipe),
1176 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1177
1178 if (pch_iir & SDE_ERROR_CPT)
1179 cpt_serr_int_handler(dev);
23e81d69
AJ		 1180}
1181
ff1f525e 1182static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1183{
1184 struct drm_device *dev = (struct drm_device *) arg;
1185 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
ab5c608b 1186 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
0e43406b
CW		 1187 irqreturn_t ret = IRQ_NONE;
1188 int i;
b1f14ad0
JB		 1189
1190 atomic_inc(&dev_priv->irq_received);
1191
8664281b
PZ		 1192 /* We get interrupts on unclaimed registers, so check for this before we
1193 * do any I915_{READ,WRITE}. */
1194 if (IS_HASWELL(dev) &&
1195 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1196 DRM_ERROR("Unclaimed register before interrupt\n");
1197 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1198 }
1199
b1f14ad0
JB		 1200 /* disable master interrupt before clearing iir */
1201 de_ier = I915_READ(DEIER);
1202 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 1203
44498aea
PZ		 1204 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1205 * interrupts will will be stored on its back queue, and then we'll be
1206 * able to process them after we restore SDEIER (as soon as we restore
1207 * it, we'll get an interrupt if SDEIIR still has something to process
1208 * due to its back queue). */
ab5c608b
BW		 1209 if (!HAS_PCH_NOP(dev)) {
1210 sde_ier = I915_READ(SDEIER);
1211 I915_WRITE(SDEIER, 0);
1212 POSTING_READ(SDEIER);
1213 }
44498aea 1214
8664281b
PZ		 1215 /* On Haswell, also mask ERR_INT because we don't want to risk
1216 * generating "unclaimed register" interrupts from inside the interrupt
1217 * handler. */
4bc9d430
DV		 1218 if (IS_HASWELL(dev)) {
1219 spin_lock(&dev_priv->irq_lock);
8664281b 1220 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
4bc9d430
DV		 1221 spin_unlock(&dev_priv->irq_lock);
1222 }
8664281b 1223
b1f14ad0 1224 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 1225 if (gt_iir) {
1226 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1227 I915_WRITE(GTIIR, gt_iir);
1228 ret = IRQ_HANDLED;
b1f14ad0
JB		 1229 }
1230
0e43406b
CW		 1231 de_iir = I915_READ(DEIIR);
1232 if (de_iir) {
8664281b
PZ		 1233 if (de_iir & DE_ERR_INT_IVB)
1234 ivb_err_int_handler(dev);
1235
ce99c256
DV		 1236 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1237 dp_aux_irq_handler(dev);
1238
0e43406b 1239 if (de_iir & DE_GSE_IVB)
81a07809 1240 intel_opregion_asle_intr(dev);
0e43406b
CW		 1241
1242 for (i = 0; i < 3; i++) {
74d44445
DV		 1243 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1244 drm_handle_vblank(dev, i);
0e43406b
CW		 1245 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1246 intel_prepare_page_flip(dev, i);
1247 intel_finish_page_flip_plane(dev, i);
1248 }
0e43406b 1249 }
b615b57a 1250
0e43406b 1251 /* check event from PCH */
ab5c608b 1252 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
0e43406b 1253 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 1254
23e81d69 1255 cpt_irq_handler(dev, pch_iir);
b1f14ad0 1256
0e43406b
CW		 1257 /* clear PCH hotplug event before clear CPU irq */
1258 I915_WRITE(SDEIIR, pch_iir);
1259 }
b615b57a 1260
0e43406b
CW		 1261 I915_WRITE(DEIIR, de_iir);
1262 ret = IRQ_HANDLED;
b1f14ad0
JB		 1263 }
1264
0e43406b
CW		 1265 pm_iir = I915_READ(GEN6_PMIIR);
1266 if (pm_iir) {
baf02a1f
BW		 1267 if (IS_HASWELL(dev))
1268 hsw_pm_irq_handler(dev_priv, pm_iir);
4848405c 1269 else if (pm_iir & GEN6_PM_RPS_EVENTS)
0e43406b
CW		 1270 gen6_queue_rps_work(dev_priv, pm_iir);
1271 I915_WRITE(GEN6_PMIIR, pm_iir);
1272 ret = IRQ_HANDLED;
1273 }
b1f14ad0 1274
4bc9d430
DV		 1275 if (IS_HASWELL(dev)) {
1276 spin_lock(&dev_priv->irq_lock);
1277 if (ivb_can_enable_err_int(dev))
1278 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1279 spin_unlock(&dev_priv->irq_lock);
1280 }
8664281b 1281
b1f14ad0
JB		 1282 I915_WRITE(DEIER, de_ier);
1283 POSTING_READ(DEIER);
ab5c608b
BW		 1284 if (!HAS_PCH_NOP(dev)) {
1285 I915_WRITE(SDEIER, sde_ier);
1286 POSTING_READ(SDEIER);
1287 }
b1f14ad0
JB		 1288
1289 return ret;
1290}
1291
e7b4c6b1
DV		 1292static void ilk_gt_irq_handler(struct drm_device *dev,
1293 struct drm_i915_private *dev_priv,
1294 u32 gt_iir)
1295{
cc609d5d
BW		 1296 if (gt_iir &
1297 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1298 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1299 if (gt_iir & ILK_BSD_USER_INTERRUPT)
e7b4c6b1
DV		 1300 notify_ring(dev, &dev_priv->ring[VCS]);
1301}
1302
ff1f525e 1303static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 1304{
4697995b 1305 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 1306 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1307 int ret = IRQ_NONE;
44498aea 1308 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
881f47b6 1309
4697995b
JB		 1310 atomic_inc(&dev_priv->irq_received);
1311
2d109a84
ZN		 1312 /* disable master interrupt before clearing iir */
1313 de_ier = I915_READ(DEIER);
1314 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 1315 POSTING_READ(DEIER);
2d109a84 1316
44498aea
PZ		 1317 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1318 * interrupts will will be stored on its back queue, and then we'll be
1319 * able to process them after we restore SDEIER (as soon as we restore
1320 * it, we'll get an interrupt if SDEIIR still has something to process
1321 * due to its back queue). */
1322 sde_ier = I915_READ(SDEIER);
1323 I915_WRITE(SDEIER, 0);
1324 POSTING_READ(SDEIER);
1325
036a4a7d
ZW		 1326 de_iir = I915_READ(DEIIR);
1327 gt_iir = I915_READ(GTIIR);
3b8d8d91 1328 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 1329
acd15b6c 1330 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 1331 goto done;
036a4a7d 1332
c7c85101 1333 ret = IRQ_HANDLED;
036a4a7d 1334
e7b4c6b1
DV		 1335 if (IS_GEN5(dev))
1336 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1337 else
1338 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 1339
ce99c256
DV		 1340 if (de_iir & DE_AUX_CHANNEL_A)
1341 dp_aux_irq_handler(dev);
1342
c7c85101 1343 if (de_iir & DE_GSE)
81a07809 1344 intel_opregion_asle_intr(dev);
c650156a 1345
74d44445
DV		 1346 if (de_iir & DE_PIPEA_VBLANK)
1347 drm_handle_vblank(dev, 0);
1348
1349 if (de_iir & DE_PIPEB_VBLANK)
1350 drm_handle_vblank(dev, 1);
1351
de032bf4
PZ		 1352 if (de_iir & DE_POISON)
1353 DRM_ERROR("Poison interrupt\n");
1354
8664281b
PZ		 1355 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1356 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1357 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1358
1359 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1360 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1361 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1362
f072d2e7 1363 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 1364 intel_prepare_page_flip(dev, 0);
2bbda389 1365 intel_finish_page_flip_plane(dev, 0);
f072d2e7 1366 }
013d5aa2 1367
f072d2e7 1368 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 1369 intel_prepare_page_flip(dev, 1);
2bbda389 1370 intel_finish_page_flip_plane(dev, 1);
f072d2e7 1371 }
013d5aa2 1372
c7c85101 1373 /* check event from PCH */
776ad806 1374 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 1375 u32 pch_iir = I915_READ(SDEIIR);
1376
23e81d69
AJ		 1377 if (HAS_PCH_CPT(dev))
1378 cpt_irq_handler(dev, pch_iir);
1379 else
1380 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 1381
1382 /* should clear PCH hotplug event before clear CPU irq */
1383 I915_WRITE(SDEIIR, pch_iir);
776ad806 1384 }
036a4a7d 1385
73edd18f
DV		 1386 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1387 ironlake_handle_rps_change(dev);
f97108d1 1388
4848405c 1389 if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
fc6826d1 1390 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 1391
c7c85101
ZN		 1392 I915_WRITE(GTIIR, gt_iir);
1393 I915_WRITE(DEIIR, de_iir);
4912d041 1394 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 1395
1396done:
2d109a84 1397 I915_WRITE(DEIER, de_ier);
3143a2bf 1398 POSTING_READ(DEIER);
44498aea
PZ		 1399 I915_WRITE(SDEIER, sde_ier);
1400 POSTING_READ(SDEIER);
2d109a84 1401
036a4a7d
ZW		 1402 return ret;
1403}
1404
8a905236
JB		 1405/**
1406 * i915_error_work_func - do process context error handling work
1407 * @work: work struct
1408 *
1409 * Fire an error uevent so userspace can see that a hang or error
1410 * was detected.
1411 */
1412static void i915_error_work_func(struct work_struct *work)
1413{
1f83fee0
DV		 1414 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1415 work);
1416 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1417 gpu_error);
8a905236 1418 struct drm_device *dev = dev_priv->dev;
f69061be 1419 struct intel_ring_buffer *ring;
f316a42c
BG		 1420 char *error_event[] = { "ERROR=1", NULL };
1421 char *reset_event[] = { "RESET=1", NULL };
1422 char *reset_done_event[] = { "ERROR=0", NULL };
f69061be 1423 int i, ret;
8a905236 1424
f316a42c
BG		 1425 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1426
7db0ba24
DV		 1427 /*
1428 * Note that there's only one work item which does gpu resets, so we
1429 * need not worry about concurrent gpu resets potentially incrementing
1430 * error->reset_counter twice. We only need to take care of another
1431 * racing irq/hangcheck declaring the gpu dead for a second time. A
1432 * quick check for that is good enough: schedule_work ensures the
1433 * correct ordering between hang detection and this work item, and since
1434 * the reset in-progress bit is only ever set by code outside of this
1435 * work we don't need to worry about any other races.
1436 */
1437 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1438 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1439 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1440 reset_event);
1f83fee0 1441
f69061be
DV		 1442 ret = i915_reset(dev);
1443
1444 if (ret == 0) {
1445 /*
1446 * After all the gem state is reset, increment the reset
1447 * counter and wake up everyone waiting for the reset to
1448 * complete.
1449 *
1450 * Since unlock operations are a one-sided barrier only,
1451 * we need to insert a barrier here to order any seqno
1452 * updates before
1453 * the counter increment.
1454 */
1455 smp_mb__before_atomic_inc();
1456 atomic_inc(&dev_priv->gpu_error.reset_counter);
1457
1458 kobject_uevent_env(&dev->primary->kdev.kobj,
1459 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1460 } else {
1461 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1462 }
1f83fee0 1463
f69061be
DV		 1464 for_each_ring(ring, dev_priv, i)
1465 wake_up_all(&ring->irq_queue);
1466
96a02917
VS		 1467 intel_display_handle_reset(dev);
1468
1f83fee0 1469 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 1470 }
8a905236
JB		 1471}
1472
85f9e50d
DV		 1473/* NB: please notice the memset */
1474static void i915_get_extra_instdone(struct drm_device *dev,
1475 uint32_t *instdone)
1476{
1477 struct drm_i915_private *dev_priv = dev->dev_private;
1478 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1479
1480 switch(INTEL_INFO(dev)->gen) {
1481 case 2:
1482 case 3:
1483 instdone[0] = I915_READ(INSTDONE);
1484 break;
1485 case 4:
1486 case 5:
1487 case 6:
1488 instdone[0] = I915_READ(INSTDONE_I965);
1489 instdone[1] = I915_READ(INSTDONE1);
1490 break;
1491 default:
1492 WARN_ONCE(1, "Unsupported platform\n");
1493 case 7:
1494 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1495 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1496 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1497 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1498 break;
1499 }
1500}
1501
3bd3c932 1502#ifdef CONFIG_DEBUG_FS
9df30794 1503static struct drm_i915_error_object *
d0d045e8
BW		 1504i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1505 struct drm_i915_gem_object *src,
1506 const int num_pages)
9df30794
CW		 1507{
1508 struct drm_i915_error_object *dst;
d0d045e8 1509 int i;
e56660dd 1510 u32 reloc_offset;
9df30794 1511
05394f39 1512 if (src == NULL || src->pages == NULL)
9df30794
CW		 1513 return NULL;
1514
d0d045e8 1515 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 1516 if (dst == NULL)
1517 return NULL;
1518
05394f39 1519 reloc_offset = src->gtt_offset;
d0d045e8 1520 for (i = 0; i < num_pages; i++) {
788885ae 1521 unsigned long flags;
e56660dd 1522 void *d;
788885ae 1523
e56660dd 1524 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 1525 if (d == NULL)
1526 goto unwind;
e56660dd 1527
788885ae 1528 local_irq_save(flags);
5d4545ae 1529 if (reloc_offset < dev_priv->gtt.mappable_end &&
74898d7e 1530 src->has_global_gtt_mapping) {
172975aa
CW		 1531 void __iomem *s;
1532
1533 /* Simply ignore tiling or any overlapping fence.
1534 * It's part of the error state, and this hopefully
1535 * captures what the GPU read.
1536 */
1537
5d4545ae 1538 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
172975aa
CW		 1539 reloc_offset);
1540 memcpy_fromio(d, s, PAGE_SIZE);
1541 io_mapping_unmap_atomic(s);
960e3564
CW		 1542 } else if (src->stolen) {
1543 unsigned long offset;
1544
1545 offset = dev_priv->mm.stolen_base;
1546 offset += src->stolen->start;
1547 offset += i << PAGE_SHIFT;
1548
1a240d4d 1549 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 1550 } else {
9da3da66 1551 struct page *page;
172975aa
CW		 1552 void *s;
1553
9da3da66 1554 page = i915_gem_object_get_page(src, i);
172975aa 1555
9da3da66
CW		 1556 drm_clflush_pages(&page, 1);
1557
1558 s = kmap_atomic(page);
172975aa
CW		 1559 memcpy(d, s, PAGE_SIZE);
1560 kunmap_atomic(s);
1561
9da3da66 1562 drm_clflush_pages(&page, 1);
172975aa 1563 }
788885ae 1564 local_irq_restore(flags);
e56660dd 1565
9da3da66 1566 dst->pages[i] = d;
e56660dd
CW		 1567
1568 reloc_offset += PAGE_SIZE;
9df30794 1569 }
d0d045e8 1570 dst->page_count = num_pages;
05394f39 1571 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 1572
1573 return dst;
1574
1575unwind:
9da3da66
CW		 1576 while (i--)
1577 kfree(dst->pages[i]);
9df30794
CW		 1578 kfree(dst);
1579 return NULL;
1580}
d0d045e8
BW		 1581#define i915_error_object_create(dev_priv, src) \
1582 i915_error_object_create_sized((dev_priv), (src), \
1583 (src)->base.size>>PAGE_SHIFT)
9df30794
CW		 1584
1585static void
1586i915_error_object_free(struct drm_i915_error_object *obj)
1587{
1588 int page;
1589
1590 if (obj == NULL)
1591 return;
1592
1593 for (page = 0; page < obj->page_count; page++)
1594 kfree(obj->pages[page]);
1595
1596 kfree(obj);
1597}
1598
742cbee8
DV		 1599void
1600i915_error_state_free(struct kref *error_ref)
9df30794 1601{
742cbee8
DV		 1602 struct drm_i915_error_state *error = container_of(error_ref,
1603 typeof(*error), ref);
e2f973d5
CW		 1604 int i;
1605
52d39a21
CW		 1606 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1607 i915_error_object_free(error->ring[i].batchbuffer);
1608 i915_error_object_free(error->ring[i].ringbuffer);
7ed73da0 1609 i915_error_object_free(error->ring[i].ctx);
52d39a21
CW		 1610 kfree(error->ring[i].requests);
1611 }
e2f973d5 1612
9df30794 1613 kfree(error->active_bo);
6ef3d427 1614 kfree(error->overlay);
7ed73da0 1615 kfree(error->display);
9df30794
CW		 1616 kfree(error);
1617}
1b50247a
CW		 1618static void capture_bo(struct drm_i915_error_buffer *err,
1619 struct drm_i915_gem_object *obj)
1620{
1621 err->size = obj->base.size;
1622 err->name = obj->base.name;
0201f1ec
CW		 1623 err->rseqno = obj->last_read_seqno;
1624 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1625 err->gtt_offset = obj->gtt_offset;
1626 err->read_domains = obj->base.read_domains;
1627 err->write_domain = obj->base.write_domain;
1628 err->fence_reg = obj->fence_reg;
1629 err->pinned = 0;
1630 if (obj->pin_count > 0)
1631 err->pinned = 1;
1632 if (obj->user_pin_count > 0)
1633 err->pinned = -1;
1634 err->tiling = obj->tiling_mode;
1635 err->dirty = obj->dirty;
1636 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1637 err->ring = obj->ring ? obj->ring->id : -1;
1638 err->cache_level = obj->cache_level;
1639}
9df30794 1640
1b50247a
CW		 1641static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1642 int count, struct list_head *head)
c724e8a9
CW		 1643{
1644 struct drm_i915_gem_object *obj;
1645 int i = 0;
1646
1647 list_for_each_entry(obj, head, mm_list) {
1b50247a 1648 capture_bo(err++, obj);
c724e8a9
CW		 1649 if (++i == count)
1650 break;
1b50247a
CW		 1651 }
1652
1653 return i;
1654}
1655
1656static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1657 int count, struct list_head *head)
1658{
1659 struct drm_i915_gem_object *obj;
1660 int i = 0;
1661
35c20a60 1662 list_for_each_entry(obj, head, global_list) {
1b50247a
CW		 1663 if (obj->pin_count == 0)
1664 continue;
c724e8a9 1665
1b50247a
CW		 1666 capture_bo(err++, obj);
1667 if (++i == count)
1668 break;
c724e8a9
CW		 1669 }
1670
1671 return i;
1672}
1673
748ebc60
CW		 1674static void i915_gem_record_fences(struct drm_device *dev,
1675 struct drm_i915_error_state *error)
1676{
1677 struct drm_i915_private *dev_priv = dev->dev_private;
1678 int i;
1679
1680 /* Fences */
1681 switch (INTEL_INFO(dev)->gen) {
775d17b6 1682 case 7:
748ebc60 1683 case 6:
42b5aeab 1684 for (i = 0; i < dev_priv->num_fence_regs; i++)
748ebc60
CW		 1685 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1686 break;
1687 case 5:
1688 case 4:
1689 for (i = 0; i < 16; i++)
1690 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1691 break;
1692 case 3:
1693 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1694 for (i = 0; i < 8; i++)
1695 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1696 case 2:
1697 for (i = 0; i < 8; i++)
1698 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1699 break;
1700
7dbf9d6e
BW		 1701 default:
1702 BUG();
748ebc60
CW		 1703 }
1704}
1705
bcfb2e28
CW		 1706static struct drm_i915_error_object *
1707i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1708 struct intel_ring_buffer *ring)
1709{
1710 struct drm_i915_gem_object *obj;
1711 u32 seqno;
1712
1713 if (!ring->get_seqno)
1714 return NULL;
1715
b45305fc
DV		 1716 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1717 u32 acthd = I915_READ(ACTHD);
1718
1719 if (WARN_ON(ring->id != RCS))
1720 return NULL;
1721
1722 obj = ring->private;
1723 if (acthd >= obj->gtt_offset &&
1724 acthd < obj->gtt_offset + obj->base.size)
1725 return i915_error_object_create(dev_priv, obj);
1726 }
1727
b2eadbc8 1728 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1729 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1730 if (obj->ring != ring)
1731 continue;
1732
0201f1ec 1733 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1734 continue;
1735
1736 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1737 continue;
1738
1739 /* We need to copy these to an anonymous buffer as the simplest
1740 * method to avoid being overwritten by userspace.
1741 */
1742 return i915_error_object_create(dev_priv, obj);
1743 }
1744
1745 return NULL;
1746}
1747
d27b1e0e
DV		 1748static void i915_record_ring_state(struct drm_device *dev,
1749 struct drm_i915_error_state *error,
1750 struct intel_ring_buffer *ring)
1751{
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753
33f3f518 1754 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1755 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1756 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1757 error->semaphore_mboxes[ring->id][0]
1758 = I915_READ(RING_SYNC_0(ring->mmio_base));
1759 error->semaphore_mboxes[ring->id][1]
1760 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1761 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1762 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1763 }
c1cd90ed 1764
d27b1e0e 1765 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1766 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1767 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1768 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1769 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1770 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1771 if (ring->id == RCS)
d27b1e0e 1772 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1773 } else {
9d2f41fa 1774 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1775 error->ipeir[ring->id] = I915_READ(IPEIR);
1776 error->ipehr[ring->id] = I915_READ(IPEHR);
1777 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1778 }
1779
9574b3fe 1780 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1781 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1782 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1783 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1784 error->head[ring->id] = I915_READ_HEAD(ring);
1785 error->tail[ring->id] = I915_READ_TAIL(ring);
0f3b6849 1786 error->ctl[ring->id] = I915_READ_CTL(ring);
7e3b8737
DV		 1787
1788 error->cpu_ring_head[ring->id] = ring->head;
1789 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1790}
1791
8c123e54
BW		 1792
1793static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1794 struct drm_i915_error_state *error,
1795 struct drm_i915_error_ring *ering)
1796{
1797 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1798 struct drm_i915_gem_object *obj;
1799
1800 /* Currently render ring is the only HW context user */
1801 if (ring->id != RCS || !error->ccid)
1802 return;
1803
35c20a60 1804 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
8c123e54
BW		 1805 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1806 ering->ctx = i915_error_object_create_sized(dev_priv,
1807 obj, 1);
1808 }
1809 }
1810}
1811
52d39a21
CW		 1812static void i915_gem_record_rings(struct drm_device *dev,
1813 struct drm_i915_error_state *error)
1814{
1815 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1816 struct intel_ring_buffer *ring;
52d39a21
CW		 1817 struct drm_i915_gem_request *request;
1818 int i, count;
1819
b4519513 1820 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1821 i915_record_ring_state(dev, error, ring);
1822
1823 error->ring[i].batchbuffer =
1824 i915_error_first_batchbuffer(dev_priv, ring);
1825
1826 error->ring[i].ringbuffer =
1827 i915_error_object_create(dev_priv, ring->obj);
1828
8c123e54
BW		 1829
1830 i915_gem_record_active_context(ring, error, &error->ring[i]);
1831
52d39a21
CW		 1832 count = 0;
1833 list_for_each_entry(request, &ring->request_list, list)
1834 count++;
1835
1836 error->ring[i].num_requests = count;
1837 error->ring[i].requests =
1838 kmalloc(count*sizeof(struct drm_i915_error_request),
1839 GFP_ATOMIC);
1840 if (error->ring[i].requests == NULL) {
1841 error->ring[i].num_requests = 0;
1842 continue;
1843 }
1844
1845 count = 0;
1846 list_for_each_entry(request, &ring->request_list, list) {
1847 struct drm_i915_error_request *erq;
1848
1849 erq = &error->ring[i].requests[count++];
1850 erq->seqno = request->seqno;
1851 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1852 erq->tail = request->tail;
52d39a21
CW		 1853 }
1854 }
1855}
1856
8a905236
JB		 1857/**
1858 * i915_capture_error_state - capture an error record for later analysis
1859 * @dev: drm device
1860 *
1861 * Should be called when an error is detected (either a hang or an error
1862 * interrupt) to capture error state from the time of the error. Fills
1863 * out a structure which becomes available in debugfs for user level tools
1864 * to pick up.
1865 */
63eeaf38
JB		 1866static void i915_capture_error_state(struct drm_device *dev)
1867{
1868 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1869 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1870 struct drm_i915_error_state *error;
1871 unsigned long flags;
9db4a9c7 1872 int i, pipe;
63eeaf38 1873
99584db3
DV		 1874 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1875 error = dev_priv->gpu_error.first_error;
1876 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1877 if (error)
1878 return;
63eeaf38 1879
9db4a9c7 1880 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1881 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1882 if (!error) {
9df30794
CW		 1883 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1884 return;
63eeaf38
JB		 1885 }
1886
5d83d294 1887 DRM_INFO("capturing error event; look for more information in "
2f86f191 1888 "/sys/kernel/debug/dri/%d/i915_error_state\n",
b6f7833b 1889 dev->primary->index);
2fa772f3 1890
742cbee8 1891 kref_init(&error->ref);
63eeaf38
JB		 1892 error->eir = I915_READ(EIR);
1893 error->pgtbl_er = I915_READ(PGTBL_ER);
211816ec
BW		 1894 if (HAS_HW_CONTEXTS(dev))
1895 error->ccid = I915_READ(CCID);
be998e2e
BW		 1896
1897 if (HAS_PCH_SPLIT(dev))
1898 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1899 else if (IS_VALLEYVIEW(dev))
1900 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1901 else if (IS_GEN2(dev))
1902 error->ier = I915_READ16(IER);
1903 else
1904 error->ier = I915_READ(IER);
1905
0f3b6849
CW		 1906 if (INTEL_INFO(dev)->gen >= 6)
1907 error->derrmr = I915_READ(DERRMR);
1908
1909 if (IS_VALLEYVIEW(dev))
1910 error->forcewake = I915_READ(FORCEWAKE_VLV);
1911 else if (INTEL_INFO(dev)->gen >= 7)
1912 error->forcewake = I915_READ(FORCEWAKE_MT);
1913 else if (INTEL_INFO(dev)->gen == 6)
1914 error->forcewake = I915_READ(FORCEWAKE);
1915
4f3308b9
PZ		 1916 if (!HAS_PCH_SPLIT(dev))
1917 for_each_pipe(pipe)
1918 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1919
33f3f518 1920 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1921 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1922 error->done_reg = I915_READ(DONE_REG);
1923 }
d27b1e0e 1924
71e172e8
BW		 1925 if (INTEL_INFO(dev)->gen == 7)
1926 error->err_int = I915_READ(GEN7_ERR_INT);
1927
050ee91f
BW		 1928 i915_get_extra_instdone(dev, error->extra_instdone);
1929
748ebc60 1930 i915_gem_record_fences(dev, error);
52d39a21 1931 i915_gem_record_rings(dev, error);
9df30794 1932
c724e8a9 1933 /* Record buffers on the active and pinned lists. */
9df30794 1934 error->active_bo = NULL;
c724e8a9 1935 error->pinned_bo = NULL;
9df30794 1936
bcfb2e28
CW		 1937 i = 0;
1938 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1939 i++;
1940 error->active_bo_count = i;
35c20a60 1941 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1b50247a
CW		 1942 if (obj->pin_count)
1943 i++;
bcfb2e28 1944 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1945
8e934dbf
CW		 1946 error->active_bo = NULL;
1947 error->pinned_bo = NULL;
bcfb2e28
CW		 1948 if (i) {
1949 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1950 GFP_ATOMIC);
c724e8a9
CW		 1951 if (error->active_bo)
1952 error->pinned_bo =
1953 error->active_bo + error->active_bo_count;
9df30794
CW		 1954 }
1955
c724e8a9
CW		 1956 if (error->active_bo)
1957 error->active_bo_count =
1b50247a
CW		 1958 capture_active_bo(error->active_bo,
1959 error->active_bo_count,
1960 &dev_priv->mm.active_list);
c724e8a9
CW		 1961
1962 if (error->pinned_bo)
1963 error->pinned_bo_count =
1b50247a
CW		 1964 capture_pinned_bo(error->pinned_bo,
1965 error->pinned_bo_count,
6c085a72 1966 &dev_priv->mm.bound_list);
c724e8a9 1967
9df30794
CW		 1968 do_gettimeofday(&error->time);
1969
6ef3d427 1970 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1971 error->display = intel_display_capture_error_state(dev);
6ef3d427 1972
99584db3
DV		 1973 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1974 if (dev_priv->gpu_error.first_error == NULL) {
1975 dev_priv->gpu_error.first_error = error;
9df30794
CW		 1976 error = NULL;
1977 }
99584db3 1978 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1979
1980 if (error)
742cbee8 1981 i915_error_state_free(&error->ref);
9df30794
CW		 1982}
1983
1984void i915_destroy_error_state(struct drm_device *dev)
1985{
1986 struct drm_i915_private *dev_priv = dev->dev_private;
1987 struct drm_i915_error_state *error;
6dc0e816 1988 unsigned long flags;
9df30794 1989
99584db3
DV		 1990 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1991 error = dev_priv->gpu_error.first_error;
1992 dev_priv->gpu_error.first_error = NULL;
1993 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1994
1995 if (error)
742cbee8 1996 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1997}
3bd3c932
CW		 1998#else
1999#define i915_capture_error_state(x)
2000#endif
63eeaf38 2001
35aed2e6 2002static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2003{
2004 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2005 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2006 u32 eir = I915_READ(EIR);
050ee91f 2007 int pipe, i;
8a905236 2008
35aed2e6
CW		 2009 if (!eir)
2010 return;
8a905236 2011
a70491cc 2012 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2013
bd9854f9
BW		 2014 i915_get_extra_instdone(dev, instdone);
2015
8a905236
JB		 2016 if (IS_G4X(dev)) {
2017 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2018 u32 ipeir = I915_READ(IPEIR_I965);
2019
a70491cc
JP		 2020 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2021 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2022 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2023 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2024 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2025 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2026 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2027 POSTING_READ(IPEIR_I965);
8a905236
JB		 2028 }
2029 if (eir & GM45_ERROR_PAGE_TABLE) {
2030 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2031 pr_err("page table error\n");
2032 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2033 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2034 POSTING_READ(PGTBL_ER);
8a905236
JB		 2035 }
2036 }
2037
a6c45cf0 2038 if (!IS_GEN2(dev)) {
8a905236
JB		 2039 if (eir & I915_ERROR_PAGE_TABLE) {
2040 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2041 pr_err("page table error\n");
2042 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2043 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2044 POSTING_READ(PGTBL_ER);
8a905236
JB		 2045 }
2046 }
2047
2048 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2049 pr_err("memory refresh error:\n");
9db4a9c7 2050 for_each_pipe(pipe)
a70491cc 2051 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2052 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2053 /* pipestat has already been acked */
2054 }
2055 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2056 pr_err("instruction error\n");
2057 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2058 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2059 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2060 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2061 u32 ipeir = I915_READ(IPEIR);
2062
a70491cc
JP		 2063 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2064 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2065 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2066 I915_WRITE(IPEIR, ipeir);
3143a2bf 2067 POSTING_READ(IPEIR);
8a905236
JB		 2068 } else {
2069 u32 ipeir = I915_READ(IPEIR_I965);
2070
a70491cc
JP		 2071 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2072 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2073 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2074 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2075 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2076 POSTING_READ(IPEIR_I965);
8a905236
JB		 2077 }
2078 }
2079
2080 I915_WRITE(EIR, eir);
3143a2bf 2081 POSTING_READ(EIR);
8a905236
JB		 2082 eir = I915_READ(EIR);
2083 if (eir) {
2084 /*
2085 * some errors might have become stuck,
2086 * mask them.
2087 */
2088 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2089 I915_WRITE(EMR, I915_READ(EMR) | eir);
2090 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2091 }
35aed2e6
CW		 2092}
2093
2094/**
2095 * i915_handle_error - handle an error interrupt
2096 * @dev: drm device
2097 *
2098 * Do some basic checking of regsiter state at error interrupt time and
2099 * dump it to the syslog. Also call i915_capture_error_state() to make
2100 * sure we get a record and make it available in debugfs. Fire a uevent
2101 * so userspace knows something bad happened (should trigger collection
2102 * of a ring dump etc.).
2103 */
527f9e90 2104void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 2105{
2106 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 2107 struct intel_ring_buffer *ring;
2108 int i;
35aed2e6
CW		 2109
2110 i915_capture_error_state(dev);
2111 i915_report_and_clear_eir(dev);
8a905236 2112
ba1234d1 2113 if (wedged) {
f69061be
DV		 2114 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2115 &dev_priv->gpu_error.reset_counter);
ba1234d1 2116
11ed50ec 2117 /*
1f83fee0
DV		 2118 * Wakeup waiting processes so that the reset work item
2119 * doesn't deadlock trying to grab various locks.
11ed50ec 2120 */
b4519513
CW		 2121 for_each_ring(ring, dev_priv, i)
2122 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 2123 }
2124
99584db3 2125 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 2126}
2127
21ad8330 2128static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 2129{
2130 drm_i915_private_t *dev_priv = dev->dev_private;
2131 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2133 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2134 struct intel_unpin_work *work;
2135 unsigned long flags;
2136 bool stall_detected;
2137
2138 /* Ignore early vblank irqs */
2139 if (intel_crtc == NULL)
2140 return;
2141
2142 spin_lock_irqsave(&dev->event_lock, flags);
2143 work = intel_crtc->unpin_work;
2144
e7d841ca
CW		 2145 if (work == NULL ||
2146 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2147 !work->enable_stall_check) {
4e5359cd
SF		 2148 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2149 spin_unlock_irqrestore(&dev->event_lock, flags);
2150 return;
2151 }
2152
2153 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2154 obj = work->pending_flip_obj;
a6c45cf0 2155 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2156 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 2157 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2158 obj->gtt_offset;
4e5359cd 2159 } else {
9db4a9c7 2160 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 2161 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 2162 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 2163 crtc->x * crtc->fb->bits_per_pixel/8);
2164 }
2165
2166 spin_unlock_irqrestore(&dev->event_lock, flags);
2167
2168 if (stall_detected) {
2169 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2170 intel_prepare_page_flip(dev, intel_crtc->plane);
2171 }
2172}
2173
42f52ef8
KP		 2174/* Called from drm generic code, passed 'crtc' which
2175 * we use as a pipe index
2176 */
f71d4af4 2177static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2178{
2179 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2180 unsigned long irqflags;
71e0ffa5 2181
5eddb70b 2182 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2183 return -EINVAL;
0a3e67a4 2184
1ec14ad3 2185 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2186 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 2187 i915_enable_pipestat(dev_priv, pipe,
2188 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 2189 else
7c463586
KP		 2190 i915_enable_pipestat(dev_priv, pipe,
2191 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 2192
2193 /* maintain vblank delivery even in deep C-states */
2194 if (dev_priv->info->gen == 3)
6b26c86d 2195 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 2196 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2197
0a3e67a4
JB		 2198 return 0;
2199}
2200
f71d4af4 2201static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2202{
2203 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2204 unsigned long irqflags;
2205
2206 if (!i915_pipe_enabled(dev, pipe))
2207 return -EINVAL;
2208
2209 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2210 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2211 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 2212 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2213
2214 return 0;
2215}
2216
f71d4af4 2217static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2218{
2219 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2220 unsigned long irqflags;
2221
2222 if (!i915_pipe_enabled(dev, pipe))
2223 return -EINVAL;
2224
2225 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2226 ironlake_enable_display_irq(dev_priv,
2227 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 2228 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2229
2230 return 0;
2231}
2232
7e231dbe
JB		 2233static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2234{
2235 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2236 unsigned long irqflags;
31acc7f5 2237 u32 imr;
7e231dbe
JB		 2238
2239 if (!i915_pipe_enabled(dev, pipe))
2240 return -EINVAL;
2241
2242 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 2243 imr = I915_READ(VLV_IMR);
31acc7f5 2244 if (pipe == 0)
7e231dbe 2245 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2246 else
7e231dbe 2247 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2248 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 2249 i915_enable_pipestat(dev_priv, pipe,
2250 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 2251 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2252
2253 return 0;
2254}
2255
42f52ef8
KP		 2256/* Called from drm generic code, passed 'crtc' which
2257 * we use as a pipe index
2258 */
f71d4af4 2259static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2260{
2261 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2262 unsigned long irqflags;
0a3e67a4 2263
1ec14ad3 2264 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 2265 if (dev_priv->info->gen == 3)
6b26c86d 2266 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2267
f796cf8f
JB		 2268 i915_disable_pipestat(dev_priv, pipe,
2269 PIPE_VBLANK_INTERRUPT_ENABLE |
2270 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2271 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2272}
2273
f71d4af4 2274static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2275{
2276 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2277 unsigned long irqflags;
2278
2279 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2280 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2281 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 2282 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 2283}
2284
f71d4af4 2285static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2286{
2287 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2288 unsigned long irqflags;
2289
2290 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2291 ironlake_disable_display_irq(dev_priv,
2292 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 2293 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2294}
2295
7e231dbe
JB		 2296static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2297{
2298 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2299 unsigned long irqflags;
31acc7f5 2300 u32 imr;
7e231dbe
JB		 2301
2302 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2303 i915_disable_pipestat(dev_priv, pipe,
2304 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 2305 imr = I915_READ(VLV_IMR);
31acc7f5 2306 if (pipe == 0)
7e231dbe 2307 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2308 else
7e231dbe 2309 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2310 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 2311 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2312}
2313
893eead0
CW		 2314static u32
2315ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2316{
893eead0
CW		 2317 return list_entry(ring->request_list.prev,
2318 struct drm_i915_gem_request, list)->seqno;
2319}
2320
9107e9d2
CW		 2321static bool
2322ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2323{
2324 return (list_empty(&ring->request_list) ||
2325 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 2326}
2327
6274f212
CW		 2328static struct intel_ring_buffer *
2329semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 2330{
2331 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 2332 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 2333
2334 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2335 if ((ipehr & ~(0x3 << 16)) !=
2336 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 2337 return NULL;
a24a11e6
CW		 2338
2339 /* ACTHD is likely pointing to the dword after the actual command,
2340 * so scan backwards until we find the MBOX.
2341 */
6274f212 2342 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 2343 acthd_min = max((int)acthd - 3 * 4, 0);
2344 do {
2345 cmd = ioread32(ring->virtual_start + acthd);
2346 if (cmd == ipehr)
2347 break;
2348
2349 acthd -= 4;
2350 if (acthd < acthd_min)
6274f212 2351 return NULL;
a24a11e6
CW		 2352 } while (1);
2353
6274f212
CW		 2354 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2355 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 2356}
2357
6274f212
CW		 2358static int semaphore_passed(struct intel_ring_buffer *ring)
2359{
2360 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2361 struct intel_ring_buffer *signaller;
2362 u32 seqno, ctl;
2363
2364 ring->hangcheck.deadlock = true;
2365
2366 signaller = semaphore_waits_for(ring, &seqno);
2367 if (signaller == NULL || signaller->hangcheck.deadlock)
2368 return -1;
2369
2370 /* cursory check for an unkickable deadlock */
2371 ctl = I915_READ_CTL(signaller);
2372 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2373 return -1;
2374
2375 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2376}
2377
2378static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2379{
2380 struct intel_ring_buffer *ring;
2381 int i;
2382
2383 for_each_ring(ring, dev_priv, i)
2384 ring->hangcheck.deadlock = false;
2385}
2386
ad8beaea
MK		 2387static enum intel_ring_hangcheck_action
2388ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 2389{
2390 struct drm_device *dev = ring->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2392 u32 tmp;
2393
6274f212
CW		 2394 if (ring->hangcheck.acthd != acthd)
2395 return active;
2396
9107e9d2 2397 if (IS_GEN2(dev))
6274f212 2398 return hung;
9107e9d2
CW		 2399
2400 /* Is the chip hanging on a WAIT_FOR_EVENT?
2401 * If so we can simply poke the RB_WAIT bit
2402 * and break the hang. This should work on
2403 * all but the second generation chipsets.
2404 */
2405 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 2406 if (tmp & RING_WAIT) {
2407 DRM_ERROR("Kicking stuck wait on %s\n",
2408 ring->name);
2409 I915_WRITE_CTL(ring, tmp);
6274f212
CW		 2410 return kick;
2411 }
2412
2413 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2414 switch (semaphore_passed(ring)) {
2415 default:
2416 return hung;
2417 case 1:
2418 DRM_ERROR("Kicking stuck semaphore on %s\n",
2419 ring->name);
2420 I915_WRITE_CTL(ring, tmp);
2421 return kick;
2422 case 0:
2423 return wait;
2424 }
9107e9d2 2425 }
ed5cbb03 2426
6274f212 2427 return hung;
ed5cbb03
MK		 2428}
2429
f65d9421
BG		 2430/**
2431 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2432 * batchbuffers in a long time. We keep track per ring seqno progress and
2433 * if there are no progress, hangcheck score for that ring is increased.
2434 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2435 * we kick the ring. If we see no progress on three subsequent calls
2436 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421
BG		 2437 */
2438void i915_hangcheck_elapsed(unsigned long data)
2439{
2440 struct drm_device *dev = (struct drm_device *)data;
2441 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 2442 struct intel_ring_buffer *ring;
b4519513 2443 int i;
05407ff8 2444 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2445 bool stuck[I915_NUM_RINGS] = { 0 };
2446#define BUSY 1
2447#define KICK 5
2448#define HUNG 20
2449#define FIRE 30
893eead0 2450
3e0dc6b0
BW		 2451 if (!i915_enable_hangcheck)
2452 return;
2453
b4519513 2454 for_each_ring(ring, dev_priv, i) {
05407ff8 2455 u32 seqno, acthd;
9107e9d2 2456 bool busy = true;
05407ff8 2457
6274f212
CW		 2458 semaphore_clear_deadlocks(dev_priv);
2459
05407ff8
MK		 2460 seqno = ring->get_seqno(ring, false);
2461 acthd = intel_ring_get_active_head(ring);
b4519513 2462
9107e9d2
CW		 2463 if (ring->hangcheck.seqno == seqno) {
2464 if (ring_idle(ring, seqno)) {
2465 if (waitqueue_active(&ring->irq_queue)) {
2466 /* Issue a wake-up to catch stuck h/w. */
2467 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2468 ring->name);
2469 wake_up_all(&ring->irq_queue);
2470 ring->hangcheck.score += HUNG;
2471 } else
2472 busy = false;
05407ff8 2473 } else {
9107e9d2
CW		 2474 int score;
2475
6274f212
CW		 2476 /* We always increment the hangcheck score
2477 * if the ring is busy and still processing
2478 * the same request, so that no single request
2479 * can run indefinitely (such as a chain of
2480 * batches). The only time we do not increment
2481 * the hangcheck score on this ring, if this
2482 * ring is in a legitimate wait for another
2483 * ring. In that case the waiting ring is a
2484 * victim and we want to be sure we catch the
2485 * right culprit. Then every time we do kick
2486 * the ring, add a small increment to the
2487 * score so that we can catch a batch that is
2488 * being repeatedly kicked and so responsible
2489 * for stalling the machine.
2490 */
ad8beaea
MK		 2491 ring->hangcheck.action = ring_stuck(ring,
2492 acthd);
2493
2494 switch (ring->hangcheck.action) {
6274f212
CW		 2495 case wait:
2496 score = 0;
2497 break;
2498 case active:
9107e9d2 2499 score = BUSY;
6274f212
CW		 2500 break;
2501 case kick:
2502 score = KICK;
2503 break;
2504 case hung:
2505 score = HUNG;
2506 stuck[i] = true;
2507 break;
2508 }
9107e9d2 2509 ring->hangcheck.score += score;
05407ff8 2510 }
9107e9d2
CW		 2511 } else {
2512 /* Gradually reduce the count so that we catch DoS
2513 * attempts across multiple batches.
2514 */
2515 if (ring->hangcheck.score > 0)
2516 ring->hangcheck.score--;
d1e61e7f
CW		 2517 }
2518
05407ff8
MK		 2519 ring->hangcheck.seqno = seqno;
2520 ring->hangcheck.acthd = acthd;
9107e9d2 2521 busy_count += busy;
893eead0 2522 }
b9201c14 2523
92cab734 2524 for_each_ring(ring, dev_priv, i) {
9107e9d2 2525 if (ring->hangcheck.score > FIRE) {
acd78c11 2526 DRM_ERROR("%s on %s\n",
05407ff8 2527 stuck[i] ? "stuck" : "no progress",
a43adf07
CW		 2528 ring->name);
2529 rings_hung++;
92cab734
MK		 2530 }
2531 }
2532
05407ff8
MK		 2533 if (rings_hung)
2534 return i915_handle_error(dev, true);
f65d9421 2535
05407ff8
MK		 2536 if (busy_count)
2537 /* Reset timer case chip hangs without another request
2538 * being added */
2539 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2540 round_jiffies_up(jiffies +
2541 DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2542}
2543
91738a95
PZ		 2544static void ibx_irq_preinstall(struct drm_device *dev)
2545{
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2547
2548 if (HAS_PCH_NOP(dev))
2549 return;
2550
2551 /* south display irq */
2552 I915_WRITE(SDEIMR, 0xffffffff);
2553 /*
2554 * SDEIER is also touched by the interrupt handler to work around missed
2555 * PCH interrupts. Hence we can't update it after the interrupt handler
2556 * is enabled - instead we unconditionally enable all PCH interrupt
2557 * sources here, but then only unmask them as needed with SDEIMR.
2558 */
2559 I915_WRITE(SDEIER, 0xffffffff);
2560 POSTING_READ(SDEIER);
2561}
2562
1da177e4
LT		 2563/* drm_dma.h hooks
2564*/
f71d4af4 2565static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2566{
2567 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2568
4697995b
JB		 2569 atomic_set(&dev_priv->irq_received, 0);
2570
036a4a7d 2571 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2572
036a4a7d
ZW		 2573 /* XXX hotplug from PCH */
2574
2575 I915_WRITE(DEIMR, 0xffffffff);
2576 I915_WRITE(DEIER, 0x0);
3143a2bf 2577 POSTING_READ(DEIER);
036a4a7d
ZW		 2578
2579 /* and GT */
2580 I915_WRITE(GTIMR, 0xffffffff);
2581 I915_WRITE(GTIER, 0x0);
3143a2bf 2582 POSTING_READ(GTIER);
c650156a 2583
91738a95 2584 ibx_irq_preinstall(dev);
7d99163d
BW		 2585}
2586
2587static void ivybridge_irq_preinstall(struct drm_device *dev)
2588{
2589 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2590
2591 atomic_set(&dev_priv->irq_received, 0);
2592
2593 I915_WRITE(HWSTAM, 0xeffe);
2594
2595 /* XXX hotplug from PCH */
2596
2597 I915_WRITE(DEIMR, 0xffffffff);
2598 I915_WRITE(DEIER, 0x0);
2599 POSTING_READ(DEIER);
2600
2601 /* and GT */
2602 I915_WRITE(GTIMR, 0xffffffff);
2603 I915_WRITE(GTIER, 0x0);
2604 POSTING_READ(GTIER);
2605
eda63ffb
BW		 2606 /* Power management */
2607 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2608 I915_WRITE(GEN6_PMIER, 0x0);
2609 POSTING_READ(GEN6_PMIER);
2610
91738a95 2611 ibx_irq_preinstall(dev);
036a4a7d
ZW		 2612}
2613
7e231dbe
JB		 2614static void valleyview_irq_preinstall(struct drm_device *dev)
2615{
2616 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2617 int pipe;
2618
2619 atomic_set(&dev_priv->irq_received, 0);
2620
7e231dbe
JB		 2621 /* VLV magic */
2622 I915_WRITE(VLV_IMR, 0);
2623 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2624 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2625 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2626
7e231dbe
JB		 2627 /* and GT */
2628 I915_WRITE(GTIIR, I915_READ(GTIIR));
2629 I915_WRITE(GTIIR, I915_READ(GTIIR));
2630 I915_WRITE(GTIMR, 0xffffffff);
2631 I915_WRITE(GTIER, 0x0);
2632 POSTING_READ(GTIER);
2633
2634 I915_WRITE(DPINVGTT, 0xff);
2635
2636 I915_WRITE(PORT_HOTPLUG_EN, 0);
2637 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2638 for_each_pipe(pipe)
2639 I915_WRITE(PIPESTAT(pipe), 0xffff);
2640 I915_WRITE(VLV_IIR, 0xffffffff);
2641 I915_WRITE(VLV_IMR, 0xffffffff);
2642 I915_WRITE(VLV_IER, 0x0);
2643 POSTING_READ(VLV_IER);
2644}
2645
82a28bcf 2646static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2647{
2648 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2649 struct drm_mode_config *mode_config = &dev->mode_config;
2650 struct intel_encoder *intel_encoder;
2651 u32 mask = ~I915_READ(SDEIMR);
2652 u32 hotplug;
2653
2654 if (HAS_PCH_IBX(dev)) {
995e6b3d 2655 mask &= ~SDE_HOTPLUG_MASK;
82a28bcf 2656 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed
EE		 2657 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2658 mask |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2659 } else {
995e6b3d 2660 mask &= ~SDE_HOTPLUG_MASK_CPT;
82a28bcf 2661 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed
EE		 2662 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2663 mask |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2664 }
7fe0b973 2665
82a28bcf
DV		 2666 I915_WRITE(SDEIMR, ~mask);
2667
2668 /*
2669 * Enable digital hotplug on the PCH, and configure the DP short pulse
2670 * duration to 2ms (which is the minimum in the Display Port spec)
2671 *
2672 * This register is the same on all known PCH chips.
2673 */
7fe0b973
KP		 2674 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2675 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2676 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2677 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2678 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2679 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2680}
2681
d46da437
PZ		 2682static void ibx_irq_postinstall(struct drm_device *dev)
2683{
2684 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2685 u32 mask;
e5868a31 2686
692a04cf
DV		 2687 if (HAS_PCH_NOP(dev))
2688 return;
2689
8664281b
PZ		 2690 if (HAS_PCH_IBX(dev)) {
2691 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2692 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2693 } else {
2694 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2695
2696 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2697 }
ab5c608b 2698
d46da437
PZ		 2699 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2700 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2701}
2702
f71d4af4 2703static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2704{
4bc9d430
DV		 2705 unsigned long irqflags;
2706
036a4a7d
ZW		 2707 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2708 /* enable kind of interrupts always enabled */
013d5aa2 2709 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
ce99c256 2710 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
8664281b 2711 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
de032bf4 2712 DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
cc609d5d 2713 u32 gt_irqs;
036a4a7d 2714
1ec14ad3 2715 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2716
2717 /* should always can generate irq */
2718 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2719 I915_WRITE(DEIMR, dev_priv->irq_mask);
6005ce42
DV		 2720 I915_WRITE(DEIER, display_mask |
2721 DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT);
3143a2bf 2722 POSTING_READ(DEIER);
036a4a7d 2723
1ec14ad3 2724 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 2725
2726 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 2727 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 2728
cc609d5d
BW		 2729 gt_irqs = GT_RENDER_USER_INTERRUPT;
2730
1ec14ad3 2731 if (IS_GEN6(dev))
cc609d5d 2732 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
1ec14ad3 2733 else
cc609d5d
BW		 2734 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2735 ILK_BSD_USER_INTERRUPT;
2736
2737 I915_WRITE(GTIER, gt_irqs);
3143a2bf 2738 POSTING_READ(GTIER);
036a4a7d 2739
d46da437 2740 ibx_irq_postinstall(dev);
7fe0b973 2741
f97108d1 2742 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2743 /* Enable PCU event interrupts
2744 *
2745 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2746 * setup is guaranteed to run in single-threaded context. But we
2747 * need it to make the assert_spin_locked happy. */
2748 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2749 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2750 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2751 }
2752
036a4a7d
ZW		 2753 return 0;
2754}
2755
f71d4af4 2756static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2757{
2758 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2759 /* enable kind of interrupts always enabled */
b615b57a
CW		 2760 u32 display_mask =
2761 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2762 DE_PLANEC_FLIP_DONE_IVB |
2763 DE_PLANEB_FLIP_DONE_IVB |
ce99c256 2764 DE_PLANEA_FLIP_DONE_IVB |
8664281b
PZ		 2765 DE_AUX_CHANNEL_A_IVB |
2766 DE_ERR_INT_IVB;
12638c57 2767 u32 pm_irqs = GEN6_PM_RPS_EVENTS;
cc609d5d 2768 u32 gt_irqs;
b1f14ad0 2769
b1f14ad0
JB		 2770 dev_priv->irq_mask = ~display_mask;
2771
2772 /* should always can generate irq */
8664281b 2773 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
b1f14ad0
JB		 2774 I915_WRITE(DEIIR, I915_READ(DEIIR));
2775 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 2776 I915_WRITE(DEIER,
2777 display_mask |
2778 DE_PIPEC_VBLANK_IVB |
2779 DE_PIPEB_VBLANK_IVB |
2780 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 2781 POSTING_READ(DEIER);
2782
cc609d5d 2783 dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2784
2785 I915_WRITE(GTIIR, I915_READ(GTIIR));
2786 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2787
cc609d5d
BW		 2788 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2789 GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2790 I915_WRITE(GTIER, gt_irqs);
b1f14ad0
JB		 2791 POSTING_READ(GTIER);
2792
12638c57
BW		 2793 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2794 if (HAS_VEBOX(dev))
2795 pm_irqs |= PM_VEBOX_USER_INTERRUPT |
2796 PM_VEBOX_CS_ERROR_INTERRUPT;
2797
2798 /* Our enable/disable rps functions may touch these registers so
2799 * make sure to set a known state for only the non-RPS bits.
2800 * The RMW is extra paranoia since this should be called after being set
2801 * to a known state in preinstall.
2802 * */
2803 I915_WRITE(GEN6_PMIMR,
2804 (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs);
2805 I915_WRITE(GEN6_PMIER,
2806 (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs);
2807 POSTING_READ(GEN6_PMIER);
eda63ffb 2808
d46da437 2809 ibx_irq_postinstall(dev);
7fe0b973 2810
b1f14ad0
JB		 2811 return 0;
2812}
2813
7e231dbe
JB		 2814static int valleyview_irq_postinstall(struct drm_device *dev)
2815{
2816 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
cc609d5d 2817 u32 gt_irqs;
7e231dbe 2818 u32 enable_mask;
31acc7f5 2819 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
7e231dbe
JB		 2820
2821 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2822 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2823 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2824 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2825 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2826
31acc7f5
JB		 2827 /*
2828 *Leave vblank interrupts masked initially. enable/disable will
2829 * toggle them based on usage.
2830 */
2831 dev_priv->irq_mask = (~enable_mask) |
2832 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2833 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2834
20afbda2
DV		 2835 I915_WRITE(PORT_HOTPLUG_EN, 0);
2836 POSTING_READ(PORT_HOTPLUG_EN);
2837
7e231dbe
JB		 2838 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2839 I915_WRITE(VLV_IER, enable_mask);
2840 I915_WRITE(VLV_IIR, 0xffffffff);
2841 I915_WRITE(PIPESTAT(0), 0xffff);
2842 I915_WRITE(PIPESTAT(1), 0xffff);
2843 POSTING_READ(VLV_IER);
2844
31acc7f5 2845 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2846 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5
JB		 2847 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2848
7e231dbe
JB		 2849 I915_WRITE(VLV_IIR, 0xffffffff);
2850 I915_WRITE(VLV_IIR, 0xffffffff);
2851
7e231dbe 2852 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2853 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5 2854
cc609d5d
BW		 2855 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2856 GT_BLT_USER_INTERRUPT;
2857 I915_WRITE(GTIER, gt_irqs);
7e231dbe
JB		 2858 POSTING_READ(GTIER);
2859
2860 /* ack & enable invalid PTE error interrupts */
2861#if 0 /* FIXME: add support to irq handler for checking these bits */
2862 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2863 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2864#endif
2865
2866 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2867
2868 return 0;
2869}
2870
7e231dbe
JB		 2871static void valleyview_irq_uninstall(struct drm_device *dev)
2872{
2873 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2874 int pipe;
2875
2876 if (!dev_priv)
2877 return;
2878
ac4c16c5
EE		 2879 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2880
7e231dbe
JB		 2881 for_each_pipe(pipe)
2882 I915_WRITE(PIPESTAT(pipe), 0xffff);
2883
2884 I915_WRITE(HWSTAM, 0xffffffff);
2885 I915_WRITE(PORT_HOTPLUG_EN, 0);
2886 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2887 for_each_pipe(pipe)
2888 I915_WRITE(PIPESTAT(pipe), 0xffff);
2889 I915_WRITE(VLV_IIR, 0xffffffff);
2890 I915_WRITE(VLV_IMR, 0xffffffff);
2891 I915_WRITE(VLV_IER, 0x0);
2892 POSTING_READ(VLV_IER);
2893}
2894
f71d4af4 2895static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2896{
2897 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2898
2899 if (!dev_priv)
2900 return;
2901
ac4c16c5
EE		 2902 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2903
036a4a7d
ZW		 2904 I915_WRITE(HWSTAM, 0xffffffff);
2905
2906 I915_WRITE(DEIMR, 0xffffffff);
2907 I915_WRITE(DEIER, 0x0);
2908 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2909 if (IS_GEN7(dev))
2910 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2911
2912 I915_WRITE(GTIMR, 0xffffffff);
2913 I915_WRITE(GTIER, 0x0);
2914 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2915
ab5c608b
BW		 2916 if (HAS_PCH_NOP(dev))
2917 return;
2918
192aac1f
KP		 2919 I915_WRITE(SDEIMR, 0xffffffff);
2920 I915_WRITE(SDEIER, 0x0);
2921 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2922 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2923 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2924}
2925
a266c7d5 2926static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2927{
2928 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2929 int pipe;
91e3738e 2930
a266c7d5 2931 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2932
9db4a9c7
JB		 2933 for_each_pipe(pipe)
2934 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2935 I915_WRITE16(IMR, 0xffff);
2936 I915_WRITE16(IER, 0x0);
2937 POSTING_READ16(IER);
c2798b19
CW		 2938}
2939
2940static int i8xx_irq_postinstall(struct drm_device *dev)
2941{
2942 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2943
c2798b19
CW		 2944 I915_WRITE16(EMR,
2945 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2946
2947 /* Unmask the interrupts that we always want on. */
2948 dev_priv->irq_mask =
2949 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2950 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2951 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2952 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2953 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2954 I915_WRITE16(IMR, dev_priv->irq_mask);
2955
2956 I915_WRITE16(IER,
2957 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2958 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2959 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2960 I915_USER_INTERRUPT);
2961 POSTING_READ16(IER);
2962
2963 return 0;
2964}
2965
90a72f87
VS		 2966/*
2967 * Returns true when a page flip has completed.
2968 */
2969static bool i8xx_handle_vblank(struct drm_device *dev,
2970 int pipe, u16 iir)
2971{
2972 drm_i915_private_t *dev_priv = dev->dev_private;
2973 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2974
2975 if (!drm_handle_vblank(dev, pipe))
2976 return false;
2977
2978 if ((iir & flip_pending) == 0)
2979 return false;
2980
2981 intel_prepare_page_flip(dev, pipe);
2982
2983 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2984 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2985 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2986 * the flip is completed (no longer pending). Since this doesn't raise
2987 * an interrupt per se, we watch for the change at vblank.
2988 */
2989 if (I915_READ16(ISR) & flip_pending)
2990 return false;
2991
2992 intel_finish_page_flip(dev, pipe);
2993
2994 return true;
2995}
2996
ff1f525e 2997static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2998{
2999 struct drm_device *dev = (struct drm_device *) arg;
3000 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 3001 u16 iir, new_iir;
3002 u32 pipe_stats[2];
3003 unsigned long irqflags;
3004 int irq_received;
3005 int pipe;
3006 u16 flip_mask =
3007 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3008 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3009
3010 atomic_inc(&dev_priv->irq_received);
3011
3012 iir = I915_READ16(IIR);
3013 if (iir == 0)
3014 return IRQ_NONE;
3015
3016 while (iir & ~flip_mask) {
3017 /* Can't rely on pipestat interrupt bit in iir as it might
3018 * have been cleared after the pipestat interrupt was received.
3019 * It doesn't set the bit in iir again, but it still produces
3020 * interrupts (for non-MSI).
3021 */
3022 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3023 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3024 i915_handle_error(dev, false);
3025
3026 for_each_pipe(pipe) {
3027 int reg = PIPESTAT(pipe);
3028 pipe_stats[pipe] = I915_READ(reg);
3029
3030 /*
3031 * Clear the PIPE*STAT regs before the IIR
3032 */
3033 if (pipe_stats[pipe] & 0x8000ffff) {
3034 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3035 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3036 pipe_name(pipe));
3037 I915_WRITE(reg, pipe_stats[pipe]);
3038 irq_received = 1;
3039 }
3040 }
3041 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3042
3043 I915_WRITE16(IIR, iir & ~flip_mask);
3044 new_iir = I915_READ16(IIR); /* Flush posted writes */
3045
d05c617e 3046 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 3047
3048 if (iir & I915_USER_INTERRUPT)
3049 notify_ring(dev, &dev_priv->ring[RCS]);
3050
3051 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3052 i8xx_handle_vblank(dev, 0, iir))
3053 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 3054
3055 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3056 i8xx_handle_vblank(dev, 1, iir))
3057 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 3058
3059 iir = new_iir;
3060 }
3061
3062 return IRQ_HANDLED;
3063}
3064
3065static void i8xx_irq_uninstall(struct drm_device * dev)
3066{
3067 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3068 int pipe;
3069
c2798b19
CW		 3070 for_each_pipe(pipe) {
3071 /* Clear enable bits; then clear status bits */
3072 I915_WRITE(PIPESTAT(pipe), 0);
3073 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3074 }
3075 I915_WRITE16(IMR, 0xffff);
3076 I915_WRITE16(IER, 0x0);
3077 I915_WRITE16(IIR, I915_READ16(IIR));
3078}
3079
a266c7d5
CW		 3080static void i915_irq_preinstall(struct drm_device * dev)
3081{
3082 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3083 int pipe;
3084
3085 atomic_set(&dev_priv->irq_received, 0);
3086
3087 if (I915_HAS_HOTPLUG(dev)) {
3088 I915_WRITE(PORT_HOTPLUG_EN, 0);
3089 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3090 }
3091
00d98ebd 3092 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 3093 for_each_pipe(pipe)
3094 I915_WRITE(PIPESTAT(pipe), 0);
3095 I915_WRITE(IMR, 0xffffffff);
3096 I915_WRITE(IER, 0x0);
3097 POSTING_READ(IER);
3098}
3099
3100static int i915_irq_postinstall(struct drm_device *dev)
3101{
3102 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 3103 u32 enable_mask;
a266c7d5 3104
38bde180
CW		 3105 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3106
3107 /* Unmask the interrupts that we always want on. */
3108 dev_priv->irq_mask =
3109 ~(I915_ASLE_INTERRUPT |
3110 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3111 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3112 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3113 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3114 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3115
3116 enable_mask =
3117 I915_ASLE_INTERRUPT |
3118 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3119 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3120 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3121 I915_USER_INTERRUPT;
3122
a266c7d5 3123 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3124 I915_WRITE(PORT_HOTPLUG_EN, 0);
3125 POSTING_READ(PORT_HOTPLUG_EN);
3126
a266c7d5
CW		 3127 /* Enable in IER... */
3128 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3129 /* and unmask in IMR */
3130 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3131 }
3132
a266c7d5
CW		 3133 I915_WRITE(IMR, dev_priv->irq_mask);
3134 I915_WRITE(IER, enable_mask);
3135 POSTING_READ(IER);
3136
f49e38dd 3137 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3138
3139 return 0;
3140}
3141
90a72f87
VS		 3142/*
3143 * Returns true when a page flip has completed.
3144 */
3145static bool i915_handle_vblank(struct drm_device *dev,
3146 int plane, int pipe, u32 iir)
3147{
3148 drm_i915_private_t *dev_priv = dev->dev_private;
3149 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3150
3151 if (!drm_handle_vblank(dev, pipe))
3152 return false;
3153
3154 if ((iir & flip_pending) == 0)
3155 return false;
3156
3157 intel_prepare_page_flip(dev, plane);
3158
3159 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3160 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3161 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3162 * the flip is completed (no longer pending). Since this doesn't raise
3163 * an interrupt per se, we watch for the change at vblank.
3164 */
3165 if (I915_READ(ISR) & flip_pending)
3166 return false;
3167
3168 intel_finish_page_flip(dev, pipe);
3169
3170 return true;
3171}
3172
ff1f525e 3173static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 3174{
3175 struct drm_device *dev = (struct drm_device *) arg;
3176 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 3177 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 3178 unsigned long irqflags;
38bde180
CW		 3179 u32 flip_mask =
3180 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3181 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3182 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 3183
3184 atomic_inc(&dev_priv->irq_received);
3185
3186 iir = I915_READ(IIR);
38bde180
CW		 3187 do {
3188 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3189 bool blc_event = false;
a266c7d5
CW		 3190
3191 /* Can't rely on pipestat interrupt bit in iir as it might
3192 * have been cleared after the pipestat interrupt was received.
3193 * It doesn't set the bit in iir again, but it still produces
3194 * interrupts (for non-MSI).
3195 */
3196 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3197 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3198 i915_handle_error(dev, false);
3199
3200 for_each_pipe(pipe) {
3201 int reg = PIPESTAT(pipe);
3202 pipe_stats[pipe] = I915_READ(reg);
3203
38bde180 3204 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 3205 if (pipe_stats[pipe] & 0x8000ffff) {
3206 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3207 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3208 pipe_name(pipe));
3209 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3210 irq_received = true;
a266c7d5
CW		 3211 }
3212 }
3213 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3214
3215 if (!irq_received)
3216 break;
3217
a266c7d5
CW		 3218 /* Consume port. Then clear IIR or we'll miss events */
3219 if ((I915_HAS_HOTPLUG(dev)) &&
3220 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3221 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 3222 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 3223
3224 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3225 hotplug_status);
91d131d2
DV		 3226
3227 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3228
a266c7d5 3229 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 3230 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 3231 }
3232
38bde180 3233 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3234 new_iir = I915_READ(IIR); /* Flush posted writes */
3235
a266c7d5
CW		 3236 if (iir & I915_USER_INTERRUPT)
3237 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3238
a266c7d5 3239 for_each_pipe(pipe) {
38bde180
CW		 3240 int plane = pipe;
3241 if (IS_MOBILE(dev))
3242 plane = !plane;
90a72f87 3243
8291ee90 3244 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3245 i915_handle_vblank(dev, plane, pipe, iir))
3246 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3247
3248 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3249 blc_event = true;
3250 }
3251
a266c7d5
CW		 3252 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3253 intel_opregion_asle_intr(dev);
3254
3255 /* With MSI, interrupts are only generated when iir
3256 * transitions from zero to nonzero. If another bit got
3257 * set while we were handling the existing iir bits, then
3258 * we would never get another interrupt.
3259 *
3260 * This is fine on non-MSI as well, as if we hit this path
3261 * we avoid exiting the interrupt handler only to generate
3262 * another one.
3263 *
3264 * Note that for MSI this could cause a stray interrupt report
3265 * if an interrupt landed in the time between writing IIR and
3266 * the posting read. This should be rare enough to never
3267 * trigger the 99% of 100,000 interrupts test for disabling
3268 * stray interrupts.
3269 */
38bde180 3270 ret = IRQ_HANDLED;
a266c7d5 3271 iir = new_iir;
38bde180 3272 } while (iir & ~flip_mask);
a266c7d5 3273
d05c617e 3274 i915_update_dri1_breadcrumb(dev);
8291ee90 3275
a266c7d5
CW		 3276 return ret;
3277}
3278
3279static void i915_irq_uninstall(struct drm_device * dev)
3280{
3281 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3282 int pipe;
3283
ac4c16c5
EE		 3284 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3285
a266c7d5
CW		 3286 if (I915_HAS_HOTPLUG(dev)) {
3287 I915_WRITE(PORT_HOTPLUG_EN, 0);
3288 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3289 }
3290
00d98ebd 3291 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3292 for_each_pipe(pipe) {
3293 /* Clear enable bits; then clear status bits */
a266c7d5 3294 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3295 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3296 }
a266c7d5
CW		 3297 I915_WRITE(IMR, 0xffffffff);
3298 I915_WRITE(IER, 0x0);
3299
a266c7d5
CW		 3300 I915_WRITE(IIR, I915_READ(IIR));
3301}
3302
3303static void i965_irq_preinstall(struct drm_device * dev)
3304{
3305 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3306 int pipe;
3307
3308 atomic_set(&dev_priv->irq_received, 0);
3309
adca4730
CW		 3310 I915_WRITE(PORT_HOTPLUG_EN, 0);
3311 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3312
3313 I915_WRITE(HWSTAM, 0xeffe);
3314 for_each_pipe(pipe)
3315 I915_WRITE(PIPESTAT(pipe), 0);
3316 I915_WRITE(IMR, 0xffffffff);
3317 I915_WRITE(IER, 0x0);
3318 POSTING_READ(IER);
3319}
3320
3321static int i965_irq_postinstall(struct drm_device *dev)
3322{
3323 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 3324 u32 enable_mask;
a266c7d5
CW		 3325 u32 error_mask;
3326
a266c7d5 3327 /* Unmask the interrupts that we always want on. */
bbba0a97 3328 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3329 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3330 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3331 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3332 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3333 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3334 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3335
3336 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3337 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3338 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3339 enable_mask |= I915_USER_INTERRUPT;
3340
3341 if (IS_G4X(dev))
3342 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3343
515ac2bb 3344 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
a266c7d5 3345
a266c7d5
CW		 3346 /*
3347 * Enable some error detection, note the instruction error mask
3348 * bit is reserved, so we leave it masked.
3349 */
3350 if (IS_G4X(dev)) {
3351 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3352 GM45_ERROR_MEM_PRIV |
3353 GM45_ERROR_CP_PRIV |
3354 I915_ERROR_MEMORY_REFRESH);
3355 } else {
3356 error_mask = ~(I915_ERROR_PAGE_TABLE |
3357 I915_ERROR_MEMORY_REFRESH);
3358 }
3359 I915_WRITE(EMR, error_mask);
3360
3361 I915_WRITE(IMR, dev_priv->irq_mask);
3362 I915_WRITE(IER, enable_mask);
3363 POSTING_READ(IER);
3364
20afbda2
DV		 3365 I915_WRITE(PORT_HOTPLUG_EN, 0);
3366 POSTING_READ(PORT_HOTPLUG_EN);
3367
f49e38dd 3368 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3369
3370 return 0;
3371}
3372
bac56d5b 3373static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 3374{
3375 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 3376 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3377 struct intel_encoder *intel_encoder;
20afbda2
DV		 3378 u32 hotplug_en;
3379
b5ea2d56
DV		 3380 assert_spin_locked(&dev_priv->irq_lock);
3381
bac56d5b
EE		 3382 if (I915_HAS_HOTPLUG(dev)) {
3383 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3384 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3385 /* Note HDMI and DP share hotplug bits */
e5868a31 3386 /* enable bits are the same for all generations */
cd569aed
EE		 3387 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3388 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3389 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3390 /* Programming the CRT detection parameters tends
3391 to generate a spurious hotplug event about three
3392 seconds later. So just do it once.
3393 */
3394 if (IS_G4X(dev))
3395 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3396 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3397 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3398
bac56d5b
EE		 3399 /* Ignore TV since it's buggy */
3400 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3401 }
a266c7d5
CW		 3402}
3403
ff1f525e 3404static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3405{
3406 struct drm_device *dev = (struct drm_device *) arg;
3407 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 3408 u32 iir, new_iir;
3409 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 3410 unsigned long irqflags;
3411 int irq_received;
3412 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3413 u32 flip_mask =
3414 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3415 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 3416
3417 atomic_inc(&dev_priv->irq_received);
3418
3419 iir = I915_READ(IIR);
3420
a266c7d5 3421 for (;;) {
2c8ba29f
CW		 3422 bool blc_event = false;
3423
21ad8330 3424 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 3425
3426 /* Can't rely on pipestat interrupt bit in iir as it might
3427 * have been cleared after the pipestat interrupt was received.
3428 * It doesn't set the bit in iir again, but it still produces
3429 * interrupts (for non-MSI).
3430 */
3431 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3432 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3433 i915_handle_error(dev, false);
3434
3435 for_each_pipe(pipe) {
3436 int reg = PIPESTAT(pipe);
3437 pipe_stats[pipe] = I915_READ(reg);
3438
3439 /*
3440 * Clear the PIPE*STAT regs before the IIR
3441 */
3442 if (pipe_stats[pipe] & 0x8000ffff) {
3443 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3444 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3445 pipe_name(pipe));
3446 I915_WRITE(reg, pipe_stats[pipe]);
3447 irq_received = 1;
3448 }
3449 }
3450 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3451
3452 if (!irq_received)
3453 break;
3454
3455 ret = IRQ_HANDLED;
3456
3457 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3458 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3459 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3460 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3461 HOTPLUG_INT_STATUS_G4X :
4f7fd709 3462 HOTPLUG_INT_STATUS_I915);
a266c7d5
CW		 3463
3464 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3465 hotplug_status);
91d131d2
DV		 3466
3467 intel_hpd_irq_handler(dev, hotplug_trigger,
3468 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3469
a266c7d5
CW		 3470 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3471 I915_READ(PORT_HOTPLUG_STAT);
3472 }
3473
21ad8330 3474 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3475 new_iir = I915_READ(IIR); /* Flush posted writes */
3476
a266c7d5
CW		 3477 if (iir & I915_USER_INTERRUPT)
3478 notify_ring(dev, &dev_priv->ring[RCS]);
3479 if (iir & I915_BSD_USER_INTERRUPT)
3480 notify_ring(dev, &dev_priv->ring[VCS]);
3481
a266c7d5 3482 for_each_pipe(pipe) {
2c8ba29f 3483 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3484 i915_handle_vblank(dev, pipe, pipe, iir))
3485 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3486
3487 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3488 blc_event = true;
3489 }
3490
3491
3492 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3493 intel_opregion_asle_intr(dev);
3494
515ac2bb
DV		 3495 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3496 gmbus_irq_handler(dev);
3497
a266c7d5
CW		 3498 /* With MSI, interrupts are only generated when iir
3499 * transitions from zero to nonzero. If another bit got
3500 * set while we were handling the existing iir bits, then
3501 * we would never get another interrupt.
3502 *
3503 * This is fine on non-MSI as well, as if we hit this path
3504 * we avoid exiting the interrupt handler only to generate
3505 * another one.
3506 *
3507 * Note that for MSI this could cause a stray interrupt report
3508 * if an interrupt landed in the time between writing IIR and
3509 * the posting read. This should be rare enough to never
3510 * trigger the 99% of 100,000 interrupts test for disabling
3511 * stray interrupts.
3512 */
3513 iir = new_iir;
3514 }
3515
d05c617e 3516 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3517
a266c7d5
CW		 3518 return ret;
3519}
3520
3521static void i965_irq_uninstall(struct drm_device * dev)
3522{
3523 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3524 int pipe;
3525
3526 if (!dev_priv)
3527 return;
3528
ac4c16c5
EE		 3529 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3530
adca4730
CW		 3531 I915_WRITE(PORT_HOTPLUG_EN, 0);
3532 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3533
3534 I915_WRITE(HWSTAM, 0xffffffff);
3535 for_each_pipe(pipe)
3536 I915_WRITE(PIPESTAT(pipe), 0);
3537 I915_WRITE(IMR, 0xffffffff);
3538 I915_WRITE(IER, 0x0);
3539
3540 for_each_pipe(pipe)
3541 I915_WRITE(PIPESTAT(pipe),
3542 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3543 I915_WRITE(IIR, I915_READ(IIR));
3544}
3545
ac4c16c5
EE		 3546static void i915_reenable_hotplug_timer_func(unsigned long data)
3547{
3548 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3549 struct drm_device *dev = dev_priv->dev;
3550 struct drm_mode_config *mode_config = &dev->mode_config;
3551 unsigned long irqflags;
3552 int i;
3553
3554 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3555 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3556 struct drm_connector *connector;
3557
3558 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3559 continue;
3560
3561 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3562
3563 list_for_each_entry(connector, &mode_config->connector_list, head) {
3564 struct intel_connector *intel_connector = to_intel_connector(connector);
3565
3566 if (intel_connector->encoder->hpd_pin == i) {
3567 if (connector->polled != intel_connector->polled)
3568 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3569 drm_get_connector_name(connector));
3570 connector->polled = intel_connector->polled;
3571 if (!connector->polled)
3572 connector->polled = DRM_CONNECTOR_POLL_HPD;
3573 }
3574 }
3575 }
3576 if (dev_priv->display.hpd_irq_setup)
3577 dev_priv->display.hpd_irq_setup(dev);
3578 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3579}
3580
f71d4af4
JB		 3581void intel_irq_init(struct drm_device *dev)
3582{
8b2e326d
CW		 3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584
3585 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3586 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3587 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3588 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3589
99584db3
DV		 3590 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3591 i915_hangcheck_elapsed,
61bac78e 3592 (unsigned long) dev);
ac4c16c5
EE		 3593 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3594 (unsigned long) dev_priv);
61bac78e 3595
97a19a24 3596 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3597
f71d4af4
JB		 3598 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3599 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 3600 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3601 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3602 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3603 }
3604
c3613de9
KP		 3605 if (drm_core_check_feature(dev, DRIVER_MODESET))
3606 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3607 else
3608 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 3609 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3610
7e231dbe
JB		 3611 if (IS_VALLEYVIEW(dev)) {
3612 dev->driver->irq_handler = valleyview_irq_handler;
3613 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3614 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3615 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3616 dev->driver->enable_vblank = valleyview_enable_vblank;
3617 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3618 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4a06e201 3619 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7d99163d 3620 /* Share uninstall handlers with ILK/SNB */
f71d4af4 3621 dev->driver->irq_handler = ivybridge_irq_handler;
7d99163d 3622 dev->driver->irq_preinstall = ivybridge_irq_preinstall;
f71d4af4
JB		 3623 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3624 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3625 dev->driver->enable_vblank = ivybridge_enable_vblank;
3626 dev->driver->disable_vblank = ivybridge_disable_vblank;
82a28bcf 3627 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 3628 } else if (HAS_PCH_SPLIT(dev)) {
3629 dev->driver->irq_handler = ironlake_irq_handler;
3630 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3631 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3632 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3633 dev->driver->enable_vblank = ironlake_enable_vblank;
3634 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3635 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3636 } else {
c2798b19
CW		 3637 if (INTEL_INFO(dev)->gen == 2) {
3638 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3639 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3640 dev->driver->irq_handler = i8xx_irq_handler;
3641 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3642 } else if (INTEL_INFO(dev)->gen == 3) {
3643 dev->driver->irq_preinstall = i915_irq_preinstall;
3644 dev->driver->irq_postinstall = i915_irq_postinstall;
3645 dev->driver->irq_uninstall = i915_irq_uninstall;
3646 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3647 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3648 } else {
a266c7d5
CW		 3649 dev->driver->irq_preinstall = i965_irq_preinstall;
3650 dev->driver->irq_postinstall = i965_irq_postinstall;
3651 dev->driver->irq_uninstall = i965_irq_uninstall;
3652 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3653 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3654 }
f71d4af4
JB		 3655 dev->driver->enable_vblank = i915_enable_vblank;
3656 dev->driver->disable_vblank = i915_disable_vblank;
3657 }
3658}
20afbda2
DV		 3659
3660void intel_hpd_init(struct drm_device *dev)
3661{
3662 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3663 struct drm_mode_config *mode_config = &dev->mode_config;
3664 struct drm_connector *connector;
b5ea2d56 3665 unsigned long irqflags;
821450c6 3666 int i;
20afbda2 3667
821450c6
EE		 3668 for (i = 1; i < HPD_NUM_PINS; i++) {
3669 dev_priv->hpd_stats[i].hpd_cnt = 0;
3670 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3671 }
3672 list_for_each_entry(connector, &mode_config->connector_list, head) {
3673 struct intel_connector *intel_connector = to_intel_connector(connector);
3674 connector->polled = intel_connector->polled;
3675 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3676 connector->polled = DRM_CONNECTOR_POLL_HPD;
3677 }
b5ea2d56
DV		 3678
3679 /* Interrupt setup is already guaranteed to be single-threaded, this is
3680 * just to make the assert_spin_locked checks happy. */
3681 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3682 if (dev_priv->display.hpd_irq_setup)
3683 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3684 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3685}
Linux kernel - Deliverables
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