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drm/i915: add new Haswell DIP controls registers
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
f97108d1
JB		 299static void i915_handle_rps_change(struct drm_device *dev)
300{
301 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 302 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 303 u8 new_delay = dev_priv->cur_delay;
304
7648fa99 305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
310
311 /* Handle RCS change request from hw */
b5b72e89 312 if (busy_up > max_avg) {
f97108d1
JB		 313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
b5b72e89 317 } else if (busy_down < min_avg) {
f97108d1
JB		 318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
322 }
323
7648fa99
JB		 324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
f97108d1
JB		 326
327 return;
328}
329
549f7365
CW		 330static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
332{
333 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 334
475553de
CW		 335 if (ring->obj == NULL)
336 return;
337
6d171cb4 338 trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
9862e600 339
549f7365 340 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 341 if (i915_enable_hangcheck) {
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer,
344 jiffies +
345 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
346 }
549f7365
CW		 347}
348
4912d041 349static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 350{
4912d041
BW		 351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
352 rps_work);
3b8d8d91 353 u8 new_delay = dev_priv->cur_delay;
4912d041
BW		 354 u32 pm_iir, pm_imr;
355
356 spin_lock_irq(&dev_priv->rps_lock);
357 pm_iir = dev_priv->pm_iir;
358 dev_priv->pm_iir = 0;
359 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 360 I915_WRITE(GEN6_PMIMR, 0);
4912d041 361 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 362
3b8d8d91
JB		 363 if (!pm_iir)
364 return;
365
4912d041 366 mutex_lock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 367 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
368 if (dev_priv->cur_delay != dev_priv->max_delay)
369 new_delay = dev_priv->cur_delay + 1;
370 if (new_delay > dev_priv->max_delay)
371 new_delay = dev_priv->max_delay;
372 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
4912d041 373 gen6_gt_force_wake_get(dev_priv);
3b8d8d91
JB		 374 if (dev_priv->cur_delay != dev_priv->min_delay)
375 new_delay = dev_priv->cur_delay - 1;
376 if (new_delay < dev_priv->min_delay) {
377 new_delay = dev_priv->min_delay;
378 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
379 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
380 ((new_delay << 16) & 0x3f0000));
381 } else {
382 /* Make sure we continue to get down interrupts
383 * until we hit the minimum frequency */
384 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
385 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
386 }
4912d041 387 gen6_gt_force_wake_put(dev_priv);
3b8d8d91
JB		 388 }
389
4912d041 390 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91
JB		 391 dev_priv->cur_delay = new_delay;
392
4912d041
BW		 393 /*
394 * rps_lock not held here because clearing is non-destructive. There is
395 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
396 * by holding struct_mutex for the duration of the write.
397 */
4912d041 398 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 399}
400
e7b4c6b1
DV		 401static void snb_gt_irq_handler(struct drm_device *dev,
402 struct drm_i915_private *dev_priv,
403 u32 gt_iir)
404{
405
406 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
407 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
408 notify_ring(dev, &dev_priv->ring[RCS]);
409 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
410 notify_ring(dev, &dev_priv->ring[VCS]);
411 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
412 notify_ring(dev, &dev_priv->ring[BCS]);
413
414 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
415 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
416 GT_RENDER_CS_ERROR_INTERRUPT)) {
417 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
418 i915_handle_error(dev, false);
419 }
420}
421
fc6826d1
CW		 422static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
423 u32 pm_iir)
424{
425 unsigned long flags;
426
427 /*
428 * IIR bits should never already be set because IMR should
429 * prevent an interrupt from being shown in IIR. The warning
430 * displays a case where we've unsafely cleared
431 * dev_priv->pm_iir. Although missing an interrupt of the same
432 * type is not a problem, it displays a problem in the logic.
433 *
434 * The mask bit in IMR is cleared by rps_work.
435 */
436
437 spin_lock_irqsave(&dev_priv->rps_lock, flags);
438 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
439 dev_priv->pm_iir |= pm_iir;
440 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
441 POSTING_READ(GEN6_PMIMR);
442 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
443
444 queue_work(dev_priv->wq, &dev_priv->rps_work);
445}
446
7e231dbe
JB		 447static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
448{
449 struct drm_device *dev = (struct drm_device *) arg;
450 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
451 u32 iir, gt_iir, pm_iir;
452 irqreturn_t ret = IRQ_NONE;
453 unsigned long irqflags;
454 int pipe;
455 u32 pipe_stats[I915_MAX_PIPES];
456 u32 vblank_status;
457 int vblank = 0;
458 bool blc_event;
459
460 atomic_inc(&dev_priv->irq_received);
461
462 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
463 PIPE_VBLANK_INTERRUPT_STATUS;
464
465 while (true) {
466 iir = I915_READ(VLV_IIR);
467 gt_iir = I915_READ(GTIIR);
468 pm_iir = I915_READ(GEN6_PMIIR);
469
470 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
471 goto out;
472
473 ret = IRQ_HANDLED;
474
e7b4c6b1 475 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 476
477 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
478 for_each_pipe(pipe) {
479 int reg = PIPESTAT(pipe);
480 pipe_stats[pipe] = I915_READ(reg);
481
482 /*
483 * Clear the PIPE*STAT regs before the IIR
484 */
485 if (pipe_stats[pipe] & 0x8000ffff) {
486 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
487 DRM_DEBUG_DRIVER("pipe %c underrun\n",
488 pipe_name(pipe));
489 I915_WRITE(reg, pipe_stats[pipe]);
490 }
491 }
492 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
493
494 /* Consume port. Then clear IIR or we'll miss events */
495 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
496 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
497
498 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
499 hotplug_status);
500 if (hotplug_status & dev_priv->hotplug_supported_mask)
501 queue_work(dev_priv->wq,
502 &dev_priv->hotplug_work);
503
504 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
505 I915_READ(PORT_HOTPLUG_STAT);
506 }
507
508
509 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
510 drm_handle_vblank(dev, 0);
511 vblank++;
e0f608d7 512 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 513 }
514
515 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
516 drm_handle_vblank(dev, 1);
517 vblank++;
e0f608d7 518 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 519 }
520
521 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
522 blc_event = true;
523
fc6826d1
CW		 524 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
525 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 526
527 I915_WRITE(GTIIR, gt_iir);
528 I915_WRITE(GEN6_PMIIR, pm_iir);
529 I915_WRITE(VLV_IIR, iir);
530 }
531
532out:
533 return ret;
534}
535
9adab8b5 536static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 537{
538 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 539 int pipe;
776ad806 540
776ad806
JB		 541 if (pch_iir & SDE_AUDIO_POWER_MASK)
542 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
543 (pch_iir & SDE_AUDIO_POWER_MASK) >>
544 SDE_AUDIO_POWER_SHIFT);
545
546 if (pch_iir & SDE_GMBUS)
547 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
548
549 if (pch_iir & SDE_AUDIO_HDCP_MASK)
550 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
551
552 if (pch_iir & SDE_AUDIO_TRANS_MASK)
553 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
554
555 if (pch_iir & SDE_POISON)
556 DRM_ERROR("PCH poison interrupt\n");
557
9db4a9c7
JB		 558 if (pch_iir & SDE_FDI_MASK)
559 for_each_pipe(pipe)
560 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
561 pipe_name(pipe),
562 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 563
564 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
565 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
566
567 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
568 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
569
570 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
571 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
572 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
573 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
574}
575
f71d4af4 576static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 577{
578 struct drm_device *dev = (struct drm_device *) arg;
579 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 580 u32 de_iir, gt_iir, de_ier, pm_iir;
581 irqreturn_t ret = IRQ_NONE;
582 int i;
b1f14ad0
JB		 583
584 atomic_inc(&dev_priv->irq_received);
585
586 /* disable master interrupt before clearing iir */
587 de_ier = I915_READ(DEIER);
588 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 589
b1f14ad0 590 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 591 if (gt_iir) {
592 snb_gt_irq_handler(dev, dev_priv, gt_iir);
593 I915_WRITE(GTIIR, gt_iir);
594 ret = IRQ_HANDLED;
b1f14ad0
JB		 595 }
596
0e43406b
CW		 597 de_iir = I915_READ(DEIIR);
598 if (de_iir) {
599 if (de_iir & DE_GSE_IVB)
600 intel_opregion_gse_intr(dev);
601
602 for (i = 0; i < 3; i++) {
603 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
604 intel_prepare_page_flip(dev, i);
605 intel_finish_page_flip_plane(dev, i);
606 }
607 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
608 drm_handle_vblank(dev, i);
609 }
b615b57a 610
0e43406b
CW		 611 /* check event from PCH */
612 if (de_iir & DE_PCH_EVENT_IVB) {
613 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 614
0e43406b
CW		 615 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
616 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
617 pch_irq_handler(dev, pch_iir);
b1f14ad0 618
0e43406b
CW		 619 /* clear PCH hotplug event before clear CPU irq */
620 I915_WRITE(SDEIIR, pch_iir);
621 }
b615b57a 622
0e43406b
CW		 623 I915_WRITE(DEIIR, de_iir);
624 ret = IRQ_HANDLED;
b1f14ad0
JB		 625 }
626
0e43406b
CW		 627 pm_iir = I915_READ(GEN6_PMIIR);
628 if (pm_iir) {
629 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
630 gen6_queue_rps_work(dev_priv, pm_iir);
631 I915_WRITE(GEN6_PMIIR, pm_iir);
632 ret = IRQ_HANDLED;
633 }
b1f14ad0 634
b1f14ad0
JB		 635 I915_WRITE(DEIER, de_ier);
636 POSTING_READ(DEIER);
637
638 return ret;
639}
640
e7b4c6b1
DV		 641static void ilk_gt_irq_handler(struct drm_device *dev,
642 struct drm_i915_private *dev_priv,
643 u32 gt_iir)
644{
645 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
646 notify_ring(dev, &dev_priv->ring[RCS]);
647 if (gt_iir & GT_BSD_USER_INTERRUPT)
648 notify_ring(dev, &dev_priv->ring[VCS]);
649}
650
f71d4af4 651static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 652{
4697995b 653 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 654 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
655 int ret = IRQ_NONE;
3b8d8d91 656 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 657 u32 hotplug_mask;
881f47b6 658
4697995b
JB		 659 atomic_inc(&dev_priv->irq_received);
660
2d109a84
ZN		 661 /* disable master interrupt before clearing iir */
662 de_ier = I915_READ(DEIER);
663 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 664 POSTING_READ(DEIER);
2d109a84 665
036a4a7d
ZW		 666 de_iir = I915_READ(DEIIR);
667 gt_iir = I915_READ(GTIIR);
c650156a 668 pch_iir = I915_READ(SDEIIR);
3b8d8d91 669 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 670
3b8d8d91
JB		 671 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
672 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 673 goto done;
036a4a7d 674
2d7b8366
YL		 675 if (HAS_PCH_CPT(dev))
676 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
677 else
678 hotplug_mask = SDE_HOTPLUG_MASK;
679
c7c85101 680 ret = IRQ_HANDLED;
036a4a7d 681
e7b4c6b1
DV		 682 if (IS_GEN5(dev))
683 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
684 else
685 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 686
c7c85101 687 if (de_iir & DE_GSE)
3b617967 688 intel_opregion_gse_intr(dev);
c650156a 689
f072d2e7 690 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 691 intel_prepare_page_flip(dev, 0);
2bbda389 692 intel_finish_page_flip_plane(dev, 0);
f072d2e7 693 }
013d5aa2 694
f072d2e7 695 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 696 intel_prepare_page_flip(dev, 1);
2bbda389 697 intel_finish_page_flip_plane(dev, 1);
f072d2e7 698 }
013d5aa2 699
f072d2e7 700 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 701 drm_handle_vblank(dev, 0);
702
f072d2e7 703 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 704 drm_handle_vblank(dev, 1);
705
c7c85101 706 /* check event from PCH */
776ad806
JB		 707 if (de_iir & DE_PCH_EVENT) {
708 if (pch_iir & hotplug_mask)
709 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
9adab8b5 710 pch_irq_handler(dev, pch_iir);
776ad806 711 }
036a4a7d 712
f97108d1 713 if (de_iir & DE_PCU_EVENT) {
7648fa99 714 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 715 i915_handle_rps_change(dev);
716 }
717
fc6826d1
CW		 718 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
719 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 720
c7c85101
ZN		 721 /* should clear PCH hotplug event before clear CPU irq */
722 I915_WRITE(SDEIIR, pch_iir);
723 I915_WRITE(GTIIR, gt_iir);
724 I915_WRITE(DEIIR, de_iir);
4912d041 725 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 726
727done:
2d109a84 728 I915_WRITE(DEIER, de_ier);
3143a2bf 729 POSTING_READ(DEIER);
2d109a84 730
036a4a7d
ZW		 731 return ret;
732}
733
8a905236
JB		 734/**
735 * i915_error_work_func - do process context error handling work
736 * @work: work struct
737 *
738 * Fire an error uevent so userspace can see that a hang or error
739 * was detected.
740 */
741static void i915_error_work_func(struct work_struct *work)
742{
743 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
744 error_work);
745 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 746 char *error_event[] = { "ERROR=1", NULL };
747 char *reset_event[] = { "RESET=1", NULL };
748 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 749
f316a42c
BG		 750 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
751
ba1234d1 752 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 753 DRM_DEBUG_DRIVER("resetting chip\n");
754 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 755 if (!i915_reset(dev)) {
f803aa55
CW		 756 atomic_set(&dev_priv->mm.wedged, 0);
757 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 758 }
30dbf0c0 759 complete_all(&dev_priv->error_completion);
f316a42c 760 }
8a905236
JB		 761}
762
3bd3c932 763#ifdef CONFIG_DEBUG_FS
9df30794 764static struct drm_i915_error_object *
bcfb2e28 765i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 766 struct drm_i915_gem_object *src)
9df30794
CW		 767{
768 struct drm_i915_error_object *dst;
9df30794 769 int page, page_count;
e56660dd 770 u32 reloc_offset;
9df30794 771
05394f39 772 if (src == NULL || src->pages == NULL)
9df30794
CW		 773 return NULL;
774
05394f39 775 page_count = src->base.size / PAGE_SIZE;
9df30794 776
0206e353 777 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 778 if (dst == NULL)
779 return NULL;
780
05394f39 781 reloc_offset = src->gtt_offset;
9df30794 782 for (page = 0; page < page_count; page++) {
788885ae 783 unsigned long flags;
e56660dd 784 void *d;
788885ae 785
e56660dd 786 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 787 if (d == NULL)
788 goto unwind;
e56660dd 789
788885ae 790 local_irq_save(flags);
74898d7e
DV		 791 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
792 src->has_global_gtt_mapping) {
172975aa
CW		 793 void __iomem *s;
794
795 /* Simply ignore tiling or any overlapping fence.
796 * It's part of the error state, and this hopefully
797 * captures what the GPU read.
798 */
799
800 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
801 reloc_offset);
802 memcpy_fromio(d, s, PAGE_SIZE);
803 io_mapping_unmap_atomic(s);
804 } else {
805 void *s;
806
807 drm_clflush_pages(&src->pages[page], 1);
808
809 s = kmap_atomic(src->pages[page]);
810 memcpy(d, s, PAGE_SIZE);
811 kunmap_atomic(s);
812
813 drm_clflush_pages(&src->pages[page], 1);
814 }
788885ae 815 local_irq_restore(flags);
e56660dd 816
9df30794 817 dst->pages[page] = d;
e56660dd
CW		 818
819 reloc_offset += PAGE_SIZE;
9df30794
CW		 820 }
821 dst->page_count = page_count;
05394f39 822 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 823
824 return dst;
825
826unwind:
827 while (page--)
828 kfree(dst->pages[page]);
829 kfree(dst);
830 return NULL;
831}
832
833static void
834i915_error_object_free(struct drm_i915_error_object *obj)
835{
836 int page;
837
838 if (obj == NULL)
839 return;
840
841 for (page = 0; page < obj->page_count; page++)
842 kfree(obj->pages[page]);
843
844 kfree(obj);
845}
846
742cbee8
DV		 847void
848i915_error_state_free(struct kref *error_ref)
9df30794 849{
742cbee8
DV		 850 struct drm_i915_error_state *error = container_of(error_ref,
851 typeof(*error), ref);
e2f973d5
CW		 852 int i;
853
52d39a21
CW		 854 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
855 i915_error_object_free(error->ring[i].batchbuffer);
856 i915_error_object_free(error->ring[i].ringbuffer);
857 kfree(error->ring[i].requests);
858 }
e2f973d5 859
9df30794 860 kfree(error->active_bo);
6ef3d427 861 kfree(error->overlay);
9df30794
CW		 862 kfree(error);
863}
1b50247a
CW		 864static void capture_bo(struct drm_i915_error_buffer *err,
865 struct drm_i915_gem_object *obj)
866{
867 err->size = obj->base.size;
868 err->name = obj->base.name;
869 err->seqno = obj->last_rendering_seqno;
870 err->gtt_offset = obj->gtt_offset;
871 err->read_domains = obj->base.read_domains;
872 err->write_domain = obj->base.write_domain;
873 err->fence_reg = obj->fence_reg;
874 err->pinned = 0;
875 if (obj->pin_count > 0)
876 err->pinned = 1;
877 if (obj->user_pin_count > 0)
878 err->pinned = -1;
879 err->tiling = obj->tiling_mode;
880 err->dirty = obj->dirty;
881 err->purgeable = obj->madv != I915_MADV_WILLNEED;
882 err->ring = obj->ring ? obj->ring->id : -1;
883 err->cache_level = obj->cache_level;
884}
9df30794 885
1b50247a
CW		 886static u32 capture_active_bo(struct drm_i915_error_buffer *err,
887 int count, struct list_head *head)
c724e8a9
CW		 888{
889 struct drm_i915_gem_object *obj;
890 int i = 0;
891
892 list_for_each_entry(obj, head, mm_list) {
1b50247a 893 capture_bo(err++, obj);
c724e8a9
CW		 894 if (++i == count)
895 break;
1b50247a
CW		 896 }
897
898 return i;
899}
900
901static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
902 int count, struct list_head *head)
903{
904 struct drm_i915_gem_object *obj;
905 int i = 0;
906
907 list_for_each_entry(obj, head, gtt_list) {
908 if (obj->pin_count == 0)
909 continue;
c724e8a9 910
1b50247a
CW		 911 capture_bo(err++, obj);
912 if (++i == count)
913 break;
c724e8a9
CW		 914 }
915
916 return i;
917}
918
748ebc60
CW		 919static void i915_gem_record_fences(struct drm_device *dev,
920 struct drm_i915_error_state *error)
921{
922 struct drm_i915_private *dev_priv = dev->dev_private;
923 int i;
924
925 /* Fences */
926 switch (INTEL_INFO(dev)->gen) {
775d17b6 927 case 7:
748ebc60
CW		 928 case 6:
929 for (i = 0; i < 16; i++)
930 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
931 break;
932 case 5:
933 case 4:
934 for (i = 0; i < 16; i++)
935 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
936 break;
937 case 3:
938 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
939 for (i = 0; i < 8; i++)
940 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
941 case 2:
942 for (i = 0; i < 8; i++)
943 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
944 break;
945
946 }
947}
948
bcfb2e28
CW		 949static struct drm_i915_error_object *
950i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
951 struct intel_ring_buffer *ring)
952{
953 struct drm_i915_gem_object *obj;
954 u32 seqno;
955
956 if (!ring->get_seqno)
957 return NULL;
958
959 seqno = ring->get_seqno(ring);
960 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
961 if (obj->ring != ring)
962 continue;
963
c37d9a5d 964 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 965 continue;
966
967 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
968 continue;
969
970 /* We need to copy these to an anonymous buffer as the simplest
971 * method to avoid being overwritten by userspace.
972 */
973 return i915_error_object_create(dev_priv, obj);
974 }
975
976 return NULL;
977}
978
d27b1e0e
DV		 979static void i915_record_ring_state(struct drm_device *dev,
980 struct drm_i915_error_state *error,
981 struct intel_ring_buffer *ring)
982{
983 struct drm_i915_private *dev_priv = dev->dev_private;
984
33f3f518 985 if (INTEL_INFO(dev)->gen >= 6) {
33f3f518 986 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 987 error->semaphore_mboxes[ring->id][0]
988 = I915_READ(RING_SYNC_0(ring->mmio_base));
989 error->semaphore_mboxes[ring->id][1]
990 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 991 }
c1cd90ed 992
d27b1e0e 993 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 994 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 995 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
996 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
997 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 998 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 999 if (ring->id == RCS) {
d27b1e0e
DV		 1000 error->instdone1 = I915_READ(INSTDONE1);
1001 error->bbaddr = I915_READ64(BB_ADDR);
1002 }
1003 } else {
9d2f41fa 1004 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1005 error->ipeir[ring->id] = I915_READ(IPEIR);
1006 error->ipehr[ring->id] = I915_READ(IPEHR);
1007 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1008 }
1009
9574b3fe 1010 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1011 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 1012 error->seqno[ring->id] = ring->get_seqno(ring);
1013 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1014 error->head[ring->id] = I915_READ_HEAD(ring);
1015 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1016
1017 error->cpu_ring_head[ring->id] = ring->head;
1018 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1019}
1020
52d39a21
CW		 1021static void i915_gem_record_rings(struct drm_device *dev,
1022 struct drm_i915_error_state *error)
1023{
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 struct drm_i915_gem_request *request;
1026 int i, count;
1027
1028 for (i = 0; i < I915_NUM_RINGS; i++) {
1029 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1030
1031 if (ring->obj == NULL)
1032 continue;
1033
1034 i915_record_ring_state(dev, error, ring);
1035
1036 error->ring[i].batchbuffer =
1037 i915_error_first_batchbuffer(dev_priv, ring);
1038
1039 error->ring[i].ringbuffer =
1040 i915_error_object_create(dev_priv, ring->obj);
1041
1042 count = 0;
1043 list_for_each_entry(request, &ring->request_list, list)
1044 count++;
1045
1046 error->ring[i].num_requests = count;
1047 error->ring[i].requests =
1048 kmalloc(count*sizeof(struct drm_i915_error_request),
1049 GFP_ATOMIC);
1050 if (error->ring[i].requests == NULL) {
1051 error->ring[i].num_requests = 0;
1052 continue;
1053 }
1054
1055 count = 0;
1056 list_for_each_entry(request, &ring->request_list, list) {
1057 struct drm_i915_error_request *erq;
1058
1059 erq = &error->ring[i].requests[count++];
1060 erq->seqno = request->seqno;
1061 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1062 erq->tail = request->tail;
52d39a21
CW		 1063 }
1064 }
1065}
1066
8a905236
JB		 1067/**
1068 * i915_capture_error_state - capture an error record for later analysis
1069 * @dev: drm device
1070 *
1071 * Should be called when an error is detected (either a hang or an error
1072 * interrupt) to capture error state from the time of the error. Fills
1073 * out a structure which becomes available in debugfs for user level tools
1074 * to pick up.
1075 */
63eeaf38
JB		 1076static void i915_capture_error_state(struct drm_device *dev)
1077{
1078 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1079 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1080 struct drm_i915_error_state *error;
1081 unsigned long flags;
9db4a9c7 1082 int i, pipe;
63eeaf38
JB		 1083
1084 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1085 error = dev_priv->first_error;
1086 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1087 if (error)
1088 return;
63eeaf38 1089
9db4a9c7 1090 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1091 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1092 if (!error) {
9df30794
CW		 1093 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1094 return;
63eeaf38
JB		 1095 }
1096
b6f7833b
CW		 1097 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1098 dev->primary->index);
2fa772f3 1099
742cbee8 1100 kref_init(&error->ref);
63eeaf38
JB		 1101 error->eir = I915_READ(EIR);
1102 error->pgtbl_er = I915_READ(PGTBL_ER);
be998e2e
BW		 1103
1104 if (HAS_PCH_SPLIT(dev))
1105 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1106 else if (IS_VALLEYVIEW(dev))
1107 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1108 else if (IS_GEN2(dev))
1109 error->ier = I915_READ16(IER);
1110 else
1111 error->ier = I915_READ(IER);
1112
9db4a9c7
JB		 1113 for_each_pipe(pipe)
1114 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1115
33f3f518 1116 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1117 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1118 error->done_reg = I915_READ(DONE_REG);
1119 }
d27b1e0e 1120
748ebc60 1121 i915_gem_record_fences(dev, error);
52d39a21 1122 i915_gem_record_rings(dev, error);
9df30794 1123
c724e8a9 1124 /* Record buffers on the active and pinned lists. */
9df30794 1125 error->active_bo = NULL;
c724e8a9 1126 error->pinned_bo = NULL;
9df30794 1127
bcfb2e28
CW		 1128 i = 0;
1129 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1130 i++;
1131 error->active_bo_count = i;
1b50247a
CW		 1132 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1133 if (obj->pin_count)
1134 i++;
bcfb2e28 1135 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1136
8e934dbf
CW		 1137 error->active_bo = NULL;
1138 error->pinned_bo = NULL;
bcfb2e28
CW		 1139 if (i) {
1140 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1141 GFP_ATOMIC);
c724e8a9
CW		 1142 if (error->active_bo)
1143 error->pinned_bo =
1144 error->active_bo + error->active_bo_count;
9df30794
CW		 1145 }
1146
c724e8a9
CW		 1147 if (error->active_bo)
1148 error->active_bo_count =
1b50247a
CW		 1149 capture_active_bo(error->active_bo,
1150 error->active_bo_count,
1151 &dev_priv->mm.active_list);
c724e8a9
CW		 1152
1153 if (error->pinned_bo)
1154 error->pinned_bo_count =
1b50247a
CW		 1155 capture_pinned_bo(error->pinned_bo,
1156 error->pinned_bo_count,
1157 &dev_priv->mm.gtt_list);
c724e8a9 1158
9df30794
CW		 1159 do_gettimeofday(&error->time);
1160
6ef3d427 1161 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1162 error->display = intel_display_capture_error_state(dev);
6ef3d427 1163
9df30794
CW		 1164 spin_lock_irqsave(&dev_priv->error_lock, flags);
1165 if (dev_priv->first_error == NULL) {
1166 dev_priv->first_error = error;
1167 error = NULL;
1168 }
63eeaf38 1169 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1170
1171 if (error)
742cbee8 1172 i915_error_state_free(&error->ref);
9df30794
CW		 1173}
1174
1175void i915_destroy_error_state(struct drm_device *dev)
1176{
1177 struct drm_i915_private *dev_priv = dev->dev_private;
1178 struct drm_i915_error_state *error;
6dc0e816 1179 unsigned long flags;
9df30794 1180
6dc0e816 1181 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1182 error = dev_priv->first_error;
1183 dev_priv->first_error = NULL;
6dc0e816 1184 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1185
1186 if (error)
742cbee8 1187 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1188}
3bd3c932
CW		 1189#else
1190#define i915_capture_error_state(x)
1191#endif
63eeaf38 1192
35aed2e6 1193static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1194{
1195 struct drm_i915_private *dev_priv = dev->dev_private;
1196 u32 eir = I915_READ(EIR);
9db4a9c7 1197 int pipe;
8a905236 1198
35aed2e6
CW		 1199 if (!eir)
1200 return;
8a905236 1201
a70491cc 1202 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1203
1204 if (IS_G4X(dev)) {
1205 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1206 u32 ipeir = I915_READ(IPEIR_I965);
1207
a70491cc
JP		 1208 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1209 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1210 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1211 I915_READ(INSTDONE_I965));
a70491cc
JP		 1212 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1213 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1214 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1215 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1216 POSTING_READ(IPEIR_I965);
8a905236
JB		 1217 }
1218 if (eir & GM45_ERROR_PAGE_TABLE) {
1219 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1220 pr_err("page table error\n");
1221 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1222 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1223 POSTING_READ(PGTBL_ER);
8a905236
JB		 1224 }
1225 }
1226
a6c45cf0 1227 if (!IS_GEN2(dev)) {
8a905236
JB		 1228 if (eir & I915_ERROR_PAGE_TABLE) {
1229 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1230 pr_err("page table error\n");
1231 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1232 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1233 POSTING_READ(PGTBL_ER);
8a905236
JB		 1234 }
1235 }
1236
1237 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1238 pr_err("memory refresh error:\n");
9db4a9c7 1239 for_each_pipe(pipe)
a70491cc 1240 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1241 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1242 /* pipestat has already been acked */
1243 }
1244 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1245 pr_err("instruction error\n");
1246 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1247 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1248 u32 ipeir = I915_READ(IPEIR);
1249
a70491cc
JP		 1250 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1251 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1252 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1253 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1254 I915_WRITE(IPEIR, ipeir);
3143a2bf 1255 POSTING_READ(IPEIR);
8a905236
JB		 1256 } else {
1257 u32 ipeir = I915_READ(IPEIR_I965);
1258
a70491cc
JP		 1259 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1260 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1261 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1262 I915_READ(INSTDONE_I965));
a70491cc
JP		 1263 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1264 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1265 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1266 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1267 POSTING_READ(IPEIR_I965);
8a905236
JB		 1268 }
1269 }
1270
1271 I915_WRITE(EIR, eir);
3143a2bf 1272 POSTING_READ(EIR);
8a905236
JB		 1273 eir = I915_READ(EIR);
1274 if (eir) {
1275 /*
1276 * some errors might have become stuck,
1277 * mask them.
1278 */
1279 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1280 I915_WRITE(EMR, I915_READ(EMR) | eir);
1281 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1282 }
35aed2e6
CW		 1283}
1284
1285/**
1286 * i915_handle_error - handle an error interrupt
1287 * @dev: drm device
1288 *
1289 * Do some basic checking of regsiter state at error interrupt time and
1290 * dump it to the syslog. Also call i915_capture_error_state() to make
1291 * sure we get a record and make it available in debugfs. Fire a uevent
1292 * so userspace knows something bad happened (should trigger collection
1293 * of a ring dump etc.).
1294 */
527f9e90 1295void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1296{
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298
1299 i915_capture_error_state(dev);
1300 i915_report_and_clear_eir(dev);
8a905236 1301
ba1234d1 1302 if (wedged) {
30dbf0c0 1303 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1304 atomic_set(&dev_priv->mm.wedged, 1);
1305
11ed50ec
BG		 1306 /*
1307 * Wakeup waiting processes so they don't hang
1308 */
1ec14ad3 1309 wake_up_all(&dev_priv->ring[RCS].irq_queue);
f787a5f5 1310 if (HAS_BSD(dev))
1ec14ad3 1311 wake_up_all(&dev_priv->ring[VCS].irq_queue);
549f7365 1312 if (HAS_BLT(dev))
1ec14ad3 1313 wake_up_all(&dev_priv->ring[BCS].irq_queue);
11ed50ec
BG		 1314 }
1315
9c9fe1f8 1316 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1317}
1318
4e5359cd
SF		 1319static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1320{
1321 drm_i915_private_t *dev_priv = dev->dev_private;
1322 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1324 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1325 struct intel_unpin_work *work;
1326 unsigned long flags;
1327 bool stall_detected;
1328
1329 /* Ignore early vblank irqs */
1330 if (intel_crtc == NULL)
1331 return;
1332
1333 spin_lock_irqsave(&dev->event_lock, flags);
1334 work = intel_crtc->unpin_work;
1335
1336 if (work == NULL || work->pending || !work->enable_stall_check) {
1337 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1338 spin_unlock_irqrestore(&dev->event_lock, flags);
1339 return;
1340 }
1341
1342 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1343 obj = work->pending_flip_obj;
a6c45cf0 1344 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1345 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1346 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1347 obj->gtt_offset;
4e5359cd 1348 } else {
9db4a9c7 1349 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1350 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1351 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1352 crtc->x * crtc->fb->bits_per_pixel/8);
1353 }
1354
1355 spin_unlock_irqrestore(&dev->event_lock, flags);
1356
1357 if (stall_detected) {
1358 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1359 intel_prepare_page_flip(dev, intel_crtc->plane);
1360 }
1361}
1362
42f52ef8
KP		 1363/* Called from drm generic code, passed 'crtc' which
1364 * we use as a pipe index
1365 */
f71d4af4 1366static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1367{
1368 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1369 unsigned long irqflags;
71e0ffa5 1370
5eddb70b 1371 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1372 return -EINVAL;
0a3e67a4 1373
1ec14ad3 1374 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1375 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1376 i915_enable_pipestat(dev_priv, pipe,
1377 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1378 else
7c463586
KP		 1379 i915_enable_pipestat(dev_priv, pipe,
1380 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1381
1382 /* maintain vblank delivery even in deep C-states */
1383 if (dev_priv->info->gen == 3)
6b26c86d 1384 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1385 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1386
0a3e67a4
JB		 1387 return 0;
1388}
1389
f71d4af4 1390static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1391{
1392 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1393 unsigned long irqflags;
1394
1395 if (!i915_pipe_enabled(dev, pipe))
1396 return -EINVAL;
1397
1398 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1399 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1400 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1401 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1402
1403 return 0;
1404}
1405
f71d4af4 1406static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1407{
1408 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1409 unsigned long irqflags;
1410
1411 if (!i915_pipe_enabled(dev, pipe))
1412 return -EINVAL;
1413
1414 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1415 ironlake_enable_display_irq(dev_priv,
1416 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1417 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1418
1419 return 0;
1420}
1421
7e231dbe
JB		 1422static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1423{
1424 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1425 unsigned long irqflags;
1426 u32 dpfl, imr;
1427
1428 if (!i915_pipe_enabled(dev, pipe))
1429 return -EINVAL;
1430
1431 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1432 dpfl = I915_READ(VLV_DPFLIPSTAT);
1433 imr = I915_READ(VLV_IMR);
1434 if (pipe == 0) {
1435 dpfl |= PIPEA_VBLANK_INT_EN;
1436 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1437 } else {
1438 dpfl |= PIPEA_VBLANK_INT_EN;
1439 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1440 }
1441 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1442 I915_WRITE(VLV_IMR, imr);
1443 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1444
1445 return 0;
1446}
1447
42f52ef8
KP		 1448/* Called from drm generic code, passed 'crtc' which
1449 * we use as a pipe index
1450 */
f71d4af4 1451static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1452{
1453 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1454 unsigned long irqflags;
0a3e67a4 1455
1ec14ad3 1456 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1457 if (dev_priv->info->gen == 3)
6b26c86d 1458 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1459
f796cf8f
JB		 1460 i915_disable_pipestat(dev_priv, pipe,
1461 PIPE_VBLANK_INTERRUPT_ENABLE |
1462 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1463 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1464}
1465
f71d4af4 1466static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1467{
1468 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1469 unsigned long irqflags;
1470
1471 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1472 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1473 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1474 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1475}
1476
f71d4af4 1477static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1478{
1479 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1480 unsigned long irqflags;
1481
1482 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1483 ironlake_disable_display_irq(dev_priv,
1484 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1485 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1486}
1487
7e231dbe
JB		 1488static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1489{
1490 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1491 unsigned long irqflags;
1492 u32 dpfl, imr;
1493
1494 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1495 dpfl = I915_READ(VLV_DPFLIPSTAT);
1496 imr = I915_READ(VLV_IMR);
1497 if (pipe == 0) {
1498 dpfl &= ~PIPEA_VBLANK_INT_EN;
1499 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1500 } else {
1501 dpfl &= ~PIPEB_VBLANK_INT_EN;
1502 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1503 }
1504 I915_WRITE(VLV_IMR, imr);
1505 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1506 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1507}
1508
893eead0
CW		 1509static u32
1510ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1511{
893eead0
CW		 1512 return list_entry(ring->request_list.prev,
1513 struct drm_i915_gem_request, list)->seqno;
1514}
1515
1516static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1517{
9574b3fe
BW		 1518 /* We don't check whether the ring even exists before calling this
1519 * function. Hence check whether it's initialized. */
1520 if (ring->obj == NULL)
1521 return true;
1522
893eead0
CW		 1523 if (list_empty(&ring->request_list) ||
1524 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1525 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1526 if (waitqueue_active(&ring->irq_queue)) {
1527 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1528 ring->name);
893eead0
CW		 1529 wake_up_all(&ring->irq_queue);
1530 *err = true;
1531 }
1532 return true;
1533 }
1534 return false;
f65d9421
BG		 1535}
1536
1ec14ad3
CW		 1537static bool kick_ring(struct intel_ring_buffer *ring)
1538{
1539 struct drm_device *dev = ring->dev;
1540 struct drm_i915_private *dev_priv = dev->dev_private;
1541 u32 tmp = I915_READ_CTL(ring);
1542 if (tmp & RING_WAIT) {
1543 DRM_ERROR("Kicking stuck wait on %s\n",
1544 ring->name);
1545 I915_WRITE_CTL(ring, tmp);
1546 return true;
1547 }
1ec14ad3
CW		 1548 return false;
1549}
1550
d1e61e7f
CW		 1551static bool i915_hangcheck_hung(struct drm_device *dev)
1552{
1553 drm_i915_private_t *dev_priv = dev->dev_private;
1554
1555 if (dev_priv->hangcheck_count++ > 1) {
1556 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1557 i915_handle_error(dev, true);
1558
1559 if (!IS_GEN2(dev)) {
1560 /* Is the chip hanging on a WAIT_FOR_EVENT?
1561 * If so we can simply poke the RB_WAIT bit
1562 * and break the hang. This should work on
1563 * all but the second generation chipsets.
1564 */
1565 if (kick_ring(&dev_priv->ring[RCS]))
1566 return false;
1567
1568 if (HAS_BSD(dev) && kick_ring(&dev_priv->ring[VCS]))
1569 return false;
1570
1571 if (HAS_BLT(dev) && kick_ring(&dev_priv->ring[BCS]))
1572 return false;
1573 }
1574
1575 return true;
1576 }
1577
1578 return false;
1579}
1580
f65d9421
BG		 1581/**
1582 * This is called when the chip hasn't reported back with completed
1583 * batchbuffers in a long time. The first time this is called we simply record
1584 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1585 * again, we assume the chip is wedged and try to fix it.
1586 */
1587void i915_hangcheck_elapsed(unsigned long data)
1588{
1589 struct drm_device *dev = (struct drm_device *)data;
1590 drm_i915_private_t *dev_priv = dev->dev_private;
097354eb 1591 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
893eead0
CW		 1592 bool err = false;
1593
3e0dc6b0
BW		 1594 if (!i915_enable_hangcheck)
1595 return;
1596
893eead0 1597 /* If all work is done then ACTHD clearly hasn't advanced. */
1ec14ad3
CW		 1598 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1599 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1600 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
d1e61e7f
CW		 1601 if (err) {
1602 if (i915_hangcheck_hung(dev))
1603 return;
1604
893eead0 1605 goto repeat;
d1e61e7f
CW		 1606 }
1607
1608 dev_priv->hangcheck_count = 0;
893eead0
CW		 1609 return;
1610 }
b9201c14 1611
a6c45cf0 1612 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1613 instdone = I915_READ(INSTDONE);
1614 instdone1 = 0;
1615 } else {
cbb465e7
CW		 1616 instdone = I915_READ(INSTDONE_I965);
1617 instdone1 = I915_READ(INSTDONE1);
1618 }
097354eb
DV		 1619 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1620 acthd_bsd = HAS_BSD(dev) ?
1621 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1622 acthd_blt = HAS_BLT(dev) ?
1623 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
f65d9421 1624
cbb465e7 1625 if (dev_priv->last_acthd == acthd &&
097354eb
DV		 1626 dev_priv->last_acthd_bsd == acthd_bsd &&
1627 dev_priv->last_acthd_blt == acthd_blt &&
cbb465e7
CW		 1628 dev_priv->last_instdone == instdone &&
1629 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1630 if (i915_hangcheck_hung(dev))
cbb465e7 1631 return;
cbb465e7
CW		 1632 } else {
1633 dev_priv->hangcheck_count = 0;
1634
1635 dev_priv->last_acthd = acthd;
097354eb
DV		 1636 dev_priv->last_acthd_bsd = acthd_bsd;
1637 dev_priv->last_acthd_blt = acthd_blt;
cbb465e7
CW		 1638 dev_priv->last_instdone = instdone;
1639 dev_priv->last_instdone1 = instdone1;
1640 }
f65d9421 1641
893eead0 1642repeat:
f65d9421 1643 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1644 mod_timer(&dev_priv->hangcheck_timer,
1645 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1646}
1647
1da177e4
LT		 1648/* drm_dma.h hooks
1649*/
f71d4af4 1650static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1651{
1652 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1653
4697995b
JB		 1654 atomic_set(&dev_priv->irq_received, 0);
1655
4697995b 1656
036a4a7d 1657 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1658
036a4a7d
ZW		 1659 /* XXX hotplug from PCH */
1660
1661 I915_WRITE(DEIMR, 0xffffffff);
1662 I915_WRITE(DEIER, 0x0);
3143a2bf 1663 POSTING_READ(DEIER);
036a4a7d
ZW		 1664
1665 /* and GT */
1666 I915_WRITE(GTIMR, 0xffffffff);
1667 I915_WRITE(GTIER, 0x0);
3143a2bf 1668 POSTING_READ(GTIER);
c650156a
ZW		 1669
1670 /* south display irq */
1671 I915_WRITE(SDEIMR, 0xffffffff);
1672 I915_WRITE(SDEIER, 0x0);
3143a2bf 1673 POSTING_READ(SDEIER);
036a4a7d
ZW		 1674}
1675
7e231dbe
JB		 1676static void valleyview_irq_preinstall(struct drm_device *dev)
1677{
1678 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1679 int pipe;
1680
1681 atomic_set(&dev_priv->irq_received, 0);
1682
7e231dbe
JB		 1683 /* VLV magic */
1684 I915_WRITE(VLV_IMR, 0);
1685 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1686 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1687 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1688
7e231dbe
JB		 1689 /* and GT */
1690 I915_WRITE(GTIIR, I915_READ(GTIIR));
1691 I915_WRITE(GTIIR, I915_READ(GTIIR));
1692 I915_WRITE(GTIMR, 0xffffffff);
1693 I915_WRITE(GTIER, 0x0);
1694 POSTING_READ(GTIER);
1695
1696 I915_WRITE(DPINVGTT, 0xff);
1697
1698 I915_WRITE(PORT_HOTPLUG_EN, 0);
1699 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1700 for_each_pipe(pipe)
1701 I915_WRITE(PIPESTAT(pipe), 0xffff);
1702 I915_WRITE(VLV_IIR, 0xffffffff);
1703 I915_WRITE(VLV_IMR, 0xffffffff);
1704 I915_WRITE(VLV_IER, 0x0);
1705 POSTING_READ(VLV_IER);
1706}
1707
7fe0b973
KP		 1708/*
1709 * Enable digital hotplug on the PCH, and configure the DP short pulse
1710 * duration to 2ms (which is the minimum in the Display Port spec)
1711 *
1712 * This register is the same on all known PCH chips.
1713 */
1714
1715static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1716{
1717 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1718 u32 hotplug;
1719
1720 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1721 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1722 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1723 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1724 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1725 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1726}
1727
f71d4af4 1728static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1729{
1730 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1731 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1732 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1733 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1734 u32 render_irqs;
2d7b8366 1735 u32 hotplug_mask;
036a4a7d 1736
1ec14ad3 1737 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1738
1739 /* should always can generate irq */
1740 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1741 I915_WRITE(DEIMR, dev_priv->irq_mask);
1742 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1743 POSTING_READ(DEIER);
036a4a7d 1744
1ec14ad3 1745 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1746
1747 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1748 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1749
1ec14ad3
CW		 1750 if (IS_GEN6(dev))
1751 render_irqs =
1752 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1753 GEN6_BSD_USER_INTERRUPT |
1754 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1755 else
1756 render_irqs =
88f23b8f 1757 GT_USER_INTERRUPT |
c6df541c 1758 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1759 GT_BSD_USER_INTERRUPT;
1760 I915_WRITE(GTIER, render_irqs);
3143a2bf 1761 POSTING_READ(GTIER);
036a4a7d 1762
2d7b8366 1763 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1764 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1765 SDE_PORTB_HOTPLUG_CPT |
1766 SDE_PORTC_HOTPLUG_CPT |
1767 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1768 } else {
9035a97a
CW		 1769 hotplug_mask = (SDE_CRT_HOTPLUG |
1770 SDE_PORTB_HOTPLUG |
1771 SDE_PORTC_HOTPLUG |
1772 SDE_PORTD_HOTPLUG |
1773 SDE_AUX_MASK);
2d7b8366
YL		 1774 }
1775
1ec14ad3 1776 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1777
1778 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1779 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1780 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1781 POSTING_READ(SDEIER);
c650156a 1782
7fe0b973
KP		 1783 ironlake_enable_pch_hotplug(dev);
1784
f97108d1
JB		 1785 if (IS_IRONLAKE_M(dev)) {
1786 /* Clear & enable PCU event interrupts */
1787 I915_WRITE(DEIIR, DE_PCU_EVENT);
1788 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1789 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1790 }
1791
036a4a7d
ZW		 1792 return 0;
1793}
1794
f71d4af4 1795static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1796{
1797 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1798 /* enable kind of interrupts always enabled */
b615b57a
CW		 1799 u32 display_mask =
1800 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1801 DE_PLANEC_FLIP_DONE_IVB |
1802 DE_PLANEB_FLIP_DONE_IVB |
1803 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1804 u32 render_irqs;
1805 u32 hotplug_mask;
1806
b1f14ad0
JB		 1807 dev_priv->irq_mask = ~display_mask;
1808
1809 /* should always can generate irq */
1810 I915_WRITE(DEIIR, I915_READ(DEIIR));
1811 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1812 I915_WRITE(DEIER,
1813 display_mask |
1814 DE_PIPEC_VBLANK_IVB |
1815 DE_PIPEB_VBLANK_IVB |
1816 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1817 POSTING_READ(DEIER);
1818
1819 dev_priv->gt_irq_mask = ~0;
1820
1821 I915_WRITE(GTIIR, I915_READ(GTIIR));
1822 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1823
e2a1e2f0
BW		 1824 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1825 GEN6_BLITTER_USER_INTERRUPT;
b1f14ad0
JB		 1826 I915_WRITE(GTIER, render_irqs);
1827 POSTING_READ(GTIER);
1828
1829 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1830 SDE_PORTB_HOTPLUG_CPT |
1831 SDE_PORTC_HOTPLUG_CPT |
1832 SDE_PORTD_HOTPLUG_CPT);
1833 dev_priv->pch_irq_mask = ~hotplug_mask;
1834
1835 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1836 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1837 I915_WRITE(SDEIER, hotplug_mask);
1838 POSTING_READ(SDEIER);
1839
7fe0b973
KP		 1840 ironlake_enable_pch_hotplug(dev);
1841
b1f14ad0
JB		 1842 return 0;
1843}
1844
7e231dbe
JB		 1845static int valleyview_irq_postinstall(struct drm_device *dev)
1846{
1847 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1848 u32 render_irqs;
1849 u32 enable_mask;
1850 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1851 u16 msid;
1852
1853 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1854 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1855 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1856
1857 dev_priv->irq_mask = ~enable_mask;
1858
7e231dbe
JB		 1859 dev_priv->pipestat[0] = 0;
1860 dev_priv->pipestat[1] = 0;
1861
7e231dbe
JB		 1862 /* Hack for broken MSIs on VLV */
1863 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1864 pci_read_config_word(dev->pdev, 0x98, &msid);
1865 msid &= 0xff; /* mask out delivery bits */
1866 msid |= (1<<14);
1867 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1868
1869 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1870 I915_WRITE(VLV_IER, enable_mask);
1871 I915_WRITE(VLV_IIR, 0xffffffff);
1872 I915_WRITE(PIPESTAT(0), 0xffff);
1873 I915_WRITE(PIPESTAT(1), 0xffff);
1874 POSTING_READ(VLV_IER);
1875
1876 I915_WRITE(VLV_IIR, 0xffffffff);
1877 I915_WRITE(VLV_IIR, 0xffffffff);
1878
1879 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1880 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
e2a1e2f0 1881 GT_GEN6_BLT_USER_INTERRUPT |
7e231dbe
JB		 1882 GT_GEN6_BSD_USER_INTERRUPT |
1883 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1884 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1885 GT_PIPE_NOTIFY |
1886 GT_RENDER_CS_ERROR_INTERRUPT |
1887 GT_SYNC_STATUS |
1888 GT_USER_INTERRUPT;
1889
1890 dev_priv->gt_irq_mask = ~render_irqs;
1891
1892 I915_WRITE(GTIIR, I915_READ(GTIIR));
1893 I915_WRITE(GTIIR, I915_READ(GTIIR));
1894 I915_WRITE(GTIMR, 0);
1895 I915_WRITE(GTIER, render_irqs);
1896 POSTING_READ(GTIER);
1897
1898 /* ack & enable invalid PTE error interrupts */
1899#if 0 /* FIXME: add support to irq handler for checking these bits */
1900 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1901 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1902#endif
1903
1904 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1905#if 0 /* FIXME: check register definitions; some have moved */
1906 /* Note HDMI and DP share bits */
1907 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1908 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1909 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1910 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1911 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1912 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1913 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1914 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1915 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1916 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1917 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1918 hotplug_en |= CRT_HOTPLUG_INT_EN;
1919 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1920 }
1921#endif
1922
1923 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1924
1925 return 0;
1926}
1927
7e231dbe
JB		 1928static void valleyview_irq_uninstall(struct drm_device *dev)
1929{
1930 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1931 int pipe;
1932
1933 if (!dev_priv)
1934 return;
1935
7e231dbe
JB		 1936 for_each_pipe(pipe)
1937 I915_WRITE(PIPESTAT(pipe), 0xffff);
1938
1939 I915_WRITE(HWSTAM, 0xffffffff);
1940 I915_WRITE(PORT_HOTPLUG_EN, 0);
1941 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1942 for_each_pipe(pipe)
1943 I915_WRITE(PIPESTAT(pipe), 0xffff);
1944 I915_WRITE(VLV_IIR, 0xffffffff);
1945 I915_WRITE(VLV_IMR, 0xffffffff);
1946 I915_WRITE(VLV_IER, 0x0);
1947 POSTING_READ(VLV_IER);
1948}
1949
f71d4af4 1950static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 1951{
1952 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 1953
1954 if (!dev_priv)
1955 return;
1956
036a4a7d
ZW		 1957 I915_WRITE(HWSTAM, 0xffffffff);
1958
1959 I915_WRITE(DEIMR, 0xffffffff);
1960 I915_WRITE(DEIER, 0x0);
1961 I915_WRITE(DEIIR, I915_READ(DEIIR));
1962
1963 I915_WRITE(GTIMR, 0xffffffff);
1964 I915_WRITE(GTIER, 0x0);
1965 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 1966
1967 I915_WRITE(SDEIMR, 0xffffffff);
1968 I915_WRITE(SDEIER, 0x0);
1969 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 1970}
1971
a266c7d5 1972static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 1973{
1974 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1975 int pipe;
91e3738e 1976
a266c7d5 1977 atomic_set(&dev_priv->irq_received, 0);
5ca58282 1978
9db4a9c7
JB		 1979 for_each_pipe(pipe)
1980 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 1981 I915_WRITE16(IMR, 0xffff);
1982 I915_WRITE16(IER, 0x0);
1983 POSTING_READ16(IER);
c2798b19
CW		 1984}
1985
1986static int i8xx_irq_postinstall(struct drm_device *dev)
1987{
1988 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1989
c2798b19
CW		 1990 dev_priv->pipestat[0] = 0;
1991 dev_priv->pipestat[1] = 0;
1992
1993 I915_WRITE16(EMR,
1994 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
1995
1996 /* Unmask the interrupts that we always want on. */
1997 dev_priv->irq_mask =
1998 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1999 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2000 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2001 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2002 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2003 I915_WRITE16(IMR, dev_priv->irq_mask);
2004
2005 I915_WRITE16(IER,
2006 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2007 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2008 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2009 I915_USER_INTERRUPT);
2010 POSTING_READ16(IER);
2011
2012 return 0;
2013}
2014
2015static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2016{
2017 struct drm_device *dev = (struct drm_device *) arg;
2018 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2019 u16 iir, new_iir;
2020 u32 pipe_stats[2];
2021 unsigned long irqflags;
2022 int irq_received;
2023 int pipe;
2024 u16 flip_mask =
2025 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2026 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2027
2028 atomic_inc(&dev_priv->irq_received);
2029
2030 iir = I915_READ16(IIR);
2031 if (iir == 0)
2032 return IRQ_NONE;
2033
2034 while (iir & ~flip_mask) {
2035 /* Can't rely on pipestat interrupt bit in iir as it might
2036 * have been cleared after the pipestat interrupt was received.
2037 * It doesn't set the bit in iir again, but it still produces
2038 * interrupts (for non-MSI).
2039 */
2040 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2041 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2042 i915_handle_error(dev, false);
2043
2044 for_each_pipe(pipe) {
2045 int reg = PIPESTAT(pipe);
2046 pipe_stats[pipe] = I915_READ(reg);
2047
2048 /*
2049 * Clear the PIPE*STAT regs before the IIR
2050 */
2051 if (pipe_stats[pipe] & 0x8000ffff) {
2052 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2053 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2054 pipe_name(pipe));
2055 I915_WRITE(reg, pipe_stats[pipe]);
2056 irq_received = 1;
2057 }
2058 }
2059 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2060
2061 I915_WRITE16(IIR, iir & ~flip_mask);
2062 new_iir = I915_READ16(IIR); /* Flush posted writes */
2063
d05c617e 2064 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2065
2066 if (iir & I915_USER_INTERRUPT)
2067 notify_ring(dev, &dev_priv->ring[RCS]);
2068
2069 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2070 drm_handle_vblank(dev, 0)) {
2071 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2072 intel_prepare_page_flip(dev, 0);
2073 intel_finish_page_flip(dev, 0);
2074 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2075 }
2076 }
2077
2078 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2079 drm_handle_vblank(dev, 1)) {
2080 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2081 intel_prepare_page_flip(dev, 1);
2082 intel_finish_page_flip(dev, 1);
2083 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2084 }
2085 }
2086
2087 iir = new_iir;
2088 }
2089
2090 return IRQ_HANDLED;
2091}
2092
2093static void i8xx_irq_uninstall(struct drm_device * dev)
2094{
2095 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2096 int pipe;
2097
c2798b19
CW		 2098 for_each_pipe(pipe) {
2099 /* Clear enable bits; then clear status bits */
2100 I915_WRITE(PIPESTAT(pipe), 0);
2101 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2102 }
2103 I915_WRITE16(IMR, 0xffff);
2104 I915_WRITE16(IER, 0x0);
2105 I915_WRITE16(IIR, I915_READ16(IIR));
2106}
2107
a266c7d5
CW		 2108static void i915_irq_preinstall(struct drm_device * dev)
2109{
2110 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2111 int pipe;
2112
2113 atomic_set(&dev_priv->irq_received, 0);
2114
2115 if (I915_HAS_HOTPLUG(dev)) {
2116 I915_WRITE(PORT_HOTPLUG_EN, 0);
2117 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2118 }
2119
00d98ebd 2120 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2121 for_each_pipe(pipe)
2122 I915_WRITE(PIPESTAT(pipe), 0);
2123 I915_WRITE(IMR, 0xffffffff);
2124 I915_WRITE(IER, 0x0);
2125 POSTING_READ(IER);
2126}
2127
2128static int i915_irq_postinstall(struct drm_device *dev)
2129{
2130 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2131 u32 enable_mask;
a266c7d5 2132
a266c7d5
CW		 2133 dev_priv->pipestat[0] = 0;
2134 dev_priv->pipestat[1] = 0;
2135
38bde180
CW		 2136 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2137
2138 /* Unmask the interrupts that we always want on. */
2139 dev_priv->irq_mask =
2140 ~(I915_ASLE_INTERRUPT |
2141 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2142 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2143 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2144 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2145 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2146
2147 enable_mask =
2148 I915_ASLE_INTERRUPT |
2149 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2150 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2151 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2152 I915_USER_INTERRUPT;
2153
a266c7d5
CW		 2154 if (I915_HAS_HOTPLUG(dev)) {
2155 /* Enable in IER... */
2156 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2157 /* and unmask in IMR */
2158 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2159 }
2160
a266c7d5
CW		 2161 I915_WRITE(IMR, dev_priv->irq_mask);
2162 I915_WRITE(IER, enable_mask);
2163 POSTING_READ(IER);
2164
2165 if (I915_HAS_HOTPLUG(dev)) {
2166 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2167
a266c7d5
CW		 2168 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2169 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2170 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2171 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2172 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2173 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2174 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2175 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2176 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2177 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2178 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2179 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2180 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2181 }
2182
2183 /* Ignore TV since it's buggy */
2184
2185 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2186 }
2187
2188 intel_opregion_enable_asle(dev);
2189
2190 return 0;
2191}
2192
2193static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2194{
2195 struct drm_device *dev = (struct drm_device *) arg;
2196 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2197 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2198 unsigned long irqflags;
38bde180
CW		 2199 u32 flip_mask =
2200 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2201 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2202 u32 flip[2] = {
2203 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2204 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2205 };
2206 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2207
2208 atomic_inc(&dev_priv->irq_received);
2209
2210 iir = I915_READ(IIR);
38bde180
CW		 2211 do {
2212 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2213 bool blc_event = false;
a266c7d5
CW		 2214
2215 /* Can't rely on pipestat interrupt bit in iir as it might
2216 * have been cleared after the pipestat interrupt was received.
2217 * It doesn't set the bit in iir again, but it still produces
2218 * interrupts (for non-MSI).
2219 */
2220 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2221 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2222 i915_handle_error(dev, false);
2223
2224 for_each_pipe(pipe) {
2225 int reg = PIPESTAT(pipe);
2226 pipe_stats[pipe] = I915_READ(reg);
2227
38bde180 2228 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2229 if (pipe_stats[pipe] & 0x8000ffff) {
2230 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2231 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2232 pipe_name(pipe));
2233 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2234 irq_received = true;
a266c7d5
CW		 2235 }
2236 }
2237 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2238
2239 if (!irq_received)
2240 break;
2241
a266c7d5
CW		 2242 /* Consume port. Then clear IIR or we'll miss events */
2243 if ((I915_HAS_HOTPLUG(dev)) &&
2244 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2245 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2246
2247 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2248 hotplug_status);
2249 if (hotplug_status & dev_priv->hotplug_supported_mask)
2250 queue_work(dev_priv->wq,
2251 &dev_priv->hotplug_work);
2252
2253 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2254 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2255 }
2256
38bde180 2257 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2258 new_iir = I915_READ(IIR); /* Flush posted writes */
2259
a266c7d5
CW		 2260 if (iir & I915_USER_INTERRUPT)
2261 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2262
a266c7d5 2263 for_each_pipe(pipe) {
38bde180
CW		 2264 int plane = pipe;
2265 if (IS_MOBILE(dev))
2266 plane = !plane;
8291ee90 2267 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2268 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2269 if (iir & flip[plane]) {
2270 intel_prepare_page_flip(dev, plane);
2271 intel_finish_page_flip(dev, pipe);
2272 flip_mask &= ~flip[plane];
2273 }
a266c7d5
CW		 2274 }
2275
2276 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2277 blc_event = true;
2278 }
2279
a266c7d5
CW		 2280 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2281 intel_opregion_asle_intr(dev);
2282
2283 /* With MSI, interrupts are only generated when iir
2284 * transitions from zero to nonzero. If another bit got
2285 * set while we were handling the existing iir bits, then
2286 * we would never get another interrupt.
2287 *
2288 * This is fine on non-MSI as well, as if we hit this path
2289 * we avoid exiting the interrupt handler only to generate
2290 * another one.
2291 *
2292 * Note that for MSI this could cause a stray interrupt report
2293 * if an interrupt landed in the time between writing IIR and
2294 * the posting read. This should be rare enough to never
2295 * trigger the 99% of 100,000 interrupts test for disabling
2296 * stray interrupts.
2297 */
38bde180 2298 ret = IRQ_HANDLED;
a266c7d5 2299 iir = new_iir;
38bde180 2300 } while (iir & ~flip_mask);
a266c7d5 2301
d05c617e 2302 i915_update_dri1_breadcrumb(dev);
8291ee90 2303
a266c7d5
CW		 2304 return ret;
2305}
2306
2307static void i915_irq_uninstall(struct drm_device * dev)
2308{
2309 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2310 int pipe;
2311
a266c7d5
CW		 2312 if (I915_HAS_HOTPLUG(dev)) {
2313 I915_WRITE(PORT_HOTPLUG_EN, 0);
2314 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2315 }
2316
00d98ebd 2317 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2318 for_each_pipe(pipe) {
2319 /* Clear enable bits; then clear status bits */
a266c7d5 2320 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2321 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2322 }
a266c7d5
CW		 2323 I915_WRITE(IMR, 0xffffffff);
2324 I915_WRITE(IER, 0x0);
2325
a266c7d5
CW		 2326 I915_WRITE(IIR, I915_READ(IIR));
2327}
2328
2329static void i965_irq_preinstall(struct drm_device * dev)
2330{
2331 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2332 int pipe;
2333
2334 atomic_set(&dev_priv->irq_received, 0);
2335
2336 if (I915_HAS_HOTPLUG(dev)) {
2337 I915_WRITE(PORT_HOTPLUG_EN, 0);
2338 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2339 }
2340
2341 I915_WRITE(HWSTAM, 0xeffe);
2342 for_each_pipe(pipe)
2343 I915_WRITE(PIPESTAT(pipe), 0);
2344 I915_WRITE(IMR, 0xffffffff);
2345 I915_WRITE(IER, 0x0);
2346 POSTING_READ(IER);
2347}
2348
2349static int i965_irq_postinstall(struct drm_device *dev)
2350{
2351 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2352 u32 enable_mask;
a266c7d5
CW		 2353 u32 error_mask;
2354
a266c7d5 2355 /* Unmask the interrupts that we always want on. */
bbba0a97
CW		 2356 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2357 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2358 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2359 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2360 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2361 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2362
2363 enable_mask = ~dev_priv->irq_mask;
2364 enable_mask |= I915_USER_INTERRUPT;
2365
2366 if (IS_G4X(dev))
2367 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2368
2369 dev_priv->pipestat[0] = 0;
2370 dev_priv->pipestat[1] = 0;
2371
2372 if (I915_HAS_HOTPLUG(dev)) {
2373 /* Enable in IER... */
2374 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2375 /* and unmask in IMR */
2376 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2377 }
2378
2379 /*
2380 * Enable some error detection, note the instruction error mask
2381 * bit is reserved, so we leave it masked.
2382 */
2383 if (IS_G4X(dev)) {
2384 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2385 GM45_ERROR_MEM_PRIV |
2386 GM45_ERROR_CP_PRIV |
2387 I915_ERROR_MEMORY_REFRESH);
2388 } else {
2389 error_mask = ~(I915_ERROR_PAGE_TABLE |
2390 I915_ERROR_MEMORY_REFRESH);
2391 }
2392 I915_WRITE(EMR, error_mask);
2393
2394 I915_WRITE(IMR, dev_priv->irq_mask);
2395 I915_WRITE(IER, enable_mask);
2396 POSTING_READ(IER);
2397
2398 if (I915_HAS_HOTPLUG(dev)) {
2399 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2400
2401 /* Note HDMI and DP share bits */
2402 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2403 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2404 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2405 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2406 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2407 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2408 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2409 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2410 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2411 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2412 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2413 hotplug_en |= CRT_HOTPLUG_INT_EN;
2414
2415 /* Programming the CRT detection parameters tends
2416 to generate a spurious hotplug event about three
2417 seconds later. So just do it once.
2418 */
2419 if (IS_G4X(dev))
2420 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2421 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2422 }
2423
2424 /* Ignore TV since it's buggy */
2425
2426 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2427 }
2428
2429 intel_opregion_enable_asle(dev);
2430
2431 return 0;
2432}
2433
2434static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2435{
2436 struct drm_device *dev = (struct drm_device *) arg;
2437 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2438 u32 iir, new_iir;
2439 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2440 unsigned long irqflags;
2441 int irq_received;
2442 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2443
2444 atomic_inc(&dev_priv->irq_received);
2445
2446 iir = I915_READ(IIR);
2447
a266c7d5 2448 for (;;) {
2c8ba29f
CW		 2449 bool blc_event = false;
2450
a266c7d5
CW		 2451 irq_received = iir != 0;
2452
2453 /* Can't rely on pipestat interrupt bit in iir as it might
2454 * have been cleared after the pipestat interrupt was received.
2455 * It doesn't set the bit in iir again, but it still produces
2456 * interrupts (for non-MSI).
2457 */
2458 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2459 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2460 i915_handle_error(dev, false);
2461
2462 for_each_pipe(pipe) {
2463 int reg = PIPESTAT(pipe);
2464 pipe_stats[pipe] = I915_READ(reg);
2465
2466 /*
2467 * Clear the PIPE*STAT regs before the IIR
2468 */
2469 if (pipe_stats[pipe] & 0x8000ffff) {
2470 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2471 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2472 pipe_name(pipe));
2473 I915_WRITE(reg, pipe_stats[pipe]);
2474 irq_received = 1;
2475 }
2476 }
2477 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2478
2479 if (!irq_received)
2480 break;
2481
2482 ret = IRQ_HANDLED;
2483
2484 /* Consume port. Then clear IIR or we'll miss events */
2485 if ((I915_HAS_HOTPLUG(dev)) &&
2486 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2487 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2488
2489 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2490 hotplug_status);
2491 if (hotplug_status & dev_priv->hotplug_supported_mask)
2492 queue_work(dev_priv->wq,
2493 &dev_priv->hotplug_work);
2494
2495 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2496 I915_READ(PORT_HOTPLUG_STAT);
2497 }
2498
2499 I915_WRITE(IIR, iir);
2500 new_iir = I915_READ(IIR); /* Flush posted writes */
2501
a266c7d5
CW		 2502 if (iir & I915_USER_INTERRUPT)
2503 notify_ring(dev, &dev_priv->ring[RCS]);
2504 if (iir & I915_BSD_USER_INTERRUPT)
2505 notify_ring(dev, &dev_priv->ring[VCS]);
2506
4f7d1e79 2507 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2508 intel_prepare_page_flip(dev, 0);
a266c7d5 2509
4f7d1e79 2510 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2511 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2512
2513 for_each_pipe(pipe) {
2c8ba29f 2514 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2515 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2516 i915_pageflip_stall_check(dev, pipe);
2517 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2518 }
2519
2520 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2521 blc_event = true;
2522 }
2523
2524
2525 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2526 intel_opregion_asle_intr(dev);
2527
2528 /* With MSI, interrupts are only generated when iir
2529 * transitions from zero to nonzero. If another bit got
2530 * set while we were handling the existing iir bits, then
2531 * we would never get another interrupt.
2532 *
2533 * This is fine on non-MSI as well, as if we hit this path
2534 * we avoid exiting the interrupt handler only to generate
2535 * another one.
2536 *
2537 * Note that for MSI this could cause a stray interrupt report
2538 * if an interrupt landed in the time between writing IIR and
2539 * the posting read. This should be rare enough to never
2540 * trigger the 99% of 100,000 interrupts test for disabling
2541 * stray interrupts.
2542 */
2543 iir = new_iir;
2544 }
2545
d05c617e 2546 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2547
a266c7d5
CW		 2548 return ret;
2549}
2550
2551static void i965_irq_uninstall(struct drm_device * dev)
2552{
2553 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2554 int pipe;
2555
2556 if (!dev_priv)
2557 return;
2558
a266c7d5
CW		 2559 if (I915_HAS_HOTPLUG(dev)) {
2560 I915_WRITE(PORT_HOTPLUG_EN, 0);
2561 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2562 }
2563
2564 I915_WRITE(HWSTAM, 0xffffffff);
2565 for_each_pipe(pipe)
2566 I915_WRITE(PIPESTAT(pipe), 0);
2567 I915_WRITE(IMR, 0xffffffff);
2568 I915_WRITE(IER, 0x0);
2569
2570 for_each_pipe(pipe)
2571 I915_WRITE(PIPESTAT(pipe),
2572 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2573 I915_WRITE(IIR, I915_READ(IIR));
2574}
2575
f71d4af4
JB		 2576void intel_irq_init(struct drm_device *dev)
2577{
8b2e326d
CW		 2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579
2580 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2581 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2582 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2583
f71d4af4
JB		 2584 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2585 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7e231dbe
JB		 2586 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
2587 IS_VALLEYVIEW(dev)) {
f71d4af4
JB		 2588 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2589 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2590 }
2591
c3613de9
KP		 2592 if (drm_core_check_feature(dev, DRIVER_MODESET))
2593 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2594 else
2595 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2596 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2597
7e231dbe
JB		 2598 if (IS_VALLEYVIEW(dev)) {
2599 dev->driver->irq_handler = valleyview_irq_handler;
2600 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2601 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2602 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2603 dev->driver->enable_vblank = valleyview_enable_vblank;
2604 dev->driver->disable_vblank = valleyview_disable_vblank;
2605 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2606 /* Share pre & uninstall handlers with ILK/SNB */
2607 dev->driver->irq_handler = ivybridge_irq_handler;
2608 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2609 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2610 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2611 dev->driver->enable_vblank = ivybridge_enable_vblank;
2612 dev->driver->disable_vblank = ivybridge_disable_vblank;
2613 } else if (HAS_PCH_SPLIT(dev)) {
2614 dev->driver->irq_handler = ironlake_irq_handler;
2615 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2616 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2617 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2618 dev->driver->enable_vblank = ironlake_enable_vblank;
2619 dev->driver->disable_vblank = ironlake_disable_vblank;
2620 } else {
c2798b19
CW		 2621 if (INTEL_INFO(dev)->gen == 2) {
2622 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2623 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2624 dev->driver->irq_handler = i8xx_irq_handler;
2625 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2626 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2627 /* IIR "flip pending" means done if this bit is set */
2628 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2629
a266c7d5
CW		 2630 dev->driver->irq_preinstall = i915_irq_preinstall;
2631 dev->driver->irq_postinstall = i915_irq_postinstall;
2632 dev->driver->irq_uninstall = i915_irq_uninstall;
2633 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2634 } else {
a266c7d5
CW		 2635 dev->driver->irq_preinstall = i965_irq_preinstall;
2636 dev->driver->irq_postinstall = i965_irq_postinstall;
2637 dev->driver->irq_uninstall = i965_irq_uninstall;
2638 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2639 }
f71d4af4
JB		 2640 dev->driver->enable_vblank = i915_enable_vblank;
2641 dev->driver->disable_vblank = i915_disable_vblank;
2642 }
2643}
Linux kernel - Deliverables
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