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drm/i915: Use symbolic irqreturn for ->hpd_pulse
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
b2c88f5b 33#include <linux/circ_buf.h>
760285e7
DH		 34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
1da177e4 36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
fca52a55
DV		 40/**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
7c7e10db 48static const u32 hpd_ibx[HPD_NUM_PINS] = {
e5868a31
EE		 49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54};
55
7c7e10db 56static const u32 hpd_cpt[HPD_NUM_PINS] = {
e5868a31 57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 58 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 59 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62};
63
7c7e10db 64static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
e5868a31
EE		 65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71};
72
7c7e10db 73static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
e5868a31
EE		 74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
7c7e10db 82static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are the same */
e5868a31
EE		 83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89};
90
5c502442 91/* IIR can theoretically queue up two events. Be paranoid. */
f86f3fb0 92#define GEN8_IRQ_RESET_NDX(type, which) do { \
5c502442
PZ		 93 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
100} while (0)
101
f86f3fb0 102#define GEN5_IRQ_RESET(type) do { \
a9d356a6 103 I915_WRITE(type##IMR, 0xffffffff); \
5c502442 104 POSTING_READ(type##IMR); \
a9d356a6 105 I915_WRITE(type##IER, 0); \
5c502442
PZ		 106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
a9d356a6
PZ		 110} while (0)
111
337ba017
PZ		 112/*
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
114 */
115#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
117 if (val) { \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
119 (reg), val); \
120 I915_WRITE((reg), 0xffffffff); \
121 POSTING_READ(reg); \
122 I915_WRITE((reg), 0xffffffff); \
123 POSTING_READ(reg); \
124 } \
125} while (0)
126
35079899 127#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
337ba017 128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
35079899 129 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
7d1bd539
VS		 130 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
131 POSTING_READ(GEN8_##type##_IMR(which)); \
35079899
PZ		 132} while (0)
133
134#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
337ba017 135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
35079899 136 I915_WRITE(type##IER, (ier_val)); \
7d1bd539
VS		 137 I915_WRITE(type##IMR, (imr_val)); \
138 POSTING_READ(type##IMR); \
35079899
PZ		 139} while (0)
140
c9a9a268
ID		 141static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
142
036a4a7d 143/* For display hotplug interrupt */
47339cd9 144void
2d1013dd 145ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 146{
4bc9d430
DV		 147 assert_spin_locked(&dev_priv->irq_lock);
148
9df7575f 149 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 150 return;
c67a470b 151
1ec14ad3
CW		 152 if ((dev_priv->irq_mask & mask) != 0) {
153 dev_priv->irq_mask &= ~mask;
154 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 155 POSTING_READ(DEIMR);
036a4a7d
ZW		 156 }
157}
158
47339cd9 159void
2d1013dd 160ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 161{
4bc9d430
DV		 162 assert_spin_locked(&dev_priv->irq_lock);
163
06ffc778 164 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 165 return;
c67a470b 166
1ec14ad3
CW		 167 if ((dev_priv->irq_mask & mask) != mask) {
168 dev_priv->irq_mask |= mask;
169 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 170 POSTING_READ(DEIMR);
036a4a7d
ZW		 171 }
172}
173
43eaea13
PZ		 174/**
175 * ilk_update_gt_irq - update GTIMR
176 * @dev_priv: driver private
177 * @interrupt_mask: mask of interrupt bits to update
178 * @enabled_irq_mask: mask of interrupt bits to enable
179 */
180static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
181 uint32_t interrupt_mask,
182 uint32_t enabled_irq_mask)
183{
184 assert_spin_locked(&dev_priv->irq_lock);
185
15a17aae
DV		 186 WARN_ON(enabled_irq_mask & ~interrupt_mask);
187
9df7575f 188 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 189 return;
c67a470b 190
43eaea13
PZ		 191 dev_priv->gt_irq_mask &= ~interrupt_mask;
192 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
193 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
194 POSTING_READ(GTIMR);
195}
196
480c8033 197void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
43eaea13
PZ		 198{
199 ilk_update_gt_irq(dev_priv, mask, mask);
200}
201
480c8033 202void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
43eaea13
PZ		 203{
204 ilk_update_gt_irq(dev_priv, mask, 0);
205}
206
b900b949
ID		 207static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
208{
209 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
210}
211
a72fbc3a
ID		 212static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
213{
214 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
215}
216
b900b949
ID		 217static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
218{
219 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
220}
221
edbfdb45
PZ		 222/**
223 * snb_update_pm_irq - update GEN6_PMIMR
224 * @dev_priv: driver private
225 * @interrupt_mask: mask of interrupt bits to update
226 * @enabled_irq_mask: mask of interrupt bits to enable
227 */
228static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
229 uint32_t interrupt_mask,
230 uint32_t enabled_irq_mask)
231{
605cd25b 232 uint32_t new_val;
edbfdb45 233
15a17aae
DV		 234 WARN_ON(enabled_irq_mask & ~interrupt_mask);
235
edbfdb45
PZ		 236 assert_spin_locked(&dev_priv->irq_lock);
237
605cd25b 238 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 239 new_val &= ~interrupt_mask;
240 new_val |= (~enabled_irq_mask & interrupt_mask);
241
605cd25b
PZ		 242 if (new_val != dev_priv->pm_irq_mask) {
243 dev_priv->pm_irq_mask = new_val;
a72fbc3a
ID		 244 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
245 POSTING_READ(gen6_pm_imr(dev_priv));
f52ecbcf 246 }
edbfdb45
PZ		 247}
248
480c8033 249void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
edbfdb45 250{
9939fba2
ID		 251 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
252 return;
253
edbfdb45
PZ		 254 snb_update_pm_irq(dev_priv, mask, mask);
255}
256
9939fba2
ID		 257static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
258 uint32_t mask)
edbfdb45
PZ		 259{
260 snb_update_pm_irq(dev_priv, mask, 0);
261}
262
9939fba2
ID		 263void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
264{
265 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
266 return;
267
268 __gen6_disable_pm_irq(dev_priv, mask);
269}
270
3cc134e3
ID		 271void gen6_reset_rps_interrupts(struct drm_device *dev)
272{
273 struct drm_i915_private *dev_priv = dev->dev_private;
274 uint32_t reg = gen6_pm_iir(dev_priv);
275
276 spin_lock_irq(&dev_priv->irq_lock);
277 I915_WRITE(reg, dev_priv->pm_rps_events);
278 I915_WRITE(reg, dev_priv->pm_rps_events);
279 POSTING_READ(reg);
280 spin_unlock_irq(&dev_priv->irq_lock);
281}
282
b900b949
ID		 283void gen6_enable_rps_interrupts(struct drm_device *dev)
284{
285 struct drm_i915_private *dev_priv = dev->dev_private;
286
287 spin_lock_irq(&dev_priv->irq_lock);
78e68d36 288
b900b949 289 WARN_ON(dev_priv->rps.pm_iir);
3cc134e3 290 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
d4d70aa5 291 dev_priv->rps.interrupts_enabled = true;
78e68d36
ID		 292 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
293 dev_priv->pm_rps_events);
b900b949 294 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
78e68d36 295
b900b949
ID		 296 spin_unlock_irq(&dev_priv->irq_lock);
297}
298
59d02a1f
ID		 299u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
300{
301 /*
f24eeb19 302 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
59d02a1f 303 * if GEN6_PM_UP_EI_EXPIRED is masked.
f24eeb19
ID		 304 *
305 * TODO: verify if this can be reproduced on VLV,CHV.
59d02a1f
ID		 306 */
307 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
308 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
309
310 if (INTEL_INFO(dev_priv)->gen >= 8)
311 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
312
313 return mask;
314}
315
b900b949
ID		 316void gen6_disable_rps_interrupts(struct drm_device *dev)
317{
318 struct drm_i915_private *dev_priv = dev->dev_private;
319
d4d70aa5
ID		 320 spin_lock_irq(&dev_priv->irq_lock);
321 dev_priv->rps.interrupts_enabled = false;
322 spin_unlock_irq(&dev_priv->irq_lock);
323
324 cancel_work_sync(&dev_priv->rps.work);
325
9939fba2
ID		 326 spin_lock_irq(&dev_priv->irq_lock);
327
59d02a1f 328 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
9939fba2
ID		 329
330 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
b900b949
ID		 331 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
332 ~dev_priv->pm_rps_events);
9939fba2
ID		 333 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
334 I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
b900b949 335
b900b949 336 dev_priv->rps.pm_iir = 0;
b900b949 337
9939fba2 338 spin_unlock_irq(&dev_priv->irq_lock);
b900b949
ID		 339}
340
fee884ed
DV		 341/**
342 * ibx_display_interrupt_update - update SDEIMR
343 * @dev_priv: driver private
344 * @interrupt_mask: mask of interrupt bits to update
345 * @enabled_irq_mask: mask of interrupt bits to enable
346 */
47339cd9
DV		 347void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
348 uint32_t interrupt_mask,
349 uint32_t enabled_irq_mask)
fee884ed
DV		 350{
351 uint32_t sdeimr = I915_READ(SDEIMR);
352 sdeimr &= ~interrupt_mask;
353 sdeimr |= (~enabled_irq_mask & interrupt_mask);
354
15a17aae
DV		 355 WARN_ON(enabled_irq_mask & ~interrupt_mask);
356
fee884ed
DV		 357 assert_spin_locked(&dev_priv->irq_lock);
358
9df7575f 359 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 360 return;
c67a470b 361
fee884ed
DV		 362 I915_WRITE(SDEIMR, sdeimr);
363 POSTING_READ(SDEIMR);
364}
8664281b 365
b5ea642a 366static void
755e9019
ID		 367__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
368 u32 enable_mask, u32 status_mask)
7c463586 369{
46c06a30 370 u32 reg = PIPESTAT(pipe);
755e9019 371 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 372
b79480ba 373 assert_spin_locked(&dev_priv->irq_lock);
d518ce50 374 WARN_ON(!intel_irqs_enabled(dev_priv));
b79480ba 375
04feced9
VS		 376 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
377 status_mask & ~PIPESTAT_INT_STATUS_MASK,
378 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
379 pipe_name(pipe), enable_mask, status_mask))
755e9019
ID		 380 return;
381
382 if ((pipestat & enable_mask) == enable_mask)
46c06a30
VS		 383 return;
384
91d181dd
ID		 385 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
386
46c06a30 387 /* Enable the interrupt, clear any pending status */
755e9019 388 pipestat |= enable_mask | status_mask;
46c06a30
VS		 389 I915_WRITE(reg, pipestat);
390 POSTING_READ(reg);
7c463586
KP		 391}
392
b5ea642a 393static void
755e9019
ID		 394__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
395 u32 enable_mask, u32 status_mask)
7c463586 396{
46c06a30 397 u32 reg = PIPESTAT(pipe);
755e9019 398 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 399
b79480ba 400 assert_spin_locked(&dev_priv->irq_lock);
d518ce50 401 WARN_ON(!intel_irqs_enabled(dev_priv));
b79480ba 402
04feced9
VS		 403 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
404 status_mask & ~PIPESTAT_INT_STATUS_MASK,
405 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
406 pipe_name(pipe), enable_mask, status_mask))
46c06a30
VS		 407 return;
408
755e9019
ID		 409 if ((pipestat & enable_mask) == 0)
410 return;
411
91d181dd
ID		 412 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
413
755e9019 414 pipestat &= ~enable_mask;
46c06a30
VS		 415 I915_WRITE(reg, pipestat);
416 POSTING_READ(reg);
7c463586
KP		 417}
418
10c59c51
ID		 419static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
420{
421 u32 enable_mask = status_mask << 16;
422
423 /*
724a6905
VS		 424 * On pipe A we don't support the PSR interrupt yet,
425 * on pipe B and C the same bit MBZ.
10c59c51
ID		 426 */
427 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
428 return 0;
724a6905
VS		 429 /*
430 * On pipe B and C we don't support the PSR interrupt yet, on pipe
431 * A the same bit is for perf counters which we don't use either.
432 */
433 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
434 return 0;
10c59c51
ID		 435
436 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
437 SPRITE0_FLIP_DONE_INT_EN_VLV |
438 SPRITE1_FLIP_DONE_INT_EN_VLV);
439 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
440 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
441 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
442 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
443
444 return enable_mask;
445}
446
755e9019
ID		 447void
448i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
449 u32 status_mask)
450{
451 u32 enable_mask;
452
10c59c51
ID		 453 if (IS_VALLEYVIEW(dev_priv->dev))
454 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
455 status_mask);
456 else
457 enable_mask = status_mask << 16;
755e9019
ID		 458 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
459}
460
461void
462i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
463 u32 status_mask)
464{
465 u32 enable_mask;
466
10c59c51
ID		 467 if (IS_VALLEYVIEW(dev_priv->dev))
468 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
469 status_mask);
470 else
471 enable_mask = status_mask << 16;
755e9019
ID		 472 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
473}
474
01c66889 475/**
f49e38dd 476 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 477 */
f49e38dd 478static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 479{
2d1013dd 480 struct drm_i915_private *dev_priv = dev->dev_private;
1ec14ad3 481
f49e38dd
JN		 482 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
483 return;
484
13321786 485 spin_lock_irq(&dev_priv->irq_lock);
01c66889 486
755e9019 487 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
f898780b 488 if (INTEL_INFO(dev)->gen >= 4)
3b6c42e8 489 i915_enable_pipestat(dev_priv, PIPE_A,
755e9019 490 PIPE_LEGACY_BLC_EVENT_STATUS);
1ec14ad3 491
13321786 492 spin_unlock_irq(&dev_priv->irq_lock);
01c66889
ZY		 493}
494
0a3e67a4
JB		 495/**
496 * i915_pipe_enabled - check if a pipe is enabled
497 * @dev: DRM device
498 * @pipe: pipe to check
499 *
500 * Reading certain registers when the pipe is disabled can hang the chip.
501 * Use this routine to make sure the PLL is running and the pipe is active
502 * before reading such registers if unsure.
503 */
504static int
505i915_pipe_enabled(struct drm_device *dev, int pipe)
506{
2d1013dd 507 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56 508
a01025af
DV		 509 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
510 /* Locking is horribly broken here, but whatever. */
511 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 513
a01025af
DV		 514 return intel_crtc->active;
515 } else {
516 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
517 }
0a3e67a4
JB		 518}
519
f75f3746
VS		 520/*
521 * This timing diagram depicts the video signal in and
522 * around the vertical blanking period.
523 *
524 * Assumptions about the fictitious mode used in this example:
525 * vblank_start >= 3
526 * vsync_start = vblank_start + 1
527 * vsync_end = vblank_start + 2
528 * vtotal = vblank_start + 3
529 *
530 * start of vblank:
531 * latch double buffered registers
532 * increment frame counter (ctg+)
533 * generate start of vblank interrupt (gen4+)
534 * |
535 * | frame start:
536 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
537 * | may be shifted forward 1-3 extra lines via PIPECONF
538 * | |
539 * | | start of vsync:
540 * | | generate vsync interrupt
541 * | | |
542 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
543 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
544 * ----va---> <-----------------vb--------------------> <--------va-------------
545 * | | <----vs-----> |
546 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
547 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
548 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
549 * | | |
550 * last visible pixel first visible pixel
551 * | increment frame counter (gen3/4)
552 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
553 *
554 * x = horizontal active
555 * _ = horizontal blanking
556 * hs = horizontal sync
557 * va = vertical active
558 * vb = vertical blanking
559 * vs = vertical sync
560 * vbs = vblank_start (number)
561 *
562 * Summary:
563 * - most events happen at the start of horizontal sync
564 * - frame start happens at the start of horizontal blank, 1-4 lines
565 * (depending on PIPECONF settings) after the start of vblank
566 * - gen3/4 pixel and frame counter are synchronized with the start
567 * of horizontal active on the first line of vertical active
568 */
569
4cdb83ec
VS		 570static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
571{
572 /* Gen2 doesn't have a hardware frame counter */
573 return 0;
574}
575
42f52ef8
KP		 576/* Called from drm generic code, passed a 'crtc', which
577 * we use as a pipe index
578 */
f71d4af4 579static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4 580{
2d1013dd 581 struct drm_i915_private *dev_priv = dev->dev_private;
0a3e67a4
JB		 582 unsigned long high_frame;
583 unsigned long low_frame;
0b2a8e09 584 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
0a3e67a4
JB		 585
586 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 587 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 588 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 589 return 0;
590 }
591
391f75e2
VS		 592 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
593 struct intel_crtc *intel_crtc =
594 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
595 const struct drm_display_mode *mode =
6e3c9717 596 &intel_crtc->config->base.adjusted_mode;
391f75e2 597
0b2a8e09
VS		 598 htotal = mode->crtc_htotal;
599 hsync_start = mode->crtc_hsync_start;
600 vbl_start = mode->crtc_vblank_start;
601 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
602 vbl_start = DIV_ROUND_UP(vbl_start, 2);
391f75e2 603 } else {
a2d213dd 604 enum transcoder cpu_transcoder = (enum transcoder) pipe;
391f75e2
VS		 605
606 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
0b2a8e09 607 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
391f75e2 608 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
0b2a8e09
VS		 609 if ((I915_READ(PIPECONF(cpu_transcoder)) &
610 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
611 vbl_start = DIV_ROUND_UP(vbl_start, 2);
391f75e2
VS		 612 }
613
0b2a8e09
VS		 614 /* Convert to pixel count */
615 vbl_start *= htotal;
616
617 /* Start of vblank event occurs at start of hsync */
618 vbl_start -= htotal - hsync_start;
619
9db4a9c7
JB		 620 high_frame = PIPEFRAME(pipe);
621 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 622
0a3e67a4
JB		 623 /*
624 * High & low register fields aren't synchronized, so make sure
625 * we get a low value that's stable across two reads of the high
626 * register.
627 */
628 do {
5eddb70b 629 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 630 low = I915_READ(low_frame);
5eddb70b 631 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 632 } while (high1 != high2);
633
5eddb70b 634 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 635 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 636 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 637
638 /*
639 * The frame counter increments at beginning of active.
640 * Cook up a vblank counter by also checking the pixel
641 * counter against vblank start.
642 */
edc08d0a 643 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
0a3e67a4
JB		 644}
645
f71d4af4 646static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5 647{
2d1013dd 648 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 649 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 650
651 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 652 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 653 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 654 return 0;
655 }
656
657 return I915_READ(reg);
658}
659
ad3543ed
MK		 660/* raw reads, only for fast reads of display block, no need for forcewake etc. */
661#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
ad3543ed 662
a225f079
VS		 663static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
664{
665 struct drm_device *dev = crtc->base.dev;
666 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 667 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
a225f079 668 enum pipe pipe = crtc->pipe;
80715b2f 669 int position, vtotal;
a225f079 670
80715b2f 671 vtotal = mode->crtc_vtotal;
a225f079
VS		 672 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
673 vtotal /= 2;
674
675 if (IS_GEN2(dev))
676 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
677 else
678 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
679
680 /*
80715b2f
VS		 681 * See update_scanline_offset() for the details on the
682 * scanline_offset adjustment.
a225f079 683 */
80715b2f 684 return (position + crtc->scanline_offset) % vtotal;
a225f079
VS		 685}
686
f71d4af4 687static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
abca9e45
VS		 688 unsigned int flags, int *vpos, int *hpos,
689 ktime_t *stime, ktime_t *etime)
0af7e4df 690{
c2baf4b7
VS		 691 struct drm_i915_private *dev_priv = dev->dev_private;
692 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 694 const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
3aa18df8 695 int position;
78e8fc6b 696 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
0af7e4df
MK		 697 bool in_vbl = true;
698 int ret = 0;
ad3543ed 699 unsigned long irqflags;
0af7e4df 700
c2baf4b7 701 if (!intel_crtc->active) {
0af7e4df 702 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 703 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 704 return 0;
705 }
706
c2baf4b7 707 htotal = mode->crtc_htotal;
78e8fc6b 708 hsync_start = mode->crtc_hsync_start;
c2baf4b7
VS		 709 vtotal = mode->crtc_vtotal;
710 vbl_start = mode->crtc_vblank_start;
711 vbl_end = mode->crtc_vblank_end;
0af7e4df 712
d31faf65
VS		 713 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
714 vbl_start = DIV_ROUND_UP(vbl_start, 2);
715 vbl_end /= 2;
716 vtotal /= 2;
717 }
718
c2baf4b7
VS		 719 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
720
ad3543ed
MK		 721 /*
722 * Lock uncore.lock, as we will do multiple timing critical raw
723 * register reads, potentially with preemption disabled, so the
724 * following code must not block on uncore.lock.
725 */
726 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
78e8fc6b 727
ad3543ed
MK		 728 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
729
730 /* Get optional system timestamp before query. */
731 if (stime)
732 *stime = ktime_get();
733
7c06b08a 734 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 735 /* No obvious pixelcount register. Only query vertical
736 * scanout position from Display scan line register.
737 */
a225f079 738 position = __intel_get_crtc_scanline(intel_crtc);
0af7e4df
MK		 739 } else {
740 /* Have access to pixelcount since start of frame.
741 * We can split this into vertical and horizontal
742 * scanout position.
743 */
ad3543ed 744 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
0af7e4df 745
3aa18df8
VS		 746 /* convert to pixel counts */
747 vbl_start *= htotal;
748 vbl_end *= htotal;
749 vtotal *= htotal;
78e8fc6b 750
7e78f1cb
VS		 751 /*
752 * In interlaced modes, the pixel counter counts all pixels,
753 * so one field will have htotal more pixels. In order to avoid
754 * the reported position from jumping backwards when the pixel
755 * counter is beyond the length of the shorter field, just
756 * clamp the position the length of the shorter field. This
757 * matches how the scanline counter based position works since
758 * the scanline counter doesn't count the two half lines.
759 */
760 if (position >= vtotal)
761 position = vtotal - 1;
762
78e8fc6b
VS		 763 /*
764 * Start of vblank interrupt is triggered at start of hsync,
765 * just prior to the first active line of vblank. However we
766 * consider lines to start at the leading edge of horizontal
767 * active. So, should we get here before we've crossed into
768 * the horizontal active of the first line in vblank, we would
769 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
770 * always add htotal-hsync_start to the current pixel position.
771 */
772 position = (position + htotal - hsync_start) % vtotal;
0af7e4df
MK		 773 }
774
ad3543ed
MK		 775 /* Get optional system timestamp after query. */
776 if (etime)
777 *etime = ktime_get();
778
779 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
780
781 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
782
3aa18df8
VS		 783 in_vbl = position >= vbl_start && position < vbl_end;
784
785 /*
786 * While in vblank, position will be negative
787 * counting up towards 0 at vbl_end. And outside
788 * vblank, position will be positive counting
789 * up since vbl_end.
790 */
791 if (position >= vbl_start)
792 position -= vbl_end;
793 else
794 position += vtotal - vbl_end;
0af7e4df 795
7c06b08a 796 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3aa18df8
VS		 797 *vpos = position;
798 *hpos = 0;
799 } else {
800 *vpos = position / htotal;
801 *hpos = position - (*vpos * htotal);
802 }
0af7e4df 803
0af7e4df
MK		 804 /* In vblank? */
805 if (in_vbl)
3d3cbd84 806 ret |= DRM_SCANOUTPOS_IN_VBLANK;
0af7e4df
MK		 807
808 return ret;
809}
810
a225f079
VS		 811int intel_get_crtc_scanline(struct intel_crtc *crtc)
812{
813 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
814 unsigned long irqflags;
815 int position;
816
817 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
818 position = __intel_get_crtc_scanline(crtc);
819 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
820
821 return position;
822}
823
f71d4af4 824static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 825 int *max_error,
826 struct timeval *vblank_time,
827 unsigned flags)
828{
4041b853 829 struct drm_crtc *crtc;
0af7e4df 830
7eb552ae 831 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 832 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 833 return -EINVAL;
834 }
835
836 /* Get drm_crtc to timestamp: */
4041b853
CW		 837 crtc = intel_get_crtc_for_pipe(dev, pipe);
838 if (crtc == NULL) {
839 DRM_ERROR("Invalid crtc %d\n", pipe);
840 return -EINVAL;
841 }
842
843 if (!crtc->enabled) {
844 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
845 return -EBUSY;
846 }
0af7e4df
MK		 847
848 /* Helper routine in DRM core does all the work: */
4041b853
CW		 849 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
850 vblank_time, flags,
7da903ef 851 crtc,
6e3c9717 852 &to_intel_crtc(crtc)->config->base.adjusted_mode);
0af7e4df
MK		 853}
854
67c347ff
JN		 855static bool intel_hpd_irq_event(struct drm_device *dev,
856 struct drm_connector *connector)
321a1b30
EE		 857{
858 enum drm_connector_status old_status;
859
860 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
861 old_status = connector->status;
862
863 connector->status = connector->funcs->detect(connector, false);
67c347ff
JN		 864 if (old_status == connector->status)
865 return false;
866
867 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
321a1b30 868 connector->base.id,
c23cc417 869 connector->name,
67c347ff
JN		 870 drm_get_connector_status_name(old_status),
871 drm_get_connector_status_name(connector->status));
872
873 return true;
321a1b30
EE		 874}
875
13cf5504
DA		 876static void i915_digport_work_func(struct work_struct *work)
877{
878 struct drm_i915_private *dev_priv =
879 container_of(work, struct drm_i915_private, dig_port_work);
13cf5504
DA		 880 u32 long_port_mask, short_port_mask;
881 struct intel_digital_port *intel_dig_port;
b2c5c181 882 int i;
13cf5504
DA		 883 u32 old_bits = 0;
884
4cb21832 885 spin_lock_irq(&dev_priv->irq_lock);
13cf5504
DA		 886 long_port_mask = dev_priv->long_hpd_port_mask;
887 dev_priv->long_hpd_port_mask = 0;
888 short_port_mask = dev_priv->short_hpd_port_mask;
889 dev_priv->short_hpd_port_mask = 0;
4cb21832 890 spin_unlock_irq(&dev_priv->irq_lock);
13cf5504
DA		 891
892 for (i = 0; i < I915_MAX_PORTS; i++) {
893 bool valid = false;
894 bool long_hpd = false;
895 intel_dig_port = dev_priv->hpd_irq_port[i];
896 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
897 continue;
898
899 if (long_port_mask & (1 << i)) {
900 valid = true;
901 long_hpd = true;
902 } else if (short_port_mask & (1 << i))
903 valid = true;
904
905 if (valid) {
b2c5c181
DV		 906 enum irqreturn ret;
907
13cf5504 908 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
b2c5c181
DV		 909 if (ret == IRQ_NONE) {
910 /* fall back to old school hpd */
13cf5504
DA		 911 old_bits |= (1 << intel_dig_port->base.hpd_pin);
912 }
913 }
914 }
915
916 if (old_bits) {
4cb21832 917 spin_lock_irq(&dev_priv->irq_lock);
13cf5504 918 dev_priv->hpd_event_bits |= old_bits;
4cb21832 919 spin_unlock_irq(&dev_priv->irq_lock);
13cf5504
DA		 920 schedule_work(&dev_priv->hotplug_work);
921 }
922}
923
5ca58282
JB		 924/*
925 * Handle hotplug events outside the interrupt handler proper.
926 */
ac4c16c5
EE		 927#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
928
5ca58282
JB		 929static void i915_hotplug_work_func(struct work_struct *work)
930{
2d1013dd
JN		 931 struct drm_i915_private *dev_priv =
932 container_of(work, struct drm_i915_private, hotplug_work);
5ca58282 933 struct drm_device *dev = dev_priv->dev;
c31c4ba3 934 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 935 struct intel_connector *intel_connector;
936 struct intel_encoder *intel_encoder;
937 struct drm_connector *connector;
cd569aed 938 bool hpd_disabled = false;
321a1b30 939 bool changed = false;
142e2398 940 u32 hpd_event_bits;
4ef69c7a 941
a65e34c7 942 mutex_lock(&mode_config->mutex);
e67189ab
JB		 943 DRM_DEBUG_KMS("running encoder hotplug functions\n");
944
4cb21832 945 spin_lock_irq(&dev_priv->irq_lock);
142e2398
EE		 946
947 hpd_event_bits = dev_priv->hpd_event_bits;
948 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 949 list_for_each_entry(connector, &mode_config->connector_list, head) {
950 intel_connector = to_intel_connector(connector);
36cd7444
DA		 951 if (!intel_connector->encoder)
952 continue;
cd569aed
EE		 953 intel_encoder = intel_connector->encoder;
954 if (intel_encoder->hpd_pin > HPD_NONE &&
955 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
956 connector->polled == DRM_CONNECTOR_POLL_HPD) {
957 DRM_INFO("HPD interrupt storm detected on connector %s: "
958 "switching from hotplug detection to polling\n",
c23cc417 959 connector->name);
cd569aed
EE		 960 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
961 connector->polled = DRM_CONNECTOR_POLL_CONNECT
962 | DRM_CONNECTOR_POLL_DISCONNECT;
963 hpd_disabled = true;
964 }
142e2398
EE		 965 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
966 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
c23cc417 967 connector->name, intel_encoder->hpd_pin);
142e2398 968 }
cd569aed
EE		 969 }
970 /* if there were no outputs to poll, poll was disabled,
971 * therefore make sure it's enabled when disabling HPD on
972 * some connectors */
ac4c16c5 973 if (hpd_disabled) {
cd569aed 974 drm_kms_helper_poll_enable(dev);
6323751d
ID		 975 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
976 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
ac4c16c5 977 }
cd569aed 978
4cb21832 979 spin_unlock_irq(&dev_priv->irq_lock);
cd569aed 980
321a1b30
EE		 981 list_for_each_entry(connector, &mode_config->connector_list, head) {
982 intel_connector = to_intel_connector(connector);
36cd7444
DA		 983 if (!intel_connector->encoder)
984 continue;
321a1b30
EE		 985 intel_encoder = intel_connector->encoder;
986 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
987 if (intel_encoder->hot_plug)
988 intel_encoder->hot_plug(intel_encoder);
989 if (intel_hpd_irq_event(dev, connector))
990 changed = true;
991 }
992 }
40ee3381
KP		 993 mutex_unlock(&mode_config->mutex);
994
321a1b30
EE		 995 if (changed)
996 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 997}
998
d0ecd7e2 999static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1 1000{
2d1013dd 1001 struct drm_i915_private *dev_priv = dev->dev_private;
b5b72e89 1002 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 1003 u8 new_delay;
9270388e 1004
d0ecd7e2 1005 spin_lock(&mchdev_lock);
f97108d1 1006
73edd18f
DV		 1007 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1008
20e4d407 1009 new_delay = dev_priv->ips.cur_delay;
9270388e 1010
7648fa99 1011 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 1012 busy_up = I915_READ(RCPREVBSYTUPAVG);
1013 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 1014 max_avg = I915_READ(RCBMAXAVG);
1015 min_avg = I915_READ(RCBMINAVG);
1016
1017 /* Handle RCS change request from hw */
b5b72e89 1018 if (busy_up > max_avg) {
20e4d407
DV		 1019 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1020 new_delay = dev_priv->ips.cur_delay - 1;
1021 if (new_delay < dev_priv->ips.max_delay)
1022 new_delay = dev_priv->ips.max_delay;
b5b72e89 1023 } else if (busy_down < min_avg) {
20e4d407
DV		 1024 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1025 new_delay = dev_priv->ips.cur_delay + 1;
1026 if (new_delay > dev_priv->ips.min_delay)
1027 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 1028 }
1029
7648fa99 1030 if (ironlake_set_drps(dev, new_delay))
20e4d407 1031 dev_priv->ips.cur_delay = new_delay;
f97108d1 1032
d0ecd7e2 1033 spin_unlock(&mchdev_lock);
9270388e 1034
f97108d1
JB		 1035 return;
1036}
1037
549f7365 1038static void notify_ring(struct drm_device *dev,
a4872ba6 1039 struct intel_engine_cs *ring)
549f7365 1040{
93b0a4e0 1041 if (!intel_ring_initialized(ring))
475553de
CW		 1042 return;
1043
bcfcc8ba 1044 trace_i915_gem_request_notify(ring);
9862e600 1045
549f7365 1046 wake_up_all(&ring->irq_queue);
549f7365
CW		 1047}
1048
31685c25 1049static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
bf225f20 1050 struct intel_rps_ei *rps_ei)
31685c25
D		 1051{
1052 u32 cz_ts, cz_freq_khz;
1053 u32 render_count, media_count;
1054 u32 elapsed_render, elapsed_media, elapsed_time;
1055 u32 residency = 0;
1056
1057 cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1058 cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
1059
1060 render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1061 media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1062
bf225f20
CW		 1063 if (rps_ei->cz_clock == 0) {
1064 rps_ei->cz_clock = cz_ts;
1065 rps_ei->render_c0 = render_count;
1066 rps_ei->media_c0 = media_count;
31685c25
D		 1067
1068 return dev_priv->rps.cur_freq;
1069 }
1070
bf225f20
CW		 1071 elapsed_time = cz_ts - rps_ei->cz_clock;
1072 rps_ei->cz_clock = cz_ts;
31685c25 1073
bf225f20
CW		 1074 elapsed_render = render_count - rps_ei->render_c0;
1075 rps_ei->render_c0 = render_count;
31685c25 1076
bf225f20
CW		 1077 elapsed_media = media_count - rps_ei->media_c0;
1078 rps_ei->media_c0 = media_count;
31685c25
D		 1079
1080 /* Convert all the counters into common unit of milli sec */
1081 elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1082 elapsed_render /= cz_freq_khz;
1083 elapsed_media /= cz_freq_khz;
1084
1085 /*
1086 * Calculate overall C0 residency percentage
1087 * only if elapsed time is non zero
1088 */
1089 if (elapsed_time) {
1090 residency =
1091 ((max(elapsed_render, elapsed_media) * 100)
1092 / elapsed_time);
1093 }
1094
1095 return residency;
1096}
1097
1098/**
1099 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1100 * busy-ness calculated from C0 counters of render & media power wells
1101 * @dev_priv: DRM device private
1102 *
1103 */
4fa79042 1104static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
31685c25
D		 1105{
1106 u32 residency_C0_up = 0, residency_C0_down = 0;
4fa79042 1107 int new_delay, adj;
31685c25
D		 1108
1109 dev_priv->rps.ei_interrupt_count++;
1110
1111 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1112
1113
bf225f20
CW		 1114 if (dev_priv->rps.up_ei.cz_clock == 0) {
1115 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1116 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
31685c25
D		 1117 return dev_priv->rps.cur_freq;
1118 }
1119
1120
1121 /*
1122 * To down throttle, C0 residency should be less than down threshold
1123 * for continous EI intervals. So calculate down EI counters
1124 * once in VLV_INT_COUNT_FOR_DOWN_EI
1125 */
1126 if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1127
1128 dev_priv->rps.ei_interrupt_count = 0;
1129
1130 residency_C0_down = vlv_c0_residency(dev_priv,
bf225f20 1131 &dev_priv->rps.down_ei);
31685c25
D		 1132 } else {
1133 residency_C0_up = vlv_c0_residency(dev_priv,
bf225f20 1134 &dev_priv->rps.up_ei);
31685c25
D		 1135 }
1136
1137 new_delay = dev_priv->rps.cur_freq;
1138
1139 adj = dev_priv->rps.last_adj;
1140 /* C0 residency is greater than UP threshold. Increase Frequency */
1141 if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1142 if (adj > 0)
1143 adj *= 2;
1144 else
1145 adj = 1;
1146
1147 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1148 new_delay = dev_priv->rps.cur_freq + adj;
1149
1150 /*
1151 * For better performance, jump directly
1152 * to RPe if we're below it.
1153 */
1154 if (new_delay < dev_priv->rps.efficient_freq)
1155 new_delay = dev_priv->rps.efficient_freq;
1156
1157 } else if (!dev_priv->rps.ei_interrupt_count &&
1158 (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1159 if (adj < 0)
1160 adj *= 2;
1161 else
1162 adj = -1;
1163 /*
1164 * This means, C0 residency is less than down threshold over
1165 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1166 */
1167 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1168 new_delay = dev_priv->rps.cur_freq + adj;
1169 }
1170
1171 return new_delay;
1172}
1173
4912d041 1174static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 1175{
2d1013dd
JN		 1176 struct drm_i915_private *dev_priv =
1177 container_of(work, struct drm_i915_private, rps.work);
edbfdb45 1178 u32 pm_iir;
dd75fdc8 1179 int new_delay, adj;
4912d041 1180
59cdb63d 1181 spin_lock_irq(&dev_priv->irq_lock);
d4d70aa5
ID		 1182 /* Speed up work cancelation during disabling rps interrupts. */
1183 if (!dev_priv->rps.interrupts_enabled) {
1184 spin_unlock_irq(&dev_priv->irq_lock);
1185 return;
1186 }
c6a828d3
DV		 1187 pm_iir = dev_priv->rps.pm_iir;
1188 dev_priv->rps.pm_iir = 0;
a72fbc3a
ID		 1189 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1190 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
59cdb63d 1191 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 1192
60611c13 1193 /* Make sure we didn't queue anything we're not going to process. */
a6706b45 1194 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
60611c13 1195
a6706b45 1196 if ((pm_iir & dev_priv->pm_rps_events) == 0)
3b8d8d91
JB		 1197 return;
1198
4fc688ce 1199 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 1200
dd75fdc8 1201 adj = dev_priv->rps.last_adj;
7425034a 1202 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 1203 if (adj > 0)
1204 adj *= 2;
13a5660c
D		 1205 else {
1206 /* CHV needs even encode values */
1207 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1208 }
b39fb297 1209 new_delay = dev_priv->rps.cur_freq + adj;
7425034a
VS		 1210
1211 /*
1212 * For better performance, jump directly
1213 * to RPe if we're below it.
1214 */
b39fb297
BW		 1215 if (new_delay < dev_priv->rps.efficient_freq)
1216 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 1217 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
b39fb297
BW		 1218 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1219 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 1220 else
b39fb297 1221 new_delay = dev_priv->rps.min_freq_softlimit;
dd75fdc8 1222 adj = 0;
31685c25
D		 1223 } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1224 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
dd75fdc8
CW		 1225 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1226 if (adj < 0)
1227 adj *= 2;
13a5660c
D		 1228 else {
1229 /* CHV needs even encode values */
1230 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1231 }
b39fb297 1232 new_delay = dev_priv->rps.cur_freq + adj;
dd75fdc8 1233 } else { /* unknown event */
b39fb297 1234 new_delay = dev_priv->rps.cur_freq;
dd75fdc8 1235 }
3b8d8d91 1236
79249636
BW		 1237 /* sysfs frequency interfaces may have snuck in while servicing the
1238 * interrupt
1239 */
1272e7b8 1240 new_delay = clamp_t(int, new_delay,
b39fb297
BW		 1241 dev_priv->rps.min_freq_softlimit,
1242 dev_priv->rps.max_freq_softlimit);
27544369 1243
b39fb297 1244 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
dd75fdc8
CW		 1245
1246 if (IS_VALLEYVIEW(dev_priv->dev))
1247 valleyview_set_rps(dev_priv->dev, new_delay);
1248 else
1249 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 1250
4fc688ce 1251 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 1252}
1253
e3689190
BW		 1254
1255/**
1256 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1257 * occurred.
1258 * @work: workqueue struct
1259 *
1260 * Doesn't actually do anything except notify userspace. As a consequence of
1261 * this event, userspace should try to remap the bad rows since statistically
1262 * it is likely the same row is more likely to go bad again.
1263 */
1264static void ivybridge_parity_work(struct work_struct *work)
1265{
2d1013dd
JN		 1266 struct drm_i915_private *dev_priv =
1267 container_of(work, struct drm_i915_private, l3_parity.error_work);
e3689190 1268 u32 error_status, row, bank, subbank;
35a85ac6 1269 char *parity_event[6];
e3689190 1270 uint32_t misccpctl;
35a85ac6 1271 uint8_t slice = 0;
e3689190
BW		 1272
1273 /* We must turn off DOP level clock gating to access the L3 registers.
1274 * In order to prevent a get/put style interface, acquire struct mutex
1275 * any time we access those registers.
1276 */
1277 mutex_lock(&dev_priv->dev->struct_mutex);
1278
35a85ac6
BW		 1279 /* If we've screwed up tracking, just let the interrupt fire again */
1280 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1281 goto out;
1282
e3689190
BW		 1283 misccpctl = I915_READ(GEN7_MISCCPCTL);
1284 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1285 POSTING_READ(GEN7_MISCCPCTL);
1286
35a85ac6
BW		 1287 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1288 u32 reg;
e3689190 1289
35a85ac6
BW		 1290 slice--;
1291 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1292 break;
e3689190 1293
35a85ac6 1294 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 1295
35a85ac6 1296 reg = GEN7_L3CDERRST1 + (slice * 0x200);
e3689190 1297
35a85ac6
BW		 1298 error_status = I915_READ(reg);
1299 row = GEN7_PARITY_ERROR_ROW(error_status);
1300 bank = GEN7_PARITY_ERROR_BANK(error_status);
1301 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1302
1303 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1304 POSTING_READ(reg);
1305
1306 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1307 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1308 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1309 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1310 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1311 parity_event[5] = NULL;
1312
5bdebb18 1313 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
35a85ac6 1314 KOBJ_CHANGE, parity_event);
e3689190 1315
35a85ac6
BW		 1316 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1317 slice, row, bank, subbank);
e3689190 1318
35a85ac6
BW		 1319 kfree(parity_event[4]);
1320 kfree(parity_event[3]);
1321 kfree(parity_event[2]);
1322 kfree(parity_event[1]);
1323 }
e3689190 1324
35a85ac6 1325 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 1326
35a85ac6
BW		 1327out:
1328 WARN_ON(dev_priv->l3_parity.which_slice);
4cb21832 1329 spin_lock_irq(&dev_priv->irq_lock);
480c8033 1330 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
4cb21832 1331 spin_unlock_irq(&dev_priv->irq_lock);
35a85ac6
BW		 1332
1333 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 1334}
1335
35a85ac6 1336static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190 1337{
2d1013dd 1338 struct drm_i915_private *dev_priv = dev->dev_private;
e3689190 1339
040d2baa 1340 if (!HAS_L3_DPF(dev))
e3689190
BW		 1341 return;
1342
d0ecd7e2 1343 spin_lock(&dev_priv->irq_lock);
480c8033 1344 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 1345 spin_unlock(&dev_priv->irq_lock);
e3689190 1346
35a85ac6
BW		 1347 iir &= GT_PARITY_ERROR(dev);
1348 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1349 dev_priv->l3_parity.which_slice |= 1 << 1;
1350
1351 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1352 dev_priv->l3_parity.which_slice |= 1 << 0;
1353
a4da4fa4 1354 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1355}
1356
f1af8fc1
PZ		 1357static void ilk_gt_irq_handler(struct drm_device *dev,
1358 struct drm_i915_private *dev_priv,
1359 u32 gt_iir)
1360{
1361 if (gt_iir &
1362 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1363 notify_ring(dev, &dev_priv->ring[RCS]);
1364 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1365 notify_ring(dev, &dev_priv->ring[VCS]);
1366}
1367
e7b4c6b1
DV		 1368static void snb_gt_irq_handler(struct drm_device *dev,
1369 struct drm_i915_private *dev_priv,
1370 u32 gt_iir)
1371{
1372
cc609d5d
BW		 1373 if (gt_iir &
1374 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1375 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1376 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 1377 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 1378 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 1379 notify_ring(dev, &dev_priv->ring[BCS]);
1380
cc609d5d
BW		 1381 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1382 GT_BSD_CS_ERROR_INTERRUPT |
aaecdf61
DV		 1383 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1384 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
e3689190 1385
35a85ac6
BW		 1386 if (gt_iir & GT_PARITY_ERROR(dev))
1387 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1388}
1389
abd58f01
BW		 1390static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1391 struct drm_i915_private *dev_priv,
1392 u32 master_ctl)
1393{
e981e7b1 1394 struct intel_engine_cs *ring;
abd58f01
BW		 1395 u32 rcs, bcs, vcs;
1396 uint32_t tmp = 0;
1397 irqreturn_t ret = IRQ_NONE;
1398
1399 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1400 tmp = I915_READ(GEN8_GT_IIR(0));
1401 if (tmp) {
38cc46d7 1402 I915_WRITE(GEN8_GT_IIR(0), tmp);
abd58f01 1403 ret = IRQ_HANDLED;
e981e7b1 1404
abd58f01 1405 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
e981e7b1 1406 ring = &dev_priv->ring[RCS];
abd58f01 1407 if (rcs & GT_RENDER_USER_INTERRUPT)
e981e7b1
TD		 1408 notify_ring(dev, ring);
1409 if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
3f7531c3 1410 intel_lrc_irq_handler(ring);
e981e7b1
TD		 1411
1412 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1413 ring = &dev_priv->ring[BCS];
abd58f01 1414 if (bcs & GT_RENDER_USER_INTERRUPT)
e981e7b1
TD		 1415 notify_ring(dev, ring);
1416 if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
3f7531c3 1417 intel_lrc_irq_handler(ring);
abd58f01
BW		 1418 } else
1419 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1420 }
1421
85f9b5f9 1422 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
abd58f01
BW		 1423 tmp = I915_READ(GEN8_GT_IIR(1));
1424 if (tmp) {
38cc46d7 1425 I915_WRITE(GEN8_GT_IIR(1), tmp);
abd58f01 1426 ret = IRQ_HANDLED;
e981e7b1 1427
abd58f01 1428 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
e981e7b1 1429 ring = &dev_priv->ring[VCS];
abd58f01 1430 if (vcs & GT_RENDER_USER_INTERRUPT)
e981e7b1 1431 notify_ring(dev, ring);
73d477f6 1432 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
3f7531c3 1433 intel_lrc_irq_handler(ring);
e981e7b1 1434
85f9b5f9 1435 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
e981e7b1 1436 ring = &dev_priv->ring[VCS2];
85f9b5f9 1437 if (vcs & GT_RENDER_USER_INTERRUPT)
e981e7b1 1438 notify_ring(dev, ring);
73d477f6 1439 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
3f7531c3 1440 intel_lrc_irq_handler(ring);
abd58f01
BW		 1441 } else
1442 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1443 }
1444
0961021a
BW		 1445 if (master_ctl & GEN8_GT_PM_IRQ) {
1446 tmp = I915_READ(GEN8_GT_IIR(2));
1447 if (tmp & dev_priv->pm_rps_events) {
0961021a
BW		 1448 I915_WRITE(GEN8_GT_IIR(2),
1449 tmp & dev_priv->pm_rps_events);
38cc46d7 1450 ret = IRQ_HANDLED;
c9a9a268 1451 gen6_rps_irq_handler(dev_priv, tmp);
0961021a
BW		 1452 } else
1453 DRM_ERROR("The master control interrupt lied (PM)!\n");
1454 }
1455
abd58f01
BW		 1456 if (master_ctl & GEN8_GT_VECS_IRQ) {
1457 tmp = I915_READ(GEN8_GT_IIR(3));
1458 if (tmp) {
38cc46d7 1459 I915_WRITE(GEN8_GT_IIR(3), tmp);
abd58f01 1460 ret = IRQ_HANDLED;
e981e7b1 1461
abd58f01 1462 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
e981e7b1 1463 ring = &dev_priv->ring[VECS];
abd58f01 1464 if (vcs & GT_RENDER_USER_INTERRUPT)
e981e7b1 1465 notify_ring(dev, ring);
73d477f6 1466 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
3f7531c3 1467 intel_lrc_irq_handler(ring);
abd58f01
BW		 1468 } else
1469 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1470 }
1471
1472 return ret;
1473}
1474
b543fb04
EE		 1475#define HPD_STORM_DETECT_PERIOD 1000
1476#define HPD_STORM_THRESHOLD 5
1477
07c338ce 1478static int pch_port_to_hotplug_shift(enum port port)
13cf5504
DA		 1479{
1480 switch (port) {
1481 case PORT_A:
1482 case PORT_E:
1483 default:
1484 return -1;
1485 case PORT_B:
1486 return 0;
1487 case PORT_C:
1488 return 8;
1489 case PORT_D:
1490 return 16;
1491 }
1492}
1493
07c338ce 1494static int i915_port_to_hotplug_shift(enum port port)
13cf5504
DA		 1495{
1496 switch (port) {
1497 case PORT_A:
1498 case PORT_E:
1499 default:
1500 return -1;
1501 case PORT_B:
1502 return 17;
1503 case PORT_C:
1504 return 19;
1505 case PORT_D:
1506 return 21;
1507 }
1508}
1509
1510static inline enum port get_port_from_pin(enum hpd_pin pin)
1511{
1512 switch (pin) {
1513 case HPD_PORT_B:
1514 return PORT_B;
1515 case HPD_PORT_C:
1516 return PORT_C;
1517 case HPD_PORT_D:
1518 return PORT_D;
1519 default:
1520 return PORT_A; /* no hpd */
1521 }
1522}
1523
10a504de 1524static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba 1525 u32 hotplug_trigger,
13cf5504 1526 u32 dig_hotplug_reg,
7c7e10db 1527 const u32 hpd[HPD_NUM_PINS])
b543fb04 1528{
2d1013dd 1529 struct drm_i915_private *dev_priv = dev->dev_private;
b543fb04 1530 int i;
13cf5504 1531 enum port port;
10a504de 1532 bool storm_detected = false;
13cf5504
DA		 1533 bool queue_dig = false, queue_hp = false;
1534 u32 dig_shift;
1535 u32 dig_port_mask = 0;
b543fb04 1536
91d131d2
DV		 1537 if (!hotplug_trigger)
1538 return;
1539
13cf5504
DA		 1540 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1541 hotplug_trigger, dig_hotplug_reg);
cc9bd499 1542
b5ea2d56 1543 spin_lock(&dev_priv->irq_lock);
b543fb04 1544 for (i = 1; i < HPD_NUM_PINS; i++) {
13cf5504
DA		 1545 if (!(hpd[i] & hotplug_trigger))
1546 continue;
1547
1548 port = get_port_from_pin(i);
1549 if (port && dev_priv->hpd_irq_port[port]) {
1550 bool long_hpd;
1551
07c338ce
JN		 1552 if (HAS_PCH_SPLIT(dev)) {
1553 dig_shift = pch_port_to_hotplug_shift(port);
13cf5504 1554 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
07c338ce
JN		 1555 } else {
1556 dig_shift = i915_port_to_hotplug_shift(port);
1557 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
13cf5504
DA		 1558 }
1559
26fbb774
VS		 1560 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1561 port_name(port),
1562 long_hpd ? "long" : "short");
13cf5504
DA		 1563 /* for long HPD pulses we want to have the digital queue happen,
1564 but we still want HPD storm detection to function. */
1565 if (long_hpd) {
1566 dev_priv->long_hpd_port_mask |= (1 << port);
1567 dig_port_mask |= hpd[i];
1568 } else {
1569 /* for short HPD just trigger the digital queue */
1570 dev_priv->short_hpd_port_mask |= (1 << port);
1571 hotplug_trigger &= ~hpd[i];
1572 }
1573 queue_dig = true;
1574 }
1575 }
821450c6 1576
13cf5504 1577 for (i = 1; i < HPD_NUM_PINS; i++) {
3ff04a16
DV		 1578 if (hpd[i] & hotplug_trigger &&
1579 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1580 /*
1581 * On GMCH platforms the interrupt mask bits only
1582 * prevent irq generation, not the setting of the
1583 * hotplug bits itself. So only WARN about unexpected
1584 * interrupts on saner platforms.
1585 */
1586 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1587 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1588 hotplug_trigger, i, hpd[i]);
1589
1590 continue;
1591 }
b8f102e8 1592
b543fb04
EE		 1593 if (!(hpd[i] & hotplug_trigger) ||
1594 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1595 continue;
1596
13cf5504
DA		 1597 if (!(dig_port_mask & hpd[i])) {
1598 dev_priv->hpd_event_bits |= (1 << i);
1599 queue_hp = true;
1600 }
1601
b543fb04
EE		 1602 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1603 dev_priv->hpd_stats[i].hpd_last_jiffies
1604 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1605 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1606 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1607 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1608 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1609 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1610 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1611 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1612 storm_detected = true;
b543fb04
EE		 1613 } else {
1614 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1615 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1616 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1617 }
1618 }
1619
10a504de
DV		 1620 if (storm_detected)
1621 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1622 spin_unlock(&dev_priv->irq_lock);
5876fa0d 1623
645416f5
DV		 1624 /*
1625 * Our hotplug handler can grab modeset locks (by calling down into the
1626 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1627 * queue for otherwise the flush_work in the pageflip code will
1628 * deadlock.
1629 */
13cf5504 1630 if (queue_dig)
0e32b39c 1631 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
13cf5504
DA		 1632 if (queue_hp)
1633 schedule_work(&dev_priv->hotplug_work);
b543fb04
EE		 1634}
1635
515ac2bb
DV		 1636static void gmbus_irq_handler(struct drm_device *dev)
1637{
2d1013dd 1638 struct drm_i915_private *dev_priv = dev->dev_private;
28c70f16 1639
28c70f16 1640 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1641}
1642
ce99c256
DV		 1643static void dp_aux_irq_handler(struct drm_device *dev)
1644{
2d1013dd 1645 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 1646
9ee32fea 1647 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1648}
1649
8bf1e9f1 1650#if defined(CONFIG_DEBUG_FS)
277de95e
DV		 1651static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1652 uint32_t crc0, uint32_t crc1,
1653 uint32_t crc2, uint32_t crc3,
1654 uint32_t crc4)
8bf1e9f1
SH		 1655{
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1658 struct intel_pipe_crc_entry *entry;
ac2300d4 1659 int head, tail;
b2c88f5b 1660
d538bbdf
DL		 1661 spin_lock(&pipe_crc->lock);
1662
0c912c79 1663 if (!pipe_crc->entries) {
d538bbdf 1664 spin_unlock(&pipe_crc->lock);
34273620 1665 DRM_DEBUG_KMS("spurious interrupt\n");
0c912c79
DL		 1666 return;
1667 }
1668
d538bbdf
DL		 1669 head = pipe_crc->head;
1670 tail = pipe_crc->tail;
b2c88f5b
DL		 1671
1672 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
d538bbdf 1673 spin_unlock(&pipe_crc->lock);
b2c88f5b
DL		 1674 DRM_ERROR("CRC buffer overflowing\n");
1675 return;
1676 }
1677
1678 entry = &pipe_crc->entries[head];
8bf1e9f1 1679
8bc5e955 1680 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
eba94eb9
DV		 1681 entry->crc[0] = crc0;
1682 entry->crc[1] = crc1;
1683 entry->crc[2] = crc2;
1684 entry->crc[3] = crc3;
1685 entry->crc[4] = crc4;
b2c88f5b
DL		 1686
1687 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
d538bbdf
DL		 1688 pipe_crc->head = head;
1689
1690 spin_unlock(&pipe_crc->lock);
07144428
DL		 1691
1692 wake_up_interruptible(&pipe_crc->wq);
8bf1e9f1 1693}
277de95e
DV		 1694#else
1695static inline void
1696display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1697 uint32_t crc0, uint32_t crc1,
1698 uint32_t crc2, uint32_t crc3,
1699 uint32_t crc4) {}
1700#endif
1701
eba94eb9 1702
277de95e 1703static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5a69b89f
DV		 1704{
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706
277de95e
DV		 1707 display_pipe_crc_irq_handler(dev, pipe,
1708 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1709 0, 0, 0, 0);
5a69b89f
DV		 1710}
1711
277de95e 1712static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
eba94eb9
DV		 1713{
1714 struct drm_i915_private *dev_priv = dev->dev_private;
1715
277de95e
DV		 1716 display_pipe_crc_irq_handler(dev, pipe,
1717 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1718 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1719 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1720 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1721 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
eba94eb9 1722}
5b3a856b 1723
277de95e 1724static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5b3a856b
DV		 1725{
1726 struct drm_i915_private *dev_priv = dev->dev_private;
0b5c5ed0
DV		 1727 uint32_t res1, res2;
1728
1729 if (INTEL_INFO(dev)->gen >= 3)
1730 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1731 else
1732 res1 = 0;
1733
1734 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1735 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1736 else
1737 res2 = 0;
5b3a856b 1738
277de95e
DV		 1739 display_pipe_crc_irq_handler(dev, pipe,
1740 I915_READ(PIPE_CRC_RES_RED(pipe)),
1741 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1742 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1743 res1, res2);
5b3a856b 1744}
8bf1e9f1 1745
1403c0d4
PZ		 1746/* The RPS events need forcewake, so we add them to a work queue and mask their
1747 * IMR bits until the work is done. Other interrupts can be processed without
1748 * the work queue. */
1749static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1750{
4a74de82
ID		 1751 /* TODO: RPS on GEN9+ is not supported yet. */
1752 if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
1753 "GEN9+: unexpected RPS IRQ\n"))
132f3f17
ID		 1754 return;
1755
a6706b45 1756 if (pm_iir & dev_priv->pm_rps_events) {
59cdb63d 1757 spin_lock(&dev_priv->irq_lock);
480c8033 1758 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
d4d70aa5
ID		 1759 if (dev_priv->rps.interrupts_enabled) {
1760 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1761 queue_work(dev_priv->wq, &dev_priv->rps.work);
1762 }
59cdb63d 1763 spin_unlock(&dev_priv->irq_lock);
baf02a1f 1764 }
baf02a1f 1765
c9a9a268
ID		 1766 if (INTEL_INFO(dev_priv)->gen >= 8)
1767 return;
1768
1403c0d4
PZ		 1769 if (HAS_VEBOX(dev_priv->dev)) {
1770 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1771 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 1772
aaecdf61
DV		 1773 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1774 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
12638c57 1775 }
baf02a1f
BW		 1776}
1777
8d7849db
VS		 1778static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1779{
8d7849db
VS		 1780 if (!drm_handle_vblank(dev, pipe))
1781 return false;
1782
8d7849db
VS		 1783 return true;
1784}
1785
c1874ed7
ID		 1786static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1787{
1788 struct drm_i915_private *dev_priv = dev->dev_private;
91d181dd 1789 u32 pipe_stats[I915_MAX_PIPES] = { };
c1874ed7
ID		 1790 int pipe;
1791
58ead0d7 1792 spin_lock(&dev_priv->irq_lock);
055e393f 1793 for_each_pipe(dev_priv, pipe) {
91d181dd 1794 int reg;
bbb5eebf 1795 u32 mask, iir_bit = 0;
91d181dd 1796
bbb5eebf
DV		 1797 /*
1798 * PIPESTAT bits get signalled even when the interrupt is
1799 * disabled with the mask bits, and some of the status bits do
1800 * not generate interrupts at all (like the underrun bit). Hence
1801 * we need to be careful that we only handle what we want to
1802 * handle.
1803 */
0f239f4c
DV		 1804
1805 /* fifo underruns are filterered in the underrun handler. */
1806 mask = PIPE_FIFO_UNDERRUN_STATUS;
bbb5eebf
DV		 1807
1808 switch (pipe) {
1809 case PIPE_A:
1810 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1811 break;
1812 case PIPE_B:
1813 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1814 break;
3278f67f
VS		 1815 case PIPE_C:
1816 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1817 break;
bbb5eebf
DV		 1818 }
1819 if (iir & iir_bit)
1820 mask |= dev_priv->pipestat_irq_mask[pipe];
1821
1822 if (!mask)
91d181dd
ID		 1823 continue;
1824
1825 reg = PIPESTAT(pipe);
bbb5eebf
DV		 1826 mask |= PIPESTAT_INT_ENABLE_MASK;
1827 pipe_stats[pipe] = I915_READ(reg) & mask;
c1874ed7
ID		 1828
1829 /*
1830 * Clear the PIPE*STAT regs before the IIR
1831 */
91d181dd
ID		 1832 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1833 PIPESTAT_INT_STATUS_MASK))
c1874ed7
ID		 1834 I915_WRITE(reg, pipe_stats[pipe]);
1835 }
58ead0d7 1836 spin_unlock(&dev_priv->irq_lock);
c1874ed7 1837
055e393f 1838 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 1839 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1840 intel_pipe_handle_vblank(dev, pipe))
1841 intel_check_page_flip(dev, pipe);
c1874ed7 1842
579a9b0e 1843 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
c1874ed7
ID		 1844 intel_prepare_page_flip(dev, pipe);
1845 intel_finish_page_flip(dev, pipe);
1846 }
1847
1848 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1849 i9xx_pipe_crc_irq_handler(dev, pipe);
1850
1f7247c0
DV		 1851 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1852 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
c1874ed7
ID		 1853 }
1854
1855 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1856 gmbus_irq_handler(dev);
1857}
1858
16c6c56b
VS		 1859static void i9xx_hpd_irq_handler(struct drm_device *dev)
1860{
1861 struct drm_i915_private *dev_priv = dev->dev_private;
1862 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1863
3ff60f89
OM		 1864 if (hotplug_status) {
1865 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1866 /*
1867 * Make sure hotplug status is cleared before we clear IIR, or else we
1868 * may miss hotplug events.
1869 */
1870 POSTING_READ(PORT_HOTPLUG_STAT);
16c6c56b 1871
3ff60f89
OM		 1872 if (IS_G4X(dev)) {
1873 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
16c6c56b 1874
13cf5504 1875 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
3ff60f89
OM		 1876 } else {
1877 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
16c6c56b 1878
13cf5504 1879 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
3ff60f89 1880 }
16c6c56b 1881
3ff60f89
OM		 1882 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1883 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1884 dp_aux_irq_handler(dev);
1885 }
16c6c56b
VS		 1886}
1887
ff1f525e 1888static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe 1889{
45a83f84 1890 struct drm_device *dev = arg;
2d1013dd 1891 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 1892 u32 iir, gt_iir, pm_iir;
1893 irqreturn_t ret = IRQ_NONE;
7e231dbe 1894
7e231dbe 1895 while (true) {
3ff60f89
OM		 1896 /* Find, clear, then process each source of interrupt */
1897
7e231dbe 1898 gt_iir = I915_READ(GTIIR);
3ff60f89
OM		 1899 if (gt_iir)
1900 I915_WRITE(GTIIR, gt_iir);
1901
7e231dbe 1902 pm_iir = I915_READ(GEN6_PMIIR);
3ff60f89
OM		 1903 if (pm_iir)
1904 I915_WRITE(GEN6_PMIIR, pm_iir);
1905
1906 iir = I915_READ(VLV_IIR);
1907 if (iir) {
1908 /* Consume port before clearing IIR or we'll miss events */
1909 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1910 i9xx_hpd_irq_handler(dev);
1911 I915_WRITE(VLV_IIR, iir);
1912 }
7e231dbe
JB		 1913
1914 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1915 goto out;
1916
1917 ret = IRQ_HANDLED;
1918
3ff60f89
OM		 1919 if (gt_iir)
1920 snb_gt_irq_handler(dev, dev_priv, gt_iir);
60611c13 1921 if (pm_iir)
d0ecd7e2 1922 gen6_rps_irq_handler(dev_priv, pm_iir);
3ff60f89
OM		 1923 /* Call regardless, as some status bits might not be
1924 * signalled in iir */
1925 valleyview_pipestat_irq_handler(dev, iir);
7e231dbe
JB		 1926 }
1927
1928out:
1929 return ret;
1930}
1931
43f328d7
VS		 1932static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1933{
45a83f84 1934 struct drm_device *dev = arg;
43f328d7
VS		 1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 u32 master_ctl, iir;
1937 irqreturn_t ret = IRQ_NONE;
43f328d7 1938
8e5fd599
VS		 1939 for (;;) {
1940 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1941 iir = I915_READ(VLV_IIR);
43f328d7 1942
8e5fd599
VS		 1943 if (master_ctl == 0 && iir == 0)
1944 break;
43f328d7 1945
27b6c122
OM		 1946 ret = IRQ_HANDLED;
1947
8e5fd599 1948 I915_WRITE(GEN8_MASTER_IRQ, 0);
43f328d7 1949
27b6c122 1950 /* Find, clear, then process each source of interrupt */
43f328d7 1951
27b6c122
OM		 1952 if (iir) {
1953 /* Consume port before clearing IIR or we'll miss events */
1954 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1955 i9xx_hpd_irq_handler(dev);
1956 I915_WRITE(VLV_IIR, iir);
1957 }
43f328d7 1958
27b6c122 1959 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
43f328d7 1960
27b6c122
OM		 1961 /* Call regardless, as some status bits might not be
1962 * signalled in iir */
1963 valleyview_pipestat_irq_handler(dev, iir);
43f328d7 1964
8e5fd599
VS		 1965 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1966 POSTING_READ(GEN8_MASTER_IRQ);
8e5fd599 1967 }
3278f67f 1968
43f328d7
VS		 1969 return ret;
1970}
1971
23e81d69 1972static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806 1973{
2d1013dd 1974 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 1975 int pipe;
b543fb04 1976 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
13cf5504
DA		 1977 u32 dig_hotplug_reg;
1978
1979 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1980 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
776ad806 1981
13cf5504 1982 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
91d131d2 1983
cfc33bf7
VS		 1984 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1985 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1986 SDE_AUDIO_POWER_SHIFT);
776ad806 1987 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1988 port_name(port));
1989 }
776ad806 1990
ce99c256
DV		 1991 if (pch_iir & SDE_AUX_MASK)
1992 dp_aux_irq_handler(dev);
1993
776ad806 1994 if (pch_iir & SDE_GMBUS)
515ac2bb 1995 gmbus_irq_handler(dev);
776ad806
JB		 1996
1997 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1998 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1999
2000 if (pch_iir & SDE_AUDIO_TRANS_MASK)
2001 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2002
2003 if (pch_iir & SDE_POISON)
2004 DRM_ERROR("PCH poison interrupt\n");
2005
9db4a9c7 2006 if (pch_iir & SDE_FDI_MASK)
055e393f 2007 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 2008 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2009 pipe_name(pipe),
2010 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 2011
2012 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2013 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2014
2015 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2016 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2017
776ad806 2018 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1f7247c0 2019 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
8664281b
PZ		 2020
2021 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1f7247c0 2022 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
8664281b
PZ		 2023}
2024
2025static void ivb_err_int_handler(struct drm_device *dev)
2026{
2027 struct drm_i915_private *dev_priv = dev->dev_private;
2028 u32 err_int = I915_READ(GEN7_ERR_INT);
5a69b89f 2029 enum pipe pipe;
8664281b 2030
de032bf4
PZ		 2031 if (err_int & ERR_INT_POISON)
2032 DRM_ERROR("Poison interrupt\n");
2033
055e393f 2034 for_each_pipe(dev_priv, pipe) {
1f7247c0
DV		 2035 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2036 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
8bf1e9f1 2037
5a69b89f
DV		 2038 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2039 if (IS_IVYBRIDGE(dev))
277de95e 2040 ivb_pipe_crc_irq_handler(dev, pipe);
5a69b89f 2041 else
277de95e 2042 hsw_pipe_crc_irq_handler(dev, pipe);
5a69b89f
DV		 2043 }
2044 }
8bf1e9f1 2045
8664281b
PZ		 2046 I915_WRITE(GEN7_ERR_INT, err_int);
2047}
2048
2049static void cpt_serr_int_handler(struct drm_device *dev)
2050{
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 u32 serr_int = I915_READ(SERR_INT);
2053
de032bf4
PZ		 2054 if (serr_int & SERR_INT_POISON)
2055 DRM_ERROR("PCH poison interrupt\n");
2056
8664281b 2057 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1f7247c0 2058 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
8664281b
PZ		 2059
2060 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1f7247c0 2061 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
8664281b
PZ		 2062
2063 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1f7247c0 2064 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
8664281b
PZ		 2065
2066 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 2067}
2068
23e81d69
AJ		 2069static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2070{
2d1013dd 2071 struct drm_i915_private *dev_priv = dev->dev_private;
23e81d69 2072 int pipe;
b543fb04 2073 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
13cf5504
DA		 2074 u32 dig_hotplug_reg;
2075
2076 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2077 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
23e81d69 2078
13cf5504 2079 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
91d131d2 2080
cfc33bf7
VS		 2081 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2082 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2083 SDE_AUDIO_POWER_SHIFT_CPT);
2084 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2085 port_name(port));
2086 }
23e81d69
AJ		 2087
2088 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 2089 dp_aux_irq_handler(dev);
23e81d69
AJ		 2090
2091 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 2092 gmbus_irq_handler(dev);
23e81d69
AJ		 2093
2094 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2095 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2096
2097 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2098 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2099
2100 if (pch_iir & SDE_FDI_MASK_CPT)
055e393f 2101 for_each_pipe(dev_priv, pipe)
23e81d69
AJ		 2102 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2103 pipe_name(pipe),
2104 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 2105
2106 if (pch_iir & SDE_ERROR_CPT)
2107 cpt_serr_int_handler(dev);
23e81d69
AJ		 2108}
2109
c008bc6e
PZ		 2110static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2111{
2112 struct drm_i915_private *dev_priv = dev->dev_private;
40da17c2 2113 enum pipe pipe;
c008bc6e
PZ		 2114
2115 if (de_iir & DE_AUX_CHANNEL_A)
2116 dp_aux_irq_handler(dev);
2117
2118 if (de_iir & DE_GSE)
2119 intel_opregion_asle_intr(dev);
2120
c008bc6e
PZ		 2121 if (de_iir & DE_POISON)
2122 DRM_ERROR("Poison interrupt\n");
2123
055e393f 2124 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 2125 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2126 intel_pipe_handle_vblank(dev, pipe))
2127 intel_check_page_flip(dev, pipe);
5b3a856b 2128
40da17c2 2129 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1f7247c0 2130 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
5b3a856b 2131
40da17c2
DV		 2132 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2133 i9xx_pipe_crc_irq_handler(dev, pipe);
c008bc6e 2134
40da17c2
DV		 2135 /* plane/pipes map 1:1 on ilk+ */
2136 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2137 intel_prepare_page_flip(dev, pipe);
2138 intel_finish_page_flip_plane(dev, pipe);
2139 }
c008bc6e
PZ		 2140 }
2141
2142 /* check event from PCH */
2143 if (de_iir & DE_PCH_EVENT) {
2144 u32 pch_iir = I915_READ(SDEIIR);
2145
2146 if (HAS_PCH_CPT(dev))
2147 cpt_irq_handler(dev, pch_iir);
2148 else
2149 ibx_irq_handler(dev, pch_iir);
2150
2151 /* should clear PCH hotplug event before clear CPU irq */
2152 I915_WRITE(SDEIIR, pch_iir);
2153 }
2154
2155 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2156 ironlake_rps_change_irq_handler(dev);
2157}
2158
9719fb98
PZ		 2159static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2160{
2161 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 2162 enum pipe pipe;
9719fb98
PZ		 2163
2164 if (de_iir & DE_ERR_INT_IVB)
2165 ivb_err_int_handler(dev);
2166
2167 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2168 dp_aux_irq_handler(dev);
2169
2170 if (de_iir & DE_GSE_IVB)
2171 intel_opregion_asle_intr(dev);
2172
055e393f 2173 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 2174 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2175 intel_pipe_handle_vblank(dev, pipe))
2176 intel_check_page_flip(dev, pipe);
40da17c2
DV		 2177
2178 /* plane/pipes map 1:1 on ilk+ */
07d27e20
DL		 2179 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2180 intel_prepare_page_flip(dev, pipe);
2181 intel_finish_page_flip_plane(dev, pipe);
9719fb98
PZ		 2182 }
2183 }
2184
2185 /* check event from PCH */
2186 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2187 u32 pch_iir = I915_READ(SDEIIR);
2188
2189 cpt_irq_handler(dev, pch_iir);
2190
2191 /* clear PCH hotplug event before clear CPU irq */
2192 I915_WRITE(SDEIIR, pch_iir);
2193 }
2194}
2195
72c90f62
OM		 2196/*
2197 * To handle irqs with the minimum potential races with fresh interrupts, we:
2198 * 1 - Disable Master Interrupt Control.
2199 * 2 - Find the source(s) of the interrupt.
2200 * 3 - Clear the Interrupt Identity bits (IIR).
2201 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2202 * 5 - Re-enable Master Interrupt Control.
2203 */
f1af8fc1 2204static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0 2205{
45a83f84 2206 struct drm_device *dev = arg;
2d1013dd 2207 struct drm_i915_private *dev_priv = dev->dev_private;
f1af8fc1 2208 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 2209 irqreturn_t ret = IRQ_NONE;
b1f14ad0 2210
8664281b
PZ		 2211 /* We get interrupts on unclaimed registers, so check for this before we
2212 * do any I915_{READ,WRITE}. */
907b28c5 2213 intel_uncore_check_errors(dev);
8664281b 2214
b1f14ad0
JB		 2215 /* disable master interrupt before clearing iir */
2216 de_ier = I915_READ(DEIER);
2217 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 2218 POSTING_READ(DEIER);
b1f14ad0 2219
44498aea
PZ		 2220 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2221 * interrupts will will be stored on its back queue, and then we'll be
2222 * able to process them after we restore SDEIER (as soon as we restore
2223 * it, we'll get an interrupt if SDEIIR still has something to process
2224 * due to its back queue). */
ab5c608b
BW		 2225 if (!HAS_PCH_NOP(dev)) {
2226 sde_ier = I915_READ(SDEIER);
2227 I915_WRITE(SDEIER, 0);
2228 POSTING_READ(SDEIER);
2229 }
44498aea 2230
72c90f62
OM		 2231 /* Find, clear, then process each source of interrupt */
2232
b1f14ad0 2233 gt_iir = I915_READ(GTIIR);
0e43406b 2234 if (gt_iir) {
72c90f62
OM		 2235 I915_WRITE(GTIIR, gt_iir);
2236 ret = IRQ_HANDLED;
d8fc8a47 2237 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 2238 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 2239 else
2240 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 2241 }
2242
0e43406b
CW		 2243 de_iir = I915_READ(DEIIR);
2244 if (de_iir) {
72c90f62
OM		 2245 I915_WRITE(DEIIR, de_iir);
2246 ret = IRQ_HANDLED;
f1af8fc1
PZ		 2247 if (INTEL_INFO(dev)->gen >= 7)
2248 ivb_display_irq_handler(dev, de_iir);
2249 else
2250 ilk_display_irq_handler(dev, de_iir);
b1f14ad0
JB		 2251 }
2252
f1af8fc1
PZ		 2253 if (INTEL_INFO(dev)->gen >= 6) {
2254 u32 pm_iir = I915_READ(GEN6_PMIIR);
2255 if (pm_iir) {
f1af8fc1
PZ		 2256 I915_WRITE(GEN6_PMIIR, pm_iir);
2257 ret = IRQ_HANDLED;
72c90f62 2258 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1 2259 }
0e43406b 2260 }
b1f14ad0 2261
b1f14ad0
JB		 2262 I915_WRITE(DEIER, de_ier);
2263 POSTING_READ(DEIER);
ab5c608b
BW		 2264 if (!HAS_PCH_NOP(dev)) {
2265 I915_WRITE(SDEIER, sde_ier);
2266 POSTING_READ(SDEIER);
2267 }
b1f14ad0
JB		 2268
2269 return ret;
2270}
2271
abd58f01
BW		 2272static irqreturn_t gen8_irq_handler(int irq, void *arg)
2273{
2274 struct drm_device *dev = arg;
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 u32 master_ctl;
2277 irqreturn_t ret = IRQ_NONE;
2278 uint32_t tmp = 0;
c42664cc 2279 enum pipe pipe;
88e04703
JB		 2280 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2281
2282 if (IS_GEN9(dev))
2283 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2284 GEN9_AUX_CHANNEL_D;
abd58f01 2285
abd58f01
BW		 2286 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2287 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2288 if (!master_ctl)
2289 return IRQ_NONE;
2290
2291 I915_WRITE(GEN8_MASTER_IRQ, 0);
2292 POSTING_READ(GEN8_MASTER_IRQ);
2293
38cc46d7
OM		 2294 /* Find, clear, then process each source of interrupt */
2295
abd58f01
BW		 2296 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2297
2298 if (master_ctl & GEN8_DE_MISC_IRQ) {
2299 tmp = I915_READ(GEN8_DE_MISC_IIR);
abd58f01
BW		 2300 if (tmp) {
2301 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2302 ret = IRQ_HANDLED;
38cc46d7
OM		 2303 if (tmp & GEN8_DE_MISC_GSE)
2304 intel_opregion_asle_intr(dev);
2305 else
2306 DRM_ERROR("Unexpected DE Misc interrupt\n");
abd58f01 2307 }
38cc46d7
OM		 2308 else
2309 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
abd58f01
BW		 2310 }
2311
6d766f02
DV		 2312 if (master_ctl & GEN8_DE_PORT_IRQ) {
2313 tmp = I915_READ(GEN8_DE_PORT_IIR);
6d766f02
DV		 2314 if (tmp) {
2315 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2316 ret = IRQ_HANDLED;
88e04703
JB		 2317
2318 if (tmp & aux_mask)
38cc46d7
OM		 2319 dp_aux_irq_handler(dev);
2320 else
2321 DRM_ERROR("Unexpected DE Port interrupt\n");
6d766f02 2322 }
38cc46d7
OM		 2323 else
2324 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
6d766f02
DV		 2325 }
2326
055e393f 2327 for_each_pipe(dev_priv, pipe) {
770de83d 2328 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
abd58f01 2329
c42664cc
DV		 2330 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2331 continue;
abd58f01 2332
c42664cc 2333 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
c42664cc
DV		 2334 if (pipe_iir) {
2335 ret = IRQ_HANDLED;
2336 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
770de83d 2337
d6bbafa1
CW		 2338 if (pipe_iir & GEN8_PIPE_VBLANK &&
2339 intel_pipe_handle_vblank(dev, pipe))
2340 intel_check_page_flip(dev, pipe);
38cc46d7 2341
770de83d
DL		 2342 if (IS_GEN9(dev))
2343 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2344 else
2345 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2346
2347 if (flip_done) {
38cc46d7
OM		 2348 intel_prepare_page_flip(dev, pipe);
2349 intel_finish_page_flip_plane(dev, pipe);
2350 }
2351
2352 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2353 hsw_pipe_crc_irq_handler(dev, pipe);
2354
1f7247c0
DV		 2355 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2356 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2357 pipe);
38cc46d7 2358
770de83d
DL		 2359
2360 if (IS_GEN9(dev))
2361 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2362 else
2363 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2364
2365 if (fault_errors)
38cc46d7
OM		 2366 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2367 pipe_name(pipe),
2368 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
c42664cc 2369 } else
abd58f01
BW		 2370 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2371 }
2372
92d03a80
DV		 2373 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2374 /*
2375 * FIXME(BDW): Assume for now that the new interrupt handling
2376 * scheme also closed the SDE interrupt handling race we've seen
2377 * on older pch-split platforms. But this needs testing.
2378 */
2379 u32 pch_iir = I915_READ(SDEIIR);
92d03a80
DV		 2380 if (pch_iir) {
2381 I915_WRITE(SDEIIR, pch_iir);
2382 ret = IRQ_HANDLED;
38cc46d7
OM		 2383 cpt_irq_handler(dev, pch_iir);
2384 } else
2385 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2386
92d03a80
DV		 2387 }
2388
abd58f01
BW		 2389 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2390 POSTING_READ(GEN8_MASTER_IRQ);
2391
2392 return ret;
2393}
2394
17e1df07
DV		 2395static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2396 bool reset_completed)
2397{
a4872ba6 2398 struct intel_engine_cs *ring;
17e1df07
DV		 2399 int i;
2400
2401 /*
2402 * Notify all waiters for GPU completion events that reset state has
2403 * been changed, and that they need to restart their wait after
2404 * checking for potential errors (and bail out to drop locks if there is
2405 * a gpu reset pending so that i915_error_work_func can acquire them).
2406 */
2407
2408 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2409 for_each_ring(ring, dev_priv, i)
2410 wake_up_all(&ring->irq_queue);
2411
2412 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2413 wake_up_all(&dev_priv->pending_flip_queue);
2414
2415 /*
2416 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2417 * reset state is cleared.
2418 */
2419 if (reset_completed)
2420 wake_up_all(&dev_priv->gpu_error.reset_queue);
2421}
2422
8a905236
JB		 2423/**
2424 * i915_error_work_func - do process context error handling work
2425 * @work: work struct
2426 *
2427 * Fire an error uevent so userspace can see that a hang or error
2428 * was detected.
2429 */
2430static void i915_error_work_func(struct work_struct *work)
2431{
1f83fee0
DV		 2432 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2433 work);
2d1013dd
JN		 2434 struct drm_i915_private *dev_priv =
2435 container_of(error, struct drm_i915_private, gpu_error);
8a905236 2436 struct drm_device *dev = dev_priv->dev;
cce723ed
BW		 2437 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2438 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2439 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 2440 int ret;
8a905236 2441
5bdebb18 2442 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
f316a42c 2443
7db0ba24
DV		 2444 /*
2445 * Note that there's only one work item which does gpu resets, so we
2446 * need not worry about concurrent gpu resets potentially incrementing
2447 * error->reset_counter twice. We only need to take care of another
2448 * racing irq/hangcheck declaring the gpu dead for a second time. A
2449 * quick check for that is good enough: schedule_work ensures the
2450 * correct ordering between hang detection and this work item, and since
2451 * the reset in-progress bit is only ever set by code outside of this
2452 * work we don't need to worry about any other races.
2453 */
2454 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 2455 DRM_DEBUG_DRIVER("resetting chip\n");
5bdebb18 2456 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
7db0ba24 2457 reset_event);
1f83fee0 2458
f454c694
ID		 2459 /*
2460 * In most cases it's guaranteed that we get here with an RPM
2461 * reference held, for example because there is a pending GPU
2462 * request that won't finish until the reset is done. This
2463 * isn't the case at least when we get here by doing a
2464 * simulated reset via debugs, so get an RPM reference.
2465 */
2466 intel_runtime_pm_get(dev_priv);
7514747d
VS		 2467
2468 intel_prepare_reset(dev);
2469
17e1df07
DV		 2470 /*
2471 * All state reset _must_ be completed before we update the
2472 * reset counter, for otherwise waiters might miss the reset
2473 * pending state and not properly drop locks, resulting in
2474 * deadlocks with the reset work.
2475 */
f69061be
DV		 2476 ret = i915_reset(dev);
2477
7514747d 2478 intel_finish_reset(dev);
17e1df07 2479
f454c694
ID		 2480 intel_runtime_pm_put(dev_priv);
2481
f69061be
DV		 2482 if (ret == 0) {
2483 /*
2484 * After all the gem state is reset, increment the reset
2485 * counter and wake up everyone waiting for the reset to
2486 * complete.
2487 *
2488 * Since unlock operations are a one-sided barrier only,
2489 * we need to insert a barrier here to order any seqno
2490 * updates before
2491 * the counter increment.
2492 */
4e857c58 2493 smp_mb__before_atomic();
f69061be
DV		 2494 atomic_inc(&dev_priv->gpu_error.reset_counter);
2495
5bdebb18 2496 kobject_uevent_env(&dev->primary->kdev->kobj,
f69061be 2497 KOBJ_CHANGE, reset_done_event);
1f83fee0 2498 } else {
2ac0f450 2499 atomic_set_mask(I915_WEDGED, &error->reset_counter);
f316a42c 2500 }
1f83fee0 2501
17e1df07
DV		 2502 /*
2503 * Note: The wake_up also serves as a memory barrier so that
2504 * waiters see the update value of the reset counter atomic_t.
2505 */
2506 i915_error_wake_up(dev_priv, true);
f316a42c 2507 }
8a905236
JB		 2508}
2509
35aed2e6 2510static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2511{
2512 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2513 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2514 u32 eir = I915_READ(EIR);
050ee91f 2515 int pipe, i;
8a905236 2516
35aed2e6
CW		 2517 if (!eir)
2518 return;
8a905236 2519
a70491cc 2520 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2521
bd9854f9
BW		 2522 i915_get_extra_instdone(dev, instdone);
2523
8a905236
JB		 2524 if (IS_G4X(dev)) {
2525 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2526 u32 ipeir = I915_READ(IPEIR_I965);
2527
a70491cc
JP		 2528 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2529 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2530 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2531 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2532 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2533 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2534 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2535 POSTING_READ(IPEIR_I965);
8a905236
JB		 2536 }
2537 if (eir & GM45_ERROR_PAGE_TABLE) {
2538 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2539 pr_err("page table error\n");
2540 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2541 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2542 POSTING_READ(PGTBL_ER);
8a905236
JB		 2543 }
2544 }
2545
a6c45cf0 2546 if (!IS_GEN2(dev)) {
8a905236
JB		 2547 if (eir & I915_ERROR_PAGE_TABLE) {
2548 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2549 pr_err("page table error\n");
2550 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2551 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2552 POSTING_READ(PGTBL_ER);
8a905236
JB		 2553 }
2554 }
2555
2556 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2557 pr_err("memory refresh error:\n");
055e393f 2558 for_each_pipe(dev_priv, pipe)
a70491cc 2559 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2560 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2561 /* pipestat has already been acked */
2562 }
2563 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2564 pr_err("instruction error\n");
2565 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2566 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2567 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2568 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2569 u32 ipeir = I915_READ(IPEIR);
2570
a70491cc
JP		 2571 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2572 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2573 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2574 I915_WRITE(IPEIR, ipeir);
3143a2bf 2575 POSTING_READ(IPEIR);
8a905236
JB		 2576 } else {
2577 u32 ipeir = I915_READ(IPEIR_I965);
2578
a70491cc
JP		 2579 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2580 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2581 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2582 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2583 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2584 POSTING_READ(IPEIR_I965);
8a905236
JB		 2585 }
2586 }
2587
2588 I915_WRITE(EIR, eir);
3143a2bf 2589 POSTING_READ(EIR);
8a905236
JB		 2590 eir = I915_READ(EIR);
2591 if (eir) {
2592 /*
2593 * some errors might have become stuck,
2594 * mask them.
2595 */
2596 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2597 I915_WRITE(EMR, I915_READ(EMR) | eir);
2598 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2599 }
35aed2e6
CW		 2600}
2601
2602/**
2603 * i915_handle_error - handle an error interrupt
2604 * @dev: drm device
2605 *
2606 * Do some basic checking of regsiter state at error interrupt time and
2607 * dump it to the syslog. Also call i915_capture_error_state() to make
2608 * sure we get a record and make it available in debugfs. Fire a uevent
2609 * so userspace knows something bad happened (should trigger collection
2610 * of a ring dump etc.).
2611 */
58174462
MK		 2612void i915_handle_error(struct drm_device *dev, bool wedged,
2613 const char *fmt, ...)
35aed2e6
CW		 2614{
2615 struct drm_i915_private *dev_priv = dev->dev_private;
58174462
MK		 2616 va_list args;
2617 char error_msg[80];
35aed2e6 2618
58174462
MK		 2619 va_start(args, fmt);
2620 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2621 va_end(args);
2622
2623 i915_capture_error_state(dev, wedged, error_msg);
35aed2e6 2624 i915_report_and_clear_eir(dev);
8a905236 2625
ba1234d1 2626 if (wedged) {
f69061be
DV		 2627 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2628 &dev_priv->gpu_error.reset_counter);
ba1234d1 2629
11ed50ec 2630 /*
17e1df07
DV		 2631 * Wakeup waiting processes so that the reset work function
2632 * i915_error_work_func doesn't deadlock trying to grab various
2633 * locks. By bumping the reset counter first, the woken
2634 * processes will see a reset in progress and back off,
2635 * releasing their locks and then wait for the reset completion.
2636 * We must do this for _all_ gpu waiters that might hold locks
2637 * that the reset work needs to acquire.
2638 *
2639 * Note: The wake_up serves as the required memory barrier to
2640 * ensure that the waiters see the updated value of the reset
2641 * counter atomic_t.
11ed50ec 2642 */
17e1df07 2643 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 2644 }
2645
122f46ba
DV		 2646 /*
2647 * Our reset work can grab modeset locks (since it needs to reset the
2648 * state of outstanding pagelips). Hence it must not be run on our own
2649 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2650 * code will deadlock.
2651 */
2652 schedule_work(&dev_priv->gpu_error.work);
8a905236
JB		 2653}
2654
42f52ef8
KP		 2655/* Called from drm generic code, passed 'crtc' which
2656 * we use as a pipe index
2657 */
f71d4af4 2658static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2659{
2d1013dd 2660 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2661 unsigned long irqflags;
71e0ffa5 2662
5eddb70b 2663 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2664 return -EINVAL;
0a3e67a4 2665
1ec14ad3 2666 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2667 if (INTEL_INFO(dev)->gen >= 4)
7c463586 2668 i915_enable_pipestat(dev_priv, pipe,
755e9019 2669 PIPE_START_VBLANK_INTERRUPT_STATUS);
e9d21d7f 2670 else
7c463586 2671 i915_enable_pipestat(dev_priv, pipe,
755e9019 2672 PIPE_VBLANK_INTERRUPT_STATUS);
1ec14ad3 2673 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2674
0a3e67a4
JB		 2675 return 0;
2676}
2677
f71d4af4 2678static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2679{
2d1013dd 2680 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2681 unsigned long irqflags;
b518421f 2682 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2683 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2684
2685 if (!i915_pipe_enabled(dev, pipe))
2686 return -EINVAL;
2687
2688 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2689 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2690 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2691
2692 return 0;
2693}
2694
7e231dbe
JB		 2695static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2696{
2d1013dd 2697 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2698 unsigned long irqflags;
7e231dbe
JB		 2699
2700 if (!i915_pipe_enabled(dev, pipe))
2701 return -EINVAL;
2702
2703 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2704 i915_enable_pipestat(dev_priv, pipe,
755e9019 2705 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2706 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2707
2708 return 0;
2709}
2710
abd58f01
BW		 2711static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2712{
2713 struct drm_i915_private *dev_priv = dev->dev_private;
2714 unsigned long irqflags;
abd58f01
BW		 2715
2716 if (!i915_pipe_enabled(dev, pipe))
2717 return -EINVAL;
2718
2719 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2720 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2721 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2722 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2723 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2724 return 0;
2725}
2726
42f52ef8
KP		 2727/* Called from drm generic code, passed 'crtc' which
2728 * we use as a pipe index
2729 */
f71d4af4 2730static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2731{
2d1013dd 2732 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2733 unsigned long irqflags;
0a3e67a4 2734
1ec14ad3 2735 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2736 i915_disable_pipestat(dev_priv, pipe,
755e9019
ID		 2737 PIPE_VBLANK_INTERRUPT_STATUS |
2738 PIPE_START_VBLANK_INTERRUPT_STATUS);
f796cf8f
JB		 2739 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2740}
2741
f71d4af4 2742static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2743{
2d1013dd 2744 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2745 unsigned long irqflags;
b518421f 2746 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2747 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2748
2749 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2750 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2751 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2752}
2753
7e231dbe
JB		 2754static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2755{
2d1013dd 2756 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2757 unsigned long irqflags;
7e231dbe
JB		 2758
2759 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2760 i915_disable_pipestat(dev_priv, pipe,
755e9019 2761 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2762 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2763}
2764
abd58f01
BW		 2765static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2766{
2767 struct drm_i915_private *dev_priv = dev->dev_private;
2768 unsigned long irqflags;
abd58f01
BW		 2769
2770 if (!i915_pipe_enabled(dev, pipe))
2771 return;
2772
2773 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2774 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2775 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2776 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2777 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2778}
2779
44cdd6d2
JH		 2780static struct drm_i915_gem_request *
2781ring_last_request(struct intel_engine_cs *ring)
852835f3 2782{
893eead0 2783 return list_entry(ring->request_list.prev,
44cdd6d2 2784 struct drm_i915_gem_request, list);
893eead0
CW		 2785}
2786
9107e9d2 2787static bool
44cdd6d2 2788ring_idle(struct intel_engine_cs *ring)
9107e9d2
CW		 2789{
2790 return (list_empty(&ring->request_list) ||
1b5a433a 2791 i915_gem_request_completed(ring_last_request(ring), false));
f65d9421
BG		 2792}
2793
a028c4b0
DV		 2794static bool
2795ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2796{
2797 if (INTEL_INFO(dev)->gen >= 8) {
a6cdb93a 2798 return (ipehr >> 23) == 0x1c;
a028c4b0
DV		 2799 } else {
2800 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2801 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2802 MI_SEMAPHORE_REGISTER);
2803 }
2804}
2805
a4872ba6 2806static struct intel_engine_cs *
a6cdb93a 2807semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
921d42ea
DV		 2808{
2809 struct drm_i915_private *dev_priv = ring->dev->dev_private;
a4872ba6 2810 struct intel_engine_cs *signaller;
921d42ea
DV		 2811 int i;
2812
2813 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
a6cdb93a
RV		 2814 for_each_ring(signaller, dev_priv, i) {
2815 if (ring == signaller)
2816 continue;
2817
2818 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2819 return signaller;
2820 }
921d42ea
DV		 2821 } else {
2822 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2823
2824 for_each_ring(signaller, dev_priv, i) {
2825 if(ring == signaller)
2826 continue;
2827
ebc348b2 2828 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
921d42ea
DV		 2829 return signaller;
2830 }
2831 }
2832
a6cdb93a
RV		 2833 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2834 ring->id, ipehr, offset);
921d42ea
DV		 2835
2836 return NULL;
2837}
2838
a4872ba6
OM		 2839static struct intel_engine_cs *
2840semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
a24a11e6
CW		 2841{
2842 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88fe429d 2843 u32 cmd, ipehr, head;
a6cdb93a
RV		 2844 u64 offset = 0;
2845 int i, backwards;
a24a11e6
CW		 2846
2847 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
a028c4b0 2848 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
6274f212 2849 return NULL;
a24a11e6 2850
88fe429d
DV		 2851 /*
2852 * HEAD is likely pointing to the dword after the actual command,
2853 * so scan backwards until we find the MBOX. But limit it to just 3
a6cdb93a
RV		 2854 * or 4 dwords depending on the semaphore wait command size.
2855 * Note that we don't care about ACTHD here since that might
88fe429d
DV		 2856 * point at at batch, and semaphores are always emitted into the
2857 * ringbuffer itself.
a24a11e6 2858 */
88fe429d 2859 head = I915_READ_HEAD(ring) & HEAD_ADDR;
a6cdb93a 2860 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
88fe429d 2861
a6cdb93a 2862 for (i = backwards; i; --i) {
88fe429d
DV		 2863 /*
2864 * Be paranoid and presume the hw has gone off into the wild -
2865 * our ring is smaller than what the hardware (and hence
2866 * HEAD_ADDR) allows. Also handles wrap-around.
2867 */
ee1b1e5e 2868 head &= ring->buffer->size - 1;
88fe429d
DV		 2869
2870 /* This here seems to blow up */
ee1b1e5e 2871 cmd = ioread32(ring->buffer->virtual_start + head);
a24a11e6
CW		 2872 if (cmd == ipehr)
2873 break;
2874
88fe429d
DV		 2875 head -= 4;
2876 }
a24a11e6 2877
88fe429d
DV		 2878 if (!i)
2879 return NULL;
a24a11e6 2880
ee1b1e5e 2881 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
a6cdb93a
RV		 2882 if (INTEL_INFO(ring->dev)->gen >= 8) {
2883 offset = ioread32(ring->buffer->virtual_start + head + 12);
2884 offset <<= 32;
2885 offset = ioread32(ring->buffer->virtual_start + head + 8);
2886 }
2887 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
a24a11e6
CW		 2888}
2889
a4872ba6 2890static int semaphore_passed(struct intel_engine_cs *ring)
6274f212
CW		 2891{
2892 struct drm_i915_private *dev_priv = ring->dev->dev_private;
a4872ba6 2893 struct intel_engine_cs *signaller;
a0d036b0 2894 u32 seqno;
6274f212 2895
4be17381 2896 ring->hangcheck.deadlock++;
6274f212
CW		 2897
2898 signaller = semaphore_waits_for(ring, &seqno);
4be17381
CW		 2899 if (signaller == NULL)
2900 return -1;
2901
2902 /* Prevent pathological recursion due to driver bugs */
2903 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
6274f212
CW		 2904 return -1;
2905
4be17381
CW		 2906 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2907 return 1;
2908
a0d036b0
CW		 2909 /* cursory check for an unkickable deadlock */
2910 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2911 semaphore_passed(signaller) < 0)
4be17381
CW		 2912 return -1;
2913
2914 return 0;
6274f212
CW		 2915}
2916
2917static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2918{
a4872ba6 2919 struct intel_engine_cs *ring;
6274f212
CW		 2920 int i;
2921
2922 for_each_ring(ring, dev_priv, i)
4be17381 2923 ring->hangcheck.deadlock = 0;
6274f212
CW		 2924}
2925
ad8beaea 2926static enum intel_ring_hangcheck_action
a4872ba6 2927ring_stuck(struct intel_engine_cs *ring, u64 acthd)
1ec14ad3
CW		 2928{
2929 struct drm_device *dev = ring->dev;
2930 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2931 u32 tmp;
2932
f260fe7b
MK		 2933 if (acthd != ring->hangcheck.acthd) {
2934 if (acthd > ring->hangcheck.max_acthd) {
2935 ring->hangcheck.max_acthd = acthd;
2936 return HANGCHECK_ACTIVE;
2937 }
2938
2939 return HANGCHECK_ACTIVE_LOOP;
2940 }
6274f212 2941
9107e9d2 2942 if (IS_GEN2(dev))
f2f4d82f 2943 return HANGCHECK_HUNG;
9107e9d2
CW		 2944
2945 /* Is the chip hanging on a WAIT_FOR_EVENT?
2946 * If so we can simply poke the RB_WAIT bit
2947 * and break the hang. This should work on
2948 * all but the second generation chipsets.
2949 */
2950 tmp = I915_READ_CTL(ring);
1ec14ad3 2951 if (tmp & RING_WAIT) {
58174462
MK		 2952 i915_handle_error(dev, false,
2953 "Kicking stuck wait on %s",
2954 ring->name);
1ec14ad3 2955 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2956 return HANGCHECK_KICK;
6274f212
CW		 2957 }
2958
2959 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2960 switch (semaphore_passed(ring)) {
2961 default:
f2f4d82f 2962 return HANGCHECK_HUNG;
6274f212 2963 case 1:
58174462
MK		 2964 i915_handle_error(dev, false,
2965 "Kicking stuck semaphore on %s",
2966 ring->name);
6274f212 2967 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2968 return HANGCHECK_KICK;
6274f212 2969 case 0:
f2f4d82f 2970 return HANGCHECK_WAIT;
6274f212 2971 }
9107e9d2 2972 }
ed5cbb03 2973
f2f4d82f 2974 return HANGCHECK_HUNG;
ed5cbb03
MK		 2975}
2976
f65d9421
BG		 2977/**
2978 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2979 * batchbuffers in a long time. We keep track per ring seqno progress and
2980 * if there are no progress, hangcheck score for that ring is increased.
2981 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2982 * we kick the ring. If we see no progress on three subsequent calls
2983 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 2984 */
a658b5d2 2985static void i915_hangcheck_elapsed(unsigned long data)
f65d9421
BG		 2986{
2987 struct drm_device *dev = (struct drm_device *)data;
2d1013dd 2988 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2989 struct intel_engine_cs *ring;
b4519513 2990 int i;
05407ff8 2991 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2992 bool stuck[I915_NUM_RINGS] = { 0 };
2993#define BUSY 1
2994#define KICK 5
2995#define HUNG 20
893eead0 2996
d330a953 2997 if (!i915.enable_hangcheck)
3e0dc6b0
BW		 2998 return;
2999
b4519513 3000 for_each_ring(ring, dev_priv, i) {
50877445
CW		 3001 u64 acthd;
3002 u32 seqno;
9107e9d2 3003 bool busy = true;
05407ff8 3004
6274f212
CW		 3005 semaphore_clear_deadlocks(dev_priv);
3006
05407ff8
MK		 3007 seqno = ring->get_seqno(ring, false);
3008 acthd = intel_ring_get_active_head(ring);
b4519513 3009
9107e9d2 3010 if (ring->hangcheck.seqno == seqno) {
44cdd6d2 3011 if (ring_idle(ring)) {
da661464
MK		 3012 ring->hangcheck.action = HANGCHECK_IDLE;
3013
9107e9d2
CW		 3014 if (waitqueue_active(&ring->irq_queue)) {
3015 /* Issue a wake-up to catch stuck h/w. */
094f9a54 3016 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
f4adcd24
DV		 3017 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
3018 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3019 ring->name);
3020 else
3021 DRM_INFO("Fake missed irq on %s\n",
3022 ring->name);
094f9a54
CW		 3023 wake_up_all(&ring->irq_queue);
3024 }
3025 /* Safeguard against driver failure */
3026 ring->hangcheck.score += BUSY;
9107e9d2
CW		 3027 } else
3028 busy = false;
05407ff8 3029 } else {
6274f212
CW		 3030 /* We always increment the hangcheck score
3031 * if the ring is busy and still processing
3032 * the same request, so that no single request
3033 * can run indefinitely (such as a chain of
3034 * batches). The only time we do not increment
3035 * the hangcheck score on this ring, if this
3036 * ring is in a legitimate wait for another
3037 * ring. In that case the waiting ring is a
3038 * victim and we want to be sure we catch the
3039 * right culprit. Then every time we do kick
3040 * the ring, add a small increment to the
3041 * score so that we can catch a batch that is
3042 * being repeatedly kicked and so responsible
3043 * for stalling the machine.
3044 */
ad8beaea
MK		 3045 ring->hangcheck.action = ring_stuck(ring,
3046 acthd);
3047
3048 switch (ring->hangcheck.action) {
da661464 3049 case HANGCHECK_IDLE:
f2f4d82f 3050 case HANGCHECK_WAIT:
f2f4d82f 3051 case HANGCHECK_ACTIVE:
f260fe7b
MK		 3052 break;
3053 case HANGCHECK_ACTIVE_LOOP:
ea04cb31 3054 ring->hangcheck.score += BUSY;
6274f212 3055 break;
f2f4d82f 3056 case HANGCHECK_KICK:
ea04cb31 3057 ring->hangcheck.score += KICK;
6274f212 3058 break;
f2f4d82f 3059 case HANGCHECK_HUNG:
ea04cb31 3060 ring->hangcheck.score += HUNG;
6274f212
CW		 3061 stuck[i] = true;
3062 break;
3063 }
05407ff8 3064 }
9107e9d2 3065 } else {
da661464
MK		 3066 ring->hangcheck.action = HANGCHECK_ACTIVE;
3067
9107e9d2
CW		 3068 /* Gradually reduce the count so that we catch DoS
3069 * attempts across multiple batches.
3070 */
3071 if (ring->hangcheck.score > 0)
3072 ring->hangcheck.score--;
f260fe7b
MK		 3073
3074 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
d1e61e7f
CW		 3075 }
3076
05407ff8
MK		 3077 ring->hangcheck.seqno = seqno;
3078 ring->hangcheck.acthd = acthd;
9107e9d2 3079 busy_count += busy;
893eead0 3080 }
b9201c14 3081
92cab734 3082 for_each_ring(ring, dev_priv, i) {
b6b0fac0 3083 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
b8d88d1d
DV		 3084 DRM_INFO("%s on %s\n",
3085 stuck[i] ? "stuck" : "no progress",
3086 ring->name);
a43adf07 3087 rings_hung++;
92cab734
MK		 3088 }
3089 }
3090
05407ff8 3091 if (rings_hung)
58174462 3092 return i915_handle_error(dev, true, "Ring hung");
f65d9421 3093
05407ff8
MK		 3094 if (busy_count)
3095 /* Reset timer case chip hangs without another request
3096 * being added */
10cd45b6
MK		 3097 i915_queue_hangcheck(dev);
3098}
3099
3100void i915_queue_hangcheck(struct drm_device *dev)
3101{
3102 struct drm_i915_private *dev_priv = dev->dev_private;
672e7b7c
CW		 3103 struct timer_list *timer = &dev_priv->gpu_error.hangcheck_timer;
3104
d330a953 3105 if (!i915.enable_hangcheck)
10cd45b6
MK		 3106 return;
3107
672e7b7c 3108 /* Don't continually defer the hangcheck, but make sure it is active */
d9e600b2
CW		 3109 if (timer_pending(timer))
3110 return;
3111 mod_timer(timer,
3112 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 3113}
3114
1c69eb42 3115static void ibx_irq_reset(struct drm_device *dev)
91738a95
PZ		 3116{
3117 struct drm_i915_private *dev_priv = dev->dev_private;
3118
3119 if (HAS_PCH_NOP(dev))
3120 return;
3121
f86f3fb0 3122 GEN5_IRQ_RESET(SDE);
105b122e
PZ		 3123
3124 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3125 I915_WRITE(SERR_INT, 0xffffffff);
622364b6 3126}
105b122e 3127
622364b6
PZ		 3128/*
3129 * SDEIER is also touched by the interrupt handler to work around missed PCH
3130 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3131 * instead we unconditionally enable all PCH interrupt sources here, but then
3132 * only unmask them as needed with SDEIMR.
3133 *
3134 * This function needs to be called before interrupts are enabled.
3135 */
3136static void ibx_irq_pre_postinstall(struct drm_device *dev)
3137{
3138 struct drm_i915_private *dev_priv = dev->dev_private;
3139
3140 if (HAS_PCH_NOP(dev))
3141 return;
3142
3143 WARN_ON(I915_READ(SDEIER) != 0);
91738a95
PZ		 3144 I915_WRITE(SDEIER, 0xffffffff);
3145 POSTING_READ(SDEIER);
3146}
3147
7c4d664e 3148static void gen5_gt_irq_reset(struct drm_device *dev)
d18ea1b5
DV		 3149{
3150 struct drm_i915_private *dev_priv = dev->dev_private;
3151
f86f3fb0 3152 GEN5_IRQ_RESET(GT);
a9d356a6 3153 if (INTEL_INFO(dev)->gen >= 6)
f86f3fb0 3154 GEN5_IRQ_RESET(GEN6_PM);
d18ea1b5
DV		 3155}
3156
1da177e4
LT		 3157/* drm_dma.h hooks
3158*/
be30b29f 3159static void ironlake_irq_reset(struct drm_device *dev)
036a4a7d 3160{
2d1013dd 3161 struct drm_i915_private *dev_priv = dev->dev_private;
036a4a7d 3162
0c841212 3163 I915_WRITE(HWSTAM, 0xffffffff);
bdfcdb63 3164
f86f3fb0 3165 GEN5_IRQ_RESET(DE);
c6d954c1
PZ		 3166 if (IS_GEN7(dev))
3167 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
036a4a7d 3168
7c4d664e 3169 gen5_gt_irq_reset(dev);
c650156a 3170
1c69eb42 3171 ibx_irq_reset(dev);
7d99163d 3172}
c650156a 3173
70591a41
VS		 3174static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3175{
3176 enum pipe pipe;
3177
3178 I915_WRITE(PORT_HOTPLUG_EN, 0);
3179 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3180
3181 for_each_pipe(dev_priv, pipe)
3182 I915_WRITE(PIPESTAT(pipe), 0xffff);
3183
3184 GEN5_IRQ_RESET(VLV_);
3185}
3186
7e231dbe
JB		 3187static void valleyview_irq_preinstall(struct drm_device *dev)
3188{
2d1013dd 3189 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 3190
7e231dbe
JB		 3191 /* VLV magic */
3192 I915_WRITE(VLV_IMR, 0);
3193 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3194 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3195 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3196
7c4d664e 3197 gen5_gt_irq_reset(dev);
7e231dbe 3198
7c4cde39 3199 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
7e231dbe 3200
70591a41 3201 vlv_display_irq_reset(dev_priv);
7e231dbe
JB		 3202}
3203
d6e3cca3
DV		 3204static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3205{
3206 GEN8_IRQ_RESET_NDX(GT, 0);
3207 GEN8_IRQ_RESET_NDX(GT, 1);
3208 GEN8_IRQ_RESET_NDX(GT, 2);
3209 GEN8_IRQ_RESET_NDX(GT, 3);
3210}
3211
823f6b38 3212static void gen8_irq_reset(struct drm_device *dev)
abd58f01
BW		 3213{
3214 struct drm_i915_private *dev_priv = dev->dev_private;
3215 int pipe;
3216
abd58f01
BW		 3217 I915_WRITE(GEN8_MASTER_IRQ, 0);
3218 POSTING_READ(GEN8_MASTER_IRQ);
3219
d6e3cca3 3220 gen8_gt_irq_reset(dev_priv);
abd58f01 3221
055e393f 3222 for_each_pipe(dev_priv, pipe)
f458ebbc
DV		 3223 if (intel_display_power_is_enabled(dev_priv,
3224 POWER_DOMAIN_PIPE(pipe)))
813bde43 3225 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
abd58f01 3226
f86f3fb0
PZ		 3227 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3228 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3229 GEN5_IRQ_RESET(GEN8_PCU_);
abd58f01 3230
1c69eb42 3231 ibx_irq_reset(dev);
abd58f01 3232}
09f2344d 3233
d49bdb0e
PZ		 3234void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3235{
1180e206 3236 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
d49bdb0e 3237
13321786 3238 spin_lock_irq(&dev_priv->irq_lock);
d49bdb0e 3239 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
1180e206 3240 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
d49bdb0e 3241 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
1180e206 3242 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
13321786 3243 spin_unlock_irq(&dev_priv->irq_lock);
d49bdb0e
PZ		 3244}
3245
43f328d7
VS		 3246static void cherryview_irq_preinstall(struct drm_device *dev)
3247{
3248 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7
VS		 3249
3250 I915_WRITE(GEN8_MASTER_IRQ, 0);
3251 POSTING_READ(GEN8_MASTER_IRQ);
3252
d6e3cca3 3253 gen8_gt_irq_reset(dev_priv);
43f328d7
VS		 3254
3255 GEN5_IRQ_RESET(GEN8_PCU_);
3256
43f328d7
VS		 3257 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3258
70591a41 3259 vlv_display_irq_reset(dev_priv);
43f328d7
VS		 3260}
3261
82a28bcf 3262static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973 3263{
2d1013dd 3264 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 3265 struct intel_encoder *intel_encoder;
fee884ed 3266 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 3267
3268 if (HAS_PCH_IBX(dev)) {
fee884ed 3269 hotplug_irqs = SDE_HOTPLUG_MASK;
b2784e15 3270 for_each_intel_encoder(dev, intel_encoder)
cd569aed 3271 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 3272 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 3273 } else {
fee884ed 3274 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
b2784e15 3275 for_each_intel_encoder(dev, intel_encoder)
cd569aed 3276 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 3277 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 3278 }
7fe0b973 3279
fee884ed 3280 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 3281
3282 /*
3283 * Enable digital hotplug on the PCH, and configure the DP short pulse
3284 * duration to 2ms (which is the minimum in the Display Port spec)
3285 *
3286 * This register is the same on all known PCH chips.
3287 */
7fe0b973
KP		 3288 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3289 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3290 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3291 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3292 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3293 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3294}
3295
d46da437
PZ		 3296static void ibx_irq_postinstall(struct drm_device *dev)
3297{
2d1013dd 3298 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 3299 u32 mask;
e5868a31 3300
692a04cf
DV		 3301 if (HAS_PCH_NOP(dev))
3302 return;
3303
105b122e 3304 if (HAS_PCH_IBX(dev))
5c673b60 3305 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
105b122e 3306 else
5c673b60 3307 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
8664281b 3308
337ba017 3309 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
d46da437 3310 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 3311}
3312
0a9a8c91
DV		 3313static void gen5_gt_irq_postinstall(struct drm_device *dev)
3314{
3315 struct drm_i915_private *dev_priv = dev->dev_private;
3316 u32 pm_irqs, gt_irqs;
3317
3318 pm_irqs = gt_irqs = 0;
3319
3320 dev_priv->gt_irq_mask = ~0;
040d2baa 3321 if (HAS_L3_DPF(dev)) {
0a9a8c91 3322 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 3323 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3324 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 3325 }
3326
3327 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3328 if (IS_GEN5(dev)) {
3329 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3330 ILK_BSD_USER_INTERRUPT;
3331 } else {
3332 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3333 }
3334
35079899 3335 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
0a9a8c91
DV		 3336
3337 if (INTEL_INFO(dev)->gen >= 6) {
78e68d36
ID		 3338 /*
3339 * RPS interrupts will get enabled/disabled on demand when RPS
3340 * itself is enabled/disabled.
3341 */
0a9a8c91
DV		 3342 if (HAS_VEBOX(dev))
3343 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3344
605cd25b 3345 dev_priv->pm_irq_mask = 0xffffffff;
35079899 3346 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
0a9a8c91
DV		 3347 }
3348}
3349
f71d4af4 3350static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 3351{
2d1013dd 3352 struct drm_i915_private *dev_priv = dev->dev_private;
8e76f8dc
PZ		 3353 u32 display_mask, extra_mask;
3354
3355 if (INTEL_INFO(dev)->gen >= 7) {
3356 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3357 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3358 DE_PLANEB_FLIP_DONE_IVB |
5c673b60 3359 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
8e76f8dc 3360 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
5c673b60 3361 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
8e76f8dc
PZ		 3362 } else {
3363 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3364 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
5b3a856b 3365 DE_AUX_CHANNEL_A |
5b3a856b
DV		 3366 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3367 DE_POISON);
5c673b60
DV		 3368 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3369 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
8e76f8dc 3370 }
036a4a7d 3371
1ec14ad3 3372 dev_priv->irq_mask = ~display_mask;
036a4a7d 3373
0c841212
PZ		 3374 I915_WRITE(HWSTAM, 0xeffe);
3375
622364b6
PZ		 3376 ibx_irq_pre_postinstall(dev);
3377
35079899 3378 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
036a4a7d 3379
0a9a8c91 3380 gen5_gt_irq_postinstall(dev);
036a4a7d 3381
d46da437 3382 ibx_irq_postinstall(dev);
7fe0b973 3383
f97108d1 3384 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 3385 /* Enable PCU event interrupts
3386 *
3387 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 3388 * setup is guaranteed to run in single-threaded context. But we
3389 * need it to make the assert_spin_locked happy. */
d6207435 3390 spin_lock_irq(&dev_priv->irq_lock);
f97108d1 3391 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
d6207435 3392 spin_unlock_irq(&dev_priv->irq_lock);
f97108d1
JB		 3393 }
3394
036a4a7d
ZW		 3395 return 0;
3396}
3397
f8b79e58
ID		 3398static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3399{
3400 u32 pipestat_mask;
3401 u32 iir_mask;
120dda4f 3402 enum pipe pipe;
f8b79e58
ID		 3403
3404 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3405 PIPE_FIFO_UNDERRUN_STATUS;
3406
120dda4f
VS		 3407 for_each_pipe(dev_priv, pipe)
3408 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
f8b79e58
ID		 3409 POSTING_READ(PIPESTAT(PIPE_A));
3410
3411 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3412 PIPE_CRC_DONE_INTERRUPT_STATUS;
3413
120dda4f
VS		 3414 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3415 for_each_pipe(dev_priv, pipe)
3416 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
f8b79e58
ID		 3417
3418 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3419 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3420 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
120dda4f
VS		 3421 if (IS_CHERRYVIEW(dev_priv))
3422 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
f8b79e58
ID		 3423 dev_priv->irq_mask &= ~iir_mask;
3424
3425 I915_WRITE(VLV_IIR, iir_mask);
3426 I915_WRITE(VLV_IIR, iir_mask);
f8b79e58 3427 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
76e41860
VS		 3428 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3429 POSTING_READ(VLV_IMR);
f8b79e58
ID		 3430}
3431
3432static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3433{
3434 u32 pipestat_mask;
3435 u32 iir_mask;
120dda4f 3436 enum pipe pipe;
f8b79e58
ID		 3437
3438 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3439 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
6c7fba04 3440 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
120dda4f
VS		 3441 if (IS_CHERRYVIEW(dev_priv))
3442 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
f8b79e58
ID		 3443
3444 dev_priv->irq_mask |= iir_mask;
f8b79e58 3445 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
76e41860 3446 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
f8b79e58
ID		 3447 I915_WRITE(VLV_IIR, iir_mask);
3448 I915_WRITE(VLV_IIR, iir_mask);
3449 POSTING_READ(VLV_IIR);
3450
3451 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3452 PIPE_CRC_DONE_INTERRUPT_STATUS;
3453
120dda4f
VS		 3454 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3455 for_each_pipe(dev_priv, pipe)
3456 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
f8b79e58
ID		 3457
3458 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3459 PIPE_FIFO_UNDERRUN_STATUS;
120dda4f
VS		 3460
3461 for_each_pipe(dev_priv, pipe)
3462 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
f8b79e58
ID		 3463 POSTING_READ(PIPESTAT(PIPE_A));
3464}
3465
3466void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3467{
3468 assert_spin_locked(&dev_priv->irq_lock);
3469
3470 if (dev_priv->display_irqs_enabled)
3471 return;
3472
3473 dev_priv->display_irqs_enabled = true;
3474
950eabaf 3475 if (intel_irqs_enabled(dev_priv))
f8b79e58
ID		 3476 valleyview_display_irqs_install(dev_priv);
3477}
3478
3479void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3480{
3481 assert_spin_locked(&dev_priv->irq_lock);
3482
3483 if (!dev_priv->display_irqs_enabled)
3484 return;
3485
3486 dev_priv->display_irqs_enabled = false;
3487
950eabaf 3488 if (intel_irqs_enabled(dev_priv))
f8b79e58
ID		 3489 valleyview_display_irqs_uninstall(dev_priv);
3490}
3491
0e6c9a9e 3492static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
7e231dbe 3493{
f8b79e58 3494 dev_priv->irq_mask = ~0;
7e231dbe 3495
20afbda2
DV		 3496 I915_WRITE(PORT_HOTPLUG_EN, 0);
3497 POSTING_READ(PORT_HOTPLUG_EN);
3498
7e231dbe 3499 I915_WRITE(VLV_IIR, 0xffffffff);
76e41860
VS		 3500 I915_WRITE(VLV_IIR, 0xffffffff);
3501 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3502 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3503 POSTING_READ(VLV_IMR);
7e231dbe 3504
b79480ba
DV		 3505 /* Interrupt setup is already guaranteed to be single-threaded, this is
3506 * just to make the assert_spin_locked check happy. */
d6207435 3507 spin_lock_irq(&dev_priv->irq_lock);
f8b79e58
ID		 3508 if (dev_priv->display_irqs_enabled)
3509 valleyview_display_irqs_install(dev_priv);
d6207435 3510 spin_unlock_irq(&dev_priv->irq_lock);
0e6c9a9e
VS		 3511}
3512
3513static int valleyview_irq_postinstall(struct drm_device *dev)
3514{
3515 struct drm_i915_private *dev_priv = dev->dev_private;
3516
3517 vlv_display_irq_postinstall(dev_priv);
7e231dbe 3518
0a9a8c91 3519 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 3520
3521 /* ack & enable invalid PTE error interrupts */
3522#if 0 /* FIXME: add support to irq handler for checking these bits */
3523 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3524 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3525#endif
3526
3527 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 3528
3529 return 0;
3530}
3531
abd58f01
BW		 3532static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3533{
abd58f01
BW		 3534 /* These are interrupts we'll toggle with the ring mask register */
3535 uint32_t gt_interrupts[] = {
3536 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
73d477f6 3537 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
abd58f01 3538 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
73d477f6
OM		 3539 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3540 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
abd58f01 3541 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
73d477f6
OM		 3542 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3543 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3544 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
abd58f01 3545 0,
73d477f6
OM		 3546 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3547 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
abd58f01
BW		 3548 };
3549
0961021a 3550 dev_priv->pm_irq_mask = 0xffffffff;
9a2d2d87
D		 3551 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3552 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
78e68d36
ID		 3553 /*
3554 * RPS interrupts will get enabled/disabled on demand when RPS itself
3555 * is enabled/disabled.
3556 */
3557 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
9a2d2d87 3558 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
abd58f01
BW		 3559}
3560
3561static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3562{
770de83d
DL		 3563 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3564 uint32_t de_pipe_enables;
abd58f01 3565 int pipe;
88e04703 3566 u32 aux_en = GEN8_AUX_CHANNEL_A;
770de83d 3567
88e04703 3568 if (IS_GEN9(dev_priv)) {
770de83d
DL		 3569 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3570 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
88e04703
JB		 3571 aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3572 GEN9_AUX_CHANNEL_D;
3573 } else
770de83d
DL		 3574 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3575 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3576
3577 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3578 GEN8_PIPE_FIFO_UNDERRUN;
3579
13b3a0a7
DV		 3580 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3581 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3582 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
abd58f01 3583
055e393f 3584 for_each_pipe(dev_priv, pipe)
f458ebbc 3585 if (intel_display_power_is_enabled(dev_priv,
813bde43
PZ		 3586 POWER_DOMAIN_PIPE(pipe)))
3587 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3588 dev_priv->de_irq_mask[pipe],
3589 de_pipe_enables);
abd58f01 3590
88e04703 3591 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
abd58f01
BW		 3592}
3593
3594static int gen8_irq_postinstall(struct drm_device *dev)
3595{
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597
622364b6
PZ		 3598 ibx_irq_pre_postinstall(dev);
3599
abd58f01
BW		 3600 gen8_gt_irq_postinstall(dev_priv);
3601 gen8_de_irq_postinstall(dev_priv);
3602
3603 ibx_irq_postinstall(dev);
3604
3605 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3606 POSTING_READ(GEN8_MASTER_IRQ);
3607
3608 return 0;
3609}
3610
43f328d7
VS		 3611static int cherryview_irq_postinstall(struct drm_device *dev)
3612{
3613 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7 3614
c2b66797 3615 vlv_display_irq_postinstall(dev_priv);
43f328d7
VS		 3616
3617 gen8_gt_irq_postinstall(dev_priv);
3618
3619 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3620 POSTING_READ(GEN8_MASTER_IRQ);
3621
3622 return 0;
3623}
3624
abd58f01
BW		 3625static void gen8_irq_uninstall(struct drm_device *dev)
3626{
3627 struct drm_i915_private *dev_priv = dev->dev_private;
abd58f01
BW		 3628
3629 if (!dev_priv)
3630 return;
3631
823f6b38 3632 gen8_irq_reset(dev);
abd58f01
BW		 3633}
3634
8ea0be4f
VS		 3635static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3636{
3637 /* Interrupt setup is already guaranteed to be single-threaded, this is
3638 * just to make the assert_spin_locked check happy. */
3639 spin_lock_irq(&dev_priv->irq_lock);
3640 if (dev_priv->display_irqs_enabled)
3641 valleyview_display_irqs_uninstall(dev_priv);
3642 spin_unlock_irq(&dev_priv->irq_lock);
3643
3644 vlv_display_irq_reset(dev_priv);
3645
c352d1ba 3646 dev_priv->irq_mask = ~0;
8ea0be4f
VS		 3647}
3648
7e231dbe
JB		 3649static void valleyview_irq_uninstall(struct drm_device *dev)
3650{
2d1013dd 3651 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 3652
3653 if (!dev_priv)
3654 return;
3655
843d0e7d
ID		 3656 I915_WRITE(VLV_MASTER_IER, 0);
3657
893fce8e
VS		 3658 gen5_gt_irq_reset(dev);
3659
7e231dbe 3660 I915_WRITE(HWSTAM, 0xffffffff);
f8b79e58 3661
8ea0be4f 3662 vlv_display_irq_uninstall(dev_priv);
7e231dbe
JB		 3663}
3664
43f328d7
VS		 3665static void cherryview_irq_uninstall(struct drm_device *dev)
3666{
3667 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7
VS		 3668
3669 if (!dev_priv)
3670 return;
3671
3672 I915_WRITE(GEN8_MASTER_IRQ, 0);
3673 POSTING_READ(GEN8_MASTER_IRQ);
3674
a2c30fba 3675 gen8_gt_irq_reset(dev_priv);
43f328d7 3676
a2c30fba 3677 GEN5_IRQ_RESET(GEN8_PCU_);
43f328d7 3678
c2b66797 3679 vlv_display_irq_uninstall(dev_priv);
43f328d7
VS		 3680}
3681
f71d4af4 3682static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d 3683{
2d1013dd 3684 struct drm_i915_private *dev_priv = dev->dev_private;
4697995b
JB		 3685
3686 if (!dev_priv)
3687 return;
3688
be30b29f 3689 ironlake_irq_reset(dev);
036a4a7d
ZW		 3690}
3691
a266c7d5 3692static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4 3693{
2d1013dd 3694 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 3695 int pipe;
91e3738e 3696
055e393f 3697 for_each_pipe(dev_priv, pipe)
9db4a9c7 3698 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 3699 I915_WRITE16(IMR, 0xffff);
3700 I915_WRITE16(IER, 0x0);
3701 POSTING_READ16(IER);
c2798b19
CW		 3702}
3703
3704static int i8xx_irq_postinstall(struct drm_device *dev)
3705{
2d1013dd 3706 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19 3707
c2798b19
CW		 3708 I915_WRITE16(EMR,
3709 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3710
3711 /* Unmask the interrupts that we always want on. */
3712 dev_priv->irq_mask =
3713 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3714 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3715 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3716 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3717 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3718 I915_WRITE16(IMR, dev_priv->irq_mask);
3719
3720 I915_WRITE16(IER,
3721 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3722 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3723 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3724 I915_USER_INTERRUPT);
3725 POSTING_READ16(IER);
3726
379ef82d
DV		 3727 /* Interrupt setup is already guaranteed to be single-threaded, this is
3728 * just to make the assert_spin_locked check happy. */
d6207435 3729 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 3730 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3731 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 3732 spin_unlock_irq(&dev_priv->irq_lock);
379ef82d 3733
c2798b19
CW		 3734 return 0;
3735}
3736
90a72f87
VS		 3737/*
3738 * Returns true when a page flip has completed.
3739 */
3740static bool i8xx_handle_vblank(struct drm_device *dev,
1f1c2e24 3741 int plane, int pipe, u32 iir)
90a72f87 3742{
2d1013dd 3743 struct drm_i915_private *dev_priv = dev->dev_private;
1f1c2e24 3744 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
90a72f87 3745
8d7849db 3746 if (!intel_pipe_handle_vblank(dev, pipe))
90a72f87
VS		 3747 return false;
3748
3749 if ((iir & flip_pending) == 0)
d6bbafa1 3750 goto check_page_flip;
90a72f87 3751
90a72f87
VS		 3752 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3753 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3754 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3755 * the flip is completed (no longer pending). Since this doesn't raise
3756 * an interrupt per se, we watch for the change at vblank.
3757 */
3758 if (I915_READ16(ISR) & flip_pending)
d6bbafa1 3759 goto check_page_flip;
90a72f87 3760
7d47559e 3761 intel_prepare_page_flip(dev, plane);
90a72f87 3762 intel_finish_page_flip(dev, pipe);
90a72f87 3763 return true;
d6bbafa1
CW		 3764
3765check_page_flip:
3766 intel_check_page_flip(dev, pipe);
3767 return false;
90a72f87
VS		 3768}
3769
ff1f525e 3770static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19 3771{
45a83f84 3772 struct drm_device *dev = arg;
2d1013dd 3773 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3774 u16 iir, new_iir;
3775 u32 pipe_stats[2];
c2798b19
CW		 3776 int pipe;
3777 u16 flip_mask =
3778 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3779 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3780
c2798b19
CW		 3781 iir = I915_READ16(IIR);
3782 if (iir == 0)
3783 return IRQ_NONE;
3784
3785 while (iir & ~flip_mask) {
3786 /* Can't rely on pipestat interrupt bit in iir as it might
3787 * have been cleared after the pipestat interrupt was received.
3788 * It doesn't set the bit in iir again, but it still produces
3789 * interrupts (for non-MSI).
3790 */
222c7f51 3791 spin_lock(&dev_priv->irq_lock);
c2798b19 3792 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 3793 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
c2798b19 3794
055e393f 3795 for_each_pipe(dev_priv, pipe) {
c2798b19
CW		 3796 int reg = PIPESTAT(pipe);
3797 pipe_stats[pipe] = I915_READ(reg);
3798
3799 /*
3800 * Clear the PIPE*STAT regs before the IIR
3801 */
2d9d2b0b 3802 if (pipe_stats[pipe] & 0x8000ffff)
c2798b19 3803 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19 3804 }
222c7f51 3805 spin_unlock(&dev_priv->irq_lock);
c2798b19
CW		 3806
3807 I915_WRITE16(IIR, iir & ~flip_mask);
3808 new_iir = I915_READ16(IIR); /* Flush posted writes */
3809
c2798b19
CW		 3810 if (iir & I915_USER_INTERRUPT)
3811 notify_ring(dev, &dev_priv->ring[RCS]);
3812
055e393f 3813 for_each_pipe(dev_priv, pipe) {
1f1c2e24 3814 int plane = pipe;
3a77c4c4 3815 if (HAS_FBC(dev))
1f1c2e24
VS		 3816 plane = !plane;
3817
4356d586 3818 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
1f1c2e24
VS		 3819 i8xx_handle_vblank(dev, plane, pipe, iir))
3820 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
c2798b19 3821
4356d586 3822 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3823 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b 3824
1f7247c0
DV		 3825 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3826 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3827 pipe);
4356d586 3828 }
c2798b19
CW		 3829
3830 iir = new_iir;
3831 }
3832
3833 return IRQ_HANDLED;
3834}
3835
3836static void i8xx_irq_uninstall(struct drm_device * dev)
3837{
2d1013dd 3838 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3839 int pipe;
3840
055e393f 3841 for_each_pipe(dev_priv, pipe) {
c2798b19
CW		 3842 /* Clear enable bits; then clear status bits */
3843 I915_WRITE(PIPESTAT(pipe), 0);
3844 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3845 }
3846 I915_WRITE16(IMR, 0xffff);
3847 I915_WRITE16(IER, 0x0);
3848 I915_WRITE16(IIR, I915_READ16(IIR));
3849}
3850
a266c7d5
CW		 3851static void i915_irq_preinstall(struct drm_device * dev)
3852{
2d1013dd 3853 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3854 int pipe;
3855
a266c7d5
CW		 3856 if (I915_HAS_HOTPLUG(dev)) {
3857 I915_WRITE(PORT_HOTPLUG_EN, 0);
3858 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3859 }
3860
00d98ebd 3861 I915_WRITE16(HWSTAM, 0xeffe);
055e393f 3862 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 3863 I915_WRITE(PIPESTAT(pipe), 0);
3864 I915_WRITE(IMR, 0xffffffff);
3865 I915_WRITE(IER, 0x0);
3866 POSTING_READ(IER);
3867}
3868
3869static int i915_irq_postinstall(struct drm_device *dev)
3870{
2d1013dd 3871 struct drm_i915_private *dev_priv = dev->dev_private;
38bde180 3872 u32 enable_mask;
a266c7d5 3873
38bde180
CW		 3874 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3875
3876 /* Unmask the interrupts that we always want on. */
3877 dev_priv->irq_mask =
3878 ~(I915_ASLE_INTERRUPT |
3879 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3880 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3881 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3882 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3883 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3884
3885 enable_mask =
3886 I915_ASLE_INTERRUPT |
3887 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3888 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3889 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3890 I915_USER_INTERRUPT;
3891
a266c7d5 3892 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3893 I915_WRITE(PORT_HOTPLUG_EN, 0);
3894 POSTING_READ(PORT_HOTPLUG_EN);
3895
a266c7d5
CW		 3896 /* Enable in IER... */
3897 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3898 /* and unmask in IMR */
3899 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3900 }
3901
a266c7d5
CW		 3902 I915_WRITE(IMR, dev_priv->irq_mask);
3903 I915_WRITE(IER, enable_mask);
3904 POSTING_READ(IER);
3905
f49e38dd 3906 i915_enable_asle_pipestat(dev);
20afbda2 3907
379ef82d
DV		 3908 /* Interrupt setup is already guaranteed to be single-threaded, this is
3909 * just to make the assert_spin_locked check happy. */
d6207435 3910 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 3911 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3912 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 3913 spin_unlock_irq(&dev_priv->irq_lock);
379ef82d 3914
20afbda2
DV		 3915 return 0;
3916}
3917
90a72f87
VS		 3918/*
3919 * Returns true when a page flip has completed.
3920 */
3921static bool i915_handle_vblank(struct drm_device *dev,
3922 int plane, int pipe, u32 iir)
3923{
2d1013dd 3924 struct drm_i915_private *dev_priv = dev->dev_private;
90a72f87
VS		 3925 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3926
8d7849db 3927 if (!intel_pipe_handle_vblank(dev, pipe))
90a72f87
VS		 3928 return false;
3929
3930 if ((iir & flip_pending) == 0)
d6bbafa1 3931 goto check_page_flip;
90a72f87 3932
90a72f87
VS		 3933 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3934 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3935 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3936 * the flip is completed (no longer pending). Since this doesn't raise
3937 * an interrupt per se, we watch for the change at vblank.
3938 */
3939 if (I915_READ(ISR) & flip_pending)
d6bbafa1 3940 goto check_page_flip;
90a72f87 3941
7d47559e 3942 intel_prepare_page_flip(dev, plane);
90a72f87 3943 intel_finish_page_flip(dev, pipe);
90a72f87 3944 return true;
d6bbafa1
CW		 3945
3946check_page_flip:
3947 intel_check_page_flip(dev, pipe);
3948 return false;
90a72f87
VS		 3949}
3950
ff1f525e 3951static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5 3952{
45a83f84 3953 struct drm_device *dev = arg;
2d1013dd 3954 struct drm_i915_private *dev_priv = dev->dev_private;
8291ee90 3955 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
38bde180
CW		 3956 u32 flip_mask =
3957 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3958 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3959 int pipe, ret = IRQ_NONE;
a266c7d5 3960
a266c7d5 3961 iir = I915_READ(IIR);
38bde180
CW		 3962 do {
3963 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3964 bool blc_event = false;
a266c7d5
CW		 3965
3966 /* Can't rely on pipestat interrupt bit in iir as it might
3967 * have been cleared after the pipestat interrupt was received.
3968 * It doesn't set the bit in iir again, but it still produces
3969 * interrupts (for non-MSI).
3970 */
222c7f51 3971 spin_lock(&dev_priv->irq_lock);
a266c7d5 3972 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 3973 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
a266c7d5 3974
055e393f 3975 for_each_pipe(dev_priv, pipe) {
a266c7d5
CW		 3976 int reg = PIPESTAT(pipe);
3977 pipe_stats[pipe] = I915_READ(reg);
3978
38bde180 3979 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5 3980 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3981 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3982 irq_received = true;
a266c7d5
CW		 3983 }
3984 }
222c7f51 3985 spin_unlock(&dev_priv->irq_lock);
a266c7d5
CW		 3986
3987 if (!irq_received)
3988 break;
3989
a266c7d5 3990 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 3991 if (I915_HAS_HOTPLUG(dev) &&
3992 iir & I915_DISPLAY_PORT_INTERRUPT)
3993 i9xx_hpd_irq_handler(dev);
a266c7d5 3994
38bde180 3995 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3996 new_iir = I915_READ(IIR); /* Flush posted writes */
3997
a266c7d5
CW		 3998 if (iir & I915_USER_INTERRUPT)
3999 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 4000
055e393f 4001 for_each_pipe(dev_priv, pipe) {
38bde180 4002 int plane = pipe;
3a77c4c4 4003 if (HAS_FBC(dev))
38bde180 4004 plane = !plane;
90a72f87 4005
8291ee90 4006 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 4007 i915_handle_vblank(dev, plane, pipe, iir))
4008 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 4009
4010 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4011 blc_event = true;
4356d586
DV		 4012
4013 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 4014 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b 4015
1f7247c0
DV		 4016 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4017 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4018 pipe);
a266c7d5
CW		 4019 }
4020
a266c7d5
CW		 4021 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4022 intel_opregion_asle_intr(dev);
4023
4024 /* With MSI, interrupts are only generated when iir
4025 * transitions from zero to nonzero. If another bit got
4026 * set while we were handling the existing iir bits, then
4027 * we would never get another interrupt.
4028 *
4029 * This is fine on non-MSI as well, as if we hit this path
4030 * we avoid exiting the interrupt handler only to generate
4031 * another one.
4032 *
4033 * Note that for MSI this could cause a stray interrupt report
4034 * if an interrupt landed in the time between writing IIR and
4035 * the posting read. This should be rare enough to never
4036 * trigger the 99% of 100,000 interrupts test for disabling
4037 * stray interrupts.
4038 */
38bde180 4039 ret = IRQ_HANDLED;
a266c7d5 4040 iir = new_iir;
38bde180 4041 } while (iir & ~flip_mask);
a266c7d5
CW		 4042
4043 return ret;
4044}
4045
4046static void i915_irq_uninstall(struct drm_device * dev)
4047{
2d1013dd 4048 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4049 int pipe;
4050
a266c7d5
CW		 4051 if (I915_HAS_HOTPLUG(dev)) {
4052 I915_WRITE(PORT_HOTPLUG_EN, 0);
4053 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4054 }
4055
00d98ebd 4056 I915_WRITE16(HWSTAM, 0xffff);
055e393f 4057 for_each_pipe(dev_priv, pipe) {
55b39755 4058 /* Clear enable bits; then clear status bits */
a266c7d5 4059 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 4060 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4061 }
a266c7d5
CW		 4062 I915_WRITE(IMR, 0xffffffff);
4063 I915_WRITE(IER, 0x0);
4064
a266c7d5
CW		 4065 I915_WRITE(IIR, I915_READ(IIR));
4066}
4067
4068static void i965_irq_preinstall(struct drm_device * dev)
4069{
2d1013dd 4070 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4071 int pipe;
4072
adca4730
CW		 4073 I915_WRITE(PORT_HOTPLUG_EN, 0);
4074 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 4075
4076 I915_WRITE(HWSTAM, 0xeffe);
055e393f 4077 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4078 I915_WRITE(PIPESTAT(pipe), 0);
4079 I915_WRITE(IMR, 0xffffffff);
4080 I915_WRITE(IER, 0x0);
4081 POSTING_READ(IER);
4082}
4083
4084static int i965_irq_postinstall(struct drm_device *dev)
4085{
2d1013dd 4086 struct drm_i915_private *dev_priv = dev->dev_private;
bbba0a97 4087 u32 enable_mask;
a266c7d5
CW		 4088 u32 error_mask;
4089
a266c7d5 4090 /* Unmask the interrupts that we always want on. */
bbba0a97 4091 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 4092 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 4093 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4094 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4095 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4096 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4097 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4098
4099 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 4100 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4101 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 4102 enable_mask |= I915_USER_INTERRUPT;
4103
4104 if (IS_G4X(dev))
4105 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 4106
b79480ba
DV		 4107 /* Interrupt setup is already guaranteed to be single-threaded, this is
4108 * just to make the assert_spin_locked check happy. */
d6207435 4109 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 4110 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4111 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4112 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 4113 spin_unlock_irq(&dev_priv->irq_lock);
a266c7d5 4114
a266c7d5
CW		 4115 /*
4116 * Enable some error detection, note the instruction error mask
4117 * bit is reserved, so we leave it masked.
4118 */
4119 if (IS_G4X(dev)) {
4120 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4121 GM45_ERROR_MEM_PRIV |
4122 GM45_ERROR_CP_PRIV |
4123 I915_ERROR_MEMORY_REFRESH);
4124 } else {
4125 error_mask = ~(I915_ERROR_PAGE_TABLE |
4126 I915_ERROR_MEMORY_REFRESH);
4127 }
4128 I915_WRITE(EMR, error_mask);
4129
4130 I915_WRITE(IMR, dev_priv->irq_mask);
4131 I915_WRITE(IER, enable_mask);
4132 POSTING_READ(IER);
4133
20afbda2
DV		 4134 I915_WRITE(PORT_HOTPLUG_EN, 0);
4135 POSTING_READ(PORT_HOTPLUG_EN);
4136
f49e38dd 4137 i915_enable_asle_pipestat(dev);
20afbda2
DV		 4138
4139 return 0;
4140}
4141
bac56d5b 4142static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2 4143{
2d1013dd 4144 struct drm_i915_private *dev_priv = dev->dev_private;
cd569aed 4145 struct intel_encoder *intel_encoder;
20afbda2
DV		 4146 u32 hotplug_en;
4147
b5ea2d56
DV		 4148 assert_spin_locked(&dev_priv->irq_lock);
4149
778eb334
VS		 4150 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4151 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4152 /* Note HDMI and DP share hotplug bits */
4153 /* enable bits are the same for all generations */
4154 for_each_intel_encoder(dev, intel_encoder)
4155 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4156 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4157 /* Programming the CRT detection parameters tends
4158 to generate a spurious hotplug event about three
4159 seconds later. So just do it once.
4160 */
4161 if (IS_G4X(dev))
4162 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4163 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4164 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4165
4166 /* Ignore TV since it's buggy */
4167 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 4168}
4169
ff1f525e 4170static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5 4171{
45a83f84 4172 struct drm_device *dev = arg;
2d1013dd 4173 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4174 u32 iir, new_iir;
4175 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5 4176 int ret = IRQ_NONE, pipe;
21ad8330
VS		 4177 u32 flip_mask =
4178 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4179 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5 4180
a266c7d5
CW		 4181 iir = I915_READ(IIR);
4182
a266c7d5 4183 for (;;) {
501e01d7 4184 bool irq_received = (iir & ~flip_mask) != 0;
2c8ba29f
CW		 4185 bool blc_event = false;
4186
a266c7d5
CW		 4187 /* Can't rely on pipestat interrupt bit in iir as it might
4188 * have been cleared after the pipestat interrupt was received.
4189 * It doesn't set the bit in iir again, but it still produces
4190 * interrupts (for non-MSI).
4191 */
222c7f51 4192 spin_lock(&dev_priv->irq_lock);
a266c7d5 4193 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 4194 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
a266c7d5 4195
055e393f 4196 for_each_pipe(dev_priv, pipe) {
a266c7d5
CW		 4197 int reg = PIPESTAT(pipe);
4198 pipe_stats[pipe] = I915_READ(reg);
4199
4200 /*
4201 * Clear the PIPE*STAT regs before the IIR
4202 */
4203 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 4204 I915_WRITE(reg, pipe_stats[pipe]);
501e01d7 4205 irq_received = true;
a266c7d5
CW		 4206 }
4207 }
222c7f51 4208 spin_unlock(&dev_priv->irq_lock);
a266c7d5
CW		 4209
4210 if (!irq_received)
4211 break;
4212
4213 ret = IRQ_HANDLED;
4214
4215 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 4216 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4217 i9xx_hpd_irq_handler(dev);
a266c7d5 4218
21ad8330 4219 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 4220 new_iir = I915_READ(IIR); /* Flush posted writes */
4221
a266c7d5
CW		 4222 if (iir & I915_USER_INTERRUPT)
4223 notify_ring(dev, &dev_priv->ring[RCS]);
4224 if (iir & I915_BSD_USER_INTERRUPT)
4225 notify_ring(dev, &dev_priv->ring[VCS]);
4226
055e393f 4227 for_each_pipe(dev_priv, pipe) {
2c8ba29f 4228 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 4229 i915_handle_vblank(dev, pipe, pipe, iir))
4230 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 4231
4232 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4233 blc_event = true;
4356d586
DV		 4234
4235 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 4236 i9xx_pipe_crc_irq_handler(dev, pipe);
a266c7d5 4237
1f7247c0
DV		 4238 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4239 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2d9d2b0b 4240 }
a266c7d5
CW		 4241
4242 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4243 intel_opregion_asle_intr(dev);
4244
515ac2bb
DV		 4245 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4246 gmbus_irq_handler(dev);
4247
a266c7d5
CW		 4248 /* With MSI, interrupts are only generated when iir
4249 * transitions from zero to nonzero. If another bit got
4250 * set while we were handling the existing iir bits, then
4251 * we would never get another interrupt.
4252 *
4253 * This is fine on non-MSI as well, as if we hit this path
4254 * we avoid exiting the interrupt handler only to generate
4255 * another one.
4256 *
4257 * Note that for MSI this could cause a stray interrupt report
4258 * if an interrupt landed in the time between writing IIR and
4259 * the posting read. This should be rare enough to never
4260 * trigger the 99% of 100,000 interrupts test for disabling
4261 * stray interrupts.
4262 */
4263 iir = new_iir;
4264 }
4265
4266 return ret;
4267}
4268
4269static void i965_irq_uninstall(struct drm_device * dev)
4270{
2d1013dd 4271 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4272 int pipe;
4273
4274 if (!dev_priv)
4275 return;
4276
adca4730
CW		 4277 I915_WRITE(PORT_HOTPLUG_EN, 0);
4278 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 4279
4280 I915_WRITE(HWSTAM, 0xffffffff);
055e393f 4281 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4282 I915_WRITE(PIPESTAT(pipe), 0);
4283 I915_WRITE(IMR, 0xffffffff);
4284 I915_WRITE(IER, 0x0);
4285
055e393f 4286 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4287 I915_WRITE(PIPESTAT(pipe),
4288 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4289 I915_WRITE(IIR, I915_READ(IIR));
4290}
4291
4cb21832 4292static void intel_hpd_irq_reenable_work(struct work_struct *work)
ac4c16c5 4293{
6323751d
ID		 4294 struct drm_i915_private *dev_priv =
4295 container_of(work, typeof(*dev_priv),
4296 hotplug_reenable_work.work);
ac4c16c5
EE		 4297 struct drm_device *dev = dev_priv->dev;
4298 struct drm_mode_config *mode_config = &dev->mode_config;
ac4c16c5
EE		 4299 int i;
4300
6323751d
ID		 4301 intel_runtime_pm_get(dev_priv);
4302
4cb21832 4303 spin_lock_irq(&dev_priv->irq_lock);
ac4c16c5
EE		 4304 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4305 struct drm_connector *connector;
4306
4307 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4308 continue;
4309
4310 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4311
4312 list_for_each_entry(connector, &mode_config->connector_list, head) {
4313 struct intel_connector *intel_connector = to_intel_connector(connector);
4314
4315 if (intel_connector->encoder->hpd_pin == i) {
4316 if (connector->polled != intel_connector->polled)
4317 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
c23cc417 4318 connector->name);
ac4c16c5
EE		 4319 connector->polled = intel_connector->polled;
4320 if (!connector->polled)
4321 connector->polled = DRM_CONNECTOR_POLL_HPD;
4322 }
4323 }
4324 }
4325 if (dev_priv->display.hpd_irq_setup)
4326 dev_priv->display.hpd_irq_setup(dev);
4cb21832 4327 spin_unlock_irq(&dev_priv->irq_lock);
6323751d
ID		 4328
4329 intel_runtime_pm_put(dev_priv);
ac4c16c5
EE		 4330}
4331
fca52a55
DV		 4332/**
4333 * intel_irq_init - initializes irq support
4334 * @dev_priv: i915 device instance
4335 *
4336 * This function initializes all the irq support including work items, timers
4337 * and all the vtables. It does not setup the interrupt itself though.
4338 */
b963291c 4339void intel_irq_init(struct drm_i915_private *dev_priv)
f71d4af4 4340{
b963291c 4341 struct drm_device *dev = dev_priv->dev;
8b2e326d
CW		 4342
4343 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
13cf5504 4344 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
99584db3 4345 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 4346 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 4347 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 4348
a6706b45 4349 /* Let's track the enabled rps events */
b963291c 4350 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
6c65a587 4351 /* WaGsvRC0ResidencyMethod:vlv */
31685c25
D		 4352 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4353 else
4354 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
a6706b45 4355
99584db3
DV		 4356 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4357 i915_hangcheck_elapsed,
61bac78e 4358 (unsigned long) dev);
6323751d 4359 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4cb21832 4360 intel_hpd_irq_reenable_work);
61bac78e 4361
97a19a24 4362 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 4363
b963291c 4364 if (IS_GEN2(dev_priv)) {
4cdb83ec
VS		 4365 dev->max_vblank_count = 0;
4366 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
b963291c 4367 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
f71d4af4
JB		 4368 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4369 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
391f75e2
VS		 4370 } else {
4371 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4372 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 4373 }
4374
21da2700
VS		 4375 /*
4376 * Opt out of the vblank disable timer on everything except gen2.
4377 * Gen2 doesn't have a hardware frame counter and so depends on
4378 * vblank interrupts to produce sane vblank seuquence numbers.
4379 */
b963291c 4380 if (!IS_GEN2(dev_priv))
21da2700
VS		 4381 dev->vblank_disable_immediate = true;
4382
c2baf4b7 4383 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
c3613de9 4384 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
c2baf4b7
VS		 4385 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4386 }
f71d4af4 4387
b963291c 4388 if (IS_CHERRYVIEW(dev_priv)) {
43f328d7
VS		 4389 dev->driver->irq_handler = cherryview_irq_handler;
4390 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4391 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4392 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4393 dev->driver->enable_vblank = valleyview_enable_vblank;
4394 dev->driver->disable_vblank = valleyview_disable_vblank;
4395 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
b963291c 4396 } else if (IS_VALLEYVIEW(dev_priv)) {
7e231dbe
JB		 4397 dev->driver->irq_handler = valleyview_irq_handler;
4398 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4399 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4400 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4401 dev->driver->enable_vblank = valleyview_enable_vblank;
4402 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 4403 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
b963291c 4404 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
abd58f01 4405 dev->driver->irq_handler = gen8_irq_handler;
723761b8 4406 dev->driver->irq_preinstall = gen8_irq_reset;
abd58f01
BW		 4407 dev->driver->irq_postinstall = gen8_irq_postinstall;
4408 dev->driver->irq_uninstall = gen8_irq_uninstall;
4409 dev->driver->enable_vblank = gen8_enable_vblank;
4410 dev->driver->disable_vblank = gen8_disable_vblank;
4411 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 4412 } else if (HAS_PCH_SPLIT(dev)) {
4413 dev->driver->irq_handler = ironlake_irq_handler;
723761b8 4414 dev->driver->irq_preinstall = ironlake_irq_reset;
f71d4af4
JB		 4415 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4416 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4417 dev->driver->enable_vblank = ironlake_enable_vblank;
4418 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 4419 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 4420 } else {
b963291c 4421 if (INTEL_INFO(dev_priv)->gen == 2) {
c2798b19
CW		 4422 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4423 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4424 dev->driver->irq_handler = i8xx_irq_handler;
4425 dev->driver->irq_uninstall = i8xx_irq_uninstall;
b963291c 4426 } else if (INTEL_INFO(dev_priv)->gen == 3) {
a266c7d5
CW		 4427 dev->driver->irq_preinstall = i915_irq_preinstall;
4428 dev->driver->irq_postinstall = i915_irq_postinstall;
4429 dev->driver->irq_uninstall = i915_irq_uninstall;
4430 dev->driver->irq_handler = i915_irq_handler;
c2798b19 4431 } else {
a266c7d5
CW		 4432 dev->driver->irq_preinstall = i965_irq_preinstall;
4433 dev->driver->irq_postinstall = i965_irq_postinstall;
4434 dev->driver->irq_uninstall = i965_irq_uninstall;
4435 dev->driver->irq_handler = i965_irq_handler;
c2798b19 4436 }
778eb334
VS		 4437 if (I915_HAS_HOTPLUG(dev_priv))
4438 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
f71d4af4
JB		 4439 dev->driver->enable_vblank = i915_enable_vblank;
4440 dev->driver->disable_vblank = i915_disable_vblank;
4441 }
4442}
20afbda2 4443
fca52a55
DV		 4444/**
4445 * intel_hpd_init - initializes and enables hpd support
4446 * @dev_priv: i915 device instance
4447 *
4448 * This function enables the hotplug support. It requires that interrupts have
4449 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4450 * poll request can run concurrently to other code, so locking rules must be
4451 * obeyed.
4452 *
4453 * This is a separate step from interrupt enabling to simplify the locking rules
4454 * in the driver load and resume code.
4455 */
b963291c 4456void intel_hpd_init(struct drm_i915_private *dev_priv)
20afbda2 4457{
b963291c 4458 struct drm_device *dev = dev_priv->dev;
821450c6
EE		 4459 struct drm_mode_config *mode_config = &dev->mode_config;
4460 struct drm_connector *connector;
4461 int i;
20afbda2 4462
821450c6
EE		 4463 for (i = 1; i < HPD_NUM_PINS; i++) {
4464 dev_priv->hpd_stats[i].hpd_cnt = 0;
4465 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4466 }
4467 list_for_each_entry(connector, &mode_config->connector_list, head) {
4468 struct intel_connector *intel_connector = to_intel_connector(connector);
4469 connector->polled = intel_connector->polled;
0e32b39c
DA		 4470 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4471 connector->polled = DRM_CONNECTOR_POLL_HPD;
4472 if (intel_connector->mst_port)
821450c6
EE		 4473 connector->polled = DRM_CONNECTOR_POLL_HPD;
4474 }
b5ea2d56
DV		 4475
4476 /* Interrupt setup is already guaranteed to be single-threaded, this is
4477 * just to make the assert_spin_locked checks happy. */
d6207435 4478 spin_lock_irq(&dev_priv->irq_lock);
20afbda2
DV		 4479 if (dev_priv->display.hpd_irq_setup)
4480 dev_priv->display.hpd_irq_setup(dev);
d6207435 4481 spin_unlock_irq(&dev_priv->irq_lock);
20afbda2 4482}
c67a470b 4483
fca52a55
DV		 4484/**
4485 * intel_irq_install - enables the hardware interrupt
4486 * @dev_priv: i915 device instance
4487 *
4488 * This function enables the hardware interrupt handling, but leaves the hotplug
4489 * handling still disabled. It is called after intel_irq_init().
4490 *
4491 * In the driver load and resume code we need working interrupts in a few places
4492 * but don't want to deal with the hassle of concurrent probe and hotplug
4493 * workers. Hence the split into this two-stage approach.
4494 */
2aeb7d3a
DV		 4495int intel_irq_install(struct drm_i915_private *dev_priv)
4496{
4497 /*
4498 * We enable some interrupt sources in our postinstall hooks, so mark
4499 * interrupts as enabled _before_ actually enabling them to avoid
4500 * special cases in our ordering checks.
4501 */
4502 dev_priv->pm.irqs_enabled = true;
4503
4504 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4505}
4506
fca52a55
DV		 4507/**
4508 * intel_irq_uninstall - finilizes all irq handling
4509 * @dev_priv: i915 device instance
4510 *
4511 * This stops interrupt and hotplug handling and unregisters and frees all
4512 * resources acquired in the init functions.
4513 */
2aeb7d3a
DV		 4514void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4515{
4516 drm_irq_uninstall(dev_priv->dev);
4517 intel_hpd_cancel_work(dev_priv);
4518 dev_priv->pm.irqs_enabled = false;
4519}
4520
fca52a55
DV		 4521/**
4522 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4523 * @dev_priv: i915 device instance
4524 *
4525 * This function is used to disable interrupts at runtime, both in the runtime
4526 * pm and the system suspend/resume code.
4527 */
b963291c 4528void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
c67a470b 4529{
b963291c 4530 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
2aeb7d3a 4531 dev_priv->pm.irqs_enabled = false;
c67a470b
PZ		 4532}
4533
fca52a55
DV		 4534/**
4535 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4536 * @dev_priv: i915 device instance
4537 *
4538 * This function is used to enable interrupts at runtime, both in the runtime
4539 * pm and the system suspend/resume code.
4540 */
b963291c 4541void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
c67a470b 4542{
2aeb7d3a 4543 dev_priv->pm.irqs_enabled = true;
b963291c
DV		 4544 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4545 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
c67a470b 4546}
Linux kernel - Deliverables
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