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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e5868a31 EE |
48 | static const u32 hpd_ibx[] = { |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
54 | }; | |
55 | ||
56 | static const u32 hpd_cpt[] = { | |
57 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 58 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
59 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
60 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
61 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
62 | }; | |
63 | ||
64 | static const u32 hpd_mask_i915[] = { | |
65 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
71 | }; | |
72 | ||
704cfb87 | 73 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
80 | }; | |
81 | ||
e5868a31 EE |
82 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
83 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
84 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
85 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
86 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
87 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
88 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
89 | }; | |
90 | ||
5c502442 | 91 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 92 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
93 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
94 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
95 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
96 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
97 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
98 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
99 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
100 | } while (0) | |
101 | ||
f86f3fb0 | 102 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 103 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 104 | POSTING_READ(type##IMR); \ |
a9d356a6 | 105 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
106 | I915_WRITE(type##IIR, 0xffffffff); \ |
107 | POSTING_READ(type##IIR); \ | |
108 | I915_WRITE(type##IIR, 0xffffffff); \ | |
109 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
110 | } while (0) |
111 | ||
337ba017 PZ |
112 | /* |
113 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
114 | */ | |
115 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
116 | u32 val = I915_READ(reg); \ | |
117 | if (val) { \ | |
118 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
119 | (reg), val); \ | |
120 | I915_WRITE((reg), 0xffffffff); \ | |
121 | POSTING_READ(reg); \ | |
122 | I915_WRITE((reg), 0xffffffff); \ | |
123 | POSTING_READ(reg); \ | |
124 | } \ | |
125 | } while (0) | |
126 | ||
35079899 | 127 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 128 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 | 129 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
130 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
131 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
132 | } while (0) |
133 | ||
134 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 135 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 | 136 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
137 | I915_WRITE(type##IMR, (imr_val)); \ |
138 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
139 | } while (0) |
140 | ||
c9a9a268 ID |
141 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
142 | ||
036a4a7d | 143 | /* For display hotplug interrupt */ |
47339cd9 | 144 | void |
2d1013dd | 145 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 146 | { |
4bc9d430 DV |
147 | assert_spin_locked(&dev_priv->irq_lock); |
148 | ||
9df7575f | 149 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 150 | return; |
c67a470b | 151 | |
1ec14ad3 CW |
152 | if ((dev_priv->irq_mask & mask) != 0) { |
153 | dev_priv->irq_mask &= ~mask; | |
154 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 155 | POSTING_READ(DEIMR); |
036a4a7d ZW |
156 | } |
157 | } | |
158 | ||
47339cd9 | 159 | void |
2d1013dd | 160 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 161 | { |
4bc9d430 DV |
162 | assert_spin_locked(&dev_priv->irq_lock); |
163 | ||
06ffc778 | 164 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 165 | return; |
c67a470b | 166 | |
1ec14ad3 CW |
167 | if ((dev_priv->irq_mask & mask) != mask) { |
168 | dev_priv->irq_mask |= mask; | |
169 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 170 | POSTING_READ(DEIMR); |
036a4a7d ZW |
171 | } |
172 | } | |
173 | ||
43eaea13 PZ |
174 | /** |
175 | * ilk_update_gt_irq - update GTIMR | |
176 | * @dev_priv: driver private | |
177 | * @interrupt_mask: mask of interrupt bits to update | |
178 | * @enabled_irq_mask: mask of interrupt bits to enable | |
179 | */ | |
180 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
181 | uint32_t interrupt_mask, | |
182 | uint32_t enabled_irq_mask) | |
183 | { | |
184 | assert_spin_locked(&dev_priv->irq_lock); | |
185 | ||
9df7575f | 186 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 187 | return; |
c67a470b | 188 | |
43eaea13 PZ |
189 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
190 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
191 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
192 | POSTING_READ(GTIMR); | |
193 | } | |
194 | ||
480c8033 | 195 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
196 | { |
197 | ilk_update_gt_irq(dev_priv, mask, mask); | |
198 | } | |
199 | ||
480c8033 | 200 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
201 | { |
202 | ilk_update_gt_irq(dev_priv, mask, 0); | |
203 | } | |
204 | ||
b900b949 ID |
205 | static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) |
206 | { | |
207 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
208 | } | |
209 | ||
a72fbc3a ID |
210 | static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) |
211 | { | |
212 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
213 | } | |
214 | ||
b900b949 ID |
215 | static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) |
216 | { | |
217 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
218 | } | |
219 | ||
edbfdb45 PZ |
220 | /** |
221 | * snb_update_pm_irq - update GEN6_PMIMR | |
222 | * @dev_priv: driver private | |
223 | * @interrupt_mask: mask of interrupt bits to update | |
224 | * @enabled_irq_mask: mask of interrupt bits to enable | |
225 | */ | |
226 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
227 | uint32_t interrupt_mask, | |
228 | uint32_t enabled_irq_mask) | |
229 | { | |
605cd25b | 230 | uint32_t new_val; |
edbfdb45 PZ |
231 | |
232 | assert_spin_locked(&dev_priv->irq_lock); | |
233 | ||
605cd25b | 234 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
235 | new_val &= ~interrupt_mask; |
236 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
237 | ||
605cd25b PZ |
238 | if (new_val != dev_priv->pm_irq_mask) { |
239 | dev_priv->pm_irq_mask = new_val; | |
a72fbc3a ID |
240 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
241 | POSTING_READ(gen6_pm_imr(dev_priv)); | |
f52ecbcf | 242 | } |
edbfdb45 PZ |
243 | } |
244 | ||
480c8033 | 245 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 | 246 | { |
9939fba2 ID |
247 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
248 | return; | |
249 | ||
edbfdb45 PZ |
250 | snb_update_pm_irq(dev_priv, mask, mask); |
251 | } | |
252 | ||
9939fba2 ID |
253 | static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, |
254 | uint32_t mask) | |
edbfdb45 PZ |
255 | { |
256 | snb_update_pm_irq(dev_priv, mask, 0); | |
257 | } | |
258 | ||
9939fba2 ID |
259 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
260 | { | |
261 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
262 | return; | |
263 | ||
264 | __gen6_disable_pm_irq(dev_priv, mask); | |
265 | } | |
266 | ||
3cc134e3 ID |
267 | void gen6_reset_rps_interrupts(struct drm_device *dev) |
268 | { | |
269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
270 | uint32_t reg = gen6_pm_iir(dev_priv); | |
271 | ||
272 | spin_lock_irq(&dev_priv->irq_lock); | |
273 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
274 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
275 | POSTING_READ(reg); | |
276 | spin_unlock_irq(&dev_priv->irq_lock); | |
277 | } | |
278 | ||
b900b949 ID |
279 | void gen6_enable_rps_interrupts(struct drm_device *dev) |
280 | { | |
281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
282 | ||
283 | spin_lock_irq(&dev_priv->irq_lock); | |
284 | WARN_ON(dev_priv->rps.pm_iir); | |
3cc134e3 | 285 | WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
d4d70aa5 | 286 | dev_priv->rps.interrupts_enabled = true; |
b900b949 | 287 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
b900b949 ID |
288 | spin_unlock_irq(&dev_priv->irq_lock); |
289 | } | |
290 | ||
291 | void gen6_disable_rps_interrupts(struct drm_device *dev) | |
292 | { | |
293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
294 | ||
d4d70aa5 ID |
295 | spin_lock_irq(&dev_priv->irq_lock); |
296 | dev_priv->rps.interrupts_enabled = false; | |
297 | spin_unlock_irq(&dev_priv->irq_lock); | |
298 | ||
299 | cancel_work_sync(&dev_priv->rps.work); | |
300 | ||
9939fba2 ID |
301 | spin_lock_irq(&dev_priv->irq_lock); |
302 | ||
b900b949 ID |
303 | I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ? |
304 | ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0); | |
9939fba2 ID |
305 | |
306 | __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
b900b949 ID |
307 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & |
308 | ~dev_priv->pm_rps_events); | |
9939fba2 ID |
309 | I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); |
310 | I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); | |
b900b949 | 311 | |
b900b949 | 312 | dev_priv->rps.pm_iir = 0; |
b900b949 | 313 | |
9939fba2 | 314 | spin_unlock_irq(&dev_priv->irq_lock); |
b900b949 ID |
315 | } |
316 | ||
fee884ed DV |
317 | /** |
318 | * ibx_display_interrupt_update - update SDEIMR | |
319 | * @dev_priv: driver private | |
320 | * @interrupt_mask: mask of interrupt bits to update | |
321 | * @enabled_irq_mask: mask of interrupt bits to enable | |
322 | */ | |
47339cd9 DV |
323 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
324 | uint32_t interrupt_mask, | |
325 | uint32_t enabled_irq_mask) | |
fee884ed DV |
326 | { |
327 | uint32_t sdeimr = I915_READ(SDEIMR); | |
328 | sdeimr &= ~interrupt_mask; | |
329 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
330 | ||
331 | assert_spin_locked(&dev_priv->irq_lock); | |
332 | ||
9df7575f | 333 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 334 | return; |
c67a470b | 335 | |
fee884ed DV |
336 | I915_WRITE(SDEIMR, sdeimr); |
337 | POSTING_READ(SDEIMR); | |
338 | } | |
8664281b | 339 | |
b5ea642a | 340 | static void |
755e9019 ID |
341 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
342 | u32 enable_mask, u32 status_mask) | |
7c463586 | 343 | { |
46c06a30 | 344 | u32 reg = PIPESTAT(pipe); |
755e9019 | 345 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 346 | |
b79480ba | 347 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 348 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 349 | |
04feced9 VS |
350 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
351 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
352 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
353 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
354 | return; |
355 | ||
356 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
357 | return; |
358 | ||
91d181dd ID |
359 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
360 | ||
46c06a30 | 361 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 362 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
363 | I915_WRITE(reg, pipestat); |
364 | POSTING_READ(reg); | |
7c463586 KP |
365 | } |
366 | ||
b5ea642a | 367 | static void |
755e9019 ID |
368 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
369 | u32 enable_mask, u32 status_mask) | |
7c463586 | 370 | { |
46c06a30 | 371 | u32 reg = PIPESTAT(pipe); |
755e9019 | 372 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 373 | |
b79480ba | 374 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 375 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 376 | |
04feced9 VS |
377 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
378 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
379 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
380 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
381 | return; |
382 | ||
755e9019 ID |
383 | if ((pipestat & enable_mask) == 0) |
384 | return; | |
385 | ||
91d181dd ID |
386 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
387 | ||
755e9019 | 388 | pipestat &= ~enable_mask; |
46c06a30 VS |
389 | I915_WRITE(reg, pipestat); |
390 | POSTING_READ(reg); | |
7c463586 KP |
391 | } |
392 | ||
10c59c51 ID |
393 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
394 | { | |
395 | u32 enable_mask = status_mask << 16; | |
396 | ||
397 | /* | |
724a6905 VS |
398 | * On pipe A we don't support the PSR interrupt yet, |
399 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
400 | */ |
401 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
402 | return 0; | |
724a6905 VS |
403 | /* |
404 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
405 | * A the same bit is for perf counters which we don't use either. | |
406 | */ | |
407 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
408 | return 0; | |
10c59c51 ID |
409 | |
410 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
411 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
412 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
413 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
414 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
415 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
416 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
417 | ||
418 | return enable_mask; | |
419 | } | |
420 | ||
755e9019 ID |
421 | void |
422 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
423 | u32 status_mask) | |
424 | { | |
425 | u32 enable_mask; | |
426 | ||
10c59c51 ID |
427 | if (IS_VALLEYVIEW(dev_priv->dev)) |
428 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
429 | status_mask); | |
430 | else | |
431 | enable_mask = status_mask << 16; | |
755e9019 ID |
432 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
433 | } | |
434 | ||
435 | void | |
436 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
437 | u32 status_mask) | |
438 | { | |
439 | u32 enable_mask; | |
440 | ||
10c59c51 ID |
441 | if (IS_VALLEYVIEW(dev_priv->dev)) |
442 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
443 | status_mask); | |
444 | else | |
445 | enable_mask = status_mask << 16; | |
755e9019 ID |
446 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
447 | } | |
448 | ||
01c66889 | 449 | /** |
f49e38dd | 450 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 451 | */ |
f49e38dd | 452 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 453 | { |
2d1013dd | 454 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 455 | |
f49e38dd JN |
456 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
457 | return; | |
458 | ||
13321786 | 459 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 460 | |
755e9019 | 461 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 462 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 463 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 464 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 465 | |
13321786 | 466 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
467 | } |
468 | ||
0a3e67a4 JB |
469 | /** |
470 | * i915_pipe_enabled - check if a pipe is enabled | |
471 | * @dev: DRM device | |
472 | * @pipe: pipe to check | |
473 | * | |
474 | * Reading certain registers when the pipe is disabled can hang the chip. | |
475 | * Use this routine to make sure the PLL is running and the pipe is active | |
476 | * before reading such registers if unsure. | |
477 | */ | |
478 | static int | |
479 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
480 | { | |
2d1013dd | 481 | struct drm_i915_private *dev_priv = dev->dev_private; |
702e7a56 | 482 | |
a01025af DV |
483 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
484 | /* Locking is horribly broken here, but whatever. */ | |
485 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
486 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 487 | |
a01025af DV |
488 | return intel_crtc->active; |
489 | } else { | |
490 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
491 | } | |
0a3e67a4 JB |
492 | } |
493 | ||
f75f3746 VS |
494 | /* |
495 | * This timing diagram depicts the video signal in and | |
496 | * around the vertical blanking period. | |
497 | * | |
498 | * Assumptions about the fictitious mode used in this example: | |
499 | * vblank_start >= 3 | |
500 | * vsync_start = vblank_start + 1 | |
501 | * vsync_end = vblank_start + 2 | |
502 | * vtotal = vblank_start + 3 | |
503 | * | |
504 | * start of vblank: | |
505 | * latch double buffered registers | |
506 | * increment frame counter (ctg+) | |
507 | * generate start of vblank interrupt (gen4+) | |
508 | * | | |
509 | * | frame start: | |
510 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
511 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
512 | * | | | |
513 | * | | start of vsync: | |
514 | * | | generate vsync interrupt | |
515 | * | | | | |
516 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
517 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
518 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
519 | * | | <----vs-----> | | |
520 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
521 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
522 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
523 | * | | | | |
524 | * last visible pixel first visible pixel | |
525 | * | increment frame counter (gen3/4) | |
526 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
527 | * | |
528 | * x = horizontal active | |
529 | * _ = horizontal blanking | |
530 | * hs = horizontal sync | |
531 | * va = vertical active | |
532 | * vb = vertical blanking | |
533 | * vs = vertical sync | |
534 | * vbs = vblank_start (number) | |
535 | * | |
536 | * Summary: | |
537 | * - most events happen at the start of horizontal sync | |
538 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
539 | * (depending on PIPECONF settings) after the start of vblank | |
540 | * - gen3/4 pixel and frame counter are synchronized with the start | |
541 | * of horizontal active on the first line of vertical active | |
542 | */ | |
543 | ||
4cdb83ec VS |
544 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
545 | { | |
546 | /* Gen2 doesn't have a hardware frame counter */ | |
547 | return 0; | |
548 | } | |
549 | ||
42f52ef8 KP |
550 | /* Called from drm generic code, passed a 'crtc', which |
551 | * we use as a pipe index | |
552 | */ | |
f71d4af4 | 553 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 554 | { |
2d1013dd | 555 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
556 | unsigned long high_frame; |
557 | unsigned long low_frame; | |
0b2a8e09 | 558 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
0a3e67a4 JB |
559 | |
560 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 561 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 562 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
563 | return 0; |
564 | } | |
565 | ||
391f75e2 VS |
566 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
567 | struct intel_crtc *intel_crtc = | |
568 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
569 | const struct drm_display_mode *mode = | |
570 | &intel_crtc->config.adjusted_mode; | |
571 | ||
0b2a8e09 VS |
572 | htotal = mode->crtc_htotal; |
573 | hsync_start = mode->crtc_hsync_start; | |
574 | vbl_start = mode->crtc_vblank_start; | |
575 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
576 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 577 | } else { |
a2d213dd | 578 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
391f75e2 VS |
579 | |
580 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
0b2a8e09 | 581 | hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1; |
391f75e2 | 582 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; |
0b2a8e09 VS |
583 | if ((I915_READ(PIPECONF(cpu_transcoder)) & |
584 | PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE) | |
585 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 VS |
586 | } |
587 | ||
0b2a8e09 VS |
588 | /* Convert to pixel count */ |
589 | vbl_start *= htotal; | |
590 | ||
591 | /* Start of vblank event occurs at start of hsync */ | |
592 | vbl_start -= htotal - hsync_start; | |
593 | ||
9db4a9c7 JB |
594 | high_frame = PIPEFRAME(pipe); |
595 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 596 | |
0a3e67a4 JB |
597 | /* |
598 | * High & low register fields aren't synchronized, so make sure | |
599 | * we get a low value that's stable across two reads of the high | |
600 | * register. | |
601 | */ | |
602 | do { | |
5eddb70b | 603 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 604 | low = I915_READ(low_frame); |
5eddb70b | 605 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
606 | } while (high1 != high2); |
607 | ||
5eddb70b | 608 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 609 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 610 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
611 | |
612 | /* | |
613 | * The frame counter increments at beginning of active. | |
614 | * Cook up a vblank counter by also checking the pixel | |
615 | * counter against vblank start. | |
616 | */ | |
edc08d0a | 617 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
618 | } |
619 | ||
f71d4af4 | 620 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 621 | { |
2d1013dd | 622 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 623 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
624 | |
625 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 626 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 627 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
628 | return 0; |
629 | } | |
630 | ||
631 | return I915_READ(reg); | |
632 | } | |
633 | ||
ad3543ed MK |
634 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
635 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 636 | |
a225f079 VS |
637 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
638 | { | |
639 | struct drm_device *dev = crtc->base.dev; | |
640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
641 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
642 | enum pipe pipe = crtc->pipe; | |
80715b2f | 643 | int position, vtotal; |
a225f079 | 644 | |
80715b2f | 645 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
646 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
647 | vtotal /= 2; | |
648 | ||
649 | if (IS_GEN2(dev)) | |
650 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
651 | else | |
652 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
653 | ||
654 | /* | |
80715b2f VS |
655 | * See update_scanline_offset() for the details on the |
656 | * scanline_offset adjustment. | |
a225f079 | 657 | */ |
80715b2f | 658 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
659 | } |
660 | ||
f71d4af4 | 661 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
662 | unsigned int flags, int *vpos, int *hpos, |
663 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 664 | { |
c2baf4b7 VS |
665 | struct drm_i915_private *dev_priv = dev->dev_private; |
666 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
667 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
668 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 669 | int position; |
78e8fc6b | 670 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
671 | bool in_vbl = true; |
672 | int ret = 0; | |
ad3543ed | 673 | unsigned long irqflags; |
0af7e4df | 674 | |
c2baf4b7 | 675 | if (!intel_crtc->active) { |
0af7e4df | 676 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 677 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
678 | return 0; |
679 | } | |
680 | ||
c2baf4b7 | 681 | htotal = mode->crtc_htotal; |
78e8fc6b | 682 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
683 | vtotal = mode->crtc_vtotal; |
684 | vbl_start = mode->crtc_vblank_start; | |
685 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 686 | |
d31faf65 VS |
687 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
688 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
689 | vbl_end /= 2; | |
690 | vtotal /= 2; | |
691 | } | |
692 | ||
c2baf4b7 VS |
693 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
694 | ||
ad3543ed MK |
695 | /* |
696 | * Lock uncore.lock, as we will do multiple timing critical raw | |
697 | * register reads, potentially with preemption disabled, so the | |
698 | * following code must not block on uncore.lock. | |
699 | */ | |
700 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 701 | |
ad3543ed MK |
702 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
703 | ||
704 | /* Get optional system timestamp before query. */ | |
705 | if (stime) | |
706 | *stime = ktime_get(); | |
707 | ||
7c06b08a | 708 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
709 | /* No obvious pixelcount register. Only query vertical |
710 | * scanout position from Display scan line register. | |
711 | */ | |
a225f079 | 712 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
713 | } else { |
714 | /* Have access to pixelcount since start of frame. | |
715 | * We can split this into vertical and horizontal | |
716 | * scanout position. | |
717 | */ | |
ad3543ed | 718 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 719 | |
3aa18df8 VS |
720 | /* convert to pixel counts */ |
721 | vbl_start *= htotal; | |
722 | vbl_end *= htotal; | |
723 | vtotal *= htotal; | |
78e8fc6b | 724 | |
7e78f1cb VS |
725 | /* |
726 | * In interlaced modes, the pixel counter counts all pixels, | |
727 | * so one field will have htotal more pixels. In order to avoid | |
728 | * the reported position from jumping backwards when the pixel | |
729 | * counter is beyond the length of the shorter field, just | |
730 | * clamp the position the length of the shorter field. This | |
731 | * matches how the scanline counter based position works since | |
732 | * the scanline counter doesn't count the two half lines. | |
733 | */ | |
734 | if (position >= vtotal) | |
735 | position = vtotal - 1; | |
736 | ||
78e8fc6b VS |
737 | /* |
738 | * Start of vblank interrupt is triggered at start of hsync, | |
739 | * just prior to the first active line of vblank. However we | |
740 | * consider lines to start at the leading edge of horizontal | |
741 | * active. So, should we get here before we've crossed into | |
742 | * the horizontal active of the first line in vblank, we would | |
743 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
744 | * always add htotal-hsync_start to the current pixel position. | |
745 | */ | |
746 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
747 | } |
748 | ||
ad3543ed MK |
749 | /* Get optional system timestamp after query. */ |
750 | if (etime) | |
751 | *etime = ktime_get(); | |
752 | ||
753 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
754 | ||
755 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
756 | ||
3aa18df8 VS |
757 | in_vbl = position >= vbl_start && position < vbl_end; |
758 | ||
759 | /* | |
760 | * While in vblank, position will be negative | |
761 | * counting up towards 0 at vbl_end. And outside | |
762 | * vblank, position will be positive counting | |
763 | * up since vbl_end. | |
764 | */ | |
765 | if (position >= vbl_start) | |
766 | position -= vbl_end; | |
767 | else | |
768 | position += vtotal - vbl_end; | |
0af7e4df | 769 | |
7c06b08a | 770 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
771 | *vpos = position; |
772 | *hpos = 0; | |
773 | } else { | |
774 | *vpos = position / htotal; | |
775 | *hpos = position - (*vpos * htotal); | |
776 | } | |
0af7e4df | 777 | |
0af7e4df MK |
778 | /* In vblank? */ |
779 | if (in_vbl) | |
3d3cbd84 | 780 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
781 | |
782 | return ret; | |
783 | } | |
784 | ||
a225f079 VS |
785 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
786 | { | |
787 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
788 | unsigned long irqflags; | |
789 | int position; | |
790 | ||
791 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
792 | position = __intel_get_crtc_scanline(crtc); | |
793 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
794 | ||
795 | return position; | |
796 | } | |
797 | ||
f71d4af4 | 798 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
799 | int *max_error, |
800 | struct timeval *vblank_time, | |
801 | unsigned flags) | |
802 | { | |
4041b853 | 803 | struct drm_crtc *crtc; |
0af7e4df | 804 | |
7eb552ae | 805 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 806 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
807 | return -EINVAL; |
808 | } | |
809 | ||
810 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
811 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
812 | if (crtc == NULL) { | |
813 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
814 | return -EINVAL; | |
815 | } | |
816 | ||
817 | if (!crtc->enabled) { | |
818 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
819 | return -EBUSY; | |
820 | } | |
0af7e4df MK |
821 | |
822 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
823 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
824 | vblank_time, flags, | |
7da903ef VS |
825 | crtc, |
826 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
827 | } |
828 | ||
67c347ff JN |
829 | static bool intel_hpd_irq_event(struct drm_device *dev, |
830 | struct drm_connector *connector) | |
321a1b30 EE |
831 | { |
832 | enum drm_connector_status old_status; | |
833 | ||
834 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
835 | old_status = connector->status; | |
836 | ||
837 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
838 | if (old_status == connector->status) |
839 | return false; | |
840 | ||
841 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 | 842 | connector->base.id, |
c23cc417 | 843 | connector->name, |
67c347ff JN |
844 | drm_get_connector_status_name(old_status), |
845 | drm_get_connector_status_name(connector->status)); | |
846 | ||
847 | return true; | |
321a1b30 EE |
848 | } |
849 | ||
13cf5504 DA |
850 | static void i915_digport_work_func(struct work_struct *work) |
851 | { | |
852 | struct drm_i915_private *dev_priv = | |
853 | container_of(work, struct drm_i915_private, dig_port_work); | |
13cf5504 DA |
854 | u32 long_port_mask, short_port_mask; |
855 | struct intel_digital_port *intel_dig_port; | |
856 | int i, ret; | |
857 | u32 old_bits = 0; | |
858 | ||
4cb21832 | 859 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
860 | long_port_mask = dev_priv->long_hpd_port_mask; |
861 | dev_priv->long_hpd_port_mask = 0; | |
862 | short_port_mask = dev_priv->short_hpd_port_mask; | |
863 | dev_priv->short_hpd_port_mask = 0; | |
4cb21832 | 864 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
865 | |
866 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
867 | bool valid = false; | |
868 | bool long_hpd = false; | |
869 | intel_dig_port = dev_priv->hpd_irq_port[i]; | |
870 | if (!intel_dig_port || !intel_dig_port->hpd_pulse) | |
871 | continue; | |
872 | ||
873 | if (long_port_mask & (1 << i)) { | |
874 | valid = true; | |
875 | long_hpd = true; | |
876 | } else if (short_port_mask & (1 << i)) | |
877 | valid = true; | |
878 | ||
879 | if (valid) { | |
880 | ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd); | |
881 | if (ret == true) { | |
882 | /* if we get true fallback to old school hpd */ | |
883 | old_bits |= (1 << intel_dig_port->base.hpd_pin); | |
884 | } | |
885 | } | |
886 | } | |
887 | ||
888 | if (old_bits) { | |
4cb21832 | 889 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 | 890 | dev_priv->hpd_event_bits |= old_bits; |
4cb21832 | 891 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
892 | schedule_work(&dev_priv->hotplug_work); |
893 | } | |
894 | } | |
895 | ||
5ca58282 JB |
896 | /* |
897 | * Handle hotplug events outside the interrupt handler proper. | |
898 | */ | |
ac4c16c5 EE |
899 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
900 | ||
5ca58282 JB |
901 | static void i915_hotplug_work_func(struct work_struct *work) |
902 | { | |
2d1013dd JN |
903 | struct drm_i915_private *dev_priv = |
904 | container_of(work, struct drm_i915_private, hotplug_work); | |
5ca58282 | 905 | struct drm_device *dev = dev_priv->dev; |
c31c4ba3 | 906 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
907 | struct intel_connector *intel_connector; |
908 | struct intel_encoder *intel_encoder; | |
909 | struct drm_connector *connector; | |
cd569aed | 910 | bool hpd_disabled = false; |
321a1b30 | 911 | bool changed = false; |
142e2398 | 912 | u32 hpd_event_bits; |
4ef69c7a | 913 | |
a65e34c7 | 914 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
915 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
916 | ||
4cb21832 | 917 | spin_lock_irq(&dev_priv->irq_lock); |
142e2398 EE |
918 | |
919 | hpd_event_bits = dev_priv->hpd_event_bits; | |
920 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
921 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
922 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
923 | if (!intel_connector->encoder) |
924 | continue; | |
cd569aed EE |
925 | intel_encoder = intel_connector->encoder; |
926 | if (intel_encoder->hpd_pin > HPD_NONE && | |
927 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
928 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
929 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
930 | "switching from hotplug detection to polling\n", | |
c23cc417 | 931 | connector->name); |
cd569aed EE |
932 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; |
933 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
934 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
935 | hpd_disabled = true; | |
936 | } | |
142e2398 EE |
937 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
938 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
c23cc417 | 939 | connector->name, intel_encoder->hpd_pin); |
142e2398 | 940 | } |
cd569aed EE |
941 | } |
942 | /* if there were no outputs to poll, poll was disabled, | |
943 | * therefore make sure it's enabled when disabling HPD on | |
944 | * some connectors */ | |
ac4c16c5 | 945 | if (hpd_disabled) { |
cd569aed | 946 | drm_kms_helper_poll_enable(dev); |
6323751d ID |
947 | mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work, |
948 | msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
ac4c16c5 | 949 | } |
cd569aed | 950 | |
4cb21832 | 951 | spin_unlock_irq(&dev_priv->irq_lock); |
cd569aed | 952 | |
321a1b30 EE |
953 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
954 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
955 | if (!intel_connector->encoder) |
956 | continue; | |
321a1b30 EE |
957 | intel_encoder = intel_connector->encoder; |
958 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
959 | if (intel_encoder->hot_plug) | |
960 | intel_encoder->hot_plug(intel_encoder); | |
961 | if (intel_hpd_irq_event(dev, connector)) | |
962 | changed = true; | |
963 | } | |
964 | } | |
40ee3381 KP |
965 | mutex_unlock(&mode_config->mutex); |
966 | ||
321a1b30 EE |
967 | if (changed) |
968 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
969 | } |
970 | ||
d0ecd7e2 | 971 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 972 | { |
2d1013dd | 973 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 974 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 975 | u8 new_delay; |
9270388e | 976 | |
d0ecd7e2 | 977 | spin_lock(&mchdev_lock); |
f97108d1 | 978 | |
73edd18f DV |
979 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
980 | ||
20e4d407 | 981 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 982 | |
7648fa99 | 983 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
984 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
985 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
986 | max_avg = I915_READ(RCBMAXAVG); |
987 | min_avg = I915_READ(RCBMINAVG); | |
988 | ||
989 | /* Handle RCS change request from hw */ | |
b5b72e89 | 990 | if (busy_up > max_avg) { |
20e4d407 DV |
991 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
992 | new_delay = dev_priv->ips.cur_delay - 1; | |
993 | if (new_delay < dev_priv->ips.max_delay) | |
994 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 995 | } else if (busy_down < min_avg) { |
20e4d407 DV |
996 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
997 | new_delay = dev_priv->ips.cur_delay + 1; | |
998 | if (new_delay > dev_priv->ips.min_delay) | |
999 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
1000 | } |
1001 | ||
7648fa99 | 1002 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 1003 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 1004 | |
d0ecd7e2 | 1005 | spin_unlock(&mchdev_lock); |
9270388e | 1006 | |
f97108d1 JB |
1007 | return; |
1008 | } | |
1009 | ||
549f7365 | 1010 | static void notify_ring(struct drm_device *dev, |
a4872ba6 | 1011 | struct intel_engine_cs *ring) |
549f7365 | 1012 | { |
93b0a4e0 | 1013 | if (!intel_ring_initialized(ring)) |
475553de CW |
1014 | return; |
1015 | ||
814e9b57 | 1016 | trace_i915_gem_request_complete(ring); |
9862e600 | 1017 | |
549f7365 | 1018 | wake_up_all(&ring->irq_queue); |
549f7365 CW |
1019 | } |
1020 | ||
31685c25 | 1021 | static u32 vlv_c0_residency(struct drm_i915_private *dev_priv, |
bf225f20 | 1022 | struct intel_rps_ei *rps_ei) |
31685c25 D |
1023 | { |
1024 | u32 cz_ts, cz_freq_khz; | |
1025 | u32 render_count, media_count; | |
1026 | u32 elapsed_render, elapsed_media, elapsed_time; | |
1027 | u32 residency = 0; | |
1028 | ||
1029 | cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); | |
1030 | cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4); | |
1031 | ||
1032 | render_count = I915_READ(VLV_RENDER_C0_COUNT_REG); | |
1033 | media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG); | |
1034 | ||
bf225f20 CW |
1035 | if (rps_ei->cz_clock == 0) { |
1036 | rps_ei->cz_clock = cz_ts; | |
1037 | rps_ei->render_c0 = render_count; | |
1038 | rps_ei->media_c0 = media_count; | |
31685c25 D |
1039 | |
1040 | return dev_priv->rps.cur_freq; | |
1041 | } | |
1042 | ||
bf225f20 CW |
1043 | elapsed_time = cz_ts - rps_ei->cz_clock; |
1044 | rps_ei->cz_clock = cz_ts; | |
31685c25 | 1045 | |
bf225f20 CW |
1046 | elapsed_render = render_count - rps_ei->render_c0; |
1047 | rps_ei->render_c0 = render_count; | |
31685c25 | 1048 | |
bf225f20 CW |
1049 | elapsed_media = media_count - rps_ei->media_c0; |
1050 | rps_ei->media_c0 = media_count; | |
31685c25 D |
1051 | |
1052 | /* Convert all the counters into common unit of milli sec */ | |
1053 | elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC; | |
1054 | elapsed_render /= cz_freq_khz; | |
1055 | elapsed_media /= cz_freq_khz; | |
1056 | ||
1057 | /* | |
1058 | * Calculate overall C0 residency percentage | |
1059 | * only if elapsed time is non zero | |
1060 | */ | |
1061 | if (elapsed_time) { | |
1062 | residency = | |
1063 | ((max(elapsed_render, elapsed_media) * 100) | |
1064 | / elapsed_time); | |
1065 | } | |
1066 | ||
1067 | return residency; | |
1068 | } | |
1069 | ||
1070 | /** | |
1071 | * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU | |
1072 | * busy-ness calculated from C0 counters of render & media power wells | |
1073 | * @dev_priv: DRM device private | |
1074 | * | |
1075 | */ | |
4fa79042 | 1076 | static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv) |
31685c25 D |
1077 | { |
1078 | u32 residency_C0_up = 0, residency_C0_down = 0; | |
4fa79042 | 1079 | int new_delay, adj; |
31685c25 D |
1080 | |
1081 | dev_priv->rps.ei_interrupt_count++; | |
1082 | ||
1083 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
1084 | ||
1085 | ||
bf225f20 CW |
1086 | if (dev_priv->rps.up_ei.cz_clock == 0) { |
1087 | vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei); | |
1088 | vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei); | |
31685c25 D |
1089 | return dev_priv->rps.cur_freq; |
1090 | } | |
1091 | ||
1092 | ||
1093 | /* | |
1094 | * To down throttle, C0 residency should be less than down threshold | |
1095 | * for continous EI intervals. So calculate down EI counters | |
1096 | * once in VLV_INT_COUNT_FOR_DOWN_EI | |
1097 | */ | |
1098 | if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) { | |
1099 | ||
1100 | dev_priv->rps.ei_interrupt_count = 0; | |
1101 | ||
1102 | residency_C0_down = vlv_c0_residency(dev_priv, | |
bf225f20 | 1103 | &dev_priv->rps.down_ei); |
31685c25 D |
1104 | } else { |
1105 | residency_C0_up = vlv_c0_residency(dev_priv, | |
bf225f20 | 1106 | &dev_priv->rps.up_ei); |
31685c25 D |
1107 | } |
1108 | ||
1109 | new_delay = dev_priv->rps.cur_freq; | |
1110 | ||
1111 | adj = dev_priv->rps.last_adj; | |
1112 | /* C0 residency is greater than UP threshold. Increase Frequency */ | |
1113 | if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) { | |
1114 | if (adj > 0) | |
1115 | adj *= 2; | |
1116 | else | |
1117 | adj = 1; | |
1118 | ||
1119 | if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit) | |
1120 | new_delay = dev_priv->rps.cur_freq + adj; | |
1121 | ||
1122 | /* | |
1123 | * For better performance, jump directly | |
1124 | * to RPe if we're below it. | |
1125 | */ | |
1126 | if (new_delay < dev_priv->rps.efficient_freq) | |
1127 | new_delay = dev_priv->rps.efficient_freq; | |
1128 | ||
1129 | } else if (!dev_priv->rps.ei_interrupt_count && | |
1130 | (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) { | |
1131 | if (adj < 0) | |
1132 | adj *= 2; | |
1133 | else | |
1134 | adj = -1; | |
1135 | /* | |
1136 | * This means, C0 residency is less than down threshold over | |
1137 | * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq | |
1138 | */ | |
1139 | if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit) | |
1140 | new_delay = dev_priv->rps.cur_freq + adj; | |
1141 | } | |
1142 | ||
1143 | return new_delay; | |
1144 | } | |
1145 | ||
4912d041 | 1146 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1147 | { |
2d1013dd JN |
1148 | struct drm_i915_private *dev_priv = |
1149 | container_of(work, struct drm_i915_private, rps.work); | |
edbfdb45 | 1150 | u32 pm_iir; |
dd75fdc8 | 1151 | int new_delay, adj; |
4912d041 | 1152 | |
59cdb63d | 1153 | spin_lock_irq(&dev_priv->irq_lock); |
d4d70aa5 ID |
1154 | /* Speed up work cancelation during disabling rps interrupts. */ |
1155 | if (!dev_priv->rps.interrupts_enabled) { | |
1156 | spin_unlock_irq(&dev_priv->irq_lock); | |
1157 | return; | |
1158 | } | |
c6a828d3 DV |
1159 | pm_iir = dev_priv->rps.pm_iir; |
1160 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a ID |
1161 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
1162 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
59cdb63d | 1163 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1164 | |
60611c13 | 1165 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1166 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1167 | |
a6706b45 | 1168 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
3b8d8d91 JB |
1169 | return; |
1170 | ||
4fc688ce | 1171 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1172 | |
dd75fdc8 | 1173 | adj = dev_priv->rps.last_adj; |
7425034a | 1174 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1175 | if (adj > 0) |
1176 | adj *= 2; | |
13a5660c D |
1177 | else { |
1178 | /* CHV needs even encode values */ | |
1179 | adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1; | |
1180 | } | |
b39fb297 | 1181 | new_delay = dev_priv->rps.cur_freq + adj; |
7425034a VS |
1182 | |
1183 | /* | |
1184 | * For better performance, jump directly | |
1185 | * to RPe if we're below it. | |
1186 | */ | |
b39fb297 BW |
1187 | if (new_delay < dev_priv->rps.efficient_freq) |
1188 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1189 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1190 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1191 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1192 | else |
b39fb297 | 1193 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 | 1194 | adj = 0; |
31685c25 D |
1195 | } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1196 | new_delay = vlv_calc_delay_from_C0_counters(dev_priv); | |
dd75fdc8 CW |
1197 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { |
1198 | if (adj < 0) | |
1199 | adj *= 2; | |
13a5660c D |
1200 | else { |
1201 | /* CHV needs even encode values */ | |
1202 | adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1; | |
1203 | } | |
b39fb297 | 1204 | new_delay = dev_priv->rps.cur_freq + adj; |
dd75fdc8 | 1205 | } else { /* unknown event */ |
b39fb297 | 1206 | new_delay = dev_priv->rps.cur_freq; |
dd75fdc8 | 1207 | } |
3b8d8d91 | 1208 | |
79249636 BW |
1209 | /* sysfs frequency interfaces may have snuck in while servicing the |
1210 | * interrupt | |
1211 | */ | |
1272e7b8 | 1212 | new_delay = clamp_t(int, new_delay, |
b39fb297 BW |
1213 | dev_priv->rps.min_freq_softlimit, |
1214 | dev_priv->rps.max_freq_softlimit); | |
27544369 | 1215 | |
b39fb297 | 1216 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
dd75fdc8 CW |
1217 | |
1218 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1219 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1220 | else | |
1221 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1222 | |
4fc688ce | 1223 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1224 | } |
1225 | ||
e3689190 BW |
1226 | |
1227 | /** | |
1228 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1229 | * occurred. | |
1230 | * @work: workqueue struct | |
1231 | * | |
1232 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1233 | * this event, userspace should try to remap the bad rows since statistically | |
1234 | * it is likely the same row is more likely to go bad again. | |
1235 | */ | |
1236 | static void ivybridge_parity_work(struct work_struct *work) | |
1237 | { | |
2d1013dd JN |
1238 | struct drm_i915_private *dev_priv = |
1239 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1240 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1241 | char *parity_event[6]; |
e3689190 | 1242 | uint32_t misccpctl; |
35a85ac6 | 1243 | uint8_t slice = 0; |
e3689190 BW |
1244 | |
1245 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1246 | * In order to prevent a get/put style interface, acquire struct mutex | |
1247 | * any time we access those registers. | |
1248 | */ | |
1249 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1250 | ||
35a85ac6 BW |
1251 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1252 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1253 | goto out; | |
1254 | ||
e3689190 BW |
1255 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1256 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1257 | POSTING_READ(GEN7_MISCCPCTL); | |
1258 | ||
35a85ac6 BW |
1259 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1260 | u32 reg; | |
e3689190 | 1261 | |
35a85ac6 BW |
1262 | slice--; |
1263 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1264 | break; | |
e3689190 | 1265 | |
35a85ac6 | 1266 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1267 | |
35a85ac6 | 1268 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1269 | |
35a85ac6 BW |
1270 | error_status = I915_READ(reg); |
1271 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1272 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1273 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1274 | ||
1275 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1276 | POSTING_READ(reg); | |
1277 | ||
1278 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1279 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1280 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1281 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1282 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1283 | parity_event[5] = NULL; | |
1284 | ||
5bdebb18 | 1285 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1286 | KOBJ_CHANGE, parity_event); |
e3689190 | 1287 | |
35a85ac6 BW |
1288 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1289 | slice, row, bank, subbank); | |
e3689190 | 1290 | |
35a85ac6 BW |
1291 | kfree(parity_event[4]); |
1292 | kfree(parity_event[3]); | |
1293 | kfree(parity_event[2]); | |
1294 | kfree(parity_event[1]); | |
1295 | } | |
e3689190 | 1296 | |
35a85ac6 | 1297 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1298 | |
35a85ac6 BW |
1299 | out: |
1300 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1301 | spin_lock_irq(&dev_priv->irq_lock); |
480c8033 | 1302 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
4cb21832 | 1303 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1304 | |
1305 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1306 | } |
1307 | ||
35a85ac6 | 1308 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1309 | { |
2d1013dd | 1310 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1311 | |
040d2baa | 1312 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1313 | return; |
1314 | ||
d0ecd7e2 | 1315 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1316 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1317 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1318 | |
35a85ac6 BW |
1319 | iir &= GT_PARITY_ERROR(dev); |
1320 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1321 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1322 | ||
1323 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1324 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1325 | ||
a4da4fa4 | 1326 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1327 | } |
1328 | ||
f1af8fc1 PZ |
1329 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1330 | struct drm_i915_private *dev_priv, | |
1331 | u32 gt_iir) | |
1332 | { | |
1333 | if (gt_iir & | |
1334 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1335 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1336 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1337 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1338 | } | |
1339 | ||
e7b4c6b1 DV |
1340 | static void snb_gt_irq_handler(struct drm_device *dev, |
1341 | struct drm_i915_private *dev_priv, | |
1342 | u32 gt_iir) | |
1343 | { | |
1344 | ||
cc609d5d BW |
1345 | if (gt_iir & |
1346 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1347 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1348 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1349 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1350 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1351 | notify_ring(dev, &dev_priv->ring[BCS]); |
1352 | ||
cc609d5d BW |
1353 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1354 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1355 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1356 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1357 | |
35a85ac6 BW |
1358 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1359 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1360 | } |
1361 | ||
abd58f01 BW |
1362 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1363 | struct drm_i915_private *dev_priv, | |
1364 | u32 master_ctl) | |
1365 | { | |
e981e7b1 | 1366 | struct intel_engine_cs *ring; |
abd58f01 BW |
1367 | u32 rcs, bcs, vcs; |
1368 | uint32_t tmp = 0; | |
1369 | irqreturn_t ret = IRQ_NONE; | |
1370 | ||
1371 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1372 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1373 | if (tmp) { | |
38cc46d7 | 1374 | I915_WRITE(GEN8_GT_IIR(0), tmp); |
abd58f01 | 1375 | ret = IRQ_HANDLED; |
e981e7b1 | 1376 | |
abd58f01 | 1377 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; |
e981e7b1 | 1378 | ring = &dev_priv->ring[RCS]; |
abd58f01 | 1379 | if (rcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 TD |
1380 | notify_ring(dev, ring); |
1381 | if (rcs & GT_CONTEXT_SWITCH_INTERRUPT) | |
1382 | intel_execlists_handle_ctx_events(ring); | |
1383 | ||
1384 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1385 | ring = &dev_priv->ring[BCS]; | |
abd58f01 | 1386 | if (bcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 TD |
1387 | notify_ring(dev, ring); |
1388 | if (bcs & GT_CONTEXT_SWITCH_INTERRUPT) | |
1389 | intel_execlists_handle_ctx_events(ring); | |
abd58f01 BW |
1390 | } else |
1391 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1392 | } | |
1393 | ||
85f9b5f9 | 1394 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
abd58f01 BW |
1395 | tmp = I915_READ(GEN8_GT_IIR(1)); |
1396 | if (tmp) { | |
38cc46d7 | 1397 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
abd58f01 | 1398 | ret = IRQ_HANDLED; |
e981e7b1 | 1399 | |
abd58f01 | 1400 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; |
e981e7b1 | 1401 | ring = &dev_priv->ring[VCS]; |
abd58f01 | 1402 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1403 | notify_ring(dev, ring); |
73d477f6 | 1404 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 TD |
1405 | intel_execlists_handle_ctx_events(ring); |
1406 | ||
85f9b5f9 | 1407 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
e981e7b1 | 1408 | ring = &dev_priv->ring[VCS2]; |
85f9b5f9 | 1409 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1410 | notify_ring(dev, ring); |
73d477f6 | 1411 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 | 1412 | intel_execlists_handle_ctx_events(ring); |
abd58f01 BW |
1413 | } else |
1414 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1415 | } | |
1416 | ||
0961021a BW |
1417 | if (master_ctl & GEN8_GT_PM_IRQ) { |
1418 | tmp = I915_READ(GEN8_GT_IIR(2)); | |
1419 | if (tmp & dev_priv->pm_rps_events) { | |
0961021a BW |
1420 | I915_WRITE(GEN8_GT_IIR(2), |
1421 | tmp & dev_priv->pm_rps_events); | |
38cc46d7 | 1422 | ret = IRQ_HANDLED; |
c9a9a268 | 1423 | gen6_rps_irq_handler(dev_priv, tmp); |
0961021a BW |
1424 | } else |
1425 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1426 | } | |
1427 | ||
abd58f01 BW |
1428 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
1429 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1430 | if (tmp) { | |
38cc46d7 | 1431 | I915_WRITE(GEN8_GT_IIR(3), tmp); |
abd58f01 | 1432 | ret = IRQ_HANDLED; |
e981e7b1 | 1433 | |
abd58f01 | 1434 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; |
e981e7b1 | 1435 | ring = &dev_priv->ring[VECS]; |
abd58f01 | 1436 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1437 | notify_ring(dev, ring); |
73d477f6 | 1438 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 | 1439 | intel_execlists_handle_ctx_events(ring); |
abd58f01 BW |
1440 | } else |
1441 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1442 | } | |
1443 | ||
1444 | return ret; | |
1445 | } | |
1446 | ||
b543fb04 EE |
1447 | #define HPD_STORM_DETECT_PERIOD 1000 |
1448 | #define HPD_STORM_THRESHOLD 5 | |
1449 | ||
07c338ce | 1450 | static int pch_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1451 | { |
1452 | switch (port) { | |
1453 | case PORT_A: | |
1454 | case PORT_E: | |
1455 | default: | |
1456 | return -1; | |
1457 | case PORT_B: | |
1458 | return 0; | |
1459 | case PORT_C: | |
1460 | return 8; | |
1461 | case PORT_D: | |
1462 | return 16; | |
1463 | } | |
1464 | } | |
1465 | ||
07c338ce | 1466 | static int i915_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1467 | { |
1468 | switch (port) { | |
1469 | case PORT_A: | |
1470 | case PORT_E: | |
1471 | default: | |
1472 | return -1; | |
1473 | case PORT_B: | |
1474 | return 17; | |
1475 | case PORT_C: | |
1476 | return 19; | |
1477 | case PORT_D: | |
1478 | return 21; | |
1479 | } | |
1480 | } | |
1481 | ||
1482 | static inline enum port get_port_from_pin(enum hpd_pin pin) | |
1483 | { | |
1484 | switch (pin) { | |
1485 | case HPD_PORT_B: | |
1486 | return PORT_B; | |
1487 | case HPD_PORT_C: | |
1488 | return PORT_C; | |
1489 | case HPD_PORT_D: | |
1490 | return PORT_D; | |
1491 | default: | |
1492 | return PORT_A; /* no hpd */ | |
1493 | } | |
1494 | } | |
1495 | ||
10a504de | 1496 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba | 1497 | u32 hotplug_trigger, |
13cf5504 | 1498 | u32 dig_hotplug_reg, |
22062dba | 1499 | const u32 *hpd) |
b543fb04 | 1500 | { |
2d1013dd | 1501 | struct drm_i915_private *dev_priv = dev->dev_private; |
b543fb04 | 1502 | int i; |
13cf5504 | 1503 | enum port port; |
10a504de | 1504 | bool storm_detected = false; |
13cf5504 DA |
1505 | bool queue_dig = false, queue_hp = false; |
1506 | u32 dig_shift; | |
1507 | u32 dig_port_mask = 0; | |
b543fb04 | 1508 | |
91d131d2 DV |
1509 | if (!hotplug_trigger) |
1510 | return; | |
1511 | ||
13cf5504 DA |
1512 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n", |
1513 | hotplug_trigger, dig_hotplug_reg); | |
cc9bd499 | 1514 | |
b5ea2d56 | 1515 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1516 | for (i = 1; i < HPD_NUM_PINS; i++) { |
13cf5504 DA |
1517 | if (!(hpd[i] & hotplug_trigger)) |
1518 | continue; | |
1519 | ||
1520 | port = get_port_from_pin(i); | |
1521 | if (port && dev_priv->hpd_irq_port[port]) { | |
1522 | bool long_hpd; | |
1523 | ||
07c338ce JN |
1524 | if (HAS_PCH_SPLIT(dev)) { |
1525 | dig_shift = pch_port_to_hotplug_shift(port); | |
13cf5504 | 1526 | long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; |
07c338ce JN |
1527 | } else { |
1528 | dig_shift = i915_port_to_hotplug_shift(port); | |
1529 | long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; | |
13cf5504 DA |
1530 | } |
1531 | ||
26fbb774 VS |
1532 | DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", |
1533 | port_name(port), | |
1534 | long_hpd ? "long" : "short"); | |
13cf5504 DA |
1535 | /* for long HPD pulses we want to have the digital queue happen, |
1536 | but we still want HPD storm detection to function. */ | |
1537 | if (long_hpd) { | |
1538 | dev_priv->long_hpd_port_mask |= (1 << port); | |
1539 | dig_port_mask |= hpd[i]; | |
1540 | } else { | |
1541 | /* for short HPD just trigger the digital queue */ | |
1542 | dev_priv->short_hpd_port_mask |= (1 << port); | |
1543 | hotplug_trigger &= ~hpd[i]; | |
1544 | } | |
1545 | queue_dig = true; | |
1546 | } | |
1547 | } | |
821450c6 | 1548 | |
13cf5504 | 1549 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3ff04a16 DV |
1550 | if (hpd[i] & hotplug_trigger && |
1551 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { | |
1552 | /* | |
1553 | * On GMCH platforms the interrupt mask bits only | |
1554 | * prevent irq generation, not the setting of the | |
1555 | * hotplug bits itself. So only WARN about unexpected | |
1556 | * interrupts on saner platforms. | |
1557 | */ | |
1558 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), | |
1559 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | |
1560 | hotplug_trigger, i, hpd[i]); | |
1561 | ||
1562 | continue; | |
1563 | } | |
b8f102e8 | 1564 | |
b543fb04 EE |
1565 | if (!(hpd[i] & hotplug_trigger) || |
1566 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1567 | continue; | |
1568 | ||
13cf5504 DA |
1569 | if (!(dig_port_mask & hpd[i])) { |
1570 | dev_priv->hpd_event_bits |= (1 << i); | |
1571 | queue_hp = true; | |
1572 | } | |
1573 | ||
b543fb04 EE |
1574 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1575 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1576 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1577 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1578 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1579 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1580 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1581 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1582 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1583 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1584 | storm_detected = true; |
b543fb04 EE |
1585 | } else { |
1586 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1587 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1588 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1589 | } |
1590 | } | |
1591 | ||
10a504de DV |
1592 | if (storm_detected) |
1593 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1594 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1595 | |
645416f5 DV |
1596 | /* |
1597 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1598 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1599 | * queue for otherwise the flush_work in the pageflip code will | |
1600 | * deadlock. | |
1601 | */ | |
13cf5504 | 1602 | if (queue_dig) |
0e32b39c | 1603 | queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work); |
13cf5504 DA |
1604 | if (queue_hp) |
1605 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1606 | } |
1607 | ||
515ac2bb DV |
1608 | static void gmbus_irq_handler(struct drm_device *dev) |
1609 | { | |
2d1013dd | 1610 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1611 | |
28c70f16 | 1612 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1613 | } |
1614 | ||
ce99c256 DV |
1615 | static void dp_aux_irq_handler(struct drm_device *dev) |
1616 | { | |
2d1013dd | 1617 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1618 | |
9ee32fea | 1619 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1620 | } |
1621 | ||
8bf1e9f1 | 1622 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1623 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1624 | uint32_t crc0, uint32_t crc1, | |
1625 | uint32_t crc2, uint32_t crc3, | |
1626 | uint32_t crc4) | |
8bf1e9f1 SH |
1627 | { |
1628 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1629 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1630 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1631 | int head, tail; |
b2c88f5b | 1632 | |
d538bbdf DL |
1633 | spin_lock(&pipe_crc->lock); |
1634 | ||
0c912c79 | 1635 | if (!pipe_crc->entries) { |
d538bbdf | 1636 | spin_unlock(&pipe_crc->lock); |
34273620 | 1637 | DRM_DEBUG_KMS("spurious interrupt\n"); |
0c912c79 DL |
1638 | return; |
1639 | } | |
1640 | ||
d538bbdf DL |
1641 | head = pipe_crc->head; |
1642 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1643 | |
1644 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1645 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1646 | DRM_ERROR("CRC buffer overflowing\n"); |
1647 | return; | |
1648 | } | |
1649 | ||
1650 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1651 | |
8bc5e955 | 1652 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1653 | entry->crc[0] = crc0; |
1654 | entry->crc[1] = crc1; | |
1655 | entry->crc[2] = crc2; | |
1656 | entry->crc[3] = crc3; | |
1657 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1658 | |
1659 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1660 | pipe_crc->head = head; |
1661 | ||
1662 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1663 | |
1664 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1665 | } |
277de95e DV |
1666 | #else |
1667 | static inline void | |
1668 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1669 | uint32_t crc0, uint32_t crc1, | |
1670 | uint32_t crc2, uint32_t crc3, | |
1671 | uint32_t crc4) {} | |
1672 | #endif | |
1673 | ||
eba94eb9 | 1674 | |
277de95e | 1675 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1676 | { |
1677 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1678 | ||
277de95e DV |
1679 | display_pipe_crc_irq_handler(dev, pipe, |
1680 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1681 | 0, 0, 0, 0); | |
5a69b89f DV |
1682 | } |
1683 | ||
277de95e | 1684 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1685 | { |
1686 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1687 | ||
277de95e DV |
1688 | display_pipe_crc_irq_handler(dev, pipe, |
1689 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1690 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1691 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1692 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1693 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1694 | } |
5b3a856b | 1695 | |
277de95e | 1696 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1697 | { |
1698 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1699 | uint32_t res1, res2; |
1700 | ||
1701 | if (INTEL_INFO(dev)->gen >= 3) | |
1702 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1703 | else | |
1704 | res1 = 0; | |
1705 | ||
1706 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1707 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1708 | else | |
1709 | res2 = 0; | |
5b3a856b | 1710 | |
277de95e DV |
1711 | display_pipe_crc_irq_handler(dev, pipe, |
1712 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1713 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1714 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1715 | res1, res2); | |
5b3a856b | 1716 | } |
8bf1e9f1 | 1717 | |
1403c0d4 PZ |
1718 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1719 | * IMR bits until the work is done. Other interrupts can be processed without | |
1720 | * the work queue. */ | |
1721 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1722 | { |
4a74de82 ID |
1723 | /* TODO: RPS on GEN9+ is not supported yet. */ |
1724 | if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9, | |
1725 | "GEN9+: unexpected RPS IRQ\n")) | |
132f3f17 ID |
1726 | return; |
1727 | ||
a6706b45 | 1728 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1729 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1730 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1731 | if (dev_priv->rps.interrupts_enabled) { |
1732 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1733 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1734 | } | |
59cdb63d | 1735 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1736 | } |
baf02a1f | 1737 | |
c9a9a268 ID |
1738 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1739 | return; | |
1740 | ||
1403c0d4 PZ |
1741 | if (HAS_VEBOX(dev_priv->dev)) { |
1742 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1743 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1744 | |
aaecdf61 DV |
1745 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1746 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1747 | } |
baf02a1f BW |
1748 | } |
1749 | ||
8d7849db VS |
1750 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1751 | { | |
8d7849db VS |
1752 | if (!drm_handle_vblank(dev, pipe)) |
1753 | return false; | |
1754 | ||
8d7849db VS |
1755 | return true; |
1756 | } | |
1757 | ||
c1874ed7 ID |
1758 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1759 | { | |
1760 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1761 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1762 | int pipe; |
1763 | ||
58ead0d7 | 1764 | spin_lock(&dev_priv->irq_lock); |
055e393f | 1765 | for_each_pipe(dev_priv, pipe) { |
91d181dd | 1766 | int reg; |
bbb5eebf | 1767 | u32 mask, iir_bit = 0; |
91d181dd | 1768 | |
bbb5eebf DV |
1769 | /* |
1770 | * PIPESTAT bits get signalled even when the interrupt is | |
1771 | * disabled with the mask bits, and some of the status bits do | |
1772 | * not generate interrupts at all (like the underrun bit). Hence | |
1773 | * we need to be careful that we only handle what we want to | |
1774 | * handle. | |
1775 | */ | |
0f239f4c DV |
1776 | |
1777 | /* fifo underruns are filterered in the underrun handler. */ | |
1778 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1779 | |
1780 | switch (pipe) { | |
1781 | case PIPE_A: | |
1782 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1783 | break; | |
1784 | case PIPE_B: | |
1785 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1786 | break; | |
3278f67f VS |
1787 | case PIPE_C: |
1788 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1789 | break; | |
bbb5eebf DV |
1790 | } |
1791 | if (iir & iir_bit) | |
1792 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1793 | ||
1794 | if (!mask) | |
91d181dd ID |
1795 | continue; |
1796 | ||
1797 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1798 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1799 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1800 | |
1801 | /* | |
1802 | * Clear the PIPE*STAT regs before the IIR | |
1803 | */ | |
91d181dd ID |
1804 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1805 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1806 | I915_WRITE(reg, pipe_stats[pipe]); |
1807 | } | |
58ead0d7 | 1808 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 | 1809 | |
055e393f | 1810 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1811 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1812 | intel_pipe_handle_vblank(dev, pipe)) | |
1813 | intel_check_page_flip(dev, pipe); | |
c1874ed7 | 1814 | |
579a9b0e | 1815 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1816 | intel_prepare_page_flip(dev, pipe); |
1817 | intel_finish_page_flip(dev, pipe); | |
1818 | } | |
1819 | ||
1820 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1821 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1822 | ||
1f7247c0 DV |
1823 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1824 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1825 | } |
1826 | ||
1827 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1828 | gmbus_irq_handler(dev); | |
1829 | } | |
1830 | ||
16c6c56b VS |
1831 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1832 | { | |
1833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1834 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1835 | ||
3ff60f89 OM |
1836 | if (hotplug_status) { |
1837 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1838 | /* | |
1839 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1840 | * may miss hotplug events. | |
1841 | */ | |
1842 | POSTING_READ(PORT_HOTPLUG_STAT); | |
16c6c56b | 1843 | |
3ff60f89 OM |
1844 | if (IS_G4X(dev)) { |
1845 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
16c6c56b | 1846 | |
13cf5504 | 1847 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x); |
3ff60f89 OM |
1848 | } else { |
1849 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1850 | |
13cf5504 | 1851 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915); |
3ff60f89 | 1852 | } |
16c6c56b | 1853 | |
3ff60f89 OM |
1854 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && |
1855 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1856 | dp_aux_irq_handler(dev); | |
1857 | } | |
16c6c56b VS |
1858 | } |
1859 | ||
ff1f525e | 1860 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1861 | { |
45a83f84 | 1862 | struct drm_device *dev = arg; |
2d1013dd | 1863 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1864 | u32 iir, gt_iir, pm_iir; |
1865 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1866 | |
7e231dbe | 1867 | while (true) { |
3ff60f89 OM |
1868 | /* Find, clear, then process each source of interrupt */ |
1869 | ||
7e231dbe | 1870 | gt_iir = I915_READ(GTIIR); |
3ff60f89 OM |
1871 | if (gt_iir) |
1872 | I915_WRITE(GTIIR, gt_iir); | |
1873 | ||
7e231dbe | 1874 | pm_iir = I915_READ(GEN6_PMIIR); |
3ff60f89 OM |
1875 | if (pm_iir) |
1876 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1877 | ||
1878 | iir = I915_READ(VLV_IIR); | |
1879 | if (iir) { | |
1880 | /* Consume port before clearing IIR or we'll miss events */ | |
1881 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1882 | i9xx_hpd_irq_handler(dev); | |
1883 | I915_WRITE(VLV_IIR, iir); | |
1884 | } | |
7e231dbe JB |
1885 | |
1886 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1887 | goto out; | |
1888 | ||
1889 | ret = IRQ_HANDLED; | |
1890 | ||
3ff60f89 OM |
1891 | if (gt_iir) |
1892 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
60611c13 | 1893 | if (pm_iir) |
d0ecd7e2 | 1894 | gen6_rps_irq_handler(dev_priv, pm_iir); |
3ff60f89 OM |
1895 | /* Call regardless, as some status bits might not be |
1896 | * signalled in iir */ | |
1897 | valleyview_pipestat_irq_handler(dev, iir); | |
7e231dbe JB |
1898 | } |
1899 | ||
1900 | out: | |
1901 | return ret; | |
1902 | } | |
1903 | ||
43f328d7 VS |
1904 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1905 | { | |
45a83f84 | 1906 | struct drm_device *dev = arg; |
43f328d7 VS |
1907 | struct drm_i915_private *dev_priv = dev->dev_private; |
1908 | u32 master_ctl, iir; | |
1909 | irqreturn_t ret = IRQ_NONE; | |
43f328d7 | 1910 | |
8e5fd599 VS |
1911 | for (;;) { |
1912 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; | |
1913 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1914 | |
8e5fd599 VS |
1915 | if (master_ctl == 0 && iir == 0) |
1916 | break; | |
43f328d7 | 1917 | |
27b6c122 OM |
1918 | ret = IRQ_HANDLED; |
1919 | ||
8e5fd599 | 1920 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
43f328d7 | 1921 | |
27b6c122 | 1922 | /* Find, clear, then process each source of interrupt */ |
43f328d7 | 1923 | |
27b6c122 OM |
1924 | if (iir) { |
1925 | /* Consume port before clearing IIR or we'll miss events */ | |
1926 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1927 | i9xx_hpd_irq_handler(dev); | |
1928 | I915_WRITE(VLV_IIR, iir); | |
1929 | } | |
43f328d7 | 1930 | |
27b6c122 | 1931 | gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
43f328d7 | 1932 | |
27b6c122 OM |
1933 | /* Call regardless, as some status bits might not be |
1934 | * signalled in iir */ | |
1935 | valleyview_pipestat_irq_handler(dev, iir); | |
43f328d7 | 1936 | |
8e5fd599 VS |
1937 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
1938 | POSTING_READ(GEN8_MASTER_IRQ); | |
8e5fd599 | 1939 | } |
3278f67f | 1940 | |
43f328d7 VS |
1941 | return ret; |
1942 | } | |
1943 | ||
23e81d69 | 1944 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1945 | { |
2d1013dd | 1946 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1947 | int pipe; |
b543fb04 | 1948 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 DA |
1949 | u32 dig_hotplug_reg; |
1950 | ||
1951 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1952 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
776ad806 | 1953 | |
13cf5504 | 1954 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx); |
91d131d2 | 1955 | |
cfc33bf7 VS |
1956 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1957 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1958 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1959 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1960 | port_name(port)); |
1961 | } | |
776ad806 | 1962 | |
ce99c256 DV |
1963 | if (pch_iir & SDE_AUX_MASK) |
1964 | dp_aux_irq_handler(dev); | |
1965 | ||
776ad806 | 1966 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1967 | gmbus_irq_handler(dev); |
776ad806 JB |
1968 | |
1969 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1970 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1971 | ||
1972 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1973 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1974 | ||
1975 | if (pch_iir & SDE_POISON) | |
1976 | DRM_ERROR("PCH poison interrupt\n"); | |
1977 | ||
9db4a9c7 | 1978 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 1979 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
1980 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1981 | pipe_name(pipe), | |
1982 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1983 | |
1984 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1985 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1986 | ||
1987 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1988 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1989 | ||
776ad806 | 1990 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 1991 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1992 | |
1993 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 1994 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1995 | } |
1996 | ||
1997 | static void ivb_err_int_handler(struct drm_device *dev) | |
1998 | { | |
1999 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2000 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 2001 | enum pipe pipe; |
8664281b | 2002 | |
de032bf4 PZ |
2003 | if (err_int & ERR_INT_POISON) |
2004 | DRM_ERROR("Poison interrupt\n"); | |
2005 | ||
055e393f | 2006 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
2007 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
2008 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 2009 | |
5a69b89f DV |
2010 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
2011 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 2012 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 2013 | else |
277de95e | 2014 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
2015 | } |
2016 | } | |
8bf1e9f1 | 2017 | |
8664281b PZ |
2018 | I915_WRITE(GEN7_ERR_INT, err_int); |
2019 | } | |
2020 | ||
2021 | static void cpt_serr_int_handler(struct drm_device *dev) | |
2022 | { | |
2023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2024 | u32 serr_int = I915_READ(SERR_INT); | |
2025 | ||
de032bf4 PZ |
2026 | if (serr_int & SERR_INT_POISON) |
2027 | DRM_ERROR("PCH poison interrupt\n"); | |
2028 | ||
8664281b | 2029 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 2030 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2031 | |
2032 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 2033 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2034 | |
2035 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 2036 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
2037 | |
2038 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
2039 | } |
2040 | ||
23e81d69 AJ |
2041 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
2042 | { | |
2d1013dd | 2043 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 2044 | int pipe; |
b543fb04 | 2045 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 DA |
2046 | u32 dig_hotplug_reg; |
2047 | ||
2048 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
2049 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
23e81d69 | 2050 | |
13cf5504 | 2051 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt); |
91d131d2 | 2052 | |
cfc33bf7 VS |
2053 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
2054 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
2055 | SDE_AUDIO_POWER_SHIFT_CPT); | |
2056 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
2057 | port_name(port)); | |
2058 | } | |
23e81d69 AJ |
2059 | |
2060 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 2061 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
2062 | |
2063 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 2064 | gmbus_irq_handler(dev); |
23e81d69 AJ |
2065 | |
2066 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
2067 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
2068 | ||
2069 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
2070 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
2071 | ||
2072 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 2073 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
2074 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2075 | pipe_name(pipe), | |
2076 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
2077 | |
2078 | if (pch_iir & SDE_ERROR_CPT) | |
2079 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
2080 | } |
2081 | ||
c008bc6e PZ |
2082 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2083 | { | |
2084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 2085 | enum pipe pipe; |
c008bc6e PZ |
2086 | |
2087 | if (de_iir & DE_AUX_CHANNEL_A) | |
2088 | dp_aux_irq_handler(dev); | |
2089 | ||
2090 | if (de_iir & DE_GSE) | |
2091 | intel_opregion_asle_intr(dev); | |
2092 | ||
c008bc6e PZ |
2093 | if (de_iir & DE_POISON) |
2094 | DRM_ERROR("Poison interrupt\n"); | |
2095 | ||
055e393f | 2096 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2097 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2098 | intel_pipe_handle_vblank(dev, pipe)) | |
2099 | intel_check_page_flip(dev, pipe); | |
5b3a856b | 2100 | |
40da17c2 | 2101 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2102 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2103 | |
40da17c2 DV |
2104 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
2105 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 2106 | |
40da17c2 DV |
2107 | /* plane/pipes map 1:1 on ilk+ */ |
2108 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
2109 | intel_prepare_page_flip(dev, pipe); | |
2110 | intel_finish_page_flip_plane(dev, pipe); | |
2111 | } | |
c008bc6e PZ |
2112 | } |
2113 | ||
2114 | /* check event from PCH */ | |
2115 | if (de_iir & DE_PCH_EVENT) { | |
2116 | u32 pch_iir = I915_READ(SDEIIR); | |
2117 | ||
2118 | if (HAS_PCH_CPT(dev)) | |
2119 | cpt_irq_handler(dev, pch_iir); | |
2120 | else | |
2121 | ibx_irq_handler(dev, pch_iir); | |
2122 | ||
2123 | /* should clear PCH hotplug event before clear CPU irq */ | |
2124 | I915_WRITE(SDEIIR, pch_iir); | |
2125 | } | |
2126 | ||
2127 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
2128 | ironlake_rps_change_irq_handler(dev); | |
2129 | } | |
2130 | ||
9719fb98 PZ |
2131 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2132 | { | |
2133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 2134 | enum pipe pipe; |
9719fb98 PZ |
2135 | |
2136 | if (de_iir & DE_ERR_INT_IVB) | |
2137 | ivb_err_int_handler(dev); | |
2138 | ||
2139 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2140 | dp_aux_irq_handler(dev); | |
2141 | ||
2142 | if (de_iir & DE_GSE_IVB) | |
2143 | intel_opregion_asle_intr(dev); | |
2144 | ||
055e393f | 2145 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2146 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2147 | intel_pipe_handle_vblank(dev, pipe)) | |
2148 | intel_check_page_flip(dev, pipe); | |
40da17c2 DV |
2149 | |
2150 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2151 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2152 | intel_prepare_page_flip(dev, pipe); | |
2153 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2154 | } |
2155 | } | |
2156 | ||
2157 | /* check event from PCH */ | |
2158 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2159 | u32 pch_iir = I915_READ(SDEIIR); | |
2160 | ||
2161 | cpt_irq_handler(dev, pch_iir); | |
2162 | ||
2163 | /* clear PCH hotplug event before clear CPU irq */ | |
2164 | I915_WRITE(SDEIIR, pch_iir); | |
2165 | } | |
2166 | } | |
2167 | ||
72c90f62 OM |
2168 | /* |
2169 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2170 | * 1 - Disable Master Interrupt Control. | |
2171 | * 2 - Find the source(s) of the interrupt. | |
2172 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2173 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2174 | * 5 - Re-enable Master Interrupt Control. | |
2175 | */ | |
f1af8fc1 | 2176 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2177 | { |
45a83f84 | 2178 | struct drm_device *dev = arg; |
2d1013dd | 2179 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2180 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2181 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2182 | |
8664281b PZ |
2183 | /* We get interrupts on unclaimed registers, so check for this before we |
2184 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 2185 | intel_uncore_check_errors(dev); |
8664281b | 2186 | |
b1f14ad0 JB |
2187 | /* disable master interrupt before clearing iir */ |
2188 | de_ier = I915_READ(DEIER); | |
2189 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2190 | POSTING_READ(DEIER); |
b1f14ad0 | 2191 | |
44498aea PZ |
2192 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2193 | * interrupts will will be stored on its back queue, and then we'll be | |
2194 | * able to process them after we restore SDEIER (as soon as we restore | |
2195 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2196 | * due to its back queue). */ | |
ab5c608b BW |
2197 | if (!HAS_PCH_NOP(dev)) { |
2198 | sde_ier = I915_READ(SDEIER); | |
2199 | I915_WRITE(SDEIER, 0); | |
2200 | POSTING_READ(SDEIER); | |
2201 | } | |
44498aea | 2202 | |
72c90f62 OM |
2203 | /* Find, clear, then process each source of interrupt */ |
2204 | ||
b1f14ad0 | 2205 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2206 | if (gt_iir) { |
72c90f62 OM |
2207 | I915_WRITE(GTIIR, gt_iir); |
2208 | ret = IRQ_HANDLED; | |
d8fc8a47 | 2209 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 2210 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
2211 | else |
2212 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
b1f14ad0 JB |
2213 | } |
2214 | ||
0e43406b CW |
2215 | de_iir = I915_READ(DEIIR); |
2216 | if (de_iir) { | |
72c90f62 OM |
2217 | I915_WRITE(DEIIR, de_iir); |
2218 | ret = IRQ_HANDLED; | |
f1af8fc1 PZ |
2219 | if (INTEL_INFO(dev)->gen >= 7) |
2220 | ivb_display_irq_handler(dev, de_iir); | |
2221 | else | |
2222 | ilk_display_irq_handler(dev, de_iir); | |
b1f14ad0 JB |
2223 | } |
2224 | ||
f1af8fc1 PZ |
2225 | if (INTEL_INFO(dev)->gen >= 6) { |
2226 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2227 | if (pm_iir) { | |
f1af8fc1 PZ |
2228 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2229 | ret = IRQ_HANDLED; | |
72c90f62 | 2230 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2231 | } |
0e43406b | 2232 | } |
b1f14ad0 | 2233 | |
b1f14ad0 JB |
2234 | I915_WRITE(DEIER, de_ier); |
2235 | POSTING_READ(DEIER); | |
ab5c608b BW |
2236 | if (!HAS_PCH_NOP(dev)) { |
2237 | I915_WRITE(SDEIER, sde_ier); | |
2238 | POSTING_READ(SDEIER); | |
2239 | } | |
b1f14ad0 JB |
2240 | |
2241 | return ret; | |
2242 | } | |
2243 | ||
abd58f01 BW |
2244 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2245 | { | |
2246 | struct drm_device *dev = arg; | |
2247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2248 | u32 master_ctl; | |
2249 | irqreturn_t ret = IRQ_NONE; | |
2250 | uint32_t tmp = 0; | |
c42664cc | 2251 | enum pipe pipe; |
88e04703 JB |
2252 | u32 aux_mask = GEN8_AUX_CHANNEL_A; |
2253 | ||
2254 | if (IS_GEN9(dev)) | |
2255 | aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | | |
2256 | GEN9_AUX_CHANNEL_D; | |
abd58f01 | 2257 | |
abd58f01 BW |
2258 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
2259 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2260 | if (!master_ctl) | |
2261 | return IRQ_NONE; | |
2262 | ||
2263 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
2264 | POSTING_READ(GEN8_MASTER_IRQ); | |
2265 | ||
38cc46d7 OM |
2266 | /* Find, clear, then process each source of interrupt */ |
2267 | ||
abd58f01 BW |
2268 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
2269 | ||
2270 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2271 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
abd58f01 BW |
2272 | if (tmp) { |
2273 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2274 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2275 | if (tmp & GEN8_DE_MISC_GSE) |
2276 | intel_opregion_asle_intr(dev); | |
2277 | else | |
2278 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2279 | } |
38cc46d7 OM |
2280 | else |
2281 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2282 | } |
2283 | ||
6d766f02 DV |
2284 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2285 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
6d766f02 DV |
2286 | if (tmp) { |
2287 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
2288 | ret = IRQ_HANDLED; | |
88e04703 JB |
2289 | |
2290 | if (tmp & aux_mask) | |
38cc46d7 OM |
2291 | dp_aux_irq_handler(dev); |
2292 | else | |
2293 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
6d766f02 | 2294 | } |
38cc46d7 OM |
2295 | else |
2296 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2297 | } |
2298 | ||
055e393f | 2299 | for_each_pipe(dev_priv, pipe) { |
770de83d | 2300 | uint32_t pipe_iir, flip_done = 0, fault_errors = 0; |
abd58f01 | 2301 | |
c42664cc DV |
2302 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2303 | continue; | |
abd58f01 | 2304 | |
c42664cc | 2305 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
c42664cc DV |
2306 | if (pipe_iir) { |
2307 | ret = IRQ_HANDLED; | |
2308 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
770de83d | 2309 | |
d6bbafa1 CW |
2310 | if (pipe_iir & GEN8_PIPE_VBLANK && |
2311 | intel_pipe_handle_vblank(dev, pipe)) | |
2312 | intel_check_page_flip(dev, pipe); | |
38cc46d7 | 2313 | |
770de83d DL |
2314 | if (IS_GEN9(dev)) |
2315 | flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; | |
2316 | else | |
2317 | flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; | |
2318 | ||
2319 | if (flip_done) { | |
38cc46d7 OM |
2320 | intel_prepare_page_flip(dev, pipe); |
2321 | intel_finish_page_flip_plane(dev, pipe); | |
2322 | } | |
2323 | ||
2324 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) | |
2325 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2326 | ||
1f7247c0 DV |
2327 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) |
2328 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
2329 | pipe); | |
38cc46d7 | 2330 | |
770de83d DL |
2331 | |
2332 | if (IS_GEN9(dev)) | |
2333 | fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2334 | else | |
2335 | fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2336 | ||
2337 | if (fault_errors) | |
38cc46d7 OM |
2338 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
2339 | pipe_name(pipe), | |
2340 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
c42664cc | 2341 | } else |
abd58f01 BW |
2342 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2343 | } | |
2344 | ||
92d03a80 DV |
2345 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2346 | /* | |
2347 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2348 | * scheme also closed the SDE interrupt handling race we've seen | |
2349 | * on older pch-split platforms. But this needs testing. | |
2350 | */ | |
2351 | u32 pch_iir = I915_READ(SDEIIR); | |
92d03a80 DV |
2352 | if (pch_iir) { |
2353 | I915_WRITE(SDEIIR, pch_iir); | |
2354 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2355 | cpt_irq_handler(dev, pch_iir); |
2356 | } else | |
2357 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); | |
2358 | ||
92d03a80 DV |
2359 | } |
2360 | ||
abd58f01 BW |
2361 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2362 | POSTING_READ(GEN8_MASTER_IRQ); | |
2363 | ||
2364 | return ret; | |
2365 | } | |
2366 | ||
17e1df07 DV |
2367 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2368 | bool reset_completed) | |
2369 | { | |
a4872ba6 | 2370 | struct intel_engine_cs *ring; |
17e1df07 DV |
2371 | int i; |
2372 | ||
2373 | /* | |
2374 | * Notify all waiters for GPU completion events that reset state has | |
2375 | * been changed, and that they need to restart their wait after | |
2376 | * checking for potential errors (and bail out to drop locks if there is | |
2377 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2378 | */ | |
2379 | ||
2380 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2381 | for_each_ring(ring, dev_priv, i) | |
2382 | wake_up_all(&ring->irq_queue); | |
2383 | ||
2384 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2385 | wake_up_all(&dev_priv->pending_flip_queue); | |
2386 | ||
2387 | /* | |
2388 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2389 | * reset state is cleared. | |
2390 | */ | |
2391 | if (reset_completed) | |
2392 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2393 | } | |
2394 | ||
8a905236 JB |
2395 | /** |
2396 | * i915_error_work_func - do process context error handling work | |
2397 | * @work: work struct | |
2398 | * | |
2399 | * Fire an error uevent so userspace can see that a hang or error | |
2400 | * was detected. | |
2401 | */ | |
2402 | static void i915_error_work_func(struct work_struct *work) | |
2403 | { | |
1f83fee0 DV |
2404 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
2405 | work); | |
2d1013dd JN |
2406 | struct drm_i915_private *dev_priv = |
2407 | container_of(error, struct drm_i915_private, gpu_error); | |
8a905236 | 2408 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
2409 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2410 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2411 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2412 | int ret; |
8a905236 | 2413 | |
5bdebb18 | 2414 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2415 | |
7db0ba24 DV |
2416 | /* |
2417 | * Note that there's only one work item which does gpu resets, so we | |
2418 | * need not worry about concurrent gpu resets potentially incrementing | |
2419 | * error->reset_counter twice. We only need to take care of another | |
2420 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2421 | * quick check for that is good enough: schedule_work ensures the | |
2422 | * correct ordering between hang detection and this work item, and since | |
2423 | * the reset in-progress bit is only ever set by code outside of this | |
2424 | * work we don't need to worry about any other races. | |
2425 | */ | |
2426 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2427 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2428 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2429 | reset_event); |
1f83fee0 | 2430 | |
f454c694 ID |
2431 | /* |
2432 | * In most cases it's guaranteed that we get here with an RPM | |
2433 | * reference held, for example because there is a pending GPU | |
2434 | * request that won't finish until the reset is done. This | |
2435 | * isn't the case at least when we get here by doing a | |
2436 | * simulated reset via debugs, so get an RPM reference. | |
2437 | */ | |
2438 | intel_runtime_pm_get(dev_priv); | |
7514747d VS |
2439 | |
2440 | intel_prepare_reset(dev); | |
2441 | ||
17e1df07 DV |
2442 | /* |
2443 | * All state reset _must_ be completed before we update the | |
2444 | * reset counter, for otherwise waiters might miss the reset | |
2445 | * pending state and not properly drop locks, resulting in | |
2446 | * deadlocks with the reset work. | |
2447 | */ | |
f69061be DV |
2448 | ret = i915_reset(dev); |
2449 | ||
7514747d | 2450 | intel_finish_reset(dev); |
17e1df07 | 2451 | |
f454c694 ID |
2452 | intel_runtime_pm_put(dev_priv); |
2453 | ||
f69061be DV |
2454 | if (ret == 0) { |
2455 | /* | |
2456 | * After all the gem state is reset, increment the reset | |
2457 | * counter and wake up everyone waiting for the reset to | |
2458 | * complete. | |
2459 | * | |
2460 | * Since unlock operations are a one-sided barrier only, | |
2461 | * we need to insert a barrier here to order any seqno | |
2462 | * updates before | |
2463 | * the counter increment. | |
2464 | */ | |
4e857c58 | 2465 | smp_mb__before_atomic(); |
f69061be DV |
2466 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
2467 | ||
5bdebb18 | 2468 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2469 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2470 | } else { |
2ac0f450 | 2471 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2472 | } |
1f83fee0 | 2473 | |
17e1df07 DV |
2474 | /* |
2475 | * Note: The wake_up also serves as a memory barrier so that | |
2476 | * waiters see the update value of the reset counter atomic_t. | |
2477 | */ | |
2478 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2479 | } |
8a905236 JB |
2480 | } |
2481 | ||
35aed2e6 | 2482 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2483 | { |
2484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2485 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2486 | u32 eir = I915_READ(EIR); |
050ee91f | 2487 | int pipe, i; |
8a905236 | 2488 | |
35aed2e6 CW |
2489 | if (!eir) |
2490 | return; | |
8a905236 | 2491 | |
a70491cc | 2492 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2493 | |
bd9854f9 BW |
2494 | i915_get_extra_instdone(dev, instdone); |
2495 | ||
8a905236 JB |
2496 | if (IS_G4X(dev)) { |
2497 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2498 | u32 ipeir = I915_READ(IPEIR_I965); | |
2499 | ||
a70491cc JP |
2500 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2501 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2502 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2503 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2504 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2505 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2506 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2507 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2508 | } |
2509 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2510 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2511 | pr_err("page table error\n"); |
2512 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2513 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2514 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2515 | } |
2516 | } | |
2517 | ||
a6c45cf0 | 2518 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2519 | if (eir & I915_ERROR_PAGE_TABLE) { |
2520 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2521 | pr_err("page table error\n"); |
2522 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2523 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2524 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2525 | } |
2526 | } | |
2527 | ||
2528 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2529 | pr_err("memory refresh error:\n"); |
055e393f | 2530 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2531 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2532 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2533 | /* pipestat has already been acked */ |
2534 | } | |
2535 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2536 | pr_err("instruction error\n"); |
2537 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2538 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2539 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2540 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2541 | u32 ipeir = I915_READ(IPEIR); |
2542 | ||
a70491cc JP |
2543 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2544 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2545 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2546 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2547 | POSTING_READ(IPEIR); |
8a905236 JB |
2548 | } else { |
2549 | u32 ipeir = I915_READ(IPEIR_I965); | |
2550 | ||
a70491cc JP |
2551 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2552 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2553 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2554 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2555 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2556 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2557 | } |
2558 | } | |
2559 | ||
2560 | I915_WRITE(EIR, eir); | |
3143a2bf | 2561 | POSTING_READ(EIR); |
8a905236 JB |
2562 | eir = I915_READ(EIR); |
2563 | if (eir) { | |
2564 | /* | |
2565 | * some errors might have become stuck, | |
2566 | * mask them. | |
2567 | */ | |
2568 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2569 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2570 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2571 | } | |
35aed2e6 CW |
2572 | } |
2573 | ||
2574 | /** | |
2575 | * i915_handle_error - handle an error interrupt | |
2576 | * @dev: drm device | |
2577 | * | |
2578 | * Do some basic checking of regsiter state at error interrupt time and | |
2579 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2580 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2581 | * so userspace knows something bad happened (should trigger collection | |
2582 | * of a ring dump etc.). | |
2583 | */ | |
58174462 MK |
2584 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2585 | const char *fmt, ...) | |
35aed2e6 CW |
2586 | { |
2587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2588 | va_list args; |
2589 | char error_msg[80]; | |
35aed2e6 | 2590 | |
58174462 MK |
2591 | va_start(args, fmt); |
2592 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2593 | va_end(args); | |
2594 | ||
2595 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2596 | i915_report_and_clear_eir(dev); |
8a905236 | 2597 | |
ba1234d1 | 2598 | if (wedged) { |
f69061be DV |
2599 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2600 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2601 | |
11ed50ec | 2602 | /* |
17e1df07 DV |
2603 | * Wakeup waiting processes so that the reset work function |
2604 | * i915_error_work_func doesn't deadlock trying to grab various | |
2605 | * locks. By bumping the reset counter first, the woken | |
2606 | * processes will see a reset in progress and back off, | |
2607 | * releasing their locks and then wait for the reset completion. | |
2608 | * We must do this for _all_ gpu waiters that might hold locks | |
2609 | * that the reset work needs to acquire. | |
2610 | * | |
2611 | * Note: The wake_up serves as the required memory barrier to | |
2612 | * ensure that the waiters see the updated value of the reset | |
2613 | * counter atomic_t. | |
11ed50ec | 2614 | */ |
17e1df07 | 2615 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2616 | } |
2617 | ||
122f46ba DV |
2618 | /* |
2619 | * Our reset work can grab modeset locks (since it needs to reset the | |
2620 | * state of outstanding pagelips). Hence it must not be run on our own | |
2621 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2622 | * code will deadlock. | |
2623 | */ | |
2624 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2625 | } |
2626 | ||
42f52ef8 KP |
2627 | /* Called from drm generic code, passed 'crtc' which |
2628 | * we use as a pipe index | |
2629 | */ | |
f71d4af4 | 2630 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2631 | { |
2d1013dd | 2632 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2633 | unsigned long irqflags; |
71e0ffa5 | 2634 | |
5eddb70b | 2635 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2636 | return -EINVAL; |
0a3e67a4 | 2637 | |
1ec14ad3 | 2638 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2639 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2640 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2641 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2642 | else |
7c463586 | 2643 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2644 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2645 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2646 | |
0a3e67a4 JB |
2647 | return 0; |
2648 | } | |
2649 | ||
f71d4af4 | 2650 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2651 | { |
2d1013dd | 2652 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2653 | unsigned long irqflags; |
b518421f | 2654 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2655 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2656 | |
2657 | if (!i915_pipe_enabled(dev, pipe)) | |
2658 | return -EINVAL; | |
2659 | ||
2660 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2661 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2662 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2663 | ||
2664 | return 0; | |
2665 | } | |
2666 | ||
7e231dbe JB |
2667 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2668 | { | |
2d1013dd | 2669 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2670 | unsigned long irqflags; |
7e231dbe JB |
2671 | |
2672 | if (!i915_pipe_enabled(dev, pipe)) | |
2673 | return -EINVAL; | |
2674 | ||
2675 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2676 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2677 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2678 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2679 | ||
2680 | return 0; | |
2681 | } | |
2682 | ||
abd58f01 BW |
2683 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2684 | { | |
2685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2686 | unsigned long irqflags; | |
abd58f01 BW |
2687 | |
2688 | if (!i915_pipe_enabled(dev, pipe)) | |
2689 | return -EINVAL; | |
2690 | ||
2691 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2692 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2693 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2694 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2695 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2696 | return 0; | |
2697 | } | |
2698 | ||
42f52ef8 KP |
2699 | /* Called from drm generic code, passed 'crtc' which |
2700 | * we use as a pipe index | |
2701 | */ | |
f71d4af4 | 2702 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2703 | { |
2d1013dd | 2704 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2705 | unsigned long irqflags; |
0a3e67a4 | 2706 | |
1ec14ad3 | 2707 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2708 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2709 | PIPE_VBLANK_INTERRUPT_STATUS | |
2710 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2711 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2712 | } | |
2713 | ||
f71d4af4 | 2714 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2715 | { |
2d1013dd | 2716 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2717 | unsigned long irqflags; |
b518421f | 2718 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2719 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2720 | |
2721 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2722 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2723 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2724 | } | |
2725 | ||
7e231dbe JB |
2726 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2727 | { | |
2d1013dd | 2728 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2729 | unsigned long irqflags; |
7e231dbe JB |
2730 | |
2731 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2732 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2733 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2734 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2735 | } | |
2736 | ||
abd58f01 BW |
2737 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2738 | { | |
2739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2740 | unsigned long irqflags; | |
abd58f01 BW |
2741 | |
2742 | if (!i915_pipe_enabled(dev, pipe)) | |
2743 | return; | |
2744 | ||
2745 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2746 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2747 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2748 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2749 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2750 | } | |
2751 | ||
893eead0 | 2752 | static u32 |
a4872ba6 | 2753 | ring_last_seqno(struct intel_engine_cs *ring) |
852835f3 | 2754 | { |
893eead0 CW |
2755 | return list_entry(ring->request_list.prev, |
2756 | struct drm_i915_gem_request, list)->seqno; | |
2757 | } | |
2758 | ||
9107e9d2 | 2759 | static bool |
a4872ba6 | 2760 | ring_idle(struct intel_engine_cs *ring, u32 seqno) |
9107e9d2 CW |
2761 | { |
2762 | return (list_empty(&ring->request_list) || | |
2763 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2764 | } |
2765 | ||
a028c4b0 DV |
2766 | static bool |
2767 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2768 | { | |
2769 | if (INTEL_INFO(dev)->gen >= 8) { | |
a6cdb93a | 2770 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2771 | } else { |
2772 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2773 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2774 | MI_SEMAPHORE_REGISTER); | |
2775 | } | |
2776 | } | |
2777 | ||
a4872ba6 | 2778 | static struct intel_engine_cs * |
a6cdb93a | 2779 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
921d42ea DV |
2780 | { |
2781 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2782 | struct intel_engine_cs *signaller; |
921d42ea DV |
2783 | int i; |
2784 | ||
2785 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
a6cdb93a RV |
2786 | for_each_ring(signaller, dev_priv, i) { |
2787 | if (ring == signaller) | |
2788 | continue; | |
2789 | ||
2790 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) | |
2791 | return signaller; | |
2792 | } | |
921d42ea DV |
2793 | } else { |
2794 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2795 | ||
2796 | for_each_ring(signaller, dev_priv, i) { | |
2797 | if(ring == signaller) | |
2798 | continue; | |
2799 | ||
ebc348b2 | 2800 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2801 | return signaller; |
2802 | } | |
2803 | } | |
2804 | ||
a6cdb93a RV |
2805 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
2806 | ring->id, ipehr, offset); | |
921d42ea DV |
2807 | |
2808 | return NULL; | |
2809 | } | |
2810 | ||
a4872ba6 OM |
2811 | static struct intel_engine_cs * |
2812 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) | |
a24a11e6 CW |
2813 | { |
2814 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d | 2815 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2816 | u64 offset = 0; |
2817 | int i, backwards; | |
a24a11e6 CW |
2818 | |
2819 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2820 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2821 | return NULL; |
a24a11e6 | 2822 | |
88fe429d DV |
2823 | /* |
2824 | * HEAD is likely pointing to the dword after the actual command, | |
2825 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2826 | * or 4 dwords depending on the semaphore wait command size. |
2827 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2828 | * point at at batch, and semaphores are always emitted into the |
2829 | * ringbuffer itself. | |
a24a11e6 | 2830 | */ |
88fe429d | 2831 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
a6cdb93a | 2832 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
88fe429d | 2833 | |
a6cdb93a | 2834 | for (i = backwards; i; --i) { |
88fe429d DV |
2835 | /* |
2836 | * Be paranoid and presume the hw has gone off into the wild - | |
2837 | * our ring is smaller than what the hardware (and hence | |
2838 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2839 | */ | |
ee1b1e5e | 2840 | head &= ring->buffer->size - 1; |
88fe429d DV |
2841 | |
2842 | /* This here seems to blow up */ | |
ee1b1e5e | 2843 | cmd = ioread32(ring->buffer->virtual_start + head); |
a24a11e6 CW |
2844 | if (cmd == ipehr) |
2845 | break; | |
2846 | ||
88fe429d DV |
2847 | head -= 4; |
2848 | } | |
a24a11e6 | 2849 | |
88fe429d DV |
2850 | if (!i) |
2851 | return NULL; | |
a24a11e6 | 2852 | |
ee1b1e5e | 2853 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
a6cdb93a RV |
2854 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2855 | offset = ioread32(ring->buffer->virtual_start + head + 12); | |
2856 | offset <<= 32; | |
2857 | offset = ioread32(ring->buffer->virtual_start + head + 8); | |
2858 | } | |
2859 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); | |
a24a11e6 CW |
2860 | } |
2861 | ||
a4872ba6 | 2862 | static int semaphore_passed(struct intel_engine_cs *ring) |
6274f212 CW |
2863 | { |
2864 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2865 | struct intel_engine_cs *signaller; |
a0d036b0 | 2866 | u32 seqno; |
6274f212 | 2867 | |
4be17381 | 2868 | ring->hangcheck.deadlock++; |
6274f212 CW |
2869 | |
2870 | signaller = semaphore_waits_for(ring, &seqno); | |
4be17381 CW |
2871 | if (signaller == NULL) |
2872 | return -1; | |
2873 | ||
2874 | /* Prevent pathological recursion due to driver bugs */ | |
2875 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) | |
6274f212 CW |
2876 | return -1; |
2877 | ||
4be17381 CW |
2878 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
2879 | return 1; | |
2880 | ||
a0d036b0 CW |
2881 | /* cursory check for an unkickable deadlock */ |
2882 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
2883 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
2884 | return -1; |
2885 | ||
2886 | return 0; | |
6274f212 CW |
2887 | } |
2888 | ||
2889 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2890 | { | |
a4872ba6 | 2891 | struct intel_engine_cs *ring; |
6274f212 CW |
2892 | int i; |
2893 | ||
2894 | for_each_ring(ring, dev_priv, i) | |
4be17381 | 2895 | ring->hangcheck.deadlock = 0; |
6274f212 CW |
2896 | } |
2897 | ||
ad8beaea | 2898 | static enum intel_ring_hangcheck_action |
a4872ba6 | 2899 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
1ec14ad3 CW |
2900 | { |
2901 | struct drm_device *dev = ring->dev; | |
2902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2903 | u32 tmp; |
2904 | ||
f260fe7b MK |
2905 | if (acthd != ring->hangcheck.acthd) { |
2906 | if (acthd > ring->hangcheck.max_acthd) { | |
2907 | ring->hangcheck.max_acthd = acthd; | |
2908 | return HANGCHECK_ACTIVE; | |
2909 | } | |
2910 | ||
2911 | return HANGCHECK_ACTIVE_LOOP; | |
2912 | } | |
6274f212 | 2913 | |
9107e9d2 | 2914 | if (IS_GEN2(dev)) |
f2f4d82f | 2915 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2916 | |
2917 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2918 | * If so we can simply poke the RB_WAIT bit | |
2919 | * and break the hang. This should work on | |
2920 | * all but the second generation chipsets. | |
2921 | */ | |
2922 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2923 | if (tmp & RING_WAIT) { |
58174462 MK |
2924 | i915_handle_error(dev, false, |
2925 | "Kicking stuck wait on %s", | |
2926 | ring->name); | |
1ec14ad3 | 2927 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2928 | return HANGCHECK_KICK; |
6274f212 CW |
2929 | } |
2930 | ||
2931 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2932 | switch (semaphore_passed(ring)) { | |
2933 | default: | |
f2f4d82f | 2934 | return HANGCHECK_HUNG; |
6274f212 | 2935 | case 1: |
58174462 MK |
2936 | i915_handle_error(dev, false, |
2937 | "Kicking stuck semaphore on %s", | |
2938 | ring->name); | |
6274f212 | 2939 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2940 | return HANGCHECK_KICK; |
6274f212 | 2941 | case 0: |
f2f4d82f | 2942 | return HANGCHECK_WAIT; |
6274f212 | 2943 | } |
9107e9d2 | 2944 | } |
ed5cbb03 | 2945 | |
f2f4d82f | 2946 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2947 | } |
2948 | ||
f65d9421 BG |
2949 | /** |
2950 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2951 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2952 | * if there are no progress, hangcheck score for that ring is increased. | |
2953 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2954 | * we kick the ring. If we see no progress on three subsequent calls | |
2955 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2956 | */ |
a658b5d2 | 2957 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2958 | { |
2959 | struct drm_device *dev = (struct drm_device *)data; | |
2d1013dd | 2960 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2961 | struct intel_engine_cs *ring; |
b4519513 | 2962 | int i; |
05407ff8 | 2963 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2964 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2965 | #define BUSY 1 | |
2966 | #define KICK 5 | |
2967 | #define HUNG 20 | |
893eead0 | 2968 | |
d330a953 | 2969 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2970 | return; |
2971 | ||
b4519513 | 2972 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2973 | u64 acthd; |
2974 | u32 seqno; | |
9107e9d2 | 2975 | bool busy = true; |
05407ff8 | 2976 | |
6274f212 CW |
2977 | semaphore_clear_deadlocks(dev_priv); |
2978 | ||
05407ff8 MK |
2979 | seqno = ring->get_seqno(ring, false); |
2980 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2981 | |
9107e9d2 CW |
2982 | if (ring->hangcheck.seqno == seqno) { |
2983 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2984 | ring->hangcheck.action = HANGCHECK_IDLE; |
2985 | ||
9107e9d2 CW |
2986 | if (waitqueue_active(&ring->irq_queue)) { |
2987 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2988 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2989 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2990 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2991 | ring->name); | |
2992 | else | |
2993 | DRM_INFO("Fake missed irq on %s\n", | |
2994 | ring->name); | |
094f9a54 CW |
2995 | wake_up_all(&ring->irq_queue); |
2996 | } | |
2997 | /* Safeguard against driver failure */ | |
2998 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2999 | } else |
3000 | busy = false; | |
05407ff8 | 3001 | } else { |
6274f212 CW |
3002 | /* We always increment the hangcheck score |
3003 | * if the ring is busy and still processing | |
3004 | * the same request, so that no single request | |
3005 | * can run indefinitely (such as a chain of | |
3006 | * batches). The only time we do not increment | |
3007 | * the hangcheck score on this ring, if this | |
3008 | * ring is in a legitimate wait for another | |
3009 | * ring. In that case the waiting ring is a | |
3010 | * victim and we want to be sure we catch the | |
3011 | * right culprit. Then every time we do kick | |
3012 | * the ring, add a small increment to the | |
3013 | * score so that we can catch a batch that is | |
3014 | * being repeatedly kicked and so responsible | |
3015 | * for stalling the machine. | |
3016 | */ | |
ad8beaea MK |
3017 | ring->hangcheck.action = ring_stuck(ring, |
3018 | acthd); | |
3019 | ||
3020 | switch (ring->hangcheck.action) { | |
da661464 | 3021 | case HANGCHECK_IDLE: |
f2f4d82f | 3022 | case HANGCHECK_WAIT: |
f2f4d82f | 3023 | case HANGCHECK_ACTIVE: |
f260fe7b MK |
3024 | break; |
3025 | case HANGCHECK_ACTIVE_LOOP: | |
ea04cb31 | 3026 | ring->hangcheck.score += BUSY; |
6274f212 | 3027 | break; |
f2f4d82f | 3028 | case HANGCHECK_KICK: |
ea04cb31 | 3029 | ring->hangcheck.score += KICK; |
6274f212 | 3030 | break; |
f2f4d82f | 3031 | case HANGCHECK_HUNG: |
ea04cb31 | 3032 | ring->hangcheck.score += HUNG; |
6274f212 CW |
3033 | stuck[i] = true; |
3034 | break; | |
3035 | } | |
05407ff8 | 3036 | } |
9107e9d2 | 3037 | } else { |
da661464 MK |
3038 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
3039 | ||
9107e9d2 CW |
3040 | /* Gradually reduce the count so that we catch DoS |
3041 | * attempts across multiple batches. | |
3042 | */ | |
3043 | if (ring->hangcheck.score > 0) | |
3044 | ring->hangcheck.score--; | |
f260fe7b MK |
3045 | |
3046 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; | |
d1e61e7f CW |
3047 | } |
3048 | ||
05407ff8 MK |
3049 | ring->hangcheck.seqno = seqno; |
3050 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 3051 | busy_count += busy; |
893eead0 | 3052 | } |
b9201c14 | 3053 | |
92cab734 | 3054 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 3055 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
3056 | DRM_INFO("%s on %s\n", |
3057 | stuck[i] ? "stuck" : "no progress", | |
3058 | ring->name); | |
a43adf07 | 3059 | rings_hung++; |
92cab734 MK |
3060 | } |
3061 | } | |
3062 | ||
05407ff8 | 3063 | if (rings_hung) |
58174462 | 3064 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 3065 | |
05407ff8 MK |
3066 | if (busy_count) |
3067 | /* Reset timer case chip hangs without another request | |
3068 | * being added */ | |
10cd45b6 MK |
3069 | i915_queue_hangcheck(dev); |
3070 | } | |
3071 | ||
3072 | void i915_queue_hangcheck(struct drm_device *dev) | |
3073 | { | |
3074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
672e7b7c CW |
3075 | struct timer_list *timer = &dev_priv->gpu_error.hangcheck_timer; |
3076 | ||
d330a953 | 3077 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
3078 | return; |
3079 | ||
672e7b7c | 3080 | /* Don't continually defer the hangcheck, but make sure it is active */ |
d9e600b2 CW |
3081 | if (timer_pending(timer)) |
3082 | return; | |
3083 | mod_timer(timer, | |
3084 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
3085 | } |
3086 | ||
1c69eb42 | 3087 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
3088 | { |
3089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3090 | ||
3091 | if (HAS_PCH_NOP(dev)) | |
3092 | return; | |
3093 | ||
f86f3fb0 | 3094 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3095 | |
3096 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3097 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3098 | } |
105b122e | 3099 | |
622364b6 PZ |
3100 | /* |
3101 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3102 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3103 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3104 | * only unmask them as needed with SDEIMR. | |
3105 | * | |
3106 | * This function needs to be called before interrupts are enabled. | |
3107 | */ | |
3108 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3109 | { | |
3110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3111 | ||
3112 | if (HAS_PCH_NOP(dev)) | |
3113 | return; | |
3114 | ||
3115 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3116 | I915_WRITE(SDEIER, 0xffffffff); |
3117 | POSTING_READ(SDEIER); | |
3118 | } | |
3119 | ||
7c4d664e | 3120 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3121 | { |
3122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3123 | ||
f86f3fb0 | 3124 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3125 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3126 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3127 | } |
3128 | ||
1da177e4 LT |
3129 | /* drm_dma.h hooks |
3130 | */ | |
be30b29f | 3131 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 3132 | { |
2d1013dd | 3133 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 3134 | |
0c841212 | 3135 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 3136 | |
f86f3fb0 | 3137 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
3138 | if (IS_GEN7(dev)) |
3139 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 3140 | |
7c4d664e | 3141 | gen5_gt_irq_reset(dev); |
c650156a | 3142 | |
1c69eb42 | 3143 | ibx_irq_reset(dev); |
7d99163d | 3144 | } |
c650156a | 3145 | |
70591a41 VS |
3146 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
3147 | { | |
3148 | enum pipe pipe; | |
3149 | ||
3150 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3151 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3152 | ||
3153 | for_each_pipe(dev_priv, pipe) | |
3154 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3155 | ||
3156 | GEN5_IRQ_RESET(VLV_); | |
3157 | } | |
3158 | ||
7e231dbe JB |
3159 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3160 | { | |
2d1013dd | 3161 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3162 | |
7e231dbe JB |
3163 | /* VLV magic */ |
3164 | I915_WRITE(VLV_IMR, 0); | |
3165 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
3166 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
3167 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
3168 | ||
7c4d664e | 3169 | gen5_gt_irq_reset(dev); |
7e231dbe | 3170 | |
7c4cde39 | 3171 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
7e231dbe | 3172 | |
70591a41 | 3173 | vlv_display_irq_reset(dev_priv); |
7e231dbe JB |
3174 | } |
3175 | ||
d6e3cca3 DV |
3176 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3177 | { | |
3178 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3179 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3180 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3181 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3182 | } | |
3183 | ||
823f6b38 | 3184 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3185 | { |
3186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3187 | int pipe; | |
3188 | ||
abd58f01 BW |
3189 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3190 | POSTING_READ(GEN8_MASTER_IRQ); | |
3191 | ||
d6e3cca3 | 3192 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3193 | |
055e393f | 3194 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3195 | if (intel_display_power_is_enabled(dev_priv, |
3196 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3197 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3198 | |
f86f3fb0 PZ |
3199 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3200 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3201 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3202 | |
1c69eb42 | 3203 | ibx_irq_reset(dev); |
abd58f01 | 3204 | } |
09f2344d | 3205 | |
d49bdb0e PZ |
3206 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) |
3207 | { | |
1180e206 | 3208 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
d49bdb0e | 3209 | |
13321786 | 3210 | spin_lock_irq(&dev_priv->irq_lock); |
d49bdb0e | 3211 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], |
1180e206 | 3212 | ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); |
d49bdb0e | 3213 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], |
1180e206 | 3214 | ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); |
13321786 | 3215 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3216 | } |
3217 | ||
43f328d7 VS |
3218 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3219 | { | |
3220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3221 | |
3222 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3223 | POSTING_READ(GEN8_MASTER_IRQ); | |
3224 | ||
d6e3cca3 | 3225 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3226 | |
3227 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3228 | ||
43f328d7 VS |
3229 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
3230 | ||
70591a41 | 3231 | vlv_display_irq_reset(dev_priv); |
43f328d7 VS |
3232 | } |
3233 | ||
82a28bcf | 3234 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3235 | { |
2d1013dd | 3236 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3237 | struct intel_encoder *intel_encoder; |
fee884ed | 3238 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
3239 | |
3240 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3241 | hotplug_irqs = SDE_HOTPLUG_MASK; |
b2784e15 | 3242 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3243 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3244 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 3245 | } else { |
fee884ed | 3246 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
b2784e15 | 3247 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3248 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3249 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 3250 | } |
7fe0b973 | 3251 | |
fee884ed | 3252 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3253 | |
3254 | /* | |
3255 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
3256 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3257 | * | |
3258 | * This register is the same on all known PCH chips. | |
3259 | */ | |
7fe0b973 KP |
3260 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3261 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3262 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3263 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3264 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
3265 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
3266 | } | |
3267 | ||
d46da437 PZ |
3268 | static void ibx_irq_postinstall(struct drm_device *dev) |
3269 | { | |
2d1013dd | 3270 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3271 | u32 mask; |
e5868a31 | 3272 | |
692a04cf DV |
3273 | if (HAS_PCH_NOP(dev)) |
3274 | return; | |
3275 | ||
105b122e | 3276 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3277 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3278 | else |
5c673b60 | 3279 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3280 | |
337ba017 | 3281 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3282 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3283 | } |
3284 | ||
0a9a8c91 DV |
3285 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3286 | { | |
3287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3288 | u32 pm_irqs, gt_irqs; | |
3289 | ||
3290 | pm_irqs = gt_irqs = 0; | |
3291 | ||
3292 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3293 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3294 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3295 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3296 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3297 | } |
3298 | ||
3299 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3300 | if (IS_GEN5(dev)) { | |
3301 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3302 | ILK_BSD_USER_INTERRUPT; | |
3303 | } else { | |
3304 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3305 | } | |
3306 | ||
35079899 | 3307 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3308 | |
3309 | if (INTEL_INFO(dev)->gen >= 6) { | |
a6706b45 | 3310 | pm_irqs |= dev_priv->pm_rps_events; |
0a9a8c91 DV |
3311 | |
3312 | if (HAS_VEBOX(dev)) | |
3313 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3314 | ||
605cd25b | 3315 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3316 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3317 | } |
3318 | } | |
3319 | ||
f71d4af4 | 3320 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3321 | { |
2d1013dd | 3322 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3323 | u32 display_mask, extra_mask; |
3324 | ||
3325 | if (INTEL_INFO(dev)->gen >= 7) { | |
3326 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3327 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3328 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3329 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3330 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 3331 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
3332 | } else { |
3333 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3334 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3335 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3336 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3337 | DE_POISON); | |
5c673b60 DV |
3338 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3339 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3340 | } |
036a4a7d | 3341 | |
1ec14ad3 | 3342 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3343 | |
0c841212 PZ |
3344 | I915_WRITE(HWSTAM, 0xeffe); |
3345 | ||
622364b6 PZ |
3346 | ibx_irq_pre_postinstall(dev); |
3347 | ||
35079899 | 3348 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3349 | |
0a9a8c91 | 3350 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3351 | |
d46da437 | 3352 | ibx_irq_postinstall(dev); |
7fe0b973 | 3353 | |
f97108d1 | 3354 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3355 | /* Enable PCU event interrupts |
3356 | * | |
3357 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3358 | * setup is guaranteed to run in single-threaded context. But we |
3359 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3360 | spin_lock_irq(&dev_priv->irq_lock); |
f97108d1 | 3361 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3362 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3363 | } |
3364 | ||
036a4a7d ZW |
3365 | return 0; |
3366 | } | |
3367 | ||
f8b79e58 ID |
3368 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3369 | { | |
3370 | u32 pipestat_mask; | |
3371 | u32 iir_mask; | |
120dda4f | 3372 | enum pipe pipe; |
f8b79e58 ID |
3373 | |
3374 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3375 | PIPE_FIFO_UNDERRUN_STATUS; | |
3376 | ||
120dda4f VS |
3377 | for_each_pipe(dev_priv, pipe) |
3378 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3379 | POSTING_READ(PIPESTAT(PIPE_A)); |
3380 | ||
3381 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3382 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3383 | ||
120dda4f VS |
3384 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3385 | for_each_pipe(dev_priv, pipe) | |
3386 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3387 | |
3388 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3389 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3390 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
120dda4f VS |
3391 | if (IS_CHERRYVIEW(dev_priv)) |
3392 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3393 | dev_priv->irq_mask &= ~iir_mask; |
3394 | ||
3395 | I915_WRITE(VLV_IIR, iir_mask); | |
3396 | I915_WRITE(VLV_IIR, iir_mask); | |
f8b79e58 | 3397 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
76e41860 VS |
3398 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3399 | POSTING_READ(VLV_IMR); | |
f8b79e58 ID |
3400 | } |
3401 | ||
3402 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3403 | { | |
3404 | u32 pipestat_mask; | |
3405 | u32 iir_mask; | |
120dda4f | 3406 | enum pipe pipe; |
f8b79e58 ID |
3407 | |
3408 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3409 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3410 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
120dda4f VS |
3411 | if (IS_CHERRYVIEW(dev_priv)) |
3412 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3413 | |
3414 | dev_priv->irq_mask |= iir_mask; | |
f8b79e58 | 3415 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
76e41860 | 3416 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
f8b79e58 ID |
3417 | I915_WRITE(VLV_IIR, iir_mask); |
3418 | I915_WRITE(VLV_IIR, iir_mask); | |
3419 | POSTING_READ(VLV_IIR); | |
3420 | ||
3421 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3422 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3423 | ||
120dda4f VS |
3424 | i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3425 | for_each_pipe(dev_priv, pipe) | |
3426 | i915_disable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3427 | |
3428 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3429 | PIPE_FIFO_UNDERRUN_STATUS; | |
120dda4f VS |
3430 | |
3431 | for_each_pipe(dev_priv, pipe) | |
3432 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3433 | POSTING_READ(PIPESTAT(PIPE_A)); |
3434 | } | |
3435 | ||
3436 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3437 | { | |
3438 | assert_spin_locked(&dev_priv->irq_lock); | |
3439 | ||
3440 | if (dev_priv->display_irqs_enabled) | |
3441 | return; | |
3442 | ||
3443 | dev_priv->display_irqs_enabled = true; | |
3444 | ||
950eabaf | 3445 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3446 | valleyview_display_irqs_install(dev_priv); |
3447 | } | |
3448 | ||
3449 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3450 | { | |
3451 | assert_spin_locked(&dev_priv->irq_lock); | |
3452 | ||
3453 | if (!dev_priv->display_irqs_enabled) | |
3454 | return; | |
3455 | ||
3456 | dev_priv->display_irqs_enabled = false; | |
3457 | ||
950eabaf | 3458 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3459 | valleyview_display_irqs_uninstall(dev_priv); |
3460 | } | |
3461 | ||
0e6c9a9e | 3462 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
7e231dbe | 3463 | { |
f8b79e58 | 3464 | dev_priv->irq_mask = ~0; |
7e231dbe | 3465 | |
20afbda2 DV |
3466 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3467 | POSTING_READ(PORT_HOTPLUG_EN); | |
3468 | ||
7e231dbe | 3469 | I915_WRITE(VLV_IIR, 0xffffffff); |
76e41860 VS |
3470 | I915_WRITE(VLV_IIR, 0xffffffff); |
3471 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3472 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3473 | POSTING_READ(VLV_IMR); | |
7e231dbe | 3474 | |
b79480ba DV |
3475 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3476 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3477 | spin_lock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3478 | if (dev_priv->display_irqs_enabled) |
3479 | valleyview_display_irqs_install(dev_priv); | |
d6207435 | 3480 | spin_unlock_irq(&dev_priv->irq_lock); |
0e6c9a9e VS |
3481 | } |
3482 | ||
3483 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3484 | { | |
3485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3486 | ||
3487 | vlv_display_irq_postinstall(dev_priv); | |
7e231dbe | 3488 | |
0a9a8c91 | 3489 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3490 | |
3491 | /* ack & enable invalid PTE error interrupts */ | |
3492 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3493 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3494 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3495 | #endif | |
3496 | ||
3497 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3498 | |
3499 | return 0; | |
3500 | } | |
3501 | ||
abd58f01 BW |
3502 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3503 | { | |
abd58f01 BW |
3504 | /* These are interrupts we'll toggle with the ring mask register */ |
3505 | uint32_t gt_interrupts[] = { | |
3506 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3507 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
abd58f01 | 3508 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
73d477f6 OM |
3509 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3510 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3511 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3512 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3513 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3514 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3515 | 0, |
73d477f6 OM |
3516 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3517 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3518 | }; |
3519 | ||
0961021a | 3520 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3521 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3522 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
3523 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events); | |
3524 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); | |
abd58f01 BW |
3525 | } |
3526 | ||
3527 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3528 | { | |
770de83d DL |
3529 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3530 | uint32_t de_pipe_enables; | |
abd58f01 | 3531 | int pipe; |
88e04703 | 3532 | u32 aux_en = GEN8_AUX_CHANNEL_A; |
770de83d | 3533 | |
88e04703 | 3534 | if (IS_GEN9(dev_priv)) { |
770de83d DL |
3535 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3536 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
88e04703 JB |
3537 | aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3538 | GEN9_AUX_CHANNEL_D; | |
3539 | } else | |
770de83d DL |
3540 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3541 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3542 | ||
3543 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3544 | GEN8_PIPE_FIFO_UNDERRUN; | |
3545 | ||
13b3a0a7 DV |
3546 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3547 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3548 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3549 | |
055e393f | 3550 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3551 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3552 | POWER_DOMAIN_PIPE(pipe))) |
3553 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3554 | dev_priv->de_irq_mask[pipe], | |
3555 | de_pipe_enables); | |
abd58f01 | 3556 | |
88e04703 | 3557 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en); |
abd58f01 BW |
3558 | } |
3559 | ||
3560 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3561 | { | |
3562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3563 | ||
622364b6 PZ |
3564 | ibx_irq_pre_postinstall(dev); |
3565 | ||
abd58f01 BW |
3566 | gen8_gt_irq_postinstall(dev_priv); |
3567 | gen8_de_irq_postinstall(dev_priv); | |
3568 | ||
3569 | ibx_irq_postinstall(dev); | |
3570 | ||
3571 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3572 | POSTING_READ(GEN8_MASTER_IRQ); | |
3573 | ||
3574 | return 0; | |
3575 | } | |
3576 | ||
43f328d7 VS |
3577 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3578 | { | |
3579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 | 3580 | |
c2b66797 | 3581 | vlv_display_irq_postinstall(dev_priv); |
43f328d7 VS |
3582 | |
3583 | gen8_gt_irq_postinstall(dev_priv); | |
3584 | ||
3585 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3586 | POSTING_READ(GEN8_MASTER_IRQ); | |
3587 | ||
3588 | return 0; | |
3589 | } | |
3590 | ||
abd58f01 BW |
3591 | static void gen8_irq_uninstall(struct drm_device *dev) |
3592 | { | |
3593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3594 | |
3595 | if (!dev_priv) | |
3596 | return; | |
3597 | ||
823f6b38 | 3598 | gen8_irq_reset(dev); |
abd58f01 BW |
3599 | } |
3600 | ||
8ea0be4f VS |
3601 | static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv) |
3602 | { | |
3603 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3604 | * just to make the assert_spin_locked check happy. */ | |
3605 | spin_lock_irq(&dev_priv->irq_lock); | |
3606 | if (dev_priv->display_irqs_enabled) | |
3607 | valleyview_display_irqs_uninstall(dev_priv); | |
3608 | spin_unlock_irq(&dev_priv->irq_lock); | |
3609 | ||
3610 | vlv_display_irq_reset(dev_priv); | |
3611 | ||
c352d1ba | 3612 | dev_priv->irq_mask = ~0; |
8ea0be4f VS |
3613 | } |
3614 | ||
7e231dbe JB |
3615 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3616 | { | |
2d1013dd | 3617 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3618 | |
3619 | if (!dev_priv) | |
3620 | return; | |
3621 | ||
843d0e7d ID |
3622 | I915_WRITE(VLV_MASTER_IER, 0); |
3623 | ||
893fce8e VS |
3624 | gen5_gt_irq_reset(dev); |
3625 | ||
7e231dbe | 3626 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3627 | |
8ea0be4f | 3628 | vlv_display_irq_uninstall(dev_priv); |
7e231dbe JB |
3629 | } |
3630 | ||
43f328d7 VS |
3631 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3632 | { | |
3633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3634 | |
3635 | if (!dev_priv) | |
3636 | return; | |
3637 | ||
3638 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3639 | POSTING_READ(GEN8_MASTER_IRQ); | |
3640 | ||
a2c30fba | 3641 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3642 | |
a2c30fba | 3643 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3644 | |
c2b66797 | 3645 | vlv_display_irq_uninstall(dev_priv); |
43f328d7 VS |
3646 | } |
3647 | ||
f71d4af4 | 3648 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3649 | { |
2d1013dd | 3650 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3651 | |
3652 | if (!dev_priv) | |
3653 | return; | |
3654 | ||
be30b29f | 3655 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3656 | } |
3657 | ||
a266c7d5 | 3658 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3659 | { |
2d1013dd | 3660 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3661 | int pipe; |
91e3738e | 3662 | |
055e393f | 3663 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3664 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3665 | I915_WRITE16(IMR, 0xffff); |
3666 | I915_WRITE16(IER, 0x0); | |
3667 | POSTING_READ16(IER); | |
c2798b19 CW |
3668 | } |
3669 | ||
3670 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3671 | { | |
2d1013dd | 3672 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3673 | |
c2798b19 CW |
3674 | I915_WRITE16(EMR, |
3675 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3676 | ||
3677 | /* Unmask the interrupts that we always want on. */ | |
3678 | dev_priv->irq_mask = | |
3679 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3680 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3681 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3682 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3683 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3684 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3685 | ||
3686 | I915_WRITE16(IER, | |
3687 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3688 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3689 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3690 | I915_USER_INTERRUPT); | |
3691 | POSTING_READ16(IER); | |
3692 | ||
379ef82d DV |
3693 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3694 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3695 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3696 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3697 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3698 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3699 | |
c2798b19 CW |
3700 | return 0; |
3701 | } | |
3702 | ||
90a72f87 VS |
3703 | /* |
3704 | * Returns true when a page flip has completed. | |
3705 | */ | |
3706 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3707 | int plane, int pipe, u32 iir) |
90a72f87 | 3708 | { |
2d1013dd | 3709 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3710 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3711 | |
8d7849db | 3712 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3713 | return false; |
3714 | ||
3715 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3716 | goto check_page_flip; |
90a72f87 | 3717 | |
1f1c2e24 | 3718 | intel_prepare_page_flip(dev, plane); |
90a72f87 VS |
3719 | |
3720 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3721 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3722 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3723 | * the flip is completed (no longer pending). Since this doesn't raise | |
3724 | * an interrupt per se, we watch for the change at vblank. | |
3725 | */ | |
3726 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 3727 | goto check_page_flip; |
90a72f87 VS |
3728 | |
3729 | intel_finish_page_flip(dev, pipe); | |
90a72f87 | 3730 | return true; |
d6bbafa1 CW |
3731 | |
3732 | check_page_flip: | |
3733 | intel_check_page_flip(dev, pipe); | |
3734 | return false; | |
90a72f87 VS |
3735 | } |
3736 | ||
ff1f525e | 3737 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3738 | { |
45a83f84 | 3739 | struct drm_device *dev = arg; |
2d1013dd | 3740 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3741 | u16 iir, new_iir; |
3742 | u32 pipe_stats[2]; | |
c2798b19 CW |
3743 | int pipe; |
3744 | u16 flip_mask = | |
3745 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3746 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3747 | ||
c2798b19 CW |
3748 | iir = I915_READ16(IIR); |
3749 | if (iir == 0) | |
3750 | return IRQ_NONE; | |
3751 | ||
3752 | while (iir & ~flip_mask) { | |
3753 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3754 | * have been cleared after the pipestat interrupt was received. | |
3755 | * It doesn't set the bit in iir again, but it still produces | |
3756 | * interrupts (for non-MSI). | |
3757 | */ | |
222c7f51 | 3758 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3759 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3760 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 3761 | |
055e393f | 3762 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3763 | int reg = PIPESTAT(pipe); |
3764 | pipe_stats[pipe] = I915_READ(reg); | |
3765 | ||
3766 | /* | |
3767 | * Clear the PIPE*STAT regs before the IIR | |
3768 | */ | |
2d9d2b0b | 3769 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3770 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3771 | } |
222c7f51 | 3772 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3773 | |
3774 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3775 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3776 | ||
c2798b19 CW |
3777 | if (iir & I915_USER_INTERRUPT) |
3778 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3779 | ||
055e393f | 3780 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 3781 | int plane = pipe; |
3a77c4c4 | 3782 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3783 | plane = !plane; |
3784 | ||
4356d586 | 3785 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3786 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3787 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3788 | |
4356d586 | 3789 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3790 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3791 | |
1f7247c0 DV |
3792 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3793 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3794 | pipe); | |
4356d586 | 3795 | } |
c2798b19 CW |
3796 | |
3797 | iir = new_iir; | |
3798 | } | |
3799 | ||
3800 | return IRQ_HANDLED; | |
3801 | } | |
3802 | ||
3803 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3804 | { | |
2d1013dd | 3805 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3806 | int pipe; |
3807 | ||
055e393f | 3808 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3809 | /* Clear enable bits; then clear status bits */ |
3810 | I915_WRITE(PIPESTAT(pipe), 0); | |
3811 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3812 | } | |
3813 | I915_WRITE16(IMR, 0xffff); | |
3814 | I915_WRITE16(IER, 0x0); | |
3815 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3816 | } | |
3817 | ||
a266c7d5 CW |
3818 | static void i915_irq_preinstall(struct drm_device * dev) |
3819 | { | |
2d1013dd | 3820 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3821 | int pipe; |
3822 | ||
a266c7d5 CW |
3823 | if (I915_HAS_HOTPLUG(dev)) { |
3824 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3825 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3826 | } | |
3827 | ||
00d98ebd | 3828 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3829 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3830 | I915_WRITE(PIPESTAT(pipe), 0); |
3831 | I915_WRITE(IMR, 0xffffffff); | |
3832 | I915_WRITE(IER, 0x0); | |
3833 | POSTING_READ(IER); | |
3834 | } | |
3835 | ||
3836 | static int i915_irq_postinstall(struct drm_device *dev) | |
3837 | { | |
2d1013dd | 3838 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3839 | u32 enable_mask; |
a266c7d5 | 3840 | |
38bde180 CW |
3841 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3842 | ||
3843 | /* Unmask the interrupts that we always want on. */ | |
3844 | dev_priv->irq_mask = | |
3845 | ~(I915_ASLE_INTERRUPT | | |
3846 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3847 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3848 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3849 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3850 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3851 | ||
3852 | enable_mask = | |
3853 | I915_ASLE_INTERRUPT | | |
3854 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3855 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3856 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3857 | I915_USER_INTERRUPT; | |
3858 | ||
a266c7d5 | 3859 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3860 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3861 | POSTING_READ(PORT_HOTPLUG_EN); | |
3862 | ||
a266c7d5 CW |
3863 | /* Enable in IER... */ |
3864 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3865 | /* and unmask in IMR */ | |
3866 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3867 | } | |
3868 | ||
a266c7d5 CW |
3869 | I915_WRITE(IMR, dev_priv->irq_mask); |
3870 | I915_WRITE(IER, enable_mask); | |
3871 | POSTING_READ(IER); | |
3872 | ||
f49e38dd | 3873 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3874 | |
379ef82d DV |
3875 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3876 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3877 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3878 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3879 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3880 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3881 | |
20afbda2 DV |
3882 | return 0; |
3883 | } | |
3884 | ||
90a72f87 VS |
3885 | /* |
3886 | * Returns true when a page flip has completed. | |
3887 | */ | |
3888 | static bool i915_handle_vblank(struct drm_device *dev, | |
3889 | int plane, int pipe, u32 iir) | |
3890 | { | |
2d1013dd | 3891 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3892 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3893 | ||
8d7849db | 3894 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3895 | return false; |
3896 | ||
3897 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3898 | goto check_page_flip; |
90a72f87 VS |
3899 | |
3900 | intel_prepare_page_flip(dev, plane); | |
3901 | ||
3902 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3903 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3904 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3905 | * the flip is completed (no longer pending). Since this doesn't raise | |
3906 | * an interrupt per se, we watch for the change at vblank. | |
3907 | */ | |
3908 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 3909 | goto check_page_flip; |
90a72f87 VS |
3910 | |
3911 | intel_finish_page_flip(dev, pipe); | |
90a72f87 | 3912 | return true; |
d6bbafa1 CW |
3913 | |
3914 | check_page_flip: | |
3915 | intel_check_page_flip(dev, pipe); | |
3916 | return false; | |
90a72f87 VS |
3917 | } |
3918 | ||
ff1f525e | 3919 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3920 | { |
45a83f84 | 3921 | struct drm_device *dev = arg; |
2d1013dd | 3922 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3923 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
3924 | u32 flip_mask = |
3925 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3926 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3927 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3928 | |
a266c7d5 | 3929 | iir = I915_READ(IIR); |
38bde180 CW |
3930 | do { |
3931 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3932 | bool blc_event = false; |
a266c7d5 CW |
3933 | |
3934 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3935 | * have been cleared after the pipestat interrupt was received. | |
3936 | * It doesn't set the bit in iir again, but it still produces | |
3937 | * interrupts (for non-MSI). | |
3938 | */ | |
222c7f51 | 3939 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3940 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3941 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 3942 | |
055e393f | 3943 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
3944 | int reg = PIPESTAT(pipe); |
3945 | pipe_stats[pipe] = I915_READ(reg); | |
3946 | ||
38bde180 | 3947 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3948 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3949 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3950 | irq_received = true; |
a266c7d5 CW |
3951 | } |
3952 | } | |
222c7f51 | 3953 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
3954 | |
3955 | if (!irq_received) | |
3956 | break; | |
3957 | ||
a266c7d5 | 3958 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
3959 | if (I915_HAS_HOTPLUG(dev) && |
3960 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
3961 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3962 | |
38bde180 | 3963 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3964 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3965 | ||
a266c7d5 CW |
3966 | if (iir & I915_USER_INTERRUPT) |
3967 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3968 | |
055e393f | 3969 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 3970 | int plane = pipe; |
3a77c4c4 | 3971 | if (HAS_FBC(dev)) |
38bde180 | 3972 | plane = !plane; |
90a72f87 | 3973 | |
8291ee90 | 3974 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3975 | i915_handle_vblank(dev, plane, pipe, iir)) |
3976 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3977 | |
3978 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3979 | blc_event = true; | |
4356d586 DV |
3980 | |
3981 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3982 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3983 | |
1f7247c0 DV |
3984 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3985 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3986 | pipe); | |
a266c7d5 CW |
3987 | } |
3988 | ||
a266c7d5 CW |
3989 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3990 | intel_opregion_asle_intr(dev); | |
3991 | ||
3992 | /* With MSI, interrupts are only generated when iir | |
3993 | * transitions from zero to nonzero. If another bit got | |
3994 | * set while we were handling the existing iir bits, then | |
3995 | * we would never get another interrupt. | |
3996 | * | |
3997 | * This is fine on non-MSI as well, as if we hit this path | |
3998 | * we avoid exiting the interrupt handler only to generate | |
3999 | * another one. | |
4000 | * | |
4001 | * Note that for MSI this could cause a stray interrupt report | |
4002 | * if an interrupt landed in the time between writing IIR and | |
4003 | * the posting read. This should be rare enough to never | |
4004 | * trigger the 99% of 100,000 interrupts test for disabling | |
4005 | * stray interrupts. | |
4006 | */ | |
38bde180 | 4007 | ret = IRQ_HANDLED; |
a266c7d5 | 4008 | iir = new_iir; |
38bde180 | 4009 | } while (iir & ~flip_mask); |
a266c7d5 CW |
4010 | |
4011 | return ret; | |
4012 | } | |
4013 | ||
4014 | static void i915_irq_uninstall(struct drm_device * dev) | |
4015 | { | |
2d1013dd | 4016 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4017 | int pipe; |
4018 | ||
a266c7d5 CW |
4019 | if (I915_HAS_HOTPLUG(dev)) { |
4020 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
4021 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
4022 | } | |
4023 | ||
00d98ebd | 4024 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 4025 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 4026 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 4027 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4028 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4029 | } | |
a266c7d5 CW |
4030 | I915_WRITE(IMR, 0xffffffff); |
4031 | I915_WRITE(IER, 0x0); | |
4032 | ||
a266c7d5 CW |
4033 | I915_WRITE(IIR, I915_READ(IIR)); |
4034 | } | |
4035 | ||
4036 | static void i965_irq_preinstall(struct drm_device * dev) | |
4037 | { | |
2d1013dd | 4038 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4039 | int pipe; |
4040 | ||
adca4730 CW |
4041 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4042 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4043 | |
4044 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4045 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4046 | I915_WRITE(PIPESTAT(pipe), 0); |
4047 | I915_WRITE(IMR, 0xffffffff); | |
4048 | I915_WRITE(IER, 0x0); | |
4049 | POSTING_READ(IER); | |
4050 | } | |
4051 | ||
4052 | static int i965_irq_postinstall(struct drm_device *dev) | |
4053 | { | |
2d1013dd | 4054 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4055 | u32 enable_mask; |
a266c7d5 CW |
4056 | u32 error_mask; |
4057 | ||
a266c7d5 | 4058 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4059 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4060 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4061 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4062 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4063 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4064 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4065 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4066 | ||
4067 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4068 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4069 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4070 | enable_mask |= I915_USER_INTERRUPT; |
4071 | ||
4072 | if (IS_G4X(dev)) | |
4073 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 4074 | |
b79480ba DV |
4075 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4076 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4077 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4078 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4079 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4080 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4081 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4082 | |
a266c7d5 CW |
4083 | /* |
4084 | * Enable some error detection, note the instruction error mask | |
4085 | * bit is reserved, so we leave it masked. | |
4086 | */ | |
4087 | if (IS_G4X(dev)) { | |
4088 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4089 | GM45_ERROR_MEM_PRIV | | |
4090 | GM45_ERROR_CP_PRIV | | |
4091 | I915_ERROR_MEMORY_REFRESH); | |
4092 | } else { | |
4093 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4094 | I915_ERROR_MEMORY_REFRESH); | |
4095 | } | |
4096 | I915_WRITE(EMR, error_mask); | |
4097 | ||
4098 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4099 | I915_WRITE(IER, enable_mask); | |
4100 | POSTING_READ(IER); | |
4101 | ||
20afbda2 DV |
4102 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4103 | POSTING_READ(PORT_HOTPLUG_EN); | |
4104 | ||
f49e38dd | 4105 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4106 | |
4107 | return 0; | |
4108 | } | |
4109 | ||
bac56d5b | 4110 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4111 | { |
2d1013dd | 4112 | struct drm_i915_private *dev_priv = dev->dev_private; |
cd569aed | 4113 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
4114 | u32 hotplug_en; |
4115 | ||
b5ea2d56 DV |
4116 | assert_spin_locked(&dev_priv->irq_lock); |
4117 | ||
bac56d5b EE |
4118 | if (I915_HAS_HOTPLUG(dev)) { |
4119 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
4120 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
4121 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 4122 | /* enable bits are the same for all generations */ |
b2784e15 | 4123 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed EE |
4124 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
4125 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
4126 | /* Programming the CRT detection parameters tends |
4127 | to generate a spurious hotplug event about three | |
4128 | seconds later. So just do it once. | |
4129 | */ | |
4130 | if (IS_G4X(dev)) | |
4131 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 4132 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 4133 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 4134 | |
bac56d5b EE |
4135 | /* Ignore TV since it's buggy */ |
4136 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
4137 | } | |
a266c7d5 CW |
4138 | } |
4139 | ||
ff1f525e | 4140 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4141 | { |
45a83f84 | 4142 | struct drm_device *dev = arg; |
2d1013dd | 4143 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4144 | u32 iir, new_iir; |
4145 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4146 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4147 | u32 flip_mask = |
4148 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4149 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4150 | |
a266c7d5 CW |
4151 | iir = I915_READ(IIR); |
4152 | ||
a266c7d5 | 4153 | for (;;) { |
501e01d7 | 4154 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4155 | bool blc_event = false; |
4156 | ||
a266c7d5 CW |
4157 | /* Can't rely on pipestat interrupt bit in iir as it might |
4158 | * have been cleared after the pipestat interrupt was received. | |
4159 | * It doesn't set the bit in iir again, but it still produces | |
4160 | * interrupts (for non-MSI). | |
4161 | */ | |
222c7f51 | 4162 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4163 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4164 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4165 | |
055e393f | 4166 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4167 | int reg = PIPESTAT(pipe); |
4168 | pipe_stats[pipe] = I915_READ(reg); | |
4169 | ||
4170 | /* | |
4171 | * Clear the PIPE*STAT regs before the IIR | |
4172 | */ | |
4173 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4174 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4175 | irq_received = true; |
a266c7d5 CW |
4176 | } |
4177 | } | |
222c7f51 | 4178 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4179 | |
4180 | if (!irq_received) | |
4181 | break; | |
4182 | ||
4183 | ret = IRQ_HANDLED; | |
4184 | ||
4185 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
4186 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
4187 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4188 | |
21ad8330 | 4189 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4190 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4191 | ||
a266c7d5 CW |
4192 | if (iir & I915_USER_INTERRUPT) |
4193 | notify_ring(dev, &dev_priv->ring[RCS]); | |
4194 | if (iir & I915_BSD_USER_INTERRUPT) | |
4195 | notify_ring(dev, &dev_priv->ring[VCS]); | |
4196 | ||
055e393f | 4197 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 4198 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4199 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4200 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4201 | |
4202 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4203 | blc_event = true; | |
4356d586 DV |
4204 | |
4205 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4206 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4207 | |
1f7247c0 DV |
4208 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4209 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4210 | } |
a266c7d5 CW |
4211 | |
4212 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4213 | intel_opregion_asle_intr(dev); | |
4214 | ||
515ac2bb DV |
4215 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4216 | gmbus_irq_handler(dev); | |
4217 | ||
a266c7d5 CW |
4218 | /* With MSI, interrupts are only generated when iir |
4219 | * transitions from zero to nonzero. If another bit got | |
4220 | * set while we were handling the existing iir bits, then | |
4221 | * we would never get another interrupt. | |
4222 | * | |
4223 | * This is fine on non-MSI as well, as if we hit this path | |
4224 | * we avoid exiting the interrupt handler only to generate | |
4225 | * another one. | |
4226 | * | |
4227 | * Note that for MSI this could cause a stray interrupt report | |
4228 | * if an interrupt landed in the time between writing IIR and | |
4229 | * the posting read. This should be rare enough to never | |
4230 | * trigger the 99% of 100,000 interrupts test for disabling | |
4231 | * stray interrupts. | |
4232 | */ | |
4233 | iir = new_iir; | |
4234 | } | |
4235 | ||
4236 | return ret; | |
4237 | } | |
4238 | ||
4239 | static void i965_irq_uninstall(struct drm_device * dev) | |
4240 | { | |
2d1013dd | 4241 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4242 | int pipe; |
4243 | ||
4244 | if (!dev_priv) | |
4245 | return; | |
4246 | ||
adca4730 CW |
4247 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4248 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4249 | |
4250 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4251 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4252 | I915_WRITE(PIPESTAT(pipe), 0); |
4253 | I915_WRITE(IMR, 0xffffffff); | |
4254 | I915_WRITE(IER, 0x0); | |
4255 | ||
055e393f | 4256 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4257 | I915_WRITE(PIPESTAT(pipe), |
4258 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4259 | I915_WRITE(IIR, I915_READ(IIR)); | |
4260 | } | |
4261 | ||
4cb21832 | 4262 | static void intel_hpd_irq_reenable_work(struct work_struct *work) |
ac4c16c5 | 4263 | { |
6323751d ID |
4264 | struct drm_i915_private *dev_priv = |
4265 | container_of(work, typeof(*dev_priv), | |
4266 | hotplug_reenable_work.work); | |
ac4c16c5 EE |
4267 | struct drm_device *dev = dev_priv->dev; |
4268 | struct drm_mode_config *mode_config = &dev->mode_config; | |
ac4c16c5 EE |
4269 | int i; |
4270 | ||
6323751d ID |
4271 | intel_runtime_pm_get(dev_priv); |
4272 | ||
4cb21832 | 4273 | spin_lock_irq(&dev_priv->irq_lock); |
ac4c16c5 EE |
4274 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
4275 | struct drm_connector *connector; | |
4276 | ||
4277 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
4278 | continue; | |
4279 | ||
4280 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4281 | ||
4282 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4283 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4284 | ||
4285 | if (intel_connector->encoder->hpd_pin == i) { | |
4286 | if (connector->polled != intel_connector->polled) | |
4287 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
c23cc417 | 4288 | connector->name); |
ac4c16c5 EE |
4289 | connector->polled = intel_connector->polled; |
4290 | if (!connector->polled) | |
4291 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4292 | } | |
4293 | } | |
4294 | } | |
4295 | if (dev_priv->display.hpd_irq_setup) | |
4296 | dev_priv->display.hpd_irq_setup(dev); | |
4cb21832 | 4297 | spin_unlock_irq(&dev_priv->irq_lock); |
6323751d ID |
4298 | |
4299 | intel_runtime_pm_put(dev_priv); | |
ac4c16c5 EE |
4300 | } |
4301 | ||
fca52a55 DV |
4302 | /** |
4303 | * intel_irq_init - initializes irq support | |
4304 | * @dev_priv: i915 device instance | |
4305 | * | |
4306 | * This function initializes all the irq support including work items, timers | |
4307 | * and all the vtables. It does not setup the interrupt itself though. | |
4308 | */ | |
b963291c | 4309 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4310 | { |
b963291c | 4311 | struct drm_device *dev = dev_priv->dev; |
8b2e326d CW |
4312 | |
4313 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
13cf5504 | 4314 | INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func); |
99584db3 | 4315 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 4316 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4317 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4318 | |
a6706b45 | 4319 | /* Let's track the enabled rps events */ |
b963291c | 4320 | if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6c65a587 | 4321 | /* WaGsvRC0ResidencyMethod:vlv */ |
31685c25 D |
4322 | dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; |
4323 | else | |
4324 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4325 | |
99584db3 DV |
4326 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
4327 | i915_hangcheck_elapsed, | |
61bac78e | 4328 | (unsigned long) dev); |
6323751d | 4329 | INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, |
4cb21832 | 4330 | intel_hpd_irq_reenable_work); |
61bac78e | 4331 | |
97a19a24 | 4332 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4333 | |
b963291c | 4334 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4335 | dev->max_vblank_count = 0; |
4336 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4337 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 JB |
4338 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4339 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4340 | } else { |
4341 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4342 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4343 | } |
4344 | ||
21da2700 VS |
4345 | /* |
4346 | * Opt out of the vblank disable timer on everything except gen2. | |
4347 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4348 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4349 | */ | |
b963291c | 4350 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4351 | dev->vblank_disable_immediate = true; |
4352 | ||
c2baf4b7 | 4353 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 4354 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
4355 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
4356 | } | |
f71d4af4 | 4357 | |
b963291c | 4358 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4359 | dev->driver->irq_handler = cherryview_irq_handler; |
4360 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4361 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4362 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4363 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4364 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4365 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4366 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4367 | dev->driver->irq_handler = valleyview_irq_handler; |
4368 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4369 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4370 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4371 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4372 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4373 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4374 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4375 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4376 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4377 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4378 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4379 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4380 | dev->driver->disable_vblank = gen8_disable_vblank; | |
4381 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
4382 | } else if (HAS_PCH_SPLIT(dev)) { |
4383 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4384 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4385 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4386 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4387 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4388 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4389 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4390 | } else { |
b963291c | 4391 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4392 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4393 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4394 | dev->driver->irq_handler = i8xx_irq_handler; | |
4395 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4396 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4397 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4398 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4399 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4400 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 4401 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4402 | } else { |
a266c7d5 CW |
4403 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4404 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4405 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4406 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 4407 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4408 | } |
f71d4af4 JB |
4409 | dev->driver->enable_vblank = i915_enable_vblank; |
4410 | dev->driver->disable_vblank = i915_disable_vblank; | |
4411 | } | |
4412 | } | |
20afbda2 | 4413 | |
fca52a55 DV |
4414 | /** |
4415 | * intel_hpd_init - initializes and enables hpd support | |
4416 | * @dev_priv: i915 device instance | |
4417 | * | |
4418 | * This function enables the hotplug support. It requires that interrupts have | |
4419 | * already been enabled with intel_irq_init_hw(). From this point on hotplug and | |
4420 | * poll request can run concurrently to other code, so locking rules must be | |
4421 | * obeyed. | |
4422 | * | |
4423 | * This is a separate step from interrupt enabling to simplify the locking rules | |
4424 | * in the driver load and resume code. | |
4425 | */ | |
b963291c | 4426 | void intel_hpd_init(struct drm_i915_private *dev_priv) |
20afbda2 | 4427 | { |
b963291c | 4428 | struct drm_device *dev = dev_priv->dev; |
821450c6 EE |
4429 | struct drm_mode_config *mode_config = &dev->mode_config; |
4430 | struct drm_connector *connector; | |
4431 | int i; | |
20afbda2 | 4432 | |
821450c6 EE |
4433 | for (i = 1; i < HPD_NUM_PINS; i++) { |
4434 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
4435 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4436 | } | |
4437 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4438 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4439 | connector->polled = intel_connector->polled; | |
0e32b39c DA |
4440 | if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) |
4441 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4442 | if (intel_connector->mst_port) | |
821450c6 EE |
4443 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
4444 | } | |
b5ea2d56 DV |
4445 | |
4446 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
4447 | * just to make the assert_spin_locked checks happy. */ | |
d6207435 | 4448 | spin_lock_irq(&dev_priv->irq_lock); |
20afbda2 DV |
4449 | if (dev_priv->display.hpd_irq_setup) |
4450 | dev_priv->display.hpd_irq_setup(dev); | |
d6207435 | 4451 | spin_unlock_irq(&dev_priv->irq_lock); |
20afbda2 | 4452 | } |
c67a470b | 4453 | |
fca52a55 DV |
4454 | /** |
4455 | * intel_irq_install - enables the hardware interrupt | |
4456 | * @dev_priv: i915 device instance | |
4457 | * | |
4458 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4459 | * handling still disabled. It is called after intel_irq_init(). | |
4460 | * | |
4461 | * In the driver load and resume code we need working interrupts in a few places | |
4462 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4463 | * workers. Hence the split into this two-stage approach. | |
4464 | */ | |
2aeb7d3a DV |
4465 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4466 | { | |
4467 | /* | |
4468 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4469 | * interrupts as enabled _before_ actually enabling them to avoid | |
4470 | * special cases in our ordering checks. | |
4471 | */ | |
4472 | dev_priv->pm.irqs_enabled = true; | |
4473 | ||
4474 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4475 | } | |
4476 | ||
fca52a55 DV |
4477 | /** |
4478 | * intel_irq_uninstall - finilizes all irq handling | |
4479 | * @dev_priv: i915 device instance | |
4480 | * | |
4481 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4482 | * resources acquired in the init functions. | |
4483 | */ | |
2aeb7d3a DV |
4484 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4485 | { | |
4486 | drm_irq_uninstall(dev_priv->dev); | |
4487 | intel_hpd_cancel_work(dev_priv); | |
4488 | dev_priv->pm.irqs_enabled = false; | |
4489 | } | |
4490 | ||
fca52a55 DV |
4491 | /** |
4492 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4493 | * @dev_priv: i915 device instance | |
4494 | * | |
4495 | * This function is used to disable interrupts at runtime, both in the runtime | |
4496 | * pm and the system suspend/resume code. | |
4497 | */ | |
b963291c | 4498 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4499 | { |
b963291c | 4500 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4501 | dev_priv->pm.irqs_enabled = false; |
c67a470b PZ |
4502 | } |
4503 | ||
fca52a55 DV |
4504 | /** |
4505 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4506 | * @dev_priv: i915 device instance | |
4507 | * | |
4508 | * This function is used to enable interrupts at runtime, both in the runtime | |
4509 | * pm and the system suspend/resume code. | |
4510 | */ | |
b963291c | 4511 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4512 | { |
2aeb7d3a | 4513 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4514 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4515 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4516 | } |