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drm/i915: irq handlers don't need interrupt-safe spinlocks
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
e5868a31
EE		 73static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
036a4a7d 82/* For display hotplug interrupt */
995b6762 83static void
f2b115e6 84ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 85{
4bc9d430
DV		 86 assert_spin_locked(&dev_priv->irq_lock);
87
1ec14ad3
CW		 88 if ((dev_priv->irq_mask & mask) != 0) {
89 dev_priv->irq_mask &= ~mask;
90 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 91 POSTING_READ(DEIMR);
036a4a7d
ZW		 92 }
93}
94
0ff9800a 95static void
f2b115e6 96ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 97{
4bc9d430
DV		 98 assert_spin_locked(&dev_priv->irq_lock);
99
1ec14ad3
CW		 100 if ((dev_priv->irq_mask & mask) != mask) {
101 dev_priv->irq_mask |= mask;
102 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 103 POSTING_READ(DEIMR);
036a4a7d
ZW		 104 }
105}
106
8664281b
PZ		 107static bool ivb_can_enable_err_int(struct drm_device *dev)
108{
109 struct drm_i915_private *dev_priv = dev->dev_private;
110 struct intel_crtc *crtc;
111 enum pipe pipe;
112
4bc9d430
DV		 113 assert_spin_locked(&dev_priv->irq_lock);
114
8664281b
PZ		 115 for_each_pipe(pipe) {
116 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
117
118 if (crtc->cpu_fifo_underrun_disabled)
119 return false;
120 }
121
122 return true;
123}
124
125static bool cpt_can_enable_serr_int(struct drm_device *dev)
126{
127 struct drm_i915_private *dev_priv = dev->dev_private;
128 enum pipe pipe;
129 struct intel_crtc *crtc;
130
fee884ed
DV		 131 assert_spin_locked(&dev_priv->irq_lock);
132
8664281b
PZ		 133 for_each_pipe(pipe) {
134 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
135
136 if (crtc->pch_fifo_underrun_disabled)
137 return false;
138 }
139
140 return true;
141}
142
143static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
144 enum pipe pipe, bool enable)
145{
146 struct drm_i915_private *dev_priv = dev->dev_private;
147 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
148 DE_PIPEB_FIFO_UNDERRUN;
149
150 if (enable)
151 ironlake_enable_display_irq(dev_priv, bit);
152 else
153 ironlake_disable_display_irq(dev_priv, bit);
154}
155
156static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
7336df65 157 enum pipe pipe, bool enable)
8664281b
PZ		 158{
159 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 160 if (enable) {
7336df65
DV		 161 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
162
8664281b
PZ		 163 if (!ivb_can_enable_err_int(dev))
164 return;
165
8664281b
PZ		 166 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
167 } else {
7336df65
DV		 168 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
169
170 /* Change the state _after_ we've read out the current one. */
8664281b 171 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65
DV		 172
173 if (!was_enabled &&
174 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
175 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
176 pipe_name(pipe));
177 }
8664281b
PZ		 178 }
179}
180
fee884ed
DV		 181/**
182 * ibx_display_interrupt_update - update SDEIMR
183 * @dev_priv: driver private
184 * @interrupt_mask: mask of interrupt bits to update
185 * @enabled_irq_mask: mask of interrupt bits to enable
186 */
187static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
188 uint32_t interrupt_mask,
189 uint32_t enabled_irq_mask)
190{
191 uint32_t sdeimr = I915_READ(SDEIMR);
192 sdeimr &= ~interrupt_mask;
193 sdeimr |= (~enabled_irq_mask & interrupt_mask);
194
195 assert_spin_locked(&dev_priv->irq_lock);
196
197 I915_WRITE(SDEIMR, sdeimr);
198 POSTING_READ(SDEIMR);
199}
200#define ibx_enable_display_interrupt(dev_priv, bits) \
201 ibx_display_interrupt_update((dev_priv), (bits), (bits))
202#define ibx_disable_display_interrupt(dev_priv, bits) \
203 ibx_display_interrupt_update((dev_priv), (bits), 0)
204
de28075d
DV		 205static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
206 enum transcoder pch_transcoder,
8664281b
PZ		 207 bool enable)
208{
8664281b 209 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 210 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
211 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 212
213 if (enable)
fee884ed 214 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 215 else
fee884ed 216 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 217}
218
219static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
220 enum transcoder pch_transcoder,
221 bool enable)
222{
223 struct drm_i915_private *dev_priv = dev->dev_private;
224
225 if (enable) {
1dd246fb
DV		 226 I915_WRITE(SERR_INT,
227 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
228
8664281b
PZ		 229 if (!cpt_can_enable_serr_int(dev))
230 return;
231
fee884ed 232 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 233 } else {
1dd246fb
DV		 234 uint32_t tmp = I915_READ(SERR_INT);
235 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
236
237 /* Change the state _after_ we've read out the current one. */
fee884ed 238 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb
DV		 239
240 if (!was_enabled &&
241 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
242 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
243 transcoder_name(pch_transcoder));
244 }
8664281b 245 }
8664281b
PZ		 246}
247
248/**
249 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
250 * @dev: drm device
251 * @pipe: pipe
252 * @enable: true if we want to report FIFO underrun errors, false otherwise
253 *
254 * This function makes us disable or enable CPU fifo underruns for a specific
255 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
256 * reporting for one pipe may also disable all the other CPU error interruts for
257 * the other pipes, due to the fact that there's just one interrupt mask/enable
258 * bit for all the pipes.
259 *
260 * Returns the previous state of underrun reporting.
261 */
262bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
263 enum pipe pipe, bool enable)
264{
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
268 unsigned long flags;
269 bool ret;
270
271 spin_lock_irqsave(&dev_priv->irq_lock, flags);
272
273 ret = !intel_crtc->cpu_fifo_underrun_disabled;
274
275 if (enable == ret)
276 goto done;
277
278 intel_crtc->cpu_fifo_underrun_disabled = !enable;
279
280 if (IS_GEN5(dev) || IS_GEN6(dev))
281 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
282 else if (IS_GEN7(dev))
7336df65 283 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b
PZ		 284
285done:
286 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
287 return ret;
288}
289
290/**
291 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
292 * @dev: drm device
293 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
294 * @enable: true if we want to report FIFO underrun errors, false otherwise
295 *
296 * This function makes us disable or enable PCH fifo underruns for a specific
297 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
298 * underrun reporting for one transcoder may also disable all the other PCH
299 * error interruts for the other transcoders, due to the fact that there's just
300 * one interrupt mask/enable bit for all the transcoders.
301 *
302 * Returns the previous state of underrun reporting.
303 */
304bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
305 enum transcoder pch_transcoder,
306 bool enable)
307{
308 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 309 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 311 unsigned long flags;
312 bool ret;
313
de28075d
DV		 314 /*
315 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
316 * has only one pch transcoder A that all pipes can use. To avoid racy
317 * pch transcoder -> pipe lookups from interrupt code simply store the
318 * underrun statistics in crtc A. Since we never expose this anywhere
319 * nor use it outside of the fifo underrun code here using the "wrong"
320 * crtc on LPT won't cause issues.
321 */
8664281b
PZ		 322
323 spin_lock_irqsave(&dev_priv->irq_lock, flags);
324
325 ret = !intel_crtc->pch_fifo_underrun_disabled;
326
327 if (enable == ret)
328 goto done;
329
330 intel_crtc->pch_fifo_underrun_disabled = !enable;
331
332 if (HAS_PCH_IBX(dev))
de28075d 333 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b
PZ		 334 else
335 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
336
337done:
338 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
339 return ret;
340}
341
342
7c463586
KP		 343void
344i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
345{
46c06a30
VS		 346 u32 reg = PIPESTAT(pipe);
347 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 348
b79480ba
DV		 349 assert_spin_locked(&dev_priv->irq_lock);
350
46c06a30
VS		 351 if ((pipestat & mask) == mask)
352 return;
353
354 /* Enable the interrupt, clear any pending status */
355 pipestat |= mask | (mask >> 16);
356 I915_WRITE(reg, pipestat);
357 POSTING_READ(reg);
7c463586
KP		 358}
359
360void
361i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
362{
46c06a30
VS		 363 u32 reg = PIPESTAT(pipe);
364 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 365
b79480ba
DV		 366 assert_spin_locked(&dev_priv->irq_lock);
367
46c06a30
VS		 368 if ((pipestat & mask) == 0)
369 return;
370
371 pipestat &= ~mask;
372 I915_WRITE(reg, pipestat);
373 POSTING_READ(reg);
7c463586
KP		 374}
375
01c66889 376/**
f49e38dd 377 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 378 */
f49e38dd 379static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 380{
1ec14ad3
CW		 381 drm_i915_private_t *dev_priv = dev->dev_private;
382 unsigned long irqflags;
383
f49e38dd
JN		 384 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
385 return;
386
1ec14ad3 387 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 388
f898780b
JN		 389 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
390 if (INTEL_INFO(dev)->gen >= 4)
391 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 392
393 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 394}
395
0a3e67a4
JB		 396/**
397 * i915_pipe_enabled - check if a pipe is enabled
398 * @dev: DRM device
399 * @pipe: pipe to check
400 *
401 * Reading certain registers when the pipe is disabled can hang the chip.
402 * Use this routine to make sure the PLL is running and the pipe is active
403 * before reading such registers if unsure.
404 */
405static int
406i915_pipe_enabled(struct drm_device *dev, int pipe)
407{
408 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 409
a01025af
DV		 410 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
411 /* Locking is horribly broken here, but whatever. */
412 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 414
a01025af
DV		 415 return intel_crtc->active;
416 } else {
417 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
418 }
0a3e67a4
JB		 419}
420
42f52ef8
KP		 421/* Called from drm generic code, passed a 'crtc', which
422 * we use as a pipe index
423 */
f71d4af4 424static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 425{
426 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
427 unsigned long high_frame;
428 unsigned long low_frame;
5eddb70b 429 u32 high1, high2, low;
0a3e67a4
JB		 430
431 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 432 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 433 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 434 return 0;
435 }
436
9db4a9c7
JB		 437 high_frame = PIPEFRAME(pipe);
438 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 439
0a3e67a4
JB		 440 /*
441 * High & low register fields aren't synchronized, so make sure
442 * we get a low value that's stable across two reads of the high
443 * register.
444 */
445 do {
5eddb70b
CW		 446 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
447 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
448 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 449 } while (high1 != high2);
450
5eddb70b
CW		 451 high1 >>= PIPE_FRAME_HIGH_SHIFT;
452 low >>= PIPE_FRAME_LOW_SHIFT;
453 return (high1 << 8) | low;
0a3e67a4
JB		 454}
455
f71d4af4 456static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 457{
458 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 459 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 460
461 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 462 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 463 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 464 return 0;
465 }
466
467 return I915_READ(reg);
468}
469
f71d4af4 470static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 471 int *vpos, int *hpos)
472{
473 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
474 u32 vbl = 0, position = 0;
475 int vbl_start, vbl_end, htotal, vtotal;
476 bool in_vbl = true;
477 int ret = 0;
fe2b8f9d
PZ		 478 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
479 pipe);
0af7e4df
MK		 480
481 if (!i915_pipe_enabled(dev, pipe)) {
482 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 483 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 484 return 0;
485 }
486
487 /* Get vtotal. */
fe2b8f9d 488 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 489
490 if (INTEL_INFO(dev)->gen >= 4) {
491 /* No obvious pixelcount register. Only query vertical
492 * scanout position from Display scan line register.
493 */
494 position = I915_READ(PIPEDSL(pipe));
495
496 /* Decode into vertical scanout position. Don't have
497 * horizontal scanout position.
498 */
499 *vpos = position & 0x1fff;
500 *hpos = 0;
501 } else {
502 /* Have access to pixelcount since start of frame.
503 * We can split this into vertical and horizontal
504 * scanout position.
505 */
506 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
507
fe2b8f9d 508 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 509 *vpos = position / htotal;
510 *hpos = position - (*vpos * htotal);
511 }
512
513 /* Query vblank area. */
fe2b8f9d 514 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 515
516 /* Test position against vblank region. */
517 vbl_start = vbl & 0x1fff;
518 vbl_end = (vbl >> 16) & 0x1fff;
519
520 if ((*vpos < vbl_start) || (*vpos > vbl_end))
521 in_vbl = false;
522
523 /* Inside "upper part" of vblank area? Apply corrective offset: */
524 if (in_vbl && (*vpos >= vbl_start))
525 *vpos = *vpos - vtotal;
526
527 /* Readouts valid? */
528 if (vbl > 0)
529 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
530
531 /* In vblank? */
532 if (in_vbl)
533 ret |= DRM_SCANOUTPOS_INVBL;
534
535 return ret;
536}
537
f71d4af4 538static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 539 int *max_error,
540 struct timeval *vblank_time,
541 unsigned flags)
542{
4041b853 543 struct drm_crtc *crtc;
0af7e4df 544
7eb552ae 545 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 546 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 547 return -EINVAL;
548 }
549
550 /* Get drm_crtc to timestamp: */
4041b853
CW		 551 crtc = intel_get_crtc_for_pipe(dev, pipe);
552 if (crtc == NULL) {
553 DRM_ERROR("Invalid crtc %d\n", pipe);
554 return -EINVAL;
555 }
556
557 if (!crtc->enabled) {
558 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
559 return -EBUSY;
560 }
0af7e4df
MK		 561
562 /* Helper routine in DRM core does all the work: */
4041b853
CW		 563 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
564 vblank_time, flags,
565 crtc);
0af7e4df
MK		 566}
567
321a1b30
EE		 568static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
569{
570 enum drm_connector_status old_status;
571
572 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
573 old_status = connector->status;
574
575 connector->status = connector->funcs->detect(connector, false);
576 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
577 connector->base.id,
578 drm_get_connector_name(connector),
579 old_status, connector->status);
580 return (old_status != connector->status);
581}
582
5ca58282
JB		 583/*
584 * Handle hotplug events outside the interrupt handler proper.
585 */
ac4c16c5
EE		 586#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
587
5ca58282
JB		 588static void i915_hotplug_work_func(struct work_struct *work)
589{
590 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
591 hotplug_work);
592 struct drm_device *dev = dev_priv->dev;
c31c4ba3 593 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 594 struct intel_connector *intel_connector;
595 struct intel_encoder *intel_encoder;
596 struct drm_connector *connector;
597 unsigned long irqflags;
598 bool hpd_disabled = false;
321a1b30 599 bool changed = false;
142e2398 600 u32 hpd_event_bits;
4ef69c7a 601
52d7eced
DV		 602 /* HPD irq before everything is fully set up. */
603 if (!dev_priv->enable_hotplug_processing)
604 return;
605
a65e34c7 606 mutex_lock(&mode_config->mutex);
e67189ab
JB		 607 DRM_DEBUG_KMS("running encoder hotplug functions\n");
608
cd569aed 609 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 610
611 hpd_event_bits = dev_priv->hpd_event_bits;
612 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 613 list_for_each_entry(connector, &mode_config->connector_list, head) {
614 intel_connector = to_intel_connector(connector);
615 intel_encoder = intel_connector->encoder;
616 if (intel_encoder->hpd_pin > HPD_NONE &&
617 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
618 connector->polled == DRM_CONNECTOR_POLL_HPD) {
619 DRM_INFO("HPD interrupt storm detected on connector %s: "
620 "switching from hotplug detection to polling\n",
621 drm_get_connector_name(connector));
622 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
623 connector->polled = DRM_CONNECTOR_POLL_CONNECT
624 | DRM_CONNECTOR_POLL_DISCONNECT;
625 hpd_disabled = true;
626 }
142e2398
EE		 627 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
628 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
629 drm_get_connector_name(connector), intel_encoder->hpd_pin);
630 }
cd569aed
EE		 631 }
632 /* if there were no outputs to poll, poll was disabled,
633 * therefore make sure it's enabled when disabling HPD on
634 * some connectors */
ac4c16c5 635 if (hpd_disabled) {
cd569aed 636 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 637 mod_timer(&dev_priv->hotplug_reenable_timer,
638 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
639 }
cd569aed
EE		 640
641 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
642
321a1b30
EE		 643 list_for_each_entry(connector, &mode_config->connector_list, head) {
644 intel_connector = to_intel_connector(connector);
645 intel_encoder = intel_connector->encoder;
646 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
647 if (intel_encoder->hot_plug)
648 intel_encoder->hot_plug(intel_encoder);
649 if (intel_hpd_irq_event(dev, connector))
650 changed = true;
651 }
652 }
40ee3381
KP		 653 mutex_unlock(&mode_config->mutex);
654
321a1b30
EE		 655 if (changed)
656 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 657}
658
d0ecd7e2 659static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1
JB		 660{
661 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 662 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 663 u8 new_delay;
9270388e 664
d0ecd7e2 665 spin_lock(&mchdev_lock);
f97108d1 666
73edd18f
DV		 667 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
668
20e4d407 669 new_delay = dev_priv->ips.cur_delay;
9270388e 670
7648fa99 671 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 672 busy_up = I915_READ(RCPREVBSYTUPAVG);
673 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 674 max_avg = I915_READ(RCBMAXAVG);
675 min_avg = I915_READ(RCBMINAVG);
676
677 /* Handle RCS change request from hw */
b5b72e89 678 if (busy_up > max_avg) {
20e4d407
DV		 679 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
680 new_delay = dev_priv->ips.cur_delay - 1;
681 if (new_delay < dev_priv->ips.max_delay)
682 new_delay = dev_priv->ips.max_delay;
b5b72e89 683 } else if (busy_down < min_avg) {
20e4d407
DV		 684 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
685 new_delay = dev_priv->ips.cur_delay + 1;
686 if (new_delay > dev_priv->ips.min_delay)
687 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 688 }
689
7648fa99 690 if (ironlake_set_drps(dev, new_delay))
20e4d407 691 dev_priv->ips.cur_delay = new_delay;
f97108d1 692
d0ecd7e2 693 spin_unlock(&mchdev_lock);
9270388e 694
f97108d1
JB		 695 return;
696}
697
549f7365
CW		 698static void notify_ring(struct drm_device *dev,
699 struct intel_ring_buffer *ring)
700{
701 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 702
475553de
CW		 703 if (ring->obj == NULL)
704 return;
705
b2eadbc8 706 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 707
549f7365 708 wake_up_all(&ring->irq_queue);
3e0dc6b0 709 if (i915_enable_hangcheck) {
99584db3 710 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 711 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 712 }
549f7365
CW		 713}
714
4912d041 715static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 716{
4912d041 717 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 718 rps.work);
4912d041 719 u32 pm_iir, pm_imr;
7b9e0ae6 720 u8 new_delay;
4912d041 721
c6a828d3
DV		 722 spin_lock_irq(&dev_priv->rps.lock);
723 pm_iir = dev_priv->rps.pm_iir;
724 dev_priv->rps.pm_iir = 0;
4912d041 725 pm_imr = I915_READ(GEN6_PMIMR);
4848405c
BW		 726 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
727 I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
c6a828d3 728 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 729
4848405c 730 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 731 return;
732
4fc688ce 733 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 734
7425034a 735 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
c6a828d3 736 new_delay = dev_priv->rps.cur_delay + 1;
7425034a
VS		 737
738 /*
739 * For better performance, jump directly
740 * to RPe if we're below it.
741 */
742 if (IS_VALLEYVIEW(dev_priv->dev) &&
743 dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
744 new_delay = dev_priv->rps.rpe_delay;
745 } else
c6a828d3 746 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 747
79249636
BW		 748 /* sysfs frequency interfaces may have snuck in while servicing the
749 * interrupt
750 */
d8289c9e
VS		 751 if (new_delay >= dev_priv->rps.min_delay &&
752 new_delay <= dev_priv->rps.max_delay) {
0a073b84
JB		 753 if (IS_VALLEYVIEW(dev_priv->dev))
754 valleyview_set_rps(dev_priv->dev, new_delay);
755 else
756 gen6_set_rps(dev_priv->dev, new_delay);
79249636 757 }
3b8d8d91 758
52ceb908
JB		 759 if (IS_VALLEYVIEW(dev_priv->dev)) {
760 /*
761 * On VLV, when we enter RC6 we may not be at the minimum
762 * voltage level, so arm a timer to check. It should only
763 * fire when there's activity or once after we've entered
764 * RC6, and then won't be re-armed until the next RPS interrupt.
765 */
766 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
767 msecs_to_jiffies(100));
768 }
769
4fc688ce 770 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 771}
772
e3689190
BW		 773
774/**
775 * ivybridge_parity_work - Workqueue called when a parity error interrupt
776 * occurred.
777 * @work: workqueue struct
778 *
779 * Doesn't actually do anything except notify userspace. As a consequence of
780 * this event, userspace should try to remap the bad rows since statistically
781 * it is likely the same row is more likely to go bad again.
782 */
783static void ivybridge_parity_work(struct work_struct *work)
784{
785 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 786 l3_parity.error_work);
e3689190
BW		 787 u32 error_status, row, bank, subbank;
788 char *parity_event[5];
789 uint32_t misccpctl;
790 unsigned long flags;
791
792 /* We must turn off DOP level clock gating to access the L3 registers.
793 * In order to prevent a get/put style interface, acquire struct mutex
794 * any time we access those registers.
795 */
796 mutex_lock(&dev_priv->dev->struct_mutex);
797
798 misccpctl = I915_READ(GEN7_MISCCPCTL);
799 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
800 POSTING_READ(GEN7_MISCCPCTL);
801
802 error_status = I915_READ(GEN7_L3CDERRST1);
803 row = GEN7_PARITY_ERROR_ROW(error_status);
804 bank = GEN7_PARITY_ERROR_BANK(error_status);
805 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
806
807 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
808 GEN7_L3CDERRST1_ENABLE);
809 POSTING_READ(GEN7_L3CDERRST1);
810
811 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
812
813 spin_lock_irqsave(&dev_priv->irq_lock, flags);
cc609d5d 814 dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
e3689190
BW		 815 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
816 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
817
818 mutex_unlock(&dev_priv->dev->struct_mutex);
819
820 parity_event[0] = "L3_PARITY_ERROR=1";
821 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
822 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
823 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
824 parity_event[4] = NULL;
825
826 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
827 KOBJ_CHANGE, parity_event);
828
829 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
830 row, bank, subbank);
831
832 kfree(parity_event[3]);
833 kfree(parity_event[2]);
834 kfree(parity_event[1]);
835}
836
d0ecd7e2 837static void ivybridge_parity_error_irq_handler(struct drm_device *dev)
e3689190
BW		 838{
839 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e3689190 840
e1ef7cc2 841 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 842 return;
843
d0ecd7e2 844 spin_lock(&dev_priv->irq_lock);
cc609d5d 845 dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
e3689190 846 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
d0ecd7e2 847 spin_unlock(&dev_priv->irq_lock);
e3689190 848
a4da4fa4 849 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 850}
851
e7b4c6b1
DV		 852static void snb_gt_irq_handler(struct drm_device *dev,
853 struct drm_i915_private *dev_priv,
854 u32 gt_iir)
855{
856
cc609d5d
BW		 857 if (gt_iir &
858 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 859 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 860 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 861 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 862 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 863 notify_ring(dev, &dev_priv->ring[BCS]);
864
cc609d5d
BW		 865 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
866 GT_BSD_CS_ERROR_INTERRUPT |
867 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 868 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
869 i915_handle_error(dev, false);
870 }
e3689190 871
cc609d5d 872 if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
d0ecd7e2 873 ivybridge_parity_error_irq_handler(dev);
e7b4c6b1
DV		 874}
875
baf02a1f 876/* Legacy way of handling PM interrupts */
d0ecd7e2
DV		 877static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv,
878 u32 pm_iir)
fc6826d1 879{
fc6826d1
CW		 880 /*
881 * IIR bits should never already be set because IMR should
882 * prevent an interrupt from being shown in IIR. The warning
883 * displays a case where we've unsafely cleared
c6a828d3 884 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 885 * type is not a problem, it displays a problem in the logic.
886 *
c6a828d3 887 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 888 */
889
d0ecd7e2 890 spin_lock(&dev_priv->rps.lock);
c6a828d3
DV		 891 dev_priv->rps.pm_iir |= pm_iir;
892 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 893 POSTING_READ(GEN6_PMIMR);
d0ecd7e2 894 spin_unlock(&dev_priv->rps.lock);
fc6826d1 895
c6a828d3 896 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 897}
898
b543fb04
EE		 899#define HPD_STORM_DETECT_PERIOD 1000
900#define HPD_STORM_THRESHOLD 5
901
10a504de 902static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 903 u32 hotplug_trigger,
904 const u32 *hpd)
b543fb04
EE		 905{
906 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 907 int i;
10a504de 908 bool storm_detected = false;
b543fb04 909
91d131d2
DV		 910 if (!hotplug_trigger)
911 return;
912
b5ea2d56 913 spin_lock(&dev_priv->irq_lock);
b543fb04 914 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 915
b543fb04
EE		 916 if (!(hpd[i] & hotplug_trigger) ||
917 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
918 continue;
919
bc5ead8c 920 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 921 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
922 dev_priv->hpd_stats[i].hpd_last_jiffies
923 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
924 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
925 dev_priv->hpd_stats[i].hpd_cnt = 0;
926 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
927 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 928 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 929 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 930 storm_detected = true;
b543fb04
EE		 931 } else {
932 dev_priv->hpd_stats[i].hpd_cnt++;
933 }
934 }
935
10a504de
DV		 936 if (storm_detected)
937 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 938 spin_unlock(&dev_priv->irq_lock);
5876fa0d
DV		 939
940 queue_work(dev_priv->wq,
941 &dev_priv->hotplug_work);
b543fb04
EE		 942}
943
515ac2bb
DV		 944static void gmbus_irq_handler(struct drm_device *dev)
945{
28c70f16
DV		 946 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
947
28c70f16 948 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 949}
950
ce99c256
DV		 951static void dp_aux_irq_handler(struct drm_device *dev)
952{
9ee32fea
DV		 953 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
954
9ee32fea 955 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 956}
957
d0ecd7e2 958/* Unlike gen6_rps_irq_handler() from which this function is originally derived,
baf02a1f
BW		 959 * we must be able to deal with other PM interrupts. This is complicated because
960 * of the way in which we use the masks to defer the RPS work (which for
961 * posterity is necessary because of forcewake).
962 */
963static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
964 u32 pm_iir)
965{
d0ecd7e2 966 spin_lock(&dev_priv->rps.lock);
4848405c 967 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
baf02a1f
BW		 968 if (dev_priv->rps.pm_iir) {
969 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
970 /* never want to mask useful interrupts. (also posting read) */
4848405c 971 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
baf02a1f
BW		 972 /* TODO: if queue_work is slow, move it out of the spinlock */
973 queue_work(dev_priv->wq, &dev_priv->rps.work);
974 }
d0ecd7e2 975 spin_unlock(&dev_priv->rps.lock);
baf02a1f 976
12638c57
BW		 977 if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
978 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
979 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
980
981 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
982 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
983 i915_handle_error(dev_priv->dev, false);
984 }
985 }
baf02a1f
BW		 986}
987
ff1f525e 988static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 989{
990 struct drm_device *dev = (struct drm_device *) arg;
991 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
992 u32 iir, gt_iir, pm_iir;
993 irqreturn_t ret = IRQ_NONE;
994 unsigned long irqflags;
995 int pipe;
996 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 997
998 atomic_inc(&dev_priv->irq_received);
999
7e231dbe
JB		 1000 while (true) {
1001 iir = I915_READ(VLV_IIR);
1002 gt_iir = I915_READ(GTIIR);
1003 pm_iir = I915_READ(GEN6_PMIIR);
1004
1005 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1006 goto out;
1007
1008 ret = IRQ_HANDLED;
1009
e7b4c6b1 1010 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 1011
1012 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1013 for_each_pipe(pipe) {
1014 int reg = PIPESTAT(pipe);
1015 pipe_stats[pipe] = I915_READ(reg);
1016
1017 /*
1018 * Clear the PIPE*STAT regs before the IIR
1019 */
1020 if (pipe_stats[pipe] & 0x8000ffff) {
1021 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1022 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1023 pipe_name(pipe));
1024 I915_WRITE(reg, pipe_stats[pipe]);
1025 }
1026 }
1027 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1028
31acc7f5
JB		 1029 for_each_pipe(pipe) {
1030 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1031 drm_handle_vblank(dev, pipe);
1032
1033 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1034 intel_prepare_page_flip(dev, pipe);
1035 intel_finish_page_flip(dev, pipe);
1036 }
1037 }
1038
7e231dbe
JB		 1039 /* Consume port. Then clear IIR or we'll miss events */
1040 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1041 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1042 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 1043
1044 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1045 hotplug_status);
91d131d2
DV		 1046
1047 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1048
7e231dbe
JB		 1049 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1050 I915_READ(PORT_HOTPLUG_STAT);
1051 }
1052
515ac2bb
DV		 1053 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1054 gmbus_irq_handler(dev);
7e231dbe 1055
4848405c 1056 if (pm_iir & GEN6_PM_RPS_EVENTS)
d0ecd7e2 1057 gen6_rps_irq_handler(dev_priv, pm_iir);
7e231dbe
JB		 1058
1059 I915_WRITE(GTIIR, gt_iir);
1060 I915_WRITE(GEN6_PMIIR, pm_iir);
1061 I915_WRITE(VLV_IIR, iir);
1062 }
1063
1064out:
1065 return ret;
1066}
1067
23e81d69 1068static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1069{
1070 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1071 int pipe;
b543fb04 1072 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1073
91d131d2
DV		 1074 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1075
cfc33bf7
VS		 1076 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1077 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1078 SDE_AUDIO_POWER_SHIFT);
776ad806 1079 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1080 port_name(port));
1081 }
776ad806 1082
ce99c256
DV		 1083 if (pch_iir & SDE_AUX_MASK)
1084 dp_aux_irq_handler(dev);
1085
776ad806 1086 if (pch_iir & SDE_GMBUS)
515ac2bb 1087 gmbus_irq_handler(dev);
776ad806
JB		 1088
1089 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1090 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1091
1092 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1093 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1094
1095 if (pch_iir & SDE_POISON)
1096 DRM_ERROR("PCH poison interrupt\n");
1097
9db4a9c7
JB		 1098 if (pch_iir & SDE_FDI_MASK)
1099 for_each_pipe(pipe)
1100 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1101 pipe_name(pipe),
1102 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1103
1104 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1105 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1106
1107 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1108 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1109
776ad806 1110 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1111 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1112 false))
1113 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1114
1115 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1116 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1117 false))
1118 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1119}
1120
1121static void ivb_err_int_handler(struct drm_device *dev)
1122{
1123 struct drm_i915_private *dev_priv = dev->dev_private;
1124 u32 err_int = I915_READ(GEN7_ERR_INT);
1125
de032bf4
PZ		 1126 if (err_int & ERR_INT_POISON)
1127 DRM_ERROR("Poison interrupt\n");
1128
8664281b
PZ		 1129 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1130 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1131 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1132
1133 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1134 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1135 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1136
1137 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1138 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1139 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1140
1141 I915_WRITE(GEN7_ERR_INT, err_int);
1142}
1143
1144static void cpt_serr_int_handler(struct drm_device *dev)
1145{
1146 struct drm_i915_private *dev_priv = dev->dev_private;
1147 u32 serr_int = I915_READ(SERR_INT);
1148
de032bf4
PZ		 1149 if (serr_int & SERR_INT_POISON)
1150 DRM_ERROR("PCH poison interrupt\n");
1151
8664281b
PZ		 1152 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1153 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1154 false))
1155 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1156
1157 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1158 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1159 false))
1160 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1161
1162 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1163 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1164 false))
1165 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1166
1167 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1168}
1169
23e81d69
AJ		 1170static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1171{
1172 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1173 int pipe;
b543fb04 1174 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1175
91d131d2
DV		 1176 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1177
cfc33bf7
VS		 1178 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1179 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1180 SDE_AUDIO_POWER_SHIFT_CPT);
1181 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1182 port_name(port));
1183 }
23e81d69
AJ		 1184
1185 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1186 dp_aux_irq_handler(dev);
23e81d69
AJ		 1187
1188 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1189 gmbus_irq_handler(dev);
23e81d69
AJ		 1190
1191 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1192 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1193
1194 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1195 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1196
1197 if (pch_iir & SDE_FDI_MASK_CPT)
1198 for_each_pipe(pipe)
1199 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1200 pipe_name(pipe),
1201 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1202
1203 if (pch_iir & SDE_ERROR_CPT)
1204 cpt_serr_int_handler(dev);
23e81d69
AJ		 1205}
1206
ff1f525e 1207static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1208{
1209 struct drm_device *dev = (struct drm_device *) arg;
1210 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
ab5c608b 1211 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
0e43406b
CW		 1212 irqreturn_t ret = IRQ_NONE;
1213 int i;
b1f14ad0
JB		 1214
1215 atomic_inc(&dev_priv->irq_received);
1216
8664281b
PZ		 1217 /* We get interrupts on unclaimed registers, so check for this before we
1218 * do any I915_{READ,WRITE}. */
1219 if (IS_HASWELL(dev) &&
1220 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1221 DRM_ERROR("Unclaimed register before interrupt\n");
1222 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1223 }
1224
b1f14ad0
JB		 1225 /* disable master interrupt before clearing iir */
1226 de_ier = I915_READ(DEIER);
1227 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 1228
44498aea
PZ		 1229 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1230 * interrupts will will be stored on its back queue, and then we'll be
1231 * able to process them after we restore SDEIER (as soon as we restore
1232 * it, we'll get an interrupt if SDEIIR still has something to process
1233 * due to its back queue). */
ab5c608b
BW		 1234 if (!HAS_PCH_NOP(dev)) {
1235 sde_ier = I915_READ(SDEIER);
1236 I915_WRITE(SDEIER, 0);
1237 POSTING_READ(SDEIER);
1238 }
44498aea 1239
8664281b
PZ		 1240 /* On Haswell, also mask ERR_INT because we don't want to risk
1241 * generating "unclaimed register" interrupts from inside the interrupt
1242 * handler. */
4bc9d430
DV		 1243 if (IS_HASWELL(dev)) {
1244 spin_lock(&dev_priv->irq_lock);
8664281b 1245 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
4bc9d430
DV		 1246 spin_unlock(&dev_priv->irq_lock);
1247 }
8664281b 1248
b1f14ad0 1249 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 1250 if (gt_iir) {
1251 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1252 I915_WRITE(GTIIR, gt_iir);
1253 ret = IRQ_HANDLED;
b1f14ad0
JB		 1254 }
1255
0e43406b
CW		 1256 de_iir = I915_READ(DEIIR);
1257 if (de_iir) {
8664281b
PZ		 1258 if (de_iir & DE_ERR_INT_IVB)
1259 ivb_err_int_handler(dev);
1260
ce99c256
DV		 1261 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1262 dp_aux_irq_handler(dev);
1263
0e43406b 1264 if (de_iir & DE_GSE_IVB)
81a07809 1265 intel_opregion_asle_intr(dev);
0e43406b
CW		 1266
1267 for (i = 0; i < 3; i++) {
74d44445
DV		 1268 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1269 drm_handle_vblank(dev, i);
0e43406b
CW		 1270 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1271 intel_prepare_page_flip(dev, i);
1272 intel_finish_page_flip_plane(dev, i);
1273 }
0e43406b 1274 }
b615b57a 1275
0e43406b 1276 /* check event from PCH */
ab5c608b 1277 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
0e43406b 1278 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 1279
23e81d69 1280 cpt_irq_handler(dev, pch_iir);
b1f14ad0 1281
0e43406b
CW		 1282 /* clear PCH hotplug event before clear CPU irq */
1283 I915_WRITE(SDEIIR, pch_iir);
1284 }
b615b57a 1285
0e43406b
CW		 1286 I915_WRITE(DEIIR, de_iir);
1287 ret = IRQ_HANDLED;
b1f14ad0
JB		 1288 }
1289
0e43406b
CW		 1290 pm_iir = I915_READ(GEN6_PMIIR);
1291 if (pm_iir) {
baf02a1f
BW		 1292 if (IS_HASWELL(dev))
1293 hsw_pm_irq_handler(dev_priv, pm_iir);
4848405c 1294 else if (pm_iir & GEN6_PM_RPS_EVENTS)
d0ecd7e2 1295 gen6_rps_irq_handler(dev_priv, pm_iir);
0e43406b
CW		 1296 I915_WRITE(GEN6_PMIIR, pm_iir);
1297 ret = IRQ_HANDLED;
1298 }
b1f14ad0 1299
4bc9d430
DV		 1300 if (IS_HASWELL(dev)) {
1301 spin_lock(&dev_priv->irq_lock);
1302 if (ivb_can_enable_err_int(dev))
1303 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1304 spin_unlock(&dev_priv->irq_lock);
1305 }
8664281b 1306
b1f14ad0
JB		 1307 I915_WRITE(DEIER, de_ier);
1308 POSTING_READ(DEIER);
ab5c608b
BW		 1309 if (!HAS_PCH_NOP(dev)) {
1310 I915_WRITE(SDEIER, sde_ier);
1311 POSTING_READ(SDEIER);
1312 }
b1f14ad0
JB		 1313
1314 return ret;
1315}
1316
e7b4c6b1
DV		 1317static void ilk_gt_irq_handler(struct drm_device *dev,
1318 struct drm_i915_private *dev_priv,
1319 u32 gt_iir)
1320{
cc609d5d
BW		 1321 if (gt_iir &
1322 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1323 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1324 if (gt_iir & ILK_BSD_USER_INTERRUPT)
e7b4c6b1
DV		 1325 notify_ring(dev, &dev_priv->ring[VCS]);
1326}
1327
ff1f525e 1328static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 1329{
4697995b 1330 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 1331 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1332 int ret = IRQ_NONE;
44498aea 1333 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
881f47b6 1334
4697995b
JB		 1335 atomic_inc(&dev_priv->irq_received);
1336
2d109a84
ZN		 1337 /* disable master interrupt before clearing iir */
1338 de_ier = I915_READ(DEIER);
1339 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 1340 POSTING_READ(DEIER);
2d109a84 1341
44498aea
PZ		 1342 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1343 * interrupts will will be stored on its back queue, and then we'll be
1344 * able to process them after we restore SDEIER (as soon as we restore
1345 * it, we'll get an interrupt if SDEIIR still has something to process
1346 * due to its back queue). */
1347 sde_ier = I915_READ(SDEIER);
1348 I915_WRITE(SDEIER, 0);
1349 POSTING_READ(SDEIER);
1350
036a4a7d
ZW		 1351 de_iir = I915_READ(DEIIR);
1352 gt_iir = I915_READ(GTIIR);
3b8d8d91 1353 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 1354
acd15b6c 1355 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 1356 goto done;
036a4a7d 1357
c7c85101 1358 ret = IRQ_HANDLED;
036a4a7d 1359
e7b4c6b1
DV		 1360 if (IS_GEN5(dev))
1361 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1362 else
1363 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 1364
ce99c256
DV		 1365 if (de_iir & DE_AUX_CHANNEL_A)
1366 dp_aux_irq_handler(dev);
1367
c7c85101 1368 if (de_iir & DE_GSE)
81a07809 1369 intel_opregion_asle_intr(dev);
c650156a 1370
74d44445
DV		 1371 if (de_iir & DE_PIPEA_VBLANK)
1372 drm_handle_vblank(dev, 0);
1373
1374 if (de_iir & DE_PIPEB_VBLANK)
1375 drm_handle_vblank(dev, 1);
1376
de032bf4
PZ		 1377 if (de_iir & DE_POISON)
1378 DRM_ERROR("Poison interrupt\n");
1379
8664281b
PZ		 1380 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1381 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1382 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1383
1384 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1385 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1386 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1387
f072d2e7 1388 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 1389 intel_prepare_page_flip(dev, 0);
2bbda389 1390 intel_finish_page_flip_plane(dev, 0);
f072d2e7 1391 }
013d5aa2 1392
f072d2e7 1393 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 1394 intel_prepare_page_flip(dev, 1);
2bbda389 1395 intel_finish_page_flip_plane(dev, 1);
f072d2e7 1396 }
013d5aa2 1397
c7c85101 1398 /* check event from PCH */
776ad806 1399 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 1400 u32 pch_iir = I915_READ(SDEIIR);
1401
23e81d69
AJ		 1402 if (HAS_PCH_CPT(dev))
1403 cpt_irq_handler(dev, pch_iir);
1404 else
1405 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 1406
1407 /* should clear PCH hotplug event before clear CPU irq */
1408 I915_WRITE(SDEIIR, pch_iir);
776ad806 1409 }
036a4a7d 1410
73edd18f 1411 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
d0ecd7e2 1412 ironlake_rps_change_irq_handler(dev);
f97108d1 1413
4848405c 1414 if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
d0ecd7e2 1415 gen6_rps_irq_handler(dev_priv, pm_iir);
3b8d8d91 1416
c7c85101
ZN		 1417 I915_WRITE(GTIIR, gt_iir);
1418 I915_WRITE(DEIIR, de_iir);
4912d041 1419 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 1420
1421done:
2d109a84 1422 I915_WRITE(DEIER, de_ier);
3143a2bf 1423 POSTING_READ(DEIER);
44498aea
PZ		 1424 I915_WRITE(SDEIER, sde_ier);
1425 POSTING_READ(SDEIER);
2d109a84 1426
036a4a7d
ZW		 1427 return ret;
1428}
1429
8a905236
JB		 1430/**
1431 * i915_error_work_func - do process context error handling work
1432 * @work: work struct
1433 *
1434 * Fire an error uevent so userspace can see that a hang or error
1435 * was detected.
1436 */
1437static void i915_error_work_func(struct work_struct *work)
1438{
1f83fee0
DV		 1439 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1440 work);
1441 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1442 gpu_error);
8a905236 1443 struct drm_device *dev = dev_priv->dev;
f69061be 1444 struct intel_ring_buffer *ring;
f316a42c
BG		 1445 char *error_event[] = { "ERROR=1", NULL };
1446 char *reset_event[] = { "RESET=1", NULL };
1447 char *reset_done_event[] = { "ERROR=0", NULL };
f69061be 1448 int i, ret;
8a905236 1449
f316a42c
BG		 1450 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1451
7db0ba24
DV		 1452 /*
1453 * Note that there's only one work item which does gpu resets, so we
1454 * need not worry about concurrent gpu resets potentially incrementing
1455 * error->reset_counter twice. We only need to take care of another
1456 * racing irq/hangcheck declaring the gpu dead for a second time. A
1457 * quick check for that is good enough: schedule_work ensures the
1458 * correct ordering between hang detection and this work item, and since
1459 * the reset in-progress bit is only ever set by code outside of this
1460 * work we don't need to worry about any other races.
1461 */
1462 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1463 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1464 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1465 reset_event);
1f83fee0 1466
f69061be
DV		 1467 ret = i915_reset(dev);
1468
1469 if (ret == 0) {
1470 /*
1471 * After all the gem state is reset, increment the reset
1472 * counter and wake up everyone waiting for the reset to
1473 * complete.
1474 *
1475 * Since unlock operations are a one-sided barrier only,
1476 * we need to insert a barrier here to order any seqno
1477 * updates before
1478 * the counter increment.
1479 */
1480 smp_mb__before_atomic_inc();
1481 atomic_inc(&dev_priv->gpu_error.reset_counter);
1482
1483 kobject_uevent_env(&dev->primary->kdev.kobj,
1484 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1485 } else {
1486 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1487 }
1f83fee0 1488
f69061be
DV		 1489 for_each_ring(ring, dev_priv, i)
1490 wake_up_all(&ring->irq_queue);
1491
96a02917
VS		 1492 intel_display_handle_reset(dev);
1493
1f83fee0 1494 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 1495 }
8a905236
JB		 1496}
1497
85f9e50d
DV		 1498/* NB: please notice the memset */
1499static void i915_get_extra_instdone(struct drm_device *dev,
1500 uint32_t *instdone)
1501{
1502 struct drm_i915_private *dev_priv = dev->dev_private;
1503 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1504
1505 switch(INTEL_INFO(dev)->gen) {
1506 case 2:
1507 case 3:
1508 instdone[0] = I915_READ(INSTDONE);
1509 break;
1510 case 4:
1511 case 5:
1512 case 6:
1513 instdone[0] = I915_READ(INSTDONE_I965);
1514 instdone[1] = I915_READ(INSTDONE1);
1515 break;
1516 default:
1517 WARN_ONCE(1, "Unsupported platform\n");
1518 case 7:
1519 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1520 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1521 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1522 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1523 break;
1524 }
1525}
1526
3bd3c932 1527#ifdef CONFIG_DEBUG_FS
9df30794 1528static struct drm_i915_error_object *
d0d045e8
BW		 1529i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1530 struct drm_i915_gem_object *src,
1531 const int num_pages)
9df30794
CW		 1532{
1533 struct drm_i915_error_object *dst;
d0d045e8 1534 int i;
e56660dd 1535 u32 reloc_offset;
9df30794 1536
05394f39 1537 if (src == NULL || src->pages == NULL)
9df30794
CW		 1538 return NULL;
1539
d0d045e8 1540 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 1541 if (dst == NULL)
1542 return NULL;
1543
f343c5f6 1544 reloc_offset = dst->gtt_offset = i915_gem_obj_ggtt_offset(src);
d0d045e8 1545 for (i = 0; i < num_pages; i++) {
788885ae 1546 unsigned long flags;
e56660dd 1547 void *d;
788885ae 1548
e56660dd 1549 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 1550 if (d == NULL)
1551 goto unwind;
e56660dd 1552
788885ae 1553 local_irq_save(flags);
5d4545ae 1554 if (reloc_offset < dev_priv->gtt.mappable_end &&
74898d7e 1555 src->has_global_gtt_mapping) {
172975aa
CW		 1556 void __iomem *s;
1557
1558 /* Simply ignore tiling or any overlapping fence.
1559 * It's part of the error state, and this hopefully
1560 * captures what the GPU read.
1561 */
1562
5d4545ae 1563 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
172975aa
CW		 1564 reloc_offset);
1565 memcpy_fromio(d, s, PAGE_SIZE);
1566 io_mapping_unmap_atomic(s);
960e3564
CW		 1567 } else if (src->stolen) {
1568 unsigned long offset;
1569
1570 offset = dev_priv->mm.stolen_base;
1571 offset += src->stolen->start;
1572 offset += i << PAGE_SHIFT;
1573
1a240d4d 1574 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 1575 } else {
9da3da66 1576 struct page *page;
172975aa
CW		 1577 void *s;
1578
9da3da66 1579 page = i915_gem_object_get_page(src, i);
172975aa 1580
9da3da66
CW		 1581 drm_clflush_pages(&page, 1);
1582
1583 s = kmap_atomic(page);
172975aa
CW		 1584 memcpy(d, s, PAGE_SIZE);
1585 kunmap_atomic(s);
1586
9da3da66 1587 drm_clflush_pages(&page, 1);
172975aa 1588 }
788885ae 1589 local_irq_restore(flags);
e56660dd 1590
9da3da66 1591 dst->pages[i] = d;
e56660dd
CW		 1592
1593 reloc_offset += PAGE_SIZE;
9df30794 1594 }
d0d045e8 1595 dst->page_count = num_pages;
9df30794
CW		 1596
1597 return dst;
1598
1599unwind:
9da3da66
CW		 1600 while (i--)
1601 kfree(dst->pages[i]);
9df30794
CW		 1602 kfree(dst);
1603 return NULL;
1604}
d0d045e8
BW		 1605#define i915_error_object_create(dev_priv, src) \
1606 i915_error_object_create_sized((dev_priv), (src), \
1607 (src)->base.size>>PAGE_SHIFT)
9df30794
CW		 1608
1609static void
1610i915_error_object_free(struct drm_i915_error_object *obj)
1611{
1612 int page;
1613
1614 if (obj == NULL)
1615 return;
1616
1617 for (page = 0; page < obj->page_count; page++)
1618 kfree(obj->pages[page]);
1619
1620 kfree(obj);
1621}
1622
742cbee8
DV		 1623void
1624i915_error_state_free(struct kref *error_ref)
9df30794 1625{
742cbee8
DV		 1626 struct drm_i915_error_state *error = container_of(error_ref,
1627 typeof(*error), ref);
e2f973d5
CW		 1628 int i;
1629
52d39a21
CW		 1630 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1631 i915_error_object_free(error->ring[i].batchbuffer);
1632 i915_error_object_free(error->ring[i].ringbuffer);
7ed73da0 1633 i915_error_object_free(error->ring[i].ctx);
52d39a21
CW		 1634 kfree(error->ring[i].requests);
1635 }
e2f973d5 1636
9df30794 1637 kfree(error->active_bo);
6ef3d427 1638 kfree(error->overlay);
7ed73da0 1639 kfree(error->display);
9df30794
CW		 1640 kfree(error);
1641}
1b50247a
CW		 1642static void capture_bo(struct drm_i915_error_buffer *err,
1643 struct drm_i915_gem_object *obj)
1644{
1645 err->size = obj->base.size;
1646 err->name = obj->base.name;
0201f1ec
CW		 1647 err->rseqno = obj->last_read_seqno;
1648 err->wseqno = obj->last_write_seqno;
f343c5f6 1649 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
1b50247a
CW		 1650 err->read_domains = obj->base.read_domains;
1651 err->write_domain = obj->base.write_domain;
1652 err->fence_reg = obj->fence_reg;
1653 err->pinned = 0;
1654 if (obj->pin_count > 0)
1655 err->pinned = 1;
1656 if (obj->user_pin_count > 0)
1657 err->pinned = -1;
1658 err->tiling = obj->tiling_mode;
1659 err->dirty = obj->dirty;
1660 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1661 err->ring = obj->ring ? obj->ring->id : -1;
1662 err->cache_level = obj->cache_level;
1663}
9df30794 1664
1b50247a
CW		 1665static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1666 int count, struct list_head *head)
c724e8a9
CW		 1667{
1668 struct drm_i915_gem_object *obj;
1669 int i = 0;
1670
1671 list_for_each_entry(obj, head, mm_list) {
1b50247a 1672 capture_bo(err++, obj);
c724e8a9
CW		 1673 if (++i == count)
1674 break;
1b50247a
CW		 1675 }
1676
1677 return i;
1678}
1679
1680static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1681 int count, struct list_head *head)
1682{
1683 struct drm_i915_gem_object *obj;
1684 int i = 0;
1685
35c20a60 1686 list_for_each_entry(obj, head, global_list) {
1b50247a
CW		 1687 if (obj->pin_count == 0)
1688 continue;
c724e8a9 1689
1b50247a
CW		 1690 capture_bo(err++, obj);
1691 if (++i == count)
1692 break;
c724e8a9
CW		 1693 }
1694
1695 return i;
1696}
1697
748ebc60
CW		 1698static void i915_gem_record_fences(struct drm_device *dev,
1699 struct drm_i915_error_state *error)
1700{
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 int i;
1703
1704 /* Fences */
1705 switch (INTEL_INFO(dev)->gen) {
775d17b6 1706 case 7:
748ebc60 1707 case 6:
42b5aeab 1708 for (i = 0; i < dev_priv->num_fence_regs; i++)
748ebc60
CW		 1709 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1710 break;
1711 case 5:
1712 case 4:
1713 for (i = 0; i < 16; i++)
1714 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1715 break;
1716 case 3:
1717 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1718 for (i = 0; i < 8; i++)
1719 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1720 case 2:
1721 for (i = 0; i < 8; i++)
1722 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1723 break;
1724
7dbf9d6e
BW		 1725 default:
1726 BUG();
748ebc60
CW		 1727 }
1728}
1729
bcfb2e28
CW		 1730static struct drm_i915_error_object *
1731i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1732 struct intel_ring_buffer *ring)
1733{
1734 struct drm_i915_gem_object *obj;
1735 u32 seqno;
1736
1737 if (!ring->get_seqno)
1738 return NULL;
1739
b45305fc
DV		 1740 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1741 u32 acthd = I915_READ(ACTHD);
1742
1743 if (WARN_ON(ring->id != RCS))
1744 return NULL;
1745
1746 obj = ring->private;
f343c5f6
BW		 1747 if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
1748 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
b45305fc
DV		 1749 return i915_error_object_create(dev_priv, obj);
1750 }
1751
b2eadbc8 1752 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1753 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1754 if (obj->ring != ring)
1755 continue;
1756
0201f1ec 1757 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1758 continue;
1759
1760 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1761 continue;
1762
1763 /* We need to copy these to an anonymous buffer as the simplest
1764 * method to avoid being overwritten by userspace.
1765 */
1766 return i915_error_object_create(dev_priv, obj);
1767 }
1768
1769 return NULL;
1770}
1771
d27b1e0e
DV		 1772static void i915_record_ring_state(struct drm_device *dev,
1773 struct drm_i915_error_state *error,
1774 struct intel_ring_buffer *ring)
1775{
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777
33f3f518 1778 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1779 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1780 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1781 error->semaphore_mboxes[ring->id][0]
1782 = I915_READ(RING_SYNC_0(ring->mmio_base));
1783 error->semaphore_mboxes[ring->id][1]
1784 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1785 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1786 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1787 }
c1cd90ed 1788
d27b1e0e 1789 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1790 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1791 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1792 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1793 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1794 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1795 if (ring->id == RCS)
d27b1e0e 1796 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1797 } else {
9d2f41fa 1798 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1799 error->ipeir[ring->id] = I915_READ(IPEIR);
1800 error->ipehr[ring->id] = I915_READ(IPEHR);
1801 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1802 }
1803
9574b3fe 1804 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1805 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1806 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1807 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1808 error->head[ring->id] = I915_READ_HEAD(ring);
1809 error->tail[ring->id] = I915_READ_TAIL(ring);
0f3b6849 1810 error->ctl[ring->id] = I915_READ_CTL(ring);
7e3b8737
DV		 1811
1812 error->cpu_ring_head[ring->id] = ring->head;
1813 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1814}
1815
8c123e54
BW		 1816
1817static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1818 struct drm_i915_error_state *error,
1819 struct drm_i915_error_ring *ering)
1820{
1821 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1822 struct drm_i915_gem_object *obj;
1823
1824 /* Currently render ring is the only HW context user */
1825 if (ring->id != RCS || !error->ccid)
1826 return;
1827
35c20a60 1828 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
f343c5f6 1829 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
8c123e54
BW		 1830 ering->ctx = i915_error_object_create_sized(dev_priv,
1831 obj, 1);
3ef8fb5a 1832 break;
8c123e54
BW		 1833 }
1834 }
1835}
1836
52d39a21
CW		 1837static void i915_gem_record_rings(struct drm_device *dev,
1838 struct drm_i915_error_state *error)
1839{
1840 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1841 struct intel_ring_buffer *ring;
52d39a21
CW		 1842 struct drm_i915_gem_request *request;
1843 int i, count;
1844
b4519513 1845 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1846 i915_record_ring_state(dev, error, ring);
1847
1848 error->ring[i].batchbuffer =
1849 i915_error_first_batchbuffer(dev_priv, ring);
1850
1851 error->ring[i].ringbuffer =
1852 i915_error_object_create(dev_priv, ring->obj);
1853
8c123e54
BW		 1854
1855 i915_gem_record_active_context(ring, error, &error->ring[i]);
1856
52d39a21
CW		 1857 count = 0;
1858 list_for_each_entry(request, &ring->request_list, list)
1859 count++;
1860
1861 error->ring[i].num_requests = count;
1862 error->ring[i].requests =
1863 kmalloc(count*sizeof(struct drm_i915_error_request),
1864 GFP_ATOMIC);
1865 if (error->ring[i].requests == NULL) {
1866 error->ring[i].num_requests = 0;
1867 continue;
1868 }
1869
1870 count = 0;
1871 list_for_each_entry(request, &ring->request_list, list) {
1872 struct drm_i915_error_request *erq;
1873
1874 erq = &error->ring[i].requests[count++];
1875 erq->seqno = request->seqno;
1876 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1877 erq->tail = request->tail;
52d39a21
CW		 1878 }
1879 }
1880}
1881
26b7c224
BW		 1882static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1883 struct drm_i915_error_state *error)
1884{
1885 struct drm_i915_gem_object *obj;
1886 int i;
1887
1888 i = 0;
1889 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1890 i++;
1891 error->active_bo_count = i;
1892 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1893 if (obj->pin_count)
1894 i++;
1895 error->pinned_bo_count = i - error->active_bo_count;
1896
1897 if (i) {
1898 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1899 GFP_ATOMIC);
1900 if (error->active_bo)
1901 error->pinned_bo =
1902 error->active_bo + error->active_bo_count;
1903 }
1904
1905 if (error->active_bo)
1906 error->active_bo_count =
1907 capture_active_bo(error->active_bo,
1908 error->active_bo_count,
1909 &dev_priv->mm.active_list);
1910
1911 if (error->pinned_bo)
1912 error->pinned_bo_count =
1913 capture_pinned_bo(error->pinned_bo,
1914 error->pinned_bo_count,
1915 &dev_priv->mm.bound_list);
1916}
1917
8a905236
JB		 1918/**
1919 * i915_capture_error_state - capture an error record for later analysis
1920 * @dev: drm device
1921 *
1922 * Should be called when an error is detected (either a hang or an error
1923 * interrupt) to capture error state from the time of the error. Fills
1924 * out a structure which becomes available in debugfs for user level tools
1925 * to pick up.
1926 */
63eeaf38
JB		 1927static void i915_capture_error_state(struct drm_device *dev)
1928{
1929 struct drm_i915_private *dev_priv = dev->dev_private;
1930 struct drm_i915_error_state *error;
1931 unsigned long flags;
26b7c224 1932 int pipe;
63eeaf38 1933
99584db3
DV		 1934 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1935 error = dev_priv->gpu_error.first_error;
1936 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1937 if (error)
1938 return;
63eeaf38 1939
9db4a9c7 1940 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1941 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1942 if (!error) {
9df30794
CW		 1943 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1944 return;
63eeaf38
JB		 1945 }
1946
5d83d294 1947 DRM_INFO("capturing error event; look for more information in "
ef86ddce 1948 "/sys/class/drm/card%d/error\n", dev->primary->index);
2fa772f3 1949
742cbee8 1950 kref_init(&error->ref);
63eeaf38
JB		 1951 error->eir = I915_READ(EIR);
1952 error->pgtbl_er = I915_READ(PGTBL_ER);
211816ec
BW		 1953 if (HAS_HW_CONTEXTS(dev))
1954 error->ccid = I915_READ(CCID);
be998e2e
BW		 1955
1956 if (HAS_PCH_SPLIT(dev))
1957 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1958 else if (IS_VALLEYVIEW(dev))
1959 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1960 else if (IS_GEN2(dev))
1961 error->ier = I915_READ16(IER);
1962 else
1963 error->ier = I915_READ(IER);
1964
0f3b6849
CW		 1965 if (INTEL_INFO(dev)->gen >= 6)
1966 error->derrmr = I915_READ(DERRMR);
1967
1968 if (IS_VALLEYVIEW(dev))
1969 error->forcewake = I915_READ(FORCEWAKE_VLV);
1970 else if (INTEL_INFO(dev)->gen >= 7)
1971 error->forcewake = I915_READ(FORCEWAKE_MT);
1972 else if (INTEL_INFO(dev)->gen == 6)
1973 error->forcewake = I915_READ(FORCEWAKE);
1974
4f3308b9
PZ		 1975 if (!HAS_PCH_SPLIT(dev))
1976 for_each_pipe(pipe)
1977 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1978
33f3f518 1979 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1980 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1981 error->done_reg = I915_READ(DONE_REG);
1982 }
d27b1e0e 1983
71e172e8
BW		 1984 if (INTEL_INFO(dev)->gen == 7)
1985 error->err_int = I915_READ(GEN7_ERR_INT);
1986
050ee91f
BW		 1987 i915_get_extra_instdone(dev, error->extra_instdone);
1988
26b7c224 1989 i915_gem_capture_buffers(dev_priv, error);
748ebc60 1990 i915_gem_record_fences(dev, error);
52d39a21 1991 i915_gem_record_rings(dev, error);
9df30794 1992
9df30794
CW		 1993 do_gettimeofday(&error->time);
1994
6ef3d427 1995 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1996 error->display = intel_display_capture_error_state(dev);
6ef3d427 1997
99584db3
DV		 1998 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1999 if (dev_priv->gpu_error.first_error == NULL) {
2000 dev_priv->gpu_error.first_error = error;
9df30794
CW		 2001 error = NULL;
2002 }
99584db3 2003 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 2004
2005 if (error)
742cbee8 2006 i915_error_state_free(&error->ref);
9df30794
CW		 2007}
2008
2009void i915_destroy_error_state(struct drm_device *dev)
2010{
2011 struct drm_i915_private *dev_priv = dev->dev_private;
2012 struct drm_i915_error_state *error;
6dc0e816 2013 unsigned long flags;
9df30794 2014
99584db3
DV		 2015 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
2016 error = dev_priv->gpu_error.first_error;
2017 dev_priv->gpu_error.first_error = NULL;
2018 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 2019
2020 if (error)
742cbee8 2021 kref_put(&error->ref, i915_error_state_free);
63eeaf38 2022}
3bd3c932
CW		 2023#else
2024#define i915_capture_error_state(x)
2025#endif
63eeaf38 2026
35aed2e6 2027static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2028{
2029 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2030 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2031 u32 eir = I915_READ(EIR);
050ee91f 2032 int pipe, i;
8a905236 2033
35aed2e6
CW		 2034 if (!eir)
2035 return;
8a905236 2036
a70491cc 2037 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2038
bd9854f9
BW		 2039 i915_get_extra_instdone(dev, instdone);
2040
8a905236
JB		 2041 if (IS_G4X(dev)) {
2042 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2043 u32 ipeir = I915_READ(IPEIR_I965);
2044
a70491cc
JP		 2045 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2046 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2047 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2048 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2049 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2050 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2051 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2052 POSTING_READ(IPEIR_I965);
8a905236
JB		 2053 }
2054 if (eir & GM45_ERROR_PAGE_TABLE) {
2055 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2056 pr_err("page table error\n");
2057 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2058 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2059 POSTING_READ(PGTBL_ER);
8a905236
JB		 2060 }
2061 }
2062
a6c45cf0 2063 if (!IS_GEN2(dev)) {
8a905236
JB		 2064 if (eir & I915_ERROR_PAGE_TABLE) {
2065 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2066 pr_err("page table error\n");
2067 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2068 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2069 POSTING_READ(PGTBL_ER);
8a905236
JB		 2070 }
2071 }
2072
2073 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2074 pr_err("memory refresh error:\n");
9db4a9c7 2075 for_each_pipe(pipe)
a70491cc 2076 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2077 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2078 /* pipestat has already been acked */
2079 }
2080 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2081 pr_err("instruction error\n");
2082 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2083 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2084 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2085 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2086 u32 ipeir = I915_READ(IPEIR);
2087
a70491cc
JP		 2088 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2089 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2090 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2091 I915_WRITE(IPEIR, ipeir);
3143a2bf 2092 POSTING_READ(IPEIR);
8a905236
JB		 2093 } else {
2094 u32 ipeir = I915_READ(IPEIR_I965);
2095
a70491cc
JP		 2096 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2097 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2098 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2099 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2100 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2101 POSTING_READ(IPEIR_I965);
8a905236
JB		 2102 }
2103 }
2104
2105 I915_WRITE(EIR, eir);
3143a2bf 2106 POSTING_READ(EIR);
8a905236
JB		 2107 eir = I915_READ(EIR);
2108 if (eir) {
2109 /*
2110 * some errors might have become stuck,
2111 * mask them.
2112 */
2113 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2114 I915_WRITE(EMR, I915_READ(EMR) | eir);
2115 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2116 }
35aed2e6
CW		 2117}
2118
2119/**
2120 * i915_handle_error - handle an error interrupt
2121 * @dev: drm device
2122 *
2123 * Do some basic checking of regsiter state at error interrupt time and
2124 * dump it to the syslog. Also call i915_capture_error_state() to make
2125 * sure we get a record and make it available in debugfs. Fire a uevent
2126 * so userspace knows something bad happened (should trigger collection
2127 * of a ring dump etc.).
2128 */
527f9e90 2129void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 2130{
2131 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 2132 struct intel_ring_buffer *ring;
2133 int i;
35aed2e6
CW		 2134
2135 i915_capture_error_state(dev);
2136 i915_report_and_clear_eir(dev);
8a905236 2137
ba1234d1 2138 if (wedged) {
f69061be
DV		 2139 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2140 &dev_priv->gpu_error.reset_counter);
ba1234d1 2141
11ed50ec 2142 /*
1f83fee0
DV		 2143 * Wakeup waiting processes so that the reset work item
2144 * doesn't deadlock trying to grab various locks.
11ed50ec 2145 */
b4519513
CW		 2146 for_each_ring(ring, dev_priv, i)
2147 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 2148 }
2149
99584db3 2150 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 2151}
2152
21ad8330 2153static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 2154{
2155 drm_i915_private_t *dev_priv = dev->dev_private;
2156 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2158 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2159 struct intel_unpin_work *work;
2160 unsigned long flags;
2161 bool stall_detected;
2162
2163 /* Ignore early vblank irqs */
2164 if (intel_crtc == NULL)
2165 return;
2166
2167 spin_lock_irqsave(&dev->event_lock, flags);
2168 work = intel_crtc->unpin_work;
2169
e7d841ca
CW		 2170 if (work == NULL ||
2171 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2172 !work->enable_stall_check) {
4e5359cd
SF		 2173 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2174 spin_unlock_irqrestore(&dev->event_lock, flags);
2175 return;
2176 }
2177
2178 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2179 obj = work->pending_flip_obj;
a6c45cf0 2180 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2181 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 2182 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 2183 i915_gem_obj_ggtt_offset(obj);
4e5359cd 2184 } else {
9db4a9c7 2185 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 2186 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
01f2c773 2187 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 2188 crtc->x * crtc->fb->bits_per_pixel/8);
2189 }
2190
2191 spin_unlock_irqrestore(&dev->event_lock, flags);
2192
2193 if (stall_detected) {
2194 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2195 intel_prepare_page_flip(dev, intel_crtc->plane);
2196 }
2197}
2198
42f52ef8
KP		 2199/* Called from drm generic code, passed 'crtc' which
2200 * we use as a pipe index
2201 */
f71d4af4 2202static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2203{
2204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2205 unsigned long irqflags;
71e0ffa5 2206
5eddb70b 2207 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2208 return -EINVAL;
0a3e67a4 2209
1ec14ad3 2210 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2211 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 2212 i915_enable_pipestat(dev_priv, pipe,
2213 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 2214 else
7c463586
KP		 2215 i915_enable_pipestat(dev_priv, pipe,
2216 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 2217
2218 /* maintain vblank delivery even in deep C-states */
2219 if (dev_priv->info->gen == 3)
6b26c86d 2220 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 2221 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2222
0a3e67a4
JB		 2223 return 0;
2224}
2225
f71d4af4 2226static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2227{
2228 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2229 unsigned long irqflags;
2230
2231 if (!i915_pipe_enabled(dev, pipe))
2232 return -EINVAL;
2233
2234 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2235 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2236 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 2237 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2238
2239 return 0;
2240}
2241
f71d4af4 2242static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2243{
2244 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2245 unsigned long irqflags;
2246
2247 if (!i915_pipe_enabled(dev, pipe))
2248 return -EINVAL;
2249
2250 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2251 ironlake_enable_display_irq(dev_priv,
2252 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 2253 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2254
2255 return 0;
2256}
2257
7e231dbe
JB		 2258static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2259{
2260 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2261 unsigned long irqflags;
31acc7f5 2262 u32 imr;
7e231dbe
JB		 2263
2264 if (!i915_pipe_enabled(dev, pipe))
2265 return -EINVAL;
2266
2267 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 2268 imr = I915_READ(VLV_IMR);
31acc7f5 2269 if (pipe == 0)
7e231dbe 2270 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2271 else
7e231dbe 2272 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2273 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 2274 i915_enable_pipestat(dev_priv, pipe,
2275 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 2276 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2277
2278 return 0;
2279}
2280
42f52ef8
KP		 2281/* Called from drm generic code, passed 'crtc' which
2282 * we use as a pipe index
2283 */
f71d4af4 2284static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2285{
2286 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2287 unsigned long irqflags;
0a3e67a4 2288
1ec14ad3 2289 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 2290 if (dev_priv->info->gen == 3)
6b26c86d 2291 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2292
f796cf8f
JB		 2293 i915_disable_pipestat(dev_priv, pipe,
2294 PIPE_VBLANK_INTERRUPT_ENABLE |
2295 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2296 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2297}
2298
f71d4af4 2299static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2300{
2301 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2302 unsigned long irqflags;
2303
2304 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2305 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2306 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 2307 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 2308}
2309
f71d4af4 2310static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2311{
2312 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2313 unsigned long irqflags;
2314
2315 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2316 ironlake_disable_display_irq(dev_priv,
2317 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 2318 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2319}
2320
7e231dbe
JB		 2321static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2322{
2323 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2324 unsigned long irqflags;
31acc7f5 2325 u32 imr;
7e231dbe
JB		 2326
2327 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2328 i915_disable_pipestat(dev_priv, pipe,
2329 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 2330 imr = I915_READ(VLV_IMR);
31acc7f5 2331 if (pipe == 0)
7e231dbe 2332 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2333 else
7e231dbe 2334 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2335 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 2336 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2337}
2338
893eead0
CW		 2339static u32
2340ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2341{
893eead0
CW		 2342 return list_entry(ring->request_list.prev,
2343 struct drm_i915_gem_request, list)->seqno;
2344}
2345
9107e9d2
CW		 2346static bool
2347ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2348{
2349 return (list_empty(&ring->request_list) ||
2350 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 2351}
2352
6274f212
CW		 2353static struct intel_ring_buffer *
2354semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 2355{
2356 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 2357 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 2358
2359 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2360 if ((ipehr & ~(0x3 << 16)) !=
2361 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 2362 return NULL;
a24a11e6
CW		 2363
2364 /* ACTHD is likely pointing to the dword after the actual command,
2365 * so scan backwards until we find the MBOX.
2366 */
6274f212 2367 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 2368 acthd_min = max((int)acthd - 3 * 4, 0);
2369 do {
2370 cmd = ioread32(ring->virtual_start + acthd);
2371 if (cmd == ipehr)
2372 break;
2373
2374 acthd -= 4;
2375 if (acthd < acthd_min)
6274f212 2376 return NULL;
a24a11e6
CW		 2377 } while (1);
2378
6274f212
CW		 2379 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2380 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 2381}
2382
6274f212
CW		 2383static int semaphore_passed(struct intel_ring_buffer *ring)
2384{
2385 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2386 struct intel_ring_buffer *signaller;
2387 u32 seqno, ctl;
2388
2389 ring->hangcheck.deadlock = true;
2390
2391 signaller = semaphore_waits_for(ring, &seqno);
2392 if (signaller == NULL || signaller->hangcheck.deadlock)
2393 return -1;
2394
2395 /* cursory check for an unkickable deadlock */
2396 ctl = I915_READ_CTL(signaller);
2397 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2398 return -1;
2399
2400 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2401}
2402
2403static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2404{
2405 struct intel_ring_buffer *ring;
2406 int i;
2407
2408 for_each_ring(ring, dev_priv, i)
2409 ring->hangcheck.deadlock = false;
2410}
2411
ad8beaea
MK		 2412static enum intel_ring_hangcheck_action
2413ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 2414{
2415 struct drm_device *dev = ring->dev;
2416 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2417 u32 tmp;
2418
6274f212
CW		 2419 if (ring->hangcheck.acthd != acthd)
2420 return active;
2421
9107e9d2 2422 if (IS_GEN2(dev))
6274f212 2423 return hung;
9107e9d2
CW		 2424
2425 /* Is the chip hanging on a WAIT_FOR_EVENT?
2426 * If so we can simply poke the RB_WAIT bit
2427 * and break the hang. This should work on
2428 * all but the second generation chipsets.
2429 */
2430 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 2431 if (tmp & RING_WAIT) {
2432 DRM_ERROR("Kicking stuck wait on %s\n",
2433 ring->name);
2434 I915_WRITE_CTL(ring, tmp);
6274f212
CW		 2435 return kick;
2436 }
2437
2438 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2439 switch (semaphore_passed(ring)) {
2440 default:
2441 return hung;
2442 case 1:
2443 DRM_ERROR("Kicking stuck semaphore on %s\n",
2444 ring->name);
2445 I915_WRITE_CTL(ring, tmp);
2446 return kick;
2447 case 0:
2448 return wait;
2449 }
9107e9d2 2450 }
ed5cbb03 2451
6274f212 2452 return hung;
ed5cbb03
MK		 2453}
2454
f65d9421
BG		 2455/**
2456 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2457 * batchbuffers in a long time. We keep track per ring seqno progress and
2458 * if there are no progress, hangcheck score for that ring is increased.
2459 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2460 * we kick the ring. If we see no progress on three subsequent calls
2461 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421
BG		 2462 */
2463void i915_hangcheck_elapsed(unsigned long data)
2464{
2465 struct drm_device *dev = (struct drm_device *)data;
2466 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 2467 struct intel_ring_buffer *ring;
b4519513 2468 int i;
05407ff8 2469 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2470 bool stuck[I915_NUM_RINGS] = { 0 };
2471#define BUSY 1
2472#define KICK 5
2473#define HUNG 20
2474#define FIRE 30
893eead0 2475
3e0dc6b0
BW		 2476 if (!i915_enable_hangcheck)
2477 return;
2478
b4519513 2479 for_each_ring(ring, dev_priv, i) {
05407ff8 2480 u32 seqno, acthd;
9107e9d2 2481 bool busy = true;
05407ff8 2482
6274f212
CW		 2483 semaphore_clear_deadlocks(dev_priv);
2484
05407ff8
MK		 2485 seqno = ring->get_seqno(ring, false);
2486 acthd = intel_ring_get_active_head(ring);
b4519513 2487
9107e9d2
CW		 2488 if (ring->hangcheck.seqno == seqno) {
2489 if (ring_idle(ring, seqno)) {
2490 if (waitqueue_active(&ring->irq_queue)) {
2491 /* Issue a wake-up to catch stuck h/w. */
2492 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2493 ring->name);
2494 wake_up_all(&ring->irq_queue);
2495 ring->hangcheck.score += HUNG;
2496 } else
2497 busy = false;
05407ff8 2498 } else {
9107e9d2
CW		 2499 int score;
2500
6274f212
CW		 2501 /* We always increment the hangcheck score
2502 * if the ring is busy and still processing
2503 * the same request, so that no single request
2504 * can run indefinitely (such as a chain of
2505 * batches). The only time we do not increment
2506 * the hangcheck score on this ring, if this
2507 * ring is in a legitimate wait for another
2508 * ring. In that case the waiting ring is a
2509 * victim and we want to be sure we catch the
2510 * right culprit. Then every time we do kick
2511 * the ring, add a small increment to the
2512 * score so that we can catch a batch that is
2513 * being repeatedly kicked and so responsible
2514 * for stalling the machine.
2515 */
ad8beaea
MK		 2516 ring->hangcheck.action = ring_stuck(ring,
2517 acthd);
2518
2519 switch (ring->hangcheck.action) {
6274f212
CW		 2520 case wait:
2521 score = 0;
2522 break;
2523 case active:
9107e9d2 2524 score = BUSY;
6274f212
CW		 2525 break;
2526 case kick:
2527 score = KICK;
2528 break;
2529 case hung:
2530 score = HUNG;
2531 stuck[i] = true;
2532 break;
2533 }
9107e9d2 2534 ring->hangcheck.score += score;
05407ff8 2535 }
9107e9d2
CW		 2536 } else {
2537 /* Gradually reduce the count so that we catch DoS
2538 * attempts across multiple batches.
2539 */
2540 if (ring->hangcheck.score > 0)
2541 ring->hangcheck.score--;
d1e61e7f
CW		 2542 }
2543
05407ff8
MK		 2544 ring->hangcheck.seqno = seqno;
2545 ring->hangcheck.acthd = acthd;
9107e9d2 2546 busy_count += busy;
893eead0 2547 }
b9201c14 2548
92cab734 2549 for_each_ring(ring, dev_priv, i) {
9107e9d2 2550 if (ring->hangcheck.score > FIRE) {
acd78c11 2551 DRM_ERROR("%s on %s\n",
05407ff8 2552 stuck[i] ? "stuck" : "no progress",
a43adf07
CW		 2553 ring->name);
2554 rings_hung++;
92cab734
MK		 2555 }
2556 }
2557
05407ff8
MK		 2558 if (rings_hung)
2559 return i915_handle_error(dev, true);
f65d9421 2560
05407ff8
MK		 2561 if (busy_count)
2562 /* Reset timer case chip hangs without another request
2563 * being added */
2564 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2565 round_jiffies_up(jiffies +
2566 DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2567}
2568
91738a95
PZ		 2569static void ibx_irq_preinstall(struct drm_device *dev)
2570{
2571 struct drm_i915_private *dev_priv = dev->dev_private;
2572
2573 if (HAS_PCH_NOP(dev))
2574 return;
2575
2576 /* south display irq */
2577 I915_WRITE(SDEIMR, 0xffffffff);
2578 /*
2579 * SDEIER is also touched by the interrupt handler to work around missed
2580 * PCH interrupts. Hence we can't update it after the interrupt handler
2581 * is enabled - instead we unconditionally enable all PCH interrupt
2582 * sources here, but then only unmask them as needed with SDEIMR.
2583 */
2584 I915_WRITE(SDEIER, 0xffffffff);
2585 POSTING_READ(SDEIER);
2586}
2587
1da177e4
LT		 2588/* drm_dma.h hooks
2589*/
f71d4af4 2590static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2591{
2592 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2593
4697995b
JB		 2594 atomic_set(&dev_priv->irq_received, 0);
2595
036a4a7d 2596 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2597
036a4a7d
ZW		 2598 /* XXX hotplug from PCH */
2599
2600 I915_WRITE(DEIMR, 0xffffffff);
2601 I915_WRITE(DEIER, 0x0);
3143a2bf 2602 POSTING_READ(DEIER);
036a4a7d
ZW		 2603
2604 /* and GT */
2605 I915_WRITE(GTIMR, 0xffffffff);
2606 I915_WRITE(GTIER, 0x0);
3143a2bf 2607 POSTING_READ(GTIER);
c650156a 2608
91738a95 2609 ibx_irq_preinstall(dev);
7d99163d
BW		 2610}
2611
2612static void ivybridge_irq_preinstall(struct drm_device *dev)
2613{
2614 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2615
2616 atomic_set(&dev_priv->irq_received, 0);
2617
2618 I915_WRITE(HWSTAM, 0xeffe);
2619
2620 /* XXX hotplug from PCH */
2621
2622 I915_WRITE(DEIMR, 0xffffffff);
2623 I915_WRITE(DEIER, 0x0);
2624 POSTING_READ(DEIER);
2625
2626 /* and GT */
2627 I915_WRITE(GTIMR, 0xffffffff);
2628 I915_WRITE(GTIER, 0x0);
2629 POSTING_READ(GTIER);
2630
eda63ffb
BW		 2631 /* Power management */
2632 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2633 I915_WRITE(GEN6_PMIER, 0x0);
2634 POSTING_READ(GEN6_PMIER);
2635
91738a95 2636 ibx_irq_preinstall(dev);
036a4a7d
ZW		 2637}
2638
7e231dbe
JB		 2639static void valleyview_irq_preinstall(struct drm_device *dev)
2640{
2641 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2642 int pipe;
2643
2644 atomic_set(&dev_priv->irq_received, 0);
2645
7e231dbe
JB		 2646 /* VLV magic */
2647 I915_WRITE(VLV_IMR, 0);
2648 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2649 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2650 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2651
7e231dbe
JB		 2652 /* and GT */
2653 I915_WRITE(GTIIR, I915_READ(GTIIR));
2654 I915_WRITE(GTIIR, I915_READ(GTIIR));
2655 I915_WRITE(GTIMR, 0xffffffff);
2656 I915_WRITE(GTIER, 0x0);
2657 POSTING_READ(GTIER);
2658
2659 I915_WRITE(DPINVGTT, 0xff);
2660
2661 I915_WRITE(PORT_HOTPLUG_EN, 0);
2662 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2663 for_each_pipe(pipe)
2664 I915_WRITE(PIPESTAT(pipe), 0xffff);
2665 I915_WRITE(VLV_IIR, 0xffffffff);
2666 I915_WRITE(VLV_IMR, 0xffffffff);
2667 I915_WRITE(VLV_IER, 0x0);
2668 POSTING_READ(VLV_IER);
2669}
2670
82a28bcf 2671static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2672{
2673 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2674 struct drm_mode_config *mode_config = &dev->mode_config;
2675 struct intel_encoder *intel_encoder;
fee884ed 2676 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2677
2678 if (HAS_PCH_IBX(dev)) {
fee884ed 2679 hotplug_irqs = SDE_HOTPLUG_MASK;
82a28bcf 2680 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2681 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2682 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2683 } else {
fee884ed 2684 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
82a28bcf 2685 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2686 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2687 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2688 }
7fe0b973 2689
fee884ed 2690 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 2691
2692 /*
2693 * Enable digital hotplug on the PCH, and configure the DP short pulse
2694 * duration to 2ms (which is the minimum in the Display Port spec)
2695 *
2696 * This register is the same on all known PCH chips.
2697 */
7fe0b973
KP		 2698 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2699 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2700 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2701 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2702 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2703 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2704}
2705
d46da437
PZ		 2706static void ibx_irq_postinstall(struct drm_device *dev)
2707{
2708 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2709 u32 mask;
e5868a31 2710
692a04cf
DV		 2711 if (HAS_PCH_NOP(dev))
2712 return;
2713
8664281b
PZ		 2714 if (HAS_PCH_IBX(dev)) {
2715 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2716 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2717 } else {
2718 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2719
2720 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2721 }
ab5c608b 2722
d46da437
PZ		 2723 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2724 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2725}
2726
f71d4af4 2727static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2728{
4bc9d430
DV		 2729 unsigned long irqflags;
2730
036a4a7d
ZW		 2731 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2732 /* enable kind of interrupts always enabled */
013d5aa2 2733 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
ce99c256 2734 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
8664281b 2735 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
de032bf4 2736 DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
cc609d5d 2737 u32 gt_irqs;
036a4a7d 2738
1ec14ad3 2739 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2740
2741 /* should always can generate irq */
2742 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2743 I915_WRITE(DEIMR, dev_priv->irq_mask);
6005ce42
DV		 2744 I915_WRITE(DEIER, display_mask |
2745 DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT);
3143a2bf 2746 POSTING_READ(DEIER);
036a4a7d 2747
1ec14ad3 2748 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 2749
2750 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 2751 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 2752
cc609d5d
BW		 2753 gt_irqs = GT_RENDER_USER_INTERRUPT;
2754
1ec14ad3 2755 if (IS_GEN6(dev))
cc609d5d 2756 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
1ec14ad3 2757 else
cc609d5d
BW		 2758 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2759 ILK_BSD_USER_INTERRUPT;
2760
2761 I915_WRITE(GTIER, gt_irqs);
3143a2bf 2762 POSTING_READ(GTIER);
036a4a7d 2763
d46da437 2764 ibx_irq_postinstall(dev);
7fe0b973 2765
f97108d1 2766 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2767 /* Enable PCU event interrupts
2768 *
2769 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2770 * setup is guaranteed to run in single-threaded context. But we
2771 * need it to make the assert_spin_locked happy. */
2772 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2773 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2774 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2775 }
2776
036a4a7d
ZW		 2777 return 0;
2778}
2779
f71d4af4 2780static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2781{
2782 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2783 /* enable kind of interrupts always enabled */
b615b57a
CW		 2784 u32 display_mask =
2785 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2786 DE_PLANEC_FLIP_DONE_IVB |
2787 DE_PLANEB_FLIP_DONE_IVB |
ce99c256 2788 DE_PLANEA_FLIP_DONE_IVB |
8664281b
PZ		 2789 DE_AUX_CHANNEL_A_IVB |
2790 DE_ERR_INT_IVB;
12638c57 2791 u32 pm_irqs = GEN6_PM_RPS_EVENTS;
cc609d5d 2792 u32 gt_irqs;
b1f14ad0 2793
b1f14ad0
JB		 2794 dev_priv->irq_mask = ~display_mask;
2795
2796 /* should always can generate irq */
8664281b 2797 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
b1f14ad0
JB		 2798 I915_WRITE(DEIIR, I915_READ(DEIIR));
2799 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 2800 I915_WRITE(DEIER,
2801 display_mask |
2802 DE_PIPEC_VBLANK_IVB |
2803 DE_PIPEB_VBLANK_IVB |
2804 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 2805 POSTING_READ(DEIER);
2806
cc609d5d 2807 dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2808
2809 I915_WRITE(GTIIR, I915_READ(GTIIR));
2810 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2811
cc609d5d
BW		 2812 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2813 GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2814 I915_WRITE(GTIER, gt_irqs);
b1f14ad0
JB		 2815 POSTING_READ(GTIER);
2816
12638c57
BW		 2817 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2818 if (HAS_VEBOX(dev))
2819 pm_irqs |= PM_VEBOX_USER_INTERRUPT |
2820 PM_VEBOX_CS_ERROR_INTERRUPT;
2821
2822 /* Our enable/disable rps functions may touch these registers so
2823 * make sure to set a known state for only the non-RPS bits.
2824 * The RMW is extra paranoia since this should be called after being set
2825 * to a known state in preinstall.
2826 * */
2827 I915_WRITE(GEN6_PMIMR,
2828 (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs);
2829 I915_WRITE(GEN6_PMIER,
2830 (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs);
2831 POSTING_READ(GEN6_PMIER);
eda63ffb 2832
d46da437 2833 ibx_irq_postinstall(dev);
7fe0b973 2834
b1f14ad0
JB		 2835 return 0;
2836}
2837
7e231dbe
JB		 2838static int valleyview_irq_postinstall(struct drm_device *dev)
2839{
2840 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
cc609d5d 2841 u32 gt_irqs;
7e231dbe 2842 u32 enable_mask;
31acc7f5 2843 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
b79480ba 2844 unsigned long irqflags;
7e231dbe
JB		 2845
2846 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2847 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2848 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2849 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2850 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2851
31acc7f5
JB		 2852 /*
2853 *Leave vblank interrupts masked initially. enable/disable will
2854 * toggle them based on usage.
2855 */
2856 dev_priv->irq_mask = (~enable_mask) |
2857 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2858 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2859
20afbda2
DV		 2860 I915_WRITE(PORT_HOTPLUG_EN, 0);
2861 POSTING_READ(PORT_HOTPLUG_EN);
2862
7e231dbe
JB		 2863 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2864 I915_WRITE(VLV_IER, enable_mask);
2865 I915_WRITE(VLV_IIR, 0xffffffff);
2866 I915_WRITE(PIPESTAT(0), 0xffff);
2867 I915_WRITE(PIPESTAT(1), 0xffff);
2868 POSTING_READ(VLV_IER);
2869
b79480ba
DV		 2870 /* Interrupt setup is already guaranteed to be single-threaded, this is
2871 * just to make the assert_spin_locked check happy. */
2872 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2873 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2874 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5 2875 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
b79480ba 2876 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 2877
7e231dbe
JB		 2878 I915_WRITE(VLV_IIR, 0xffffffff);
2879 I915_WRITE(VLV_IIR, 0xffffffff);
2880
7e231dbe 2881 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2882 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5 2883
cc609d5d
BW		 2884 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2885 GT_BLT_USER_INTERRUPT;
2886 I915_WRITE(GTIER, gt_irqs);
7e231dbe
JB		 2887 POSTING_READ(GTIER);
2888
2889 /* ack & enable invalid PTE error interrupts */
2890#if 0 /* FIXME: add support to irq handler for checking these bits */
2891 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2892 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2893#endif
2894
2895 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2896
2897 return 0;
2898}
2899
7e231dbe
JB		 2900static void valleyview_irq_uninstall(struct drm_device *dev)
2901{
2902 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2903 int pipe;
2904
2905 if (!dev_priv)
2906 return;
2907
ac4c16c5
EE		 2908 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2909
7e231dbe
JB		 2910 for_each_pipe(pipe)
2911 I915_WRITE(PIPESTAT(pipe), 0xffff);
2912
2913 I915_WRITE(HWSTAM, 0xffffffff);
2914 I915_WRITE(PORT_HOTPLUG_EN, 0);
2915 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2916 for_each_pipe(pipe)
2917 I915_WRITE(PIPESTAT(pipe), 0xffff);
2918 I915_WRITE(VLV_IIR, 0xffffffff);
2919 I915_WRITE(VLV_IMR, 0xffffffff);
2920 I915_WRITE(VLV_IER, 0x0);
2921 POSTING_READ(VLV_IER);
2922}
2923
f71d4af4 2924static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2925{
2926 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2927
2928 if (!dev_priv)
2929 return;
2930
ac4c16c5
EE		 2931 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2932
036a4a7d
ZW		 2933 I915_WRITE(HWSTAM, 0xffffffff);
2934
2935 I915_WRITE(DEIMR, 0xffffffff);
2936 I915_WRITE(DEIER, 0x0);
2937 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2938 if (IS_GEN7(dev))
2939 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2940
2941 I915_WRITE(GTIMR, 0xffffffff);
2942 I915_WRITE(GTIER, 0x0);
2943 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2944
ab5c608b
BW		 2945 if (HAS_PCH_NOP(dev))
2946 return;
2947
192aac1f
KP		 2948 I915_WRITE(SDEIMR, 0xffffffff);
2949 I915_WRITE(SDEIER, 0x0);
2950 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2951 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2952 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2953}
2954
a266c7d5 2955static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2956{
2957 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2958 int pipe;
91e3738e 2959
a266c7d5 2960 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2961
9db4a9c7
JB		 2962 for_each_pipe(pipe)
2963 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2964 I915_WRITE16(IMR, 0xffff);
2965 I915_WRITE16(IER, 0x0);
2966 POSTING_READ16(IER);
c2798b19
CW		 2967}
2968
2969static int i8xx_irq_postinstall(struct drm_device *dev)
2970{
2971 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2972
c2798b19
CW		 2973 I915_WRITE16(EMR,
2974 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2975
2976 /* Unmask the interrupts that we always want on. */
2977 dev_priv->irq_mask =
2978 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2979 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2980 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2981 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2982 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2983 I915_WRITE16(IMR, dev_priv->irq_mask);
2984
2985 I915_WRITE16(IER,
2986 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2987 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2988 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2989 I915_USER_INTERRUPT);
2990 POSTING_READ16(IER);
2991
2992 return 0;
2993}
2994
90a72f87
VS		 2995/*
2996 * Returns true when a page flip has completed.
2997 */
2998static bool i8xx_handle_vblank(struct drm_device *dev,
2999 int pipe, u16 iir)
3000{
3001 drm_i915_private_t *dev_priv = dev->dev_private;
3002 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
3003
3004 if (!drm_handle_vblank(dev, pipe))
3005 return false;
3006
3007 if ((iir & flip_pending) == 0)
3008 return false;
3009
3010 intel_prepare_page_flip(dev, pipe);
3011
3012 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3013 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3014 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3015 * the flip is completed (no longer pending). Since this doesn't raise
3016 * an interrupt per se, we watch for the change at vblank.
3017 */
3018 if (I915_READ16(ISR) & flip_pending)
3019 return false;
3020
3021 intel_finish_page_flip(dev, pipe);
3022
3023 return true;
3024}
3025
ff1f525e 3026static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 3027{
3028 struct drm_device *dev = (struct drm_device *) arg;
3029 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 3030 u16 iir, new_iir;
3031 u32 pipe_stats[2];
3032 unsigned long irqflags;
3033 int irq_received;
3034 int pipe;
3035 u16 flip_mask =
3036 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3037 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3038
3039 atomic_inc(&dev_priv->irq_received);
3040
3041 iir = I915_READ16(IIR);
3042 if (iir == 0)
3043 return IRQ_NONE;
3044
3045 while (iir & ~flip_mask) {
3046 /* Can't rely on pipestat interrupt bit in iir as it might
3047 * have been cleared after the pipestat interrupt was received.
3048 * It doesn't set the bit in iir again, but it still produces
3049 * interrupts (for non-MSI).
3050 */
3051 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3052 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3053 i915_handle_error(dev, false);
3054
3055 for_each_pipe(pipe) {
3056 int reg = PIPESTAT(pipe);
3057 pipe_stats[pipe] = I915_READ(reg);
3058
3059 /*
3060 * Clear the PIPE*STAT regs before the IIR
3061 */
3062 if (pipe_stats[pipe] & 0x8000ffff) {
3063 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3064 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3065 pipe_name(pipe));
3066 I915_WRITE(reg, pipe_stats[pipe]);
3067 irq_received = 1;
3068 }
3069 }
3070 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3071
3072 I915_WRITE16(IIR, iir & ~flip_mask);
3073 new_iir = I915_READ16(IIR); /* Flush posted writes */
3074
d05c617e 3075 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 3076
3077 if (iir & I915_USER_INTERRUPT)
3078 notify_ring(dev, &dev_priv->ring[RCS]);
3079
3080 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3081 i8xx_handle_vblank(dev, 0, iir))
3082 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 3083
3084 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3085 i8xx_handle_vblank(dev, 1, iir))
3086 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 3087
3088 iir = new_iir;
3089 }
3090
3091 return IRQ_HANDLED;
3092}
3093
3094static void i8xx_irq_uninstall(struct drm_device * dev)
3095{
3096 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3097 int pipe;
3098
c2798b19
CW		 3099 for_each_pipe(pipe) {
3100 /* Clear enable bits; then clear status bits */
3101 I915_WRITE(PIPESTAT(pipe), 0);
3102 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3103 }
3104 I915_WRITE16(IMR, 0xffff);
3105 I915_WRITE16(IER, 0x0);
3106 I915_WRITE16(IIR, I915_READ16(IIR));
3107}
3108
a266c7d5
CW		 3109static void i915_irq_preinstall(struct drm_device * dev)
3110{
3111 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3112 int pipe;
3113
3114 atomic_set(&dev_priv->irq_received, 0);
3115
3116 if (I915_HAS_HOTPLUG(dev)) {
3117 I915_WRITE(PORT_HOTPLUG_EN, 0);
3118 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3119 }
3120
00d98ebd 3121 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 3122 for_each_pipe(pipe)
3123 I915_WRITE(PIPESTAT(pipe), 0);
3124 I915_WRITE(IMR, 0xffffffff);
3125 I915_WRITE(IER, 0x0);
3126 POSTING_READ(IER);
3127}
3128
3129static int i915_irq_postinstall(struct drm_device *dev)
3130{
3131 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 3132 u32 enable_mask;
a266c7d5 3133
38bde180
CW		 3134 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3135
3136 /* Unmask the interrupts that we always want on. */
3137 dev_priv->irq_mask =
3138 ~(I915_ASLE_INTERRUPT |
3139 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3140 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3141 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3142 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3143 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3144
3145 enable_mask =
3146 I915_ASLE_INTERRUPT |
3147 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3148 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3149 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3150 I915_USER_INTERRUPT;
3151
a266c7d5 3152 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3153 I915_WRITE(PORT_HOTPLUG_EN, 0);
3154 POSTING_READ(PORT_HOTPLUG_EN);
3155
a266c7d5
CW		 3156 /* Enable in IER... */
3157 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3158 /* and unmask in IMR */
3159 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3160 }
3161
a266c7d5
CW		 3162 I915_WRITE(IMR, dev_priv->irq_mask);
3163 I915_WRITE(IER, enable_mask);
3164 POSTING_READ(IER);
3165
f49e38dd 3166 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3167
3168 return 0;
3169}
3170
90a72f87
VS		 3171/*
3172 * Returns true when a page flip has completed.
3173 */
3174static bool i915_handle_vblank(struct drm_device *dev,
3175 int plane, int pipe, u32 iir)
3176{
3177 drm_i915_private_t *dev_priv = dev->dev_private;
3178 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3179
3180 if (!drm_handle_vblank(dev, pipe))
3181 return false;
3182
3183 if ((iir & flip_pending) == 0)
3184 return false;
3185
3186 intel_prepare_page_flip(dev, plane);
3187
3188 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3189 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3190 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3191 * the flip is completed (no longer pending). Since this doesn't raise
3192 * an interrupt per se, we watch for the change at vblank.
3193 */
3194 if (I915_READ(ISR) & flip_pending)
3195 return false;
3196
3197 intel_finish_page_flip(dev, pipe);
3198
3199 return true;
3200}
3201
ff1f525e 3202static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 3203{
3204 struct drm_device *dev = (struct drm_device *) arg;
3205 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 3206 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 3207 unsigned long irqflags;
38bde180
CW		 3208 u32 flip_mask =
3209 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3210 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3211 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 3212
3213 atomic_inc(&dev_priv->irq_received);
3214
3215 iir = I915_READ(IIR);
38bde180
CW		 3216 do {
3217 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3218 bool blc_event = false;
a266c7d5
CW		 3219
3220 /* Can't rely on pipestat interrupt bit in iir as it might
3221 * have been cleared after the pipestat interrupt was received.
3222 * It doesn't set the bit in iir again, but it still produces
3223 * interrupts (for non-MSI).
3224 */
3225 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3226 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3227 i915_handle_error(dev, false);
3228
3229 for_each_pipe(pipe) {
3230 int reg = PIPESTAT(pipe);
3231 pipe_stats[pipe] = I915_READ(reg);
3232
38bde180 3233 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 3234 if (pipe_stats[pipe] & 0x8000ffff) {
3235 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3236 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3237 pipe_name(pipe));
3238 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3239 irq_received = true;
a266c7d5
CW		 3240 }
3241 }
3242 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3243
3244 if (!irq_received)
3245 break;
3246
a266c7d5
CW		 3247 /* Consume port. Then clear IIR or we'll miss events */
3248 if ((I915_HAS_HOTPLUG(dev)) &&
3249 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3250 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 3251 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 3252
3253 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3254 hotplug_status);
91d131d2
DV		 3255
3256 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3257
a266c7d5 3258 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 3259 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 3260 }
3261
38bde180 3262 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3263 new_iir = I915_READ(IIR); /* Flush posted writes */
3264
a266c7d5
CW		 3265 if (iir & I915_USER_INTERRUPT)
3266 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3267
a266c7d5 3268 for_each_pipe(pipe) {
38bde180
CW		 3269 int plane = pipe;
3270 if (IS_MOBILE(dev))
3271 plane = !plane;
90a72f87 3272
8291ee90 3273 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3274 i915_handle_vblank(dev, plane, pipe, iir))
3275 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3276
3277 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3278 blc_event = true;
3279 }
3280
a266c7d5
CW		 3281 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3282 intel_opregion_asle_intr(dev);
3283
3284 /* With MSI, interrupts are only generated when iir
3285 * transitions from zero to nonzero. If another bit got
3286 * set while we were handling the existing iir bits, then
3287 * we would never get another interrupt.
3288 *
3289 * This is fine on non-MSI as well, as if we hit this path
3290 * we avoid exiting the interrupt handler only to generate
3291 * another one.
3292 *
3293 * Note that for MSI this could cause a stray interrupt report
3294 * if an interrupt landed in the time between writing IIR and
3295 * the posting read. This should be rare enough to never
3296 * trigger the 99% of 100,000 interrupts test for disabling
3297 * stray interrupts.
3298 */
38bde180 3299 ret = IRQ_HANDLED;
a266c7d5 3300 iir = new_iir;
38bde180 3301 } while (iir & ~flip_mask);
a266c7d5 3302
d05c617e 3303 i915_update_dri1_breadcrumb(dev);
8291ee90 3304
a266c7d5
CW		 3305 return ret;
3306}
3307
3308static void i915_irq_uninstall(struct drm_device * dev)
3309{
3310 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3311 int pipe;
3312
ac4c16c5
EE		 3313 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3314
a266c7d5
CW		 3315 if (I915_HAS_HOTPLUG(dev)) {
3316 I915_WRITE(PORT_HOTPLUG_EN, 0);
3317 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3318 }
3319
00d98ebd 3320 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3321 for_each_pipe(pipe) {
3322 /* Clear enable bits; then clear status bits */
a266c7d5 3323 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3324 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3325 }
a266c7d5
CW		 3326 I915_WRITE(IMR, 0xffffffff);
3327 I915_WRITE(IER, 0x0);
3328
a266c7d5
CW		 3329 I915_WRITE(IIR, I915_READ(IIR));
3330}
3331
3332static void i965_irq_preinstall(struct drm_device * dev)
3333{
3334 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3335 int pipe;
3336
3337 atomic_set(&dev_priv->irq_received, 0);
3338
adca4730
CW		 3339 I915_WRITE(PORT_HOTPLUG_EN, 0);
3340 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3341
3342 I915_WRITE(HWSTAM, 0xeffe);
3343 for_each_pipe(pipe)
3344 I915_WRITE(PIPESTAT(pipe), 0);
3345 I915_WRITE(IMR, 0xffffffff);
3346 I915_WRITE(IER, 0x0);
3347 POSTING_READ(IER);
3348}
3349
3350static int i965_irq_postinstall(struct drm_device *dev)
3351{
3352 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 3353 u32 enable_mask;
a266c7d5 3354 u32 error_mask;
b79480ba 3355 unsigned long irqflags;
a266c7d5 3356
a266c7d5 3357 /* Unmask the interrupts that we always want on. */
bbba0a97 3358 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3359 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3360 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3361 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3362 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3363 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3364 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3365
3366 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3367 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3368 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3369 enable_mask |= I915_USER_INTERRUPT;
3370
3371 if (IS_G4X(dev))
3372 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3373
b79480ba
DV		 3374 /* Interrupt setup is already guaranteed to be single-threaded, this is
3375 * just to make the assert_spin_locked check happy. */
3376 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
515ac2bb 3377 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
b79480ba 3378 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 3379
a266c7d5
CW		 3380 /*
3381 * Enable some error detection, note the instruction error mask
3382 * bit is reserved, so we leave it masked.
3383 */
3384 if (IS_G4X(dev)) {
3385 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3386 GM45_ERROR_MEM_PRIV |
3387 GM45_ERROR_CP_PRIV |
3388 I915_ERROR_MEMORY_REFRESH);
3389 } else {
3390 error_mask = ~(I915_ERROR_PAGE_TABLE |
3391 I915_ERROR_MEMORY_REFRESH);
3392 }
3393 I915_WRITE(EMR, error_mask);
3394
3395 I915_WRITE(IMR, dev_priv->irq_mask);
3396 I915_WRITE(IER, enable_mask);
3397 POSTING_READ(IER);
3398
20afbda2
DV		 3399 I915_WRITE(PORT_HOTPLUG_EN, 0);
3400 POSTING_READ(PORT_HOTPLUG_EN);
3401
f49e38dd 3402 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3403
3404 return 0;
3405}
3406
bac56d5b 3407static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 3408{
3409 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 3410 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3411 struct intel_encoder *intel_encoder;
20afbda2
DV		 3412 u32 hotplug_en;
3413
b5ea2d56
DV		 3414 assert_spin_locked(&dev_priv->irq_lock);
3415
bac56d5b
EE		 3416 if (I915_HAS_HOTPLUG(dev)) {
3417 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3418 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3419 /* Note HDMI and DP share hotplug bits */
e5868a31 3420 /* enable bits are the same for all generations */
cd569aed
EE		 3421 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3422 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3423 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3424 /* Programming the CRT detection parameters tends
3425 to generate a spurious hotplug event about three
3426 seconds later. So just do it once.
3427 */
3428 if (IS_G4X(dev))
3429 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3430 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3431 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3432
bac56d5b
EE		 3433 /* Ignore TV since it's buggy */
3434 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3435 }
a266c7d5
CW		 3436}
3437
ff1f525e 3438static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3439{
3440 struct drm_device *dev = (struct drm_device *) arg;
3441 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 3442 u32 iir, new_iir;
3443 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 3444 unsigned long irqflags;
3445 int irq_received;
3446 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3447 u32 flip_mask =
3448 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3449 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 3450
3451 atomic_inc(&dev_priv->irq_received);
3452
3453 iir = I915_READ(IIR);
3454
a266c7d5 3455 for (;;) {
2c8ba29f
CW		 3456 bool blc_event = false;
3457
21ad8330 3458 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 3459
3460 /* Can't rely on pipestat interrupt bit in iir as it might
3461 * have been cleared after the pipestat interrupt was received.
3462 * It doesn't set the bit in iir again, but it still produces
3463 * interrupts (for non-MSI).
3464 */
3465 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3466 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3467 i915_handle_error(dev, false);
3468
3469 for_each_pipe(pipe) {
3470 int reg = PIPESTAT(pipe);
3471 pipe_stats[pipe] = I915_READ(reg);
3472
3473 /*
3474 * Clear the PIPE*STAT regs before the IIR
3475 */
3476 if (pipe_stats[pipe] & 0x8000ffff) {
3477 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3478 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3479 pipe_name(pipe));
3480 I915_WRITE(reg, pipe_stats[pipe]);
3481 irq_received = 1;
3482 }
3483 }
3484 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3485
3486 if (!irq_received)
3487 break;
3488
3489 ret = IRQ_HANDLED;
3490
3491 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3492 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3493 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3494 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3495 HOTPLUG_INT_STATUS_G4X :
4f7fd709 3496 HOTPLUG_INT_STATUS_I915);
a266c7d5
CW		 3497
3498 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3499 hotplug_status);
91d131d2
DV		 3500
3501 intel_hpd_irq_handler(dev, hotplug_trigger,
3502 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3503
a266c7d5
CW		 3504 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3505 I915_READ(PORT_HOTPLUG_STAT);
3506 }
3507
21ad8330 3508 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3509 new_iir = I915_READ(IIR); /* Flush posted writes */
3510
a266c7d5
CW		 3511 if (iir & I915_USER_INTERRUPT)
3512 notify_ring(dev, &dev_priv->ring[RCS]);
3513 if (iir & I915_BSD_USER_INTERRUPT)
3514 notify_ring(dev, &dev_priv->ring[VCS]);
3515
a266c7d5 3516 for_each_pipe(pipe) {
2c8ba29f 3517 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3518 i915_handle_vblank(dev, pipe, pipe, iir))
3519 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3520
3521 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3522 blc_event = true;
3523 }
3524
3525
3526 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3527 intel_opregion_asle_intr(dev);
3528
515ac2bb
DV		 3529 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3530 gmbus_irq_handler(dev);
3531
a266c7d5
CW		 3532 /* With MSI, interrupts are only generated when iir
3533 * transitions from zero to nonzero. If another bit got
3534 * set while we were handling the existing iir bits, then
3535 * we would never get another interrupt.
3536 *
3537 * This is fine on non-MSI as well, as if we hit this path
3538 * we avoid exiting the interrupt handler only to generate
3539 * another one.
3540 *
3541 * Note that for MSI this could cause a stray interrupt report
3542 * if an interrupt landed in the time between writing IIR and
3543 * the posting read. This should be rare enough to never
3544 * trigger the 99% of 100,000 interrupts test for disabling
3545 * stray interrupts.
3546 */
3547 iir = new_iir;
3548 }
3549
d05c617e 3550 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3551
a266c7d5
CW		 3552 return ret;
3553}
3554
3555static void i965_irq_uninstall(struct drm_device * dev)
3556{
3557 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3558 int pipe;
3559
3560 if (!dev_priv)
3561 return;
3562
ac4c16c5
EE		 3563 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3564
adca4730
CW		 3565 I915_WRITE(PORT_HOTPLUG_EN, 0);
3566 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3567
3568 I915_WRITE(HWSTAM, 0xffffffff);
3569 for_each_pipe(pipe)
3570 I915_WRITE(PIPESTAT(pipe), 0);
3571 I915_WRITE(IMR, 0xffffffff);
3572 I915_WRITE(IER, 0x0);
3573
3574 for_each_pipe(pipe)
3575 I915_WRITE(PIPESTAT(pipe),
3576 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3577 I915_WRITE(IIR, I915_READ(IIR));
3578}
3579
ac4c16c5
EE		 3580static void i915_reenable_hotplug_timer_func(unsigned long data)
3581{
3582 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3583 struct drm_device *dev = dev_priv->dev;
3584 struct drm_mode_config *mode_config = &dev->mode_config;
3585 unsigned long irqflags;
3586 int i;
3587
3588 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3589 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3590 struct drm_connector *connector;
3591
3592 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3593 continue;
3594
3595 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3596
3597 list_for_each_entry(connector, &mode_config->connector_list, head) {
3598 struct intel_connector *intel_connector = to_intel_connector(connector);
3599
3600 if (intel_connector->encoder->hpd_pin == i) {
3601 if (connector->polled != intel_connector->polled)
3602 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3603 drm_get_connector_name(connector));
3604 connector->polled = intel_connector->polled;
3605 if (!connector->polled)
3606 connector->polled = DRM_CONNECTOR_POLL_HPD;
3607 }
3608 }
3609 }
3610 if (dev_priv->display.hpd_irq_setup)
3611 dev_priv->display.hpd_irq_setup(dev);
3612 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3613}
3614
f71d4af4
JB		 3615void intel_irq_init(struct drm_device *dev)
3616{
8b2e326d
CW		 3617 struct drm_i915_private *dev_priv = dev->dev_private;
3618
3619 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3620 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3621 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3622 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3623
99584db3
DV		 3624 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3625 i915_hangcheck_elapsed,
61bac78e 3626 (unsigned long) dev);
ac4c16c5
EE		 3627 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3628 (unsigned long) dev_priv);
61bac78e 3629
97a19a24 3630 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3631
f71d4af4
JB		 3632 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3633 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 3634 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3635 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3636 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3637 }
3638
c3613de9
KP		 3639 if (drm_core_check_feature(dev, DRIVER_MODESET))
3640 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3641 else
3642 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 3643 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3644
7e231dbe
JB		 3645 if (IS_VALLEYVIEW(dev)) {
3646 dev->driver->irq_handler = valleyview_irq_handler;
3647 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3648 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3649 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3650 dev->driver->enable_vblank = valleyview_enable_vblank;
3651 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3652 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4a06e201 3653 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7d99163d 3654 /* Share uninstall handlers with ILK/SNB */
f71d4af4 3655 dev->driver->irq_handler = ivybridge_irq_handler;
7d99163d 3656 dev->driver->irq_preinstall = ivybridge_irq_preinstall;
f71d4af4
JB		 3657 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3658 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3659 dev->driver->enable_vblank = ivybridge_enable_vblank;
3660 dev->driver->disable_vblank = ivybridge_disable_vblank;
82a28bcf 3661 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 3662 } else if (HAS_PCH_SPLIT(dev)) {
3663 dev->driver->irq_handler = ironlake_irq_handler;
3664 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3665 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3666 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3667 dev->driver->enable_vblank = ironlake_enable_vblank;
3668 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3669 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3670 } else {
c2798b19
CW		 3671 if (INTEL_INFO(dev)->gen == 2) {
3672 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3673 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3674 dev->driver->irq_handler = i8xx_irq_handler;
3675 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3676 } else if (INTEL_INFO(dev)->gen == 3) {
3677 dev->driver->irq_preinstall = i915_irq_preinstall;
3678 dev->driver->irq_postinstall = i915_irq_postinstall;
3679 dev->driver->irq_uninstall = i915_irq_uninstall;
3680 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3681 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3682 } else {
a266c7d5
CW		 3683 dev->driver->irq_preinstall = i965_irq_preinstall;
3684 dev->driver->irq_postinstall = i965_irq_postinstall;
3685 dev->driver->irq_uninstall = i965_irq_uninstall;
3686 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3687 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3688 }
f71d4af4
JB		 3689 dev->driver->enable_vblank = i915_enable_vblank;
3690 dev->driver->disable_vblank = i915_disable_vblank;
3691 }
3692}
20afbda2
DV		 3693
3694void intel_hpd_init(struct drm_device *dev)
3695{
3696 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3697 struct drm_mode_config *mode_config = &dev->mode_config;
3698 struct drm_connector *connector;
b5ea2d56 3699 unsigned long irqflags;
821450c6 3700 int i;
20afbda2 3701
821450c6
EE		 3702 for (i = 1; i < HPD_NUM_PINS; i++) {
3703 dev_priv->hpd_stats[i].hpd_cnt = 0;
3704 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3705 }
3706 list_for_each_entry(connector, &mode_config->connector_list, head) {
3707 struct intel_connector *intel_connector = to_intel_connector(connector);
3708 connector->polled = intel_connector->polled;
3709 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3710 connector->polled = DRM_CONNECTOR_POLL_HPD;
3711 }
b5ea2d56
DV		 3712
3713 /* Interrupt setup is already guaranteed to be single-threaded, this is
3714 * just to make the assert_spin_locked checks happy. */
3715 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3716 if (dev_priv->display.hpd_irq_setup)
3717 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3718 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3719}
Linux kernel - Deliverables
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