projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: use the default context
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
f97108d1
JB		 299static void i915_handle_rps_change(struct drm_device *dev)
300{
301 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 302 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 303 u8 new_delay = dev_priv->cur_delay;
304
7648fa99 305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
310
311 /* Handle RCS change request from hw */
b5b72e89 312 if (busy_up > max_avg) {
f97108d1
JB		 313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
b5b72e89 317 } else if (busy_down < min_avg) {
f97108d1
JB		 318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
322 }
323
7648fa99
JB		 324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
f97108d1
JB		 326
327 return;
328}
329
549f7365
CW		 330static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
332{
333 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 334
475553de
CW		 335 if (ring->obj == NULL)
336 return;
337
6d171cb4 338 trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
9862e600 339
549f7365 340 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 341 if (i915_enable_hangcheck) {
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer,
344 jiffies +
345 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
346 }
549f7365
CW		 347}
348
4912d041 349static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 350{
4912d041
BW		 351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
352 rps_work);
4912d041 353 u32 pm_iir, pm_imr;
7b9e0ae6 354 u8 new_delay;
4912d041
BW		 355
356 spin_lock_irq(&dev_priv->rps_lock);
357 pm_iir = dev_priv->pm_iir;
358 dev_priv->pm_iir = 0;
359 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 360 I915_WRITE(GEN6_PMIMR, 0);
4912d041 361 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 362
7b9e0ae6 363 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 364 return;
365
4912d041 366 mutex_lock(&dev_priv->dev->struct_mutex);
7b9e0ae6
CW		 367
368 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
369 new_delay = dev_priv->cur_delay + 1;
370 else
371 new_delay = dev_priv->cur_delay - 1;
3b8d8d91 372
4912d041 373 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 374
4912d041 375 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 376}
377
e3689190
BW		 378
379/**
380 * ivybridge_parity_work - Workqueue called when a parity error interrupt
381 * occurred.
382 * @work: workqueue struct
383 *
384 * Doesn't actually do anything except notify userspace. As a consequence of
385 * this event, userspace should try to remap the bad rows since statistically
386 * it is likely the same row is more likely to go bad again.
387 */
388static void ivybridge_parity_work(struct work_struct *work)
389{
390 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
391 parity_error_work);
392 u32 error_status, row, bank, subbank;
393 char *parity_event[5];
394 uint32_t misccpctl;
395 unsigned long flags;
396
397 /* We must turn off DOP level clock gating to access the L3 registers.
398 * In order to prevent a get/put style interface, acquire struct mutex
399 * any time we access those registers.
400 */
401 mutex_lock(&dev_priv->dev->struct_mutex);
402
403 misccpctl = I915_READ(GEN7_MISCCPCTL);
404 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
405 POSTING_READ(GEN7_MISCCPCTL);
406
407 error_status = I915_READ(GEN7_L3CDERRST1);
408 row = GEN7_PARITY_ERROR_ROW(error_status);
409 bank = GEN7_PARITY_ERROR_BANK(error_status);
410 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
411
412 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
413 GEN7_L3CDERRST1_ENABLE);
414 POSTING_READ(GEN7_L3CDERRST1);
415
416 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
417
418 spin_lock_irqsave(&dev_priv->irq_lock, flags);
419 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
420 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
421 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
422
423 mutex_unlock(&dev_priv->dev->struct_mutex);
424
425 parity_event[0] = "L3_PARITY_ERROR=1";
426 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
427 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
428 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
429 parity_event[4] = NULL;
430
431 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
432 KOBJ_CHANGE, parity_event);
433
434 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
435 row, bank, subbank);
436
437 kfree(parity_event[3]);
438 kfree(parity_event[2]);
439 kfree(parity_event[1]);
440}
441
d2ba8470 442static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 443{
444 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
445 unsigned long flags;
446
447 if (!IS_IVYBRIDGE(dev))
448 return;
449
450 spin_lock_irqsave(&dev_priv->irq_lock, flags);
451 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
452 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
453 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
454
455 queue_work(dev_priv->wq, &dev_priv->parity_error_work);
456}
457
e7b4c6b1
DV		 458static void snb_gt_irq_handler(struct drm_device *dev,
459 struct drm_i915_private *dev_priv,
460 u32 gt_iir)
461{
462
463 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
464 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
465 notify_ring(dev, &dev_priv->ring[RCS]);
466 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
467 notify_ring(dev, &dev_priv->ring[VCS]);
468 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
469 notify_ring(dev, &dev_priv->ring[BCS]);
470
471 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
472 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
473 GT_RENDER_CS_ERROR_INTERRUPT)) {
474 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
475 i915_handle_error(dev, false);
476 }
e3689190
BW		 477
478 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
479 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 480}
481
fc6826d1
CW		 482static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
483 u32 pm_iir)
484{
485 unsigned long flags;
486
487 /*
488 * IIR bits should never already be set because IMR should
489 * prevent an interrupt from being shown in IIR. The warning
490 * displays a case where we've unsafely cleared
491 * dev_priv->pm_iir. Although missing an interrupt of the same
492 * type is not a problem, it displays a problem in the logic.
493 *
494 * The mask bit in IMR is cleared by rps_work.
495 */
496
497 spin_lock_irqsave(&dev_priv->rps_lock, flags);
498 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
499 dev_priv->pm_iir |= pm_iir;
500 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
501 POSTING_READ(GEN6_PMIMR);
502 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
503
504 queue_work(dev_priv->wq, &dev_priv->rps_work);
505}
506
7e231dbe
JB		 507static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
508{
509 struct drm_device *dev = (struct drm_device *) arg;
510 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
511 u32 iir, gt_iir, pm_iir;
512 irqreturn_t ret = IRQ_NONE;
513 unsigned long irqflags;
514 int pipe;
515 u32 pipe_stats[I915_MAX_PIPES];
516 u32 vblank_status;
517 int vblank = 0;
518 bool blc_event;
519
520 atomic_inc(&dev_priv->irq_received);
521
522 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
523 PIPE_VBLANK_INTERRUPT_STATUS;
524
525 while (true) {
526 iir = I915_READ(VLV_IIR);
527 gt_iir = I915_READ(GTIIR);
528 pm_iir = I915_READ(GEN6_PMIIR);
529
530 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
531 goto out;
532
533 ret = IRQ_HANDLED;
534
e7b4c6b1 535 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 536
537 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
538 for_each_pipe(pipe) {
539 int reg = PIPESTAT(pipe);
540 pipe_stats[pipe] = I915_READ(reg);
541
542 /*
543 * Clear the PIPE*STAT regs before the IIR
544 */
545 if (pipe_stats[pipe] & 0x8000ffff) {
546 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
547 DRM_DEBUG_DRIVER("pipe %c underrun\n",
548 pipe_name(pipe));
549 I915_WRITE(reg, pipe_stats[pipe]);
550 }
551 }
552 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
553
554 /* Consume port. Then clear IIR or we'll miss events */
555 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
556 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
557
558 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
559 hotplug_status);
560 if (hotplug_status & dev_priv->hotplug_supported_mask)
561 queue_work(dev_priv->wq,
562 &dev_priv->hotplug_work);
563
564 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
565 I915_READ(PORT_HOTPLUG_STAT);
566 }
567
568
569 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
570 drm_handle_vblank(dev, 0);
571 vblank++;
e0f608d7 572 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 573 }
574
575 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
576 drm_handle_vblank(dev, 1);
577 vblank++;
e0f608d7 578 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 579 }
580
581 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
582 blc_event = true;
583
fc6826d1
CW		 584 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
585 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 586
587 I915_WRITE(GTIIR, gt_iir);
588 I915_WRITE(GEN6_PMIIR, pm_iir);
589 I915_WRITE(VLV_IIR, iir);
590 }
591
592out:
593 return ret;
594}
595
9adab8b5 596static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 597{
598 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 599 int pipe;
776ad806 600
776ad806
JB		 601 if (pch_iir & SDE_AUDIO_POWER_MASK)
602 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
603 (pch_iir & SDE_AUDIO_POWER_MASK) >>
604 SDE_AUDIO_POWER_SHIFT);
605
606 if (pch_iir & SDE_GMBUS)
607 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
608
609 if (pch_iir & SDE_AUDIO_HDCP_MASK)
610 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
611
612 if (pch_iir & SDE_AUDIO_TRANS_MASK)
613 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
614
615 if (pch_iir & SDE_POISON)
616 DRM_ERROR("PCH poison interrupt\n");
617
9db4a9c7
JB		 618 if (pch_iir & SDE_FDI_MASK)
619 for_each_pipe(pipe)
620 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
621 pipe_name(pipe),
622 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 623
624 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
625 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
626
627 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
628 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
629
630 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
631 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
632 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
633 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
634}
635
f71d4af4 636static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 637{
638 struct drm_device *dev = (struct drm_device *) arg;
639 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 640 u32 de_iir, gt_iir, de_ier, pm_iir;
641 irqreturn_t ret = IRQ_NONE;
642 int i;
b1f14ad0
JB		 643
644 atomic_inc(&dev_priv->irq_received);
645
646 /* disable master interrupt before clearing iir */
647 de_ier = I915_READ(DEIER);
648 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 649
b1f14ad0 650 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 651 if (gt_iir) {
652 snb_gt_irq_handler(dev, dev_priv, gt_iir);
653 I915_WRITE(GTIIR, gt_iir);
654 ret = IRQ_HANDLED;
b1f14ad0
JB		 655 }
656
0e43406b
CW		 657 de_iir = I915_READ(DEIIR);
658 if (de_iir) {
659 if (de_iir & DE_GSE_IVB)
660 intel_opregion_gse_intr(dev);
661
662 for (i = 0; i < 3; i++) {
663 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
664 intel_prepare_page_flip(dev, i);
665 intel_finish_page_flip_plane(dev, i);
666 }
667 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
668 drm_handle_vblank(dev, i);
669 }
b615b57a 670
0e43406b
CW		 671 /* check event from PCH */
672 if (de_iir & DE_PCH_EVENT_IVB) {
673 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 674
0e43406b
CW		 675 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
676 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
677 pch_irq_handler(dev, pch_iir);
b1f14ad0 678
0e43406b
CW		 679 /* clear PCH hotplug event before clear CPU irq */
680 I915_WRITE(SDEIIR, pch_iir);
681 }
b615b57a 682
0e43406b
CW		 683 I915_WRITE(DEIIR, de_iir);
684 ret = IRQ_HANDLED;
b1f14ad0
JB		 685 }
686
0e43406b
CW		 687 pm_iir = I915_READ(GEN6_PMIIR);
688 if (pm_iir) {
689 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
690 gen6_queue_rps_work(dev_priv, pm_iir);
691 I915_WRITE(GEN6_PMIIR, pm_iir);
692 ret = IRQ_HANDLED;
693 }
b1f14ad0 694
b1f14ad0
JB		 695 I915_WRITE(DEIER, de_ier);
696 POSTING_READ(DEIER);
697
698 return ret;
699}
700
e7b4c6b1
DV		 701static void ilk_gt_irq_handler(struct drm_device *dev,
702 struct drm_i915_private *dev_priv,
703 u32 gt_iir)
704{
705 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
706 notify_ring(dev, &dev_priv->ring[RCS]);
707 if (gt_iir & GT_BSD_USER_INTERRUPT)
708 notify_ring(dev, &dev_priv->ring[VCS]);
709}
710
f71d4af4 711static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 712{
4697995b 713 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 714 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
715 int ret = IRQ_NONE;
3b8d8d91 716 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 717 u32 hotplug_mask;
881f47b6 718
4697995b
JB		 719 atomic_inc(&dev_priv->irq_received);
720
2d109a84
ZN		 721 /* disable master interrupt before clearing iir */
722 de_ier = I915_READ(DEIER);
723 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 724 POSTING_READ(DEIER);
2d109a84 725
036a4a7d
ZW		 726 de_iir = I915_READ(DEIIR);
727 gt_iir = I915_READ(GTIIR);
c650156a 728 pch_iir = I915_READ(SDEIIR);
3b8d8d91 729 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 730
3b8d8d91
JB		 731 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
732 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 733 goto done;
036a4a7d 734
2d7b8366
YL		 735 if (HAS_PCH_CPT(dev))
736 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
737 else
738 hotplug_mask = SDE_HOTPLUG_MASK;
739
c7c85101 740 ret = IRQ_HANDLED;
036a4a7d 741
e7b4c6b1
DV		 742 if (IS_GEN5(dev))
743 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
744 else
745 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 746
c7c85101 747 if (de_iir & DE_GSE)
3b617967 748 intel_opregion_gse_intr(dev);
c650156a 749
f072d2e7 750 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 751 intel_prepare_page_flip(dev, 0);
2bbda389 752 intel_finish_page_flip_plane(dev, 0);
f072d2e7 753 }
013d5aa2 754
f072d2e7 755 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 756 intel_prepare_page_flip(dev, 1);
2bbda389 757 intel_finish_page_flip_plane(dev, 1);
f072d2e7 758 }
013d5aa2 759
f072d2e7 760 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 761 drm_handle_vblank(dev, 0);
762
f072d2e7 763 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 764 drm_handle_vblank(dev, 1);
765
c7c85101 766 /* check event from PCH */
776ad806
JB		 767 if (de_iir & DE_PCH_EVENT) {
768 if (pch_iir & hotplug_mask)
769 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
9adab8b5 770 pch_irq_handler(dev, pch_iir);
776ad806 771 }
036a4a7d 772
f97108d1 773 if (de_iir & DE_PCU_EVENT) {
7648fa99 774 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 775 i915_handle_rps_change(dev);
776 }
777
fc6826d1
CW		 778 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
779 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 780
c7c85101
ZN		 781 /* should clear PCH hotplug event before clear CPU irq */
782 I915_WRITE(SDEIIR, pch_iir);
783 I915_WRITE(GTIIR, gt_iir);
784 I915_WRITE(DEIIR, de_iir);
4912d041 785 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 786
787done:
2d109a84 788 I915_WRITE(DEIER, de_ier);
3143a2bf 789 POSTING_READ(DEIER);
2d109a84 790
036a4a7d
ZW		 791 return ret;
792}
793
8a905236
JB		 794/**
795 * i915_error_work_func - do process context error handling work
796 * @work: work struct
797 *
798 * Fire an error uevent so userspace can see that a hang or error
799 * was detected.
800 */
801static void i915_error_work_func(struct work_struct *work)
802{
803 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
804 error_work);
805 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 806 char *error_event[] = { "ERROR=1", NULL };
807 char *reset_event[] = { "RESET=1", NULL };
808 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 809
f316a42c
BG		 810 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
811
ba1234d1 812 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 813 DRM_DEBUG_DRIVER("resetting chip\n");
814 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 815 if (!i915_reset(dev)) {
f803aa55
CW		 816 atomic_set(&dev_priv->mm.wedged, 0);
817 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 818 }
30dbf0c0 819 complete_all(&dev_priv->error_completion);
f316a42c 820 }
8a905236
JB		 821}
822
3bd3c932 823#ifdef CONFIG_DEBUG_FS
9df30794 824static struct drm_i915_error_object *
bcfb2e28 825i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 826 struct drm_i915_gem_object *src)
9df30794
CW		 827{
828 struct drm_i915_error_object *dst;
9df30794 829 int page, page_count;
e56660dd 830 u32 reloc_offset;
9df30794 831
05394f39 832 if (src == NULL || src->pages == NULL)
9df30794
CW		 833 return NULL;
834
05394f39 835 page_count = src->base.size / PAGE_SIZE;
9df30794 836
0206e353 837 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 838 if (dst == NULL)
839 return NULL;
840
05394f39 841 reloc_offset = src->gtt_offset;
9df30794 842 for (page = 0; page < page_count; page++) {
788885ae 843 unsigned long flags;
e56660dd 844 void *d;
788885ae 845
e56660dd 846 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 847 if (d == NULL)
848 goto unwind;
e56660dd 849
788885ae 850 local_irq_save(flags);
74898d7e
DV		 851 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
852 src->has_global_gtt_mapping) {
172975aa
CW		 853 void __iomem *s;
854
855 /* Simply ignore tiling or any overlapping fence.
856 * It's part of the error state, and this hopefully
857 * captures what the GPU read.
858 */
859
860 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
861 reloc_offset);
862 memcpy_fromio(d, s, PAGE_SIZE);
863 io_mapping_unmap_atomic(s);
864 } else {
865 void *s;
866
867 drm_clflush_pages(&src->pages[page], 1);
868
869 s = kmap_atomic(src->pages[page]);
870 memcpy(d, s, PAGE_SIZE);
871 kunmap_atomic(s);
872
873 drm_clflush_pages(&src->pages[page], 1);
874 }
788885ae 875 local_irq_restore(flags);
e56660dd 876
9df30794 877 dst->pages[page] = d;
e56660dd
CW		 878
879 reloc_offset += PAGE_SIZE;
9df30794
CW		 880 }
881 dst->page_count = page_count;
05394f39 882 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 883
884 return dst;
885
886unwind:
887 while (page--)
888 kfree(dst->pages[page]);
889 kfree(dst);
890 return NULL;
891}
892
893static void
894i915_error_object_free(struct drm_i915_error_object *obj)
895{
896 int page;
897
898 if (obj == NULL)
899 return;
900
901 for (page = 0; page < obj->page_count; page++)
902 kfree(obj->pages[page]);
903
904 kfree(obj);
905}
906
742cbee8
DV		 907void
908i915_error_state_free(struct kref *error_ref)
9df30794 909{
742cbee8
DV		 910 struct drm_i915_error_state *error = container_of(error_ref,
911 typeof(*error), ref);
e2f973d5
CW		 912 int i;
913
52d39a21
CW		 914 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
915 i915_error_object_free(error->ring[i].batchbuffer);
916 i915_error_object_free(error->ring[i].ringbuffer);
917 kfree(error->ring[i].requests);
918 }
e2f973d5 919
9df30794 920 kfree(error->active_bo);
6ef3d427 921 kfree(error->overlay);
9df30794
CW		 922 kfree(error);
923}
1b50247a
CW		 924static void capture_bo(struct drm_i915_error_buffer *err,
925 struct drm_i915_gem_object *obj)
926{
927 err->size = obj->base.size;
928 err->name = obj->base.name;
929 err->seqno = obj->last_rendering_seqno;
930 err->gtt_offset = obj->gtt_offset;
931 err->read_domains = obj->base.read_domains;
932 err->write_domain = obj->base.write_domain;
933 err->fence_reg = obj->fence_reg;
934 err->pinned = 0;
935 if (obj->pin_count > 0)
936 err->pinned = 1;
937 if (obj->user_pin_count > 0)
938 err->pinned = -1;
939 err->tiling = obj->tiling_mode;
940 err->dirty = obj->dirty;
941 err->purgeable = obj->madv != I915_MADV_WILLNEED;
942 err->ring = obj->ring ? obj->ring->id : -1;
943 err->cache_level = obj->cache_level;
944}
9df30794 945
1b50247a
CW		 946static u32 capture_active_bo(struct drm_i915_error_buffer *err,
947 int count, struct list_head *head)
c724e8a9
CW		 948{
949 struct drm_i915_gem_object *obj;
950 int i = 0;
951
952 list_for_each_entry(obj, head, mm_list) {
1b50247a 953 capture_bo(err++, obj);
c724e8a9
CW		 954 if (++i == count)
955 break;
1b50247a
CW		 956 }
957
958 return i;
959}
960
961static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
962 int count, struct list_head *head)
963{
964 struct drm_i915_gem_object *obj;
965 int i = 0;
966
967 list_for_each_entry(obj, head, gtt_list) {
968 if (obj->pin_count == 0)
969 continue;
c724e8a9 970
1b50247a
CW		 971 capture_bo(err++, obj);
972 if (++i == count)
973 break;
c724e8a9
CW		 974 }
975
976 return i;
977}
978
748ebc60
CW		 979static void i915_gem_record_fences(struct drm_device *dev,
980 struct drm_i915_error_state *error)
981{
982 struct drm_i915_private *dev_priv = dev->dev_private;
983 int i;
984
985 /* Fences */
986 switch (INTEL_INFO(dev)->gen) {
775d17b6 987 case 7:
748ebc60
CW		 988 case 6:
989 for (i = 0; i < 16; i++)
990 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
991 break;
992 case 5:
993 case 4:
994 for (i = 0; i < 16; i++)
995 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
996 break;
997 case 3:
998 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
999 for (i = 0; i < 8; i++)
1000 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1001 case 2:
1002 for (i = 0; i < 8; i++)
1003 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1004 break;
1005
1006 }
1007}
1008
bcfb2e28
CW		 1009static struct drm_i915_error_object *
1010i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1011 struct intel_ring_buffer *ring)
1012{
1013 struct drm_i915_gem_object *obj;
1014 u32 seqno;
1015
1016 if (!ring->get_seqno)
1017 return NULL;
1018
1019 seqno = ring->get_seqno(ring);
1020 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1021 if (obj->ring != ring)
1022 continue;
1023
c37d9a5d 1024 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 1025 continue;
1026
1027 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1028 continue;
1029
1030 /* We need to copy these to an anonymous buffer as the simplest
1031 * method to avoid being overwritten by userspace.
1032 */
1033 return i915_error_object_create(dev_priv, obj);
1034 }
1035
1036 return NULL;
1037}
1038
d27b1e0e
DV		 1039static void i915_record_ring_state(struct drm_device *dev,
1040 struct drm_i915_error_state *error,
1041 struct intel_ring_buffer *ring)
1042{
1043 struct drm_i915_private *dev_priv = dev->dev_private;
1044
33f3f518 1045 if (INTEL_INFO(dev)->gen >= 6) {
33f3f518 1046 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1047 error->semaphore_mboxes[ring->id][0]
1048 = I915_READ(RING_SYNC_0(ring->mmio_base));
1049 error->semaphore_mboxes[ring->id][1]
1050 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1051 }
c1cd90ed 1052
d27b1e0e 1053 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1054 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1055 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1056 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1057 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1058 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 1059 if (ring->id == RCS) {
d27b1e0e
DV		 1060 error->instdone1 = I915_READ(INSTDONE1);
1061 error->bbaddr = I915_READ64(BB_ADDR);
1062 }
1063 } else {
9d2f41fa 1064 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1065 error->ipeir[ring->id] = I915_READ(IPEIR);
1066 error->ipehr[ring->id] = I915_READ(IPEHR);
1067 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1068 }
1069
9574b3fe 1070 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1071 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 1072 error->seqno[ring->id] = ring->get_seqno(ring);
1073 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1074 error->head[ring->id] = I915_READ_HEAD(ring);
1075 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1076
1077 error->cpu_ring_head[ring->id] = ring->head;
1078 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1079}
1080
52d39a21
CW		 1081static void i915_gem_record_rings(struct drm_device *dev,
1082 struct drm_i915_error_state *error)
1083{
1084 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1085 struct intel_ring_buffer *ring;
52d39a21
CW		 1086 struct drm_i915_gem_request *request;
1087 int i, count;
1088
b4519513 1089 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1090 i915_record_ring_state(dev, error, ring);
1091
1092 error->ring[i].batchbuffer =
1093 i915_error_first_batchbuffer(dev_priv, ring);
1094
1095 error->ring[i].ringbuffer =
1096 i915_error_object_create(dev_priv, ring->obj);
1097
1098 count = 0;
1099 list_for_each_entry(request, &ring->request_list, list)
1100 count++;
1101
1102 error->ring[i].num_requests = count;
1103 error->ring[i].requests =
1104 kmalloc(count*sizeof(struct drm_i915_error_request),
1105 GFP_ATOMIC);
1106 if (error->ring[i].requests == NULL) {
1107 error->ring[i].num_requests = 0;
1108 continue;
1109 }
1110
1111 count = 0;
1112 list_for_each_entry(request, &ring->request_list, list) {
1113 struct drm_i915_error_request *erq;
1114
1115 erq = &error->ring[i].requests[count++];
1116 erq->seqno = request->seqno;
1117 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1118 erq->tail = request->tail;
52d39a21
CW		 1119 }
1120 }
1121}
1122
8a905236
JB		 1123/**
1124 * i915_capture_error_state - capture an error record for later analysis
1125 * @dev: drm device
1126 *
1127 * Should be called when an error is detected (either a hang or an error
1128 * interrupt) to capture error state from the time of the error. Fills
1129 * out a structure which becomes available in debugfs for user level tools
1130 * to pick up.
1131 */
63eeaf38
JB		 1132static void i915_capture_error_state(struct drm_device *dev)
1133{
1134 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1135 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1136 struct drm_i915_error_state *error;
1137 unsigned long flags;
9db4a9c7 1138 int i, pipe;
63eeaf38
JB		 1139
1140 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1141 error = dev_priv->first_error;
1142 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1143 if (error)
1144 return;
63eeaf38 1145
9db4a9c7 1146 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1147 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1148 if (!error) {
9df30794
CW		 1149 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1150 return;
63eeaf38
JB		 1151 }
1152
b6f7833b
CW		 1153 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1154 dev->primary->index);
2fa772f3 1155
742cbee8 1156 kref_init(&error->ref);
63eeaf38
JB		 1157 error->eir = I915_READ(EIR);
1158 error->pgtbl_er = I915_READ(PGTBL_ER);
be998e2e
BW		 1159
1160 if (HAS_PCH_SPLIT(dev))
1161 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1162 else if (IS_VALLEYVIEW(dev))
1163 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1164 else if (IS_GEN2(dev))
1165 error->ier = I915_READ16(IER);
1166 else
1167 error->ier = I915_READ(IER);
1168
9db4a9c7
JB		 1169 for_each_pipe(pipe)
1170 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1171
33f3f518 1172 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1173 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1174 error->done_reg = I915_READ(DONE_REG);
1175 }
d27b1e0e 1176
748ebc60 1177 i915_gem_record_fences(dev, error);
52d39a21 1178 i915_gem_record_rings(dev, error);
9df30794 1179
c724e8a9 1180 /* Record buffers on the active and pinned lists. */
9df30794 1181 error->active_bo = NULL;
c724e8a9 1182 error->pinned_bo = NULL;
9df30794 1183
bcfb2e28
CW		 1184 i = 0;
1185 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1186 i++;
1187 error->active_bo_count = i;
1b50247a
CW		 1188 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1189 if (obj->pin_count)
1190 i++;
bcfb2e28 1191 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1192
8e934dbf
CW		 1193 error->active_bo = NULL;
1194 error->pinned_bo = NULL;
bcfb2e28
CW		 1195 if (i) {
1196 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1197 GFP_ATOMIC);
c724e8a9
CW		 1198 if (error->active_bo)
1199 error->pinned_bo =
1200 error->active_bo + error->active_bo_count;
9df30794
CW		 1201 }
1202
c724e8a9
CW		 1203 if (error->active_bo)
1204 error->active_bo_count =
1b50247a
CW		 1205 capture_active_bo(error->active_bo,
1206 error->active_bo_count,
1207 &dev_priv->mm.active_list);
c724e8a9
CW		 1208
1209 if (error->pinned_bo)
1210 error->pinned_bo_count =
1b50247a
CW		 1211 capture_pinned_bo(error->pinned_bo,
1212 error->pinned_bo_count,
1213 &dev_priv->mm.gtt_list);
c724e8a9 1214
9df30794
CW		 1215 do_gettimeofday(&error->time);
1216
6ef3d427 1217 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1218 error->display = intel_display_capture_error_state(dev);
6ef3d427 1219
9df30794
CW		 1220 spin_lock_irqsave(&dev_priv->error_lock, flags);
1221 if (dev_priv->first_error == NULL) {
1222 dev_priv->first_error = error;
1223 error = NULL;
1224 }
63eeaf38 1225 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1226
1227 if (error)
742cbee8 1228 i915_error_state_free(&error->ref);
9df30794
CW		 1229}
1230
1231void i915_destroy_error_state(struct drm_device *dev)
1232{
1233 struct drm_i915_private *dev_priv = dev->dev_private;
1234 struct drm_i915_error_state *error;
6dc0e816 1235 unsigned long flags;
9df30794 1236
6dc0e816 1237 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1238 error = dev_priv->first_error;
1239 dev_priv->first_error = NULL;
6dc0e816 1240 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1241
1242 if (error)
742cbee8 1243 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1244}
3bd3c932
CW		 1245#else
1246#define i915_capture_error_state(x)
1247#endif
63eeaf38 1248
35aed2e6 1249static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1250{
1251 struct drm_i915_private *dev_priv = dev->dev_private;
1252 u32 eir = I915_READ(EIR);
9db4a9c7 1253 int pipe;
8a905236 1254
35aed2e6
CW		 1255 if (!eir)
1256 return;
8a905236 1257
a70491cc 1258 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1259
1260 if (IS_G4X(dev)) {
1261 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1262 u32 ipeir = I915_READ(IPEIR_I965);
1263
a70491cc
JP		 1264 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1265 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1266 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1267 I915_READ(INSTDONE_I965));
a70491cc
JP		 1268 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1269 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1270 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1271 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1272 POSTING_READ(IPEIR_I965);
8a905236
JB		 1273 }
1274 if (eir & GM45_ERROR_PAGE_TABLE) {
1275 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1276 pr_err("page table error\n");
1277 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1278 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1279 POSTING_READ(PGTBL_ER);
8a905236
JB		 1280 }
1281 }
1282
a6c45cf0 1283 if (!IS_GEN2(dev)) {
8a905236
JB		 1284 if (eir & I915_ERROR_PAGE_TABLE) {
1285 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1286 pr_err("page table error\n");
1287 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1288 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1289 POSTING_READ(PGTBL_ER);
8a905236
JB		 1290 }
1291 }
1292
1293 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1294 pr_err("memory refresh error:\n");
9db4a9c7 1295 for_each_pipe(pipe)
a70491cc 1296 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1297 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1298 /* pipestat has already been acked */
1299 }
1300 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1301 pr_err("instruction error\n");
1302 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1303 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1304 u32 ipeir = I915_READ(IPEIR);
1305
a70491cc
JP		 1306 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1307 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1308 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1309 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1310 I915_WRITE(IPEIR, ipeir);
3143a2bf 1311 POSTING_READ(IPEIR);
8a905236
JB		 1312 } else {
1313 u32 ipeir = I915_READ(IPEIR_I965);
1314
a70491cc
JP		 1315 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1316 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1317 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1318 I915_READ(INSTDONE_I965));
a70491cc
JP		 1319 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1320 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1321 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1322 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1323 POSTING_READ(IPEIR_I965);
8a905236
JB		 1324 }
1325 }
1326
1327 I915_WRITE(EIR, eir);
3143a2bf 1328 POSTING_READ(EIR);
8a905236
JB		 1329 eir = I915_READ(EIR);
1330 if (eir) {
1331 /*
1332 * some errors might have become stuck,
1333 * mask them.
1334 */
1335 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1336 I915_WRITE(EMR, I915_READ(EMR) | eir);
1337 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1338 }
35aed2e6
CW		 1339}
1340
1341/**
1342 * i915_handle_error - handle an error interrupt
1343 * @dev: drm device
1344 *
1345 * Do some basic checking of regsiter state at error interrupt time and
1346 * dump it to the syslog. Also call i915_capture_error_state() to make
1347 * sure we get a record and make it available in debugfs. Fire a uevent
1348 * so userspace knows something bad happened (should trigger collection
1349 * of a ring dump etc.).
1350 */
527f9e90 1351void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1352{
1353 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1354 struct intel_ring_buffer *ring;
1355 int i;
35aed2e6
CW		 1356
1357 i915_capture_error_state(dev);
1358 i915_report_and_clear_eir(dev);
8a905236 1359
ba1234d1 1360 if (wedged) {
30dbf0c0 1361 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1362 atomic_set(&dev_priv->mm.wedged, 1);
1363
11ed50ec
BG		 1364 /*
1365 * Wakeup waiting processes so they don't hang
1366 */
b4519513
CW		 1367 for_each_ring(ring, dev_priv, i)
1368 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1369 }
1370
9c9fe1f8 1371 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1372}
1373
4e5359cd
SF		 1374static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1375{
1376 drm_i915_private_t *dev_priv = dev->dev_private;
1377 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1379 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1380 struct intel_unpin_work *work;
1381 unsigned long flags;
1382 bool stall_detected;
1383
1384 /* Ignore early vblank irqs */
1385 if (intel_crtc == NULL)
1386 return;
1387
1388 spin_lock_irqsave(&dev->event_lock, flags);
1389 work = intel_crtc->unpin_work;
1390
1391 if (work == NULL || work->pending || !work->enable_stall_check) {
1392 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1393 spin_unlock_irqrestore(&dev->event_lock, flags);
1394 return;
1395 }
1396
1397 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1398 obj = work->pending_flip_obj;
a6c45cf0 1399 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1400 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1401 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1402 obj->gtt_offset;
4e5359cd 1403 } else {
9db4a9c7 1404 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1405 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1406 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1407 crtc->x * crtc->fb->bits_per_pixel/8);
1408 }
1409
1410 spin_unlock_irqrestore(&dev->event_lock, flags);
1411
1412 if (stall_detected) {
1413 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1414 intel_prepare_page_flip(dev, intel_crtc->plane);
1415 }
1416}
1417
42f52ef8
KP		 1418/* Called from drm generic code, passed 'crtc' which
1419 * we use as a pipe index
1420 */
f71d4af4 1421static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1422{
1423 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1424 unsigned long irqflags;
71e0ffa5 1425
5eddb70b 1426 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1427 return -EINVAL;
0a3e67a4 1428
1ec14ad3 1429 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1430 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1431 i915_enable_pipestat(dev_priv, pipe,
1432 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1433 else
7c463586
KP		 1434 i915_enable_pipestat(dev_priv, pipe,
1435 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1436
1437 /* maintain vblank delivery even in deep C-states */
1438 if (dev_priv->info->gen == 3)
6b26c86d 1439 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1440 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1441
0a3e67a4
JB		 1442 return 0;
1443}
1444
f71d4af4 1445static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1446{
1447 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1448 unsigned long irqflags;
1449
1450 if (!i915_pipe_enabled(dev, pipe))
1451 return -EINVAL;
1452
1453 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1454 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1455 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1456 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1457
1458 return 0;
1459}
1460
f71d4af4 1461static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1462{
1463 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1464 unsigned long irqflags;
1465
1466 if (!i915_pipe_enabled(dev, pipe))
1467 return -EINVAL;
1468
1469 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1470 ironlake_enable_display_irq(dev_priv,
1471 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1472 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1473
1474 return 0;
1475}
1476
7e231dbe
JB		 1477static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1478{
1479 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1480 unsigned long irqflags;
1481 u32 dpfl, imr;
1482
1483 if (!i915_pipe_enabled(dev, pipe))
1484 return -EINVAL;
1485
1486 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1487 dpfl = I915_READ(VLV_DPFLIPSTAT);
1488 imr = I915_READ(VLV_IMR);
1489 if (pipe == 0) {
1490 dpfl |= PIPEA_VBLANK_INT_EN;
1491 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1492 } else {
1493 dpfl |= PIPEA_VBLANK_INT_EN;
1494 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1495 }
1496 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1497 I915_WRITE(VLV_IMR, imr);
1498 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1499
1500 return 0;
1501}
1502
42f52ef8
KP		 1503/* Called from drm generic code, passed 'crtc' which
1504 * we use as a pipe index
1505 */
f71d4af4 1506static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1507{
1508 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1509 unsigned long irqflags;
0a3e67a4 1510
1ec14ad3 1511 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1512 if (dev_priv->info->gen == 3)
6b26c86d 1513 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1514
f796cf8f
JB		 1515 i915_disable_pipestat(dev_priv, pipe,
1516 PIPE_VBLANK_INTERRUPT_ENABLE |
1517 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1518 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1519}
1520
f71d4af4 1521static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1522{
1523 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1524 unsigned long irqflags;
1525
1526 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1527 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1528 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1529 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1530}
1531
f71d4af4 1532static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1533{
1534 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1535 unsigned long irqflags;
1536
1537 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1538 ironlake_disable_display_irq(dev_priv,
1539 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1541}
1542
7e231dbe
JB		 1543static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1544{
1545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1546 unsigned long irqflags;
1547 u32 dpfl, imr;
1548
1549 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1550 dpfl = I915_READ(VLV_DPFLIPSTAT);
1551 imr = I915_READ(VLV_IMR);
1552 if (pipe == 0) {
1553 dpfl &= ~PIPEA_VBLANK_INT_EN;
1554 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1555 } else {
1556 dpfl &= ~PIPEB_VBLANK_INT_EN;
1557 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1558 }
1559 I915_WRITE(VLV_IMR, imr);
1560 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1561 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1562}
1563
893eead0
CW		 1564static u32
1565ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1566{
893eead0
CW		 1567 return list_entry(ring->request_list.prev,
1568 struct drm_i915_gem_request, list)->seqno;
1569}
1570
1571static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1572{
1573 if (list_empty(&ring->request_list) ||
1574 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1575 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1576 if (waitqueue_active(&ring->irq_queue)) {
1577 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1578 ring->name);
893eead0
CW		 1579 wake_up_all(&ring->irq_queue);
1580 *err = true;
1581 }
1582 return true;
1583 }
1584 return false;
f65d9421
BG		 1585}
1586
1ec14ad3
CW		 1587static bool kick_ring(struct intel_ring_buffer *ring)
1588{
1589 struct drm_device *dev = ring->dev;
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591 u32 tmp = I915_READ_CTL(ring);
1592 if (tmp & RING_WAIT) {
1593 DRM_ERROR("Kicking stuck wait on %s\n",
1594 ring->name);
1595 I915_WRITE_CTL(ring, tmp);
1596 return true;
1597 }
1ec14ad3
CW		 1598 return false;
1599}
1600
d1e61e7f
CW		 1601static bool i915_hangcheck_hung(struct drm_device *dev)
1602{
1603 drm_i915_private_t *dev_priv = dev->dev_private;
1604
1605 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1606 bool hung = true;
1607
d1e61e7f
CW		 1608 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1609 i915_handle_error(dev, true);
1610
1611 if (!IS_GEN2(dev)) {
b4519513
CW		 1612 struct intel_ring_buffer *ring;
1613 int i;
1614
d1e61e7f
CW		 1615 /* Is the chip hanging on a WAIT_FOR_EVENT?
1616 * If so we can simply poke the RB_WAIT bit
1617 * and break the hang. This should work on
1618 * all but the second generation chipsets.
1619 */
b4519513
CW		 1620 for_each_ring(ring, dev_priv, i)
1621 hung &= !kick_ring(ring);
d1e61e7f
CW		 1622 }
1623
b4519513 1624 return hung;
d1e61e7f
CW		 1625 }
1626
1627 return false;
1628}
1629
f65d9421
BG		 1630/**
1631 * This is called when the chip hasn't reported back with completed
1632 * batchbuffers in a long time. The first time this is called we simply record
1633 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1634 * again, we assume the chip is wedged and try to fix it.
1635 */
1636void i915_hangcheck_elapsed(unsigned long data)
1637{
1638 struct drm_device *dev = (struct drm_device *)data;
1639 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513
CW		 1640 uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1641 struct intel_ring_buffer *ring;
1642 bool err = false, idle;
1643 int i;
893eead0 1644
3e0dc6b0
BW		 1645 if (!i915_enable_hangcheck)
1646 return;
1647
b4519513
CW		 1648 memset(acthd, 0, sizeof(acthd));
1649 idle = true;
1650 for_each_ring(ring, dev_priv, i) {
1651 idle &= i915_hangcheck_ring_idle(ring, &err);
1652 acthd[i] = intel_ring_get_active_head(ring);
1653 }
1654
893eead0 1655 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1656 if (idle) {
d1e61e7f
CW		 1657 if (err) {
1658 if (i915_hangcheck_hung(dev))
1659 return;
1660
893eead0 1661 goto repeat;
d1e61e7f
CW		 1662 }
1663
1664 dev_priv->hangcheck_count = 0;
893eead0
CW		 1665 return;
1666 }
b9201c14 1667
a6c45cf0 1668 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1669 instdone = I915_READ(INSTDONE);
1670 instdone1 = 0;
1671 } else {
cbb465e7
CW		 1672 instdone = I915_READ(INSTDONE_I965);
1673 instdone1 = I915_READ(INSTDONE1);
1674 }
b4519513
CW		 1675
1676 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
cbb465e7
CW		 1677 dev_priv->last_instdone == instdone &&
1678 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1679 if (i915_hangcheck_hung(dev))
cbb465e7 1680 return;
cbb465e7
CW		 1681 } else {
1682 dev_priv->hangcheck_count = 0;
1683
b4519513 1684 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
cbb465e7
CW		 1685 dev_priv->last_instdone = instdone;
1686 dev_priv->last_instdone1 = instdone1;
1687 }
f65d9421 1688
893eead0 1689repeat:
f65d9421 1690 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1691 mod_timer(&dev_priv->hangcheck_timer,
1692 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1693}
1694
1da177e4
LT		 1695/* drm_dma.h hooks
1696*/
f71d4af4 1697static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1698{
1699 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1700
4697995b
JB		 1701 atomic_set(&dev_priv->irq_received, 0);
1702
036a4a7d 1703 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1704
036a4a7d
ZW		 1705 /* XXX hotplug from PCH */
1706
1707 I915_WRITE(DEIMR, 0xffffffff);
1708 I915_WRITE(DEIER, 0x0);
3143a2bf 1709 POSTING_READ(DEIER);
036a4a7d
ZW		 1710
1711 /* and GT */
1712 I915_WRITE(GTIMR, 0xffffffff);
1713 I915_WRITE(GTIER, 0x0);
3143a2bf 1714 POSTING_READ(GTIER);
c650156a
ZW		 1715
1716 /* south display irq */
1717 I915_WRITE(SDEIMR, 0xffffffff);
1718 I915_WRITE(SDEIER, 0x0);
3143a2bf 1719 POSTING_READ(SDEIER);
036a4a7d
ZW		 1720}
1721
7e231dbe
JB		 1722static void valleyview_irq_preinstall(struct drm_device *dev)
1723{
1724 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1725 int pipe;
1726
1727 atomic_set(&dev_priv->irq_received, 0);
1728
7e231dbe
JB		 1729 /* VLV magic */
1730 I915_WRITE(VLV_IMR, 0);
1731 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1732 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1733 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1734
7e231dbe
JB		 1735 /* and GT */
1736 I915_WRITE(GTIIR, I915_READ(GTIIR));
1737 I915_WRITE(GTIIR, I915_READ(GTIIR));
1738 I915_WRITE(GTIMR, 0xffffffff);
1739 I915_WRITE(GTIER, 0x0);
1740 POSTING_READ(GTIER);
1741
1742 I915_WRITE(DPINVGTT, 0xff);
1743
1744 I915_WRITE(PORT_HOTPLUG_EN, 0);
1745 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1746 for_each_pipe(pipe)
1747 I915_WRITE(PIPESTAT(pipe), 0xffff);
1748 I915_WRITE(VLV_IIR, 0xffffffff);
1749 I915_WRITE(VLV_IMR, 0xffffffff);
1750 I915_WRITE(VLV_IER, 0x0);
1751 POSTING_READ(VLV_IER);
1752}
1753
7fe0b973
KP		 1754/*
1755 * Enable digital hotplug on the PCH, and configure the DP short pulse
1756 * duration to 2ms (which is the minimum in the Display Port spec)
1757 *
1758 * This register is the same on all known PCH chips.
1759 */
1760
1761static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1762{
1763 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1764 u32 hotplug;
1765
1766 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1767 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1768 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1769 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1770 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1771 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1772}
1773
f71d4af4 1774static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1775{
1776 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1777 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1778 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1779 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1780 u32 render_irqs;
2d7b8366 1781 u32 hotplug_mask;
036a4a7d 1782
1ec14ad3 1783 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1784
1785 /* should always can generate irq */
1786 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1787 I915_WRITE(DEIMR, dev_priv->irq_mask);
1788 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1789 POSTING_READ(DEIER);
036a4a7d 1790
1ec14ad3 1791 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1792
1793 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1794 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1795
1ec14ad3
CW		 1796 if (IS_GEN6(dev))
1797 render_irqs =
1798 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1799 GEN6_BSD_USER_INTERRUPT |
1800 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1801 else
1802 render_irqs =
88f23b8f 1803 GT_USER_INTERRUPT |
c6df541c 1804 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1805 GT_BSD_USER_INTERRUPT;
1806 I915_WRITE(GTIER, render_irqs);
3143a2bf 1807 POSTING_READ(GTIER);
036a4a7d 1808
2d7b8366 1809 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1810 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1811 SDE_PORTB_HOTPLUG_CPT |
1812 SDE_PORTC_HOTPLUG_CPT |
1813 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1814 } else {
9035a97a
CW		 1815 hotplug_mask = (SDE_CRT_HOTPLUG |
1816 SDE_PORTB_HOTPLUG |
1817 SDE_PORTC_HOTPLUG |
1818 SDE_PORTD_HOTPLUG |
1819 SDE_AUX_MASK);
2d7b8366
YL		 1820 }
1821
1ec14ad3 1822 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1823
1824 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1825 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1826 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1827 POSTING_READ(SDEIER);
c650156a 1828
7fe0b973
KP		 1829 ironlake_enable_pch_hotplug(dev);
1830
f97108d1
JB		 1831 if (IS_IRONLAKE_M(dev)) {
1832 /* Clear & enable PCU event interrupts */
1833 I915_WRITE(DEIIR, DE_PCU_EVENT);
1834 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1835 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1836 }
1837
036a4a7d
ZW		 1838 return 0;
1839}
1840
f71d4af4 1841static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1842{
1843 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1844 /* enable kind of interrupts always enabled */
b615b57a
CW		 1845 u32 display_mask =
1846 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1847 DE_PLANEC_FLIP_DONE_IVB |
1848 DE_PLANEB_FLIP_DONE_IVB |
1849 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1850 u32 render_irqs;
1851 u32 hotplug_mask;
1852
b1f14ad0
JB		 1853 dev_priv->irq_mask = ~display_mask;
1854
1855 /* should always can generate irq */
1856 I915_WRITE(DEIIR, I915_READ(DEIIR));
1857 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1858 I915_WRITE(DEIER,
1859 display_mask |
1860 DE_PIPEC_VBLANK_IVB |
1861 DE_PIPEB_VBLANK_IVB |
1862 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1863 POSTING_READ(DEIER);
1864
15b9f80e 1865 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1866
1867 I915_WRITE(GTIIR, I915_READ(GTIIR));
1868 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1869
e2a1e2f0 1870 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 1871 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1872 I915_WRITE(GTIER, render_irqs);
1873 POSTING_READ(GTIER);
1874
1875 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1876 SDE_PORTB_HOTPLUG_CPT |
1877 SDE_PORTC_HOTPLUG_CPT |
1878 SDE_PORTD_HOTPLUG_CPT);
1879 dev_priv->pch_irq_mask = ~hotplug_mask;
1880
1881 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1882 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1883 I915_WRITE(SDEIER, hotplug_mask);
1884 POSTING_READ(SDEIER);
1885
7fe0b973
KP		 1886 ironlake_enable_pch_hotplug(dev);
1887
b1f14ad0
JB		 1888 return 0;
1889}
1890
7e231dbe
JB		 1891static int valleyview_irq_postinstall(struct drm_device *dev)
1892{
1893 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1894 u32 render_irqs;
1895 u32 enable_mask;
1896 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1897 u16 msid;
1898
1899 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1900 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1901 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1902
1903 dev_priv->irq_mask = ~enable_mask;
1904
7e231dbe
JB		 1905 dev_priv->pipestat[0] = 0;
1906 dev_priv->pipestat[1] = 0;
1907
7e231dbe
JB		 1908 /* Hack for broken MSIs on VLV */
1909 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1910 pci_read_config_word(dev->pdev, 0x98, &msid);
1911 msid &= 0xff; /* mask out delivery bits */
1912 msid |= (1<<14);
1913 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1914
1915 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1916 I915_WRITE(VLV_IER, enable_mask);
1917 I915_WRITE(VLV_IIR, 0xffffffff);
1918 I915_WRITE(PIPESTAT(0), 0xffff);
1919 I915_WRITE(PIPESTAT(1), 0xffff);
1920 POSTING_READ(VLV_IER);
1921
1922 I915_WRITE(VLV_IIR, 0xffffffff);
1923 I915_WRITE(VLV_IIR, 0xffffffff);
1924
1925 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1926 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
e2a1e2f0 1927 GT_GEN6_BLT_USER_INTERRUPT |
7e231dbe
JB		 1928 GT_GEN6_BSD_USER_INTERRUPT |
1929 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1930 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1931 GT_PIPE_NOTIFY |
1932 GT_RENDER_CS_ERROR_INTERRUPT |
1933 GT_SYNC_STATUS |
1934 GT_USER_INTERRUPT;
1935
1936 dev_priv->gt_irq_mask = ~render_irqs;
1937
1938 I915_WRITE(GTIIR, I915_READ(GTIIR));
1939 I915_WRITE(GTIIR, I915_READ(GTIIR));
1940 I915_WRITE(GTIMR, 0);
1941 I915_WRITE(GTIER, render_irqs);
1942 POSTING_READ(GTIER);
1943
1944 /* ack & enable invalid PTE error interrupts */
1945#if 0 /* FIXME: add support to irq handler for checking these bits */
1946 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1947 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1948#endif
1949
1950 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1951#if 0 /* FIXME: check register definitions; some have moved */
1952 /* Note HDMI and DP share bits */
1953 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1954 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1955 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1956 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1957 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1958 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1959 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1960 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1961 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1962 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1963 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1964 hotplug_en |= CRT_HOTPLUG_INT_EN;
1965 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1966 }
1967#endif
1968
1969 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1970
1971 return 0;
1972}
1973
7e231dbe
JB		 1974static void valleyview_irq_uninstall(struct drm_device *dev)
1975{
1976 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1977 int pipe;
1978
1979 if (!dev_priv)
1980 return;
1981
7e231dbe
JB		 1982 for_each_pipe(pipe)
1983 I915_WRITE(PIPESTAT(pipe), 0xffff);
1984
1985 I915_WRITE(HWSTAM, 0xffffffff);
1986 I915_WRITE(PORT_HOTPLUG_EN, 0);
1987 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1988 for_each_pipe(pipe)
1989 I915_WRITE(PIPESTAT(pipe), 0xffff);
1990 I915_WRITE(VLV_IIR, 0xffffffff);
1991 I915_WRITE(VLV_IMR, 0xffffffff);
1992 I915_WRITE(VLV_IER, 0x0);
1993 POSTING_READ(VLV_IER);
1994}
1995
f71d4af4 1996static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 1997{
1998 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 1999
2000 if (!dev_priv)
2001 return;
2002
036a4a7d
ZW		 2003 I915_WRITE(HWSTAM, 0xffffffff);
2004
2005 I915_WRITE(DEIMR, 0xffffffff);
2006 I915_WRITE(DEIER, 0x0);
2007 I915_WRITE(DEIIR, I915_READ(DEIIR));
2008
2009 I915_WRITE(GTIMR, 0xffffffff);
2010 I915_WRITE(GTIER, 0x0);
2011 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2012
2013 I915_WRITE(SDEIMR, 0xffffffff);
2014 I915_WRITE(SDEIER, 0x0);
2015 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2016}
2017
a266c7d5 2018static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2019{
2020 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2021 int pipe;
91e3738e 2022
a266c7d5 2023 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2024
9db4a9c7
JB		 2025 for_each_pipe(pipe)
2026 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2027 I915_WRITE16(IMR, 0xffff);
2028 I915_WRITE16(IER, 0x0);
2029 POSTING_READ16(IER);
c2798b19
CW		 2030}
2031
2032static int i8xx_irq_postinstall(struct drm_device *dev)
2033{
2034 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2035
c2798b19
CW		 2036 dev_priv->pipestat[0] = 0;
2037 dev_priv->pipestat[1] = 0;
2038
2039 I915_WRITE16(EMR,
2040 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2041
2042 /* Unmask the interrupts that we always want on. */
2043 dev_priv->irq_mask =
2044 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2045 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2046 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2047 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2048 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2049 I915_WRITE16(IMR, dev_priv->irq_mask);
2050
2051 I915_WRITE16(IER,
2052 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2053 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2054 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2055 I915_USER_INTERRUPT);
2056 POSTING_READ16(IER);
2057
2058 return 0;
2059}
2060
2061static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2062{
2063 struct drm_device *dev = (struct drm_device *) arg;
2064 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2065 u16 iir, new_iir;
2066 u32 pipe_stats[2];
2067 unsigned long irqflags;
2068 int irq_received;
2069 int pipe;
2070 u16 flip_mask =
2071 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2072 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2073
2074 atomic_inc(&dev_priv->irq_received);
2075
2076 iir = I915_READ16(IIR);
2077 if (iir == 0)
2078 return IRQ_NONE;
2079
2080 while (iir & ~flip_mask) {
2081 /* Can't rely on pipestat interrupt bit in iir as it might
2082 * have been cleared after the pipestat interrupt was received.
2083 * It doesn't set the bit in iir again, but it still produces
2084 * interrupts (for non-MSI).
2085 */
2086 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2087 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2088 i915_handle_error(dev, false);
2089
2090 for_each_pipe(pipe) {
2091 int reg = PIPESTAT(pipe);
2092 pipe_stats[pipe] = I915_READ(reg);
2093
2094 /*
2095 * Clear the PIPE*STAT regs before the IIR
2096 */
2097 if (pipe_stats[pipe] & 0x8000ffff) {
2098 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2099 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2100 pipe_name(pipe));
2101 I915_WRITE(reg, pipe_stats[pipe]);
2102 irq_received = 1;
2103 }
2104 }
2105 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2106
2107 I915_WRITE16(IIR, iir & ~flip_mask);
2108 new_iir = I915_READ16(IIR); /* Flush posted writes */
2109
d05c617e 2110 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2111
2112 if (iir & I915_USER_INTERRUPT)
2113 notify_ring(dev, &dev_priv->ring[RCS]);
2114
2115 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2116 drm_handle_vblank(dev, 0)) {
2117 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2118 intel_prepare_page_flip(dev, 0);
2119 intel_finish_page_flip(dev, 0);
2120 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2121 }
2122 }
2123
2124 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2125 drm_handle_vblank(dev, 1)) {
2126 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2127 intel_prepare_page_flip(dev, 1);
2128 intel_finish_page_flip(dev, 1);
2129 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2130 }
2131 }
2132
2133 iir = new_iir;
2134 }
2135
2136 return IRQ_HANDLED;
2137}
2138
2139static void i8xx_irq_uninstall(struct drm_device * dev)
2140{
2141 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2142 int pipe;
2143
c2798b19
CW		 2144 for_each_pipe(pipe) {
2145 /* Clear enable bits; then clear status bits */
2146 I915_WRITE(PIPESTAT(pipe), 0);
2147 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2148 }
2149 I915_WRITE16(IMR, 0xffff);
2150 I915_WRITE16(IER, 0x0);
2151 I915_WRITE16(IIR, I915_READ16(IIR));
2152}
2153
a266c7d5
CW		 2154static void i915_irq_preinstall(struct drm_device * dev)
2155{
2156 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2157 int pipe;
2158
2159 atomic_set(&dev_priv->irq_received, 0);
2160
2161 if (I915_HAS_HOTPLUG(dev)) {
2162 I915_WRITE(PORT_HOTPLUG_EN, 0);
2163 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2164 }
2165
00d98ebd 2166 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2167 for_each_pipe(pipe)
2168 I915_WRITE(PIPESTAT(pipe), 0);
2169 I915_WRITE(IMR, 0xffffffff);
2170 I915_WRITE(IER, 0x0);
2171 POSTING_READ(IER);
2172}
2173
2174static int i915_irq_postinstall(struct drm_device *dev)
2175{
2176 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2177 u32 enable_mask;
a266c7d5 2178
a266c7d5
CW		 2179 dev_priv->pipestat[0] = 0;
2180 dev_priv->pipestat[1] = 0;
2181
38bde180
CW		 2182 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2183
2184 /* Unmask the interrupts that we always want on. */
2185 dev_priv->irq_mask =
2186 ~(I915_ASLE_INTERRUPT |
2187 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2188 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2189 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2190 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2191 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2192
2193 enable_mask =
2194 I915_ASLE_INTERRUPT |
2195 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2196 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2197 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2198 I915_USER_INTERRUPT;
2199
a266c7d5
CW		 2200 if (I915_HAS_HOTPLUG(dev)) {
2201 /* Enable in IER... */
2202 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2203 /* and unmask in IMR */
2204 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2205 }
2206
a266c7d5
CW		 2207 I915_WRITE(IMR, dev_priv->irq_mask);
2208 I915_WRITE(IER, enable_mask);
2209 POSTING_READ(IER);
2210
2211 if (I915_HAS_HOTPLUG(dev)) {
2212 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2213
a266c7d5
CW		 2214 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2215 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2216 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2217 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2218 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2219 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2220 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2221 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2222 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2223 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2224 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2225 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2226 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2227 }
2228
2229 /* Ignore TV since it's buggy */
2230
2231 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2232 }
2233
2234 intel_opregion_enable_asle(dev);
2235
2236 return 0;
2237}
2238
2239static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2240{
2241 struct drm_device *dev = (struct drm_device *) arg;
2242 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2243 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2244 unsigned long irqflags;
38bde180
CW		 2245 u32 flip_mask =
2246 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2247 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2248 u32 flip[2] = {
2249 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2250 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2251 };
2252 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2253
2254 atomic_inc(&dev_priv->irq_received);
2255
2256 iir = I915_READ(IIR);
38bde180
CW		 2257 do {
2258 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2259 bool blc_event = false;
a266c7d5
CW		 2260
2261 /* Can't rely on pipestat interrupt bit in iir as it might
2262 * have been cleared after the pipestat interrupt was received.
2263 * It doesn't set the bit in iir again, but it still produces
2264 * interrupts (for non-MSI).
2265 */
2266 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2267 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2268 i915_handle_error(dev, false);
2269
2270 for_each_pipe(pipe) {
2271 int reg = PIPESTAT(pipe);
2272 pipe_stats[pipe] = I915_READ(reg);
2273
38bde180 2274 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2275 if (pipe_stats[pipe] & 0x8000ffff) {
2276 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2277 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2278 pipe_name(pipe));
2279 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2280 irq_received = true;
a266c7d5
CW		 2281 }
2282 }
2283 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2284
2285 if (!irq_received)
2286 break;
2287
a266c7d5
CW		 2288 /* Consume port. Then clear IIR or we'll miss events */
2289 if ((I915_HAS_HOTPLUG(dev)) &&
2290 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2291 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2292
2293 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2294 hotplug_status);
2295 if (hotplug_status & dev_priv->hotplug_supported_mask)
2296 queue_work(dev_priv->wq,
2297 &dev_priv->hotplug_work);
2298
2299 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2300 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2301 }
2302
38bde180 2303 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2304 new_iir = I915_READ(IIR); /* Flush posted writes */
2305
a266c7d5
CW		 2306 if (iir & I915_USER_INTERRUPT)
2307 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2308
a266c7d5 2309 for_each_pipe(pipe) {
38bde180
CW		 2310 int plane = pipe;
2311 if (IS_MOBILE(dev))
2312 plane = !plane;
8291ee90 2313 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2314 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2315 if (iir & flip[plane]) {
2316 intel_prepare_page_flip(dev, plane);
2317 intel_finish_page_flip(dev, pipe);
2318 flip_mask &= ~flip[plane];
2319 }
a266c7d5
CW		 2320 }
2321
2322 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2323 blc_event = true;
2324 }
2325
a266c7d5
CW		 2326 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2327 intel_opregion_asle_intr(dev);
2328
2329 /* With MSI, interrupts are only generated when iir
2330 * transitions from zero to nonzero. If another bit got
2331 * set while we were handling the existing iir bits, then
2332 * we would never get another interrupt.
2333 *
2334 * This is fine on non-MSI as well, as if we hit this path
2335 * we avoid exiting the interrupt handler only to generate
2336 * another one.
2337 *
2338 * Note that for MSI this could cause a stray interrupt report
2339 * if an interrupt landed in the time between writing IIR and
2340 * the posting read. This should be rare enough to never
2341 * trigger the 99% of 100,000 interrupts test for disabling
2342 * stray interrupts.
2343 */
38bde180 2344 ret = IRQ_HANDLED;
a266c7d5 2345 iir = new_iir;
38bde180 2346 } while (iir & ~flip_mask);
a266c7d5 2347
d05c617e 2348 i915_update_dri1_breadcrumb(dev);
8291ee90 2349
a266c7d5
CW		 2350 return ret;
2351}
2352
2353static void i915_irq_uninstall(struct drm_device * dev)
2354{
2355 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2356 int pipe;
2357
a266c7d5
CW		 2358 if (I915_HAS_HOTPLUG(dev)) {
2359 I915_WRITE(PORT_HOTPLUG_EN, 0);
2360 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2361 }
2362
00d98ebd 2363 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2364 for_each_pipe(pipe) {
2365 /* Clear enable bits; then clear status bits */
a266c7d5 2366 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2367 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2368 }
a266c7d5
CW		 2369 I915_WRITE(IMR, 0xffffffff);
2370 I915_WRITE(IER, 0x0);
2371
a266c7d5
CW		 2372 I915_WRITE(IIR, I915_READ(IIR));
2373}
2374
2375static void i965_irq_preinstall(struct drm_device * dev)
2376{
2377 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2378 int pipe;
2379
2380 atomic_set(&dev_priv->irq_received, 0);
2381
adca4730
CW		 2382 I915_WRITE(PORT_HOTPLUG_EN, 0);
2383 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2384
2385 I915_WRITE(HWSTAM, 0xeffe);
2386 for_each_pipe(pipe)
2387 I915_WRITE(PIPESTAT(pipe), 0);
2388 I915_WRITE(IMR, 0xffffffff);
2389 I915_WRITE(IER, 0x0);
2390 POSTING_READ(IER);
2391}
2392
2393static int i965_irq_postinstall(struct drm_device *dev)
2394{
2395 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2396 u32 hotplug_en;
bbba0a97 2397 u32 enable_mask;
a266c7d5
CW		 2398 u32 error_mask;
2399
a266c7d5 2400 /* Unmask the interrupts that we always want on. */
bbba0a97 2401 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2402 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2403 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2404 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2405 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2406 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2407 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2408
2409 enable_mask = ~dev_priv->irq_mask;
2410 enable_mask |= I915_USER_INTERRUPT;
2411
2412 if (IS_G4X(dev))
2413 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2414
2415 dev_priv->pipestat[0] = 0;
2416 dev_priv->pipestat[1] = 0;
2417
a266c7d5
CW		 2418 /*
2419 * Enable some error detection, note the instruction error mask
2420 * bit is reserved, so we leave it masked.
2421 */
2422 if (IS_G4X(dev)) {
2423 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2424 GM45_ERROR_MEM_PRIV |
2425 GM45_ERROR_CP_PRIV |
2426 I915_ERROR_MEMORY_REFRESH);
2427 } else {
2428 error_mask = ~(I915_ERROR_PAGE_TABLE |
2429 I915_ERROR_MEMORY_REFRESH);
2430 }
2431 I915_WRITE(EMR, error_mask);
2432
2433 I915_WRITE(IMR, dev_priv->irq_mask);
2434 I915_WRITE(IER, enable_mask);
2435 POSTING_READ(IER);
2436
adca4730
CW		 2437 /* Note HDMI and DP share hotplug bits */
2438 hotplug_en = 0;
2439 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2440 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2441 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2442 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2443 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2444 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2445 if (IS_G4X(dev)) {
2446 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2447 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2448 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2449 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2450 } else {
2451 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2452 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2453 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2454 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2455 }
adca4730
CW		 2456 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2457 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2458
adca4730
CW		 2459 /* Programming the CRT detection parameters tends
2460 to generate a spurious hotplug event about three
2461 seconds later. So just do it once.
2462 */
2463 if (IS_G4X(dev))
2464 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2465 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2466 }
a266c7d5 2467
adca4730 2468 /* Ignore TV since it's buggy */
a266c7d5 2469
adca4730 2470 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2471
2472 intel_opregion_enable_asle(dev);
2473
2474 return 0;
2475}
2476
2477static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2478{
2479 struct drm_device *dev = (struct drm_device *) arg;
2480 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2481 u32 iir, new_iir;
2482 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2483 unsigned long irqflags;
2484 int irq_received;
2485 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2486
2487 atomic_inc(&dev_priv->irq_received);
2488
2489 iir = I915_READ(IIR);
2490
a266c7d5 2491 for (;;) {
2c8ba29f
CW		 2492 bool blc_event = false;
2493
a266c7d5
CW		 2494 irq_received = iir != 0;
2495
2496 /* Can't rely on pipestat interrupt bit in iir as it might
2497 * have been cleared after the pipestat interrupt was received.
2498 * It doesn't set the bit in iir again, but it still produces
2499 * interrupts (for non-MSI).
2500 */
2501 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2502 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2503 i915_handle_error(dev, false);
2504
2505 for_each_pipe(pipe) {
2506 int reg = PIPESTAT(pipe);
2507 pipe_stats[pipe] = I915_READ(reg);
2508
2509 /*
2510 * Clear the PIPE*STAT regs before the IIR
2511 */
2512 if (pipe_stats[pipe] & 0x8000ffff) {
2513 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2514 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2515 pipe_name(pipe));
2516 I915_WRITE(reg, pipe_stats[pipe]);
2517 irq_received = 1;
2518 }
2519 }
2520 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2521
2522 if (!irq_received)
2523 break;
2524
2525 ret = IRQ_HANDLED;
2526
2527 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2528 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2529 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2530
2531 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2532 hotplug_status);
2533 if (hotplug_status & dev_priv->hotplug_supported_mask)
2534 queue_work(dev_priv->wq,
2535 &dev_priv->hotplug_work);
2536
2537 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2538 I915_READ(PORT_HOTPLUG_STAT);
2539 }
2540
2541 I915_WRITE(IIR, iir);
2542 new_iir = I915_READ(IIR); /* Flush posted writes */
2543
a266c7d5
CW		 2544 if (iir & I915_USER_INTERRUPT)
2545 notify_ring(dev, &dev_priv->ring[RCS]);
2546 if (iir & I915_BSD_USER_INTERRUPT)
2547 notify_ring(dev, &dev_priv->ring[VCS]);
2548
4f7d1e79 2549 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2550 intel_prepare_page_flip(dev, 0);
a266c7d5 2551
4f7d1e79 2552 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2553 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2554
2555 for_each_pipe(pipe) {
2c8ba29f 2556 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2557 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2558 i915_pageflip_stall_check(dev, pipe);
2559 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2560 }
2561
2562 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2563 blc_event = true;
2564 }
2565
2566
2567 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2568 intel_opregion_asle_intr(dev);
2569
2570 /* With MSI, interrupts are only generated when iir
2571 * transitions from zero to nonzero. If another bit got
2572 * set while we were handling the existing iir bits, then
2573 * we would never get another interrupt.
2574 *
2575 * This is fine on non-MSI as well, as if we hit this path
2576 * we avoid exiting the interrupt handler only to generate
2577 * another one.
2578 *
2579 * Note that for MSI this could cause a stray interrupt report
2580 * if an interrupt landed in the time between writing IIR and
2581 * the posting read. This should be rare enough to never
2582 * trigger the 99% of 100,000 interrupts test for disabling
2583 * stray interrupts.
2584 */
2585 iir = new_iir;
2586 }
2587
d05c617e 2588 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2589
a266c7d5
CW		 2590 return ret;
2591}
2592
2593static void i965_irq_uninstall(struct drm_device * dev)
2594{
2595 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2596 int pipe;
2597
2598 if (!dev_priv)
2599 return;
2600
adca4730
CW		 2601 I915_WRITE(PORT_HOTPLUG_EN, 0);
2602 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2603
2604 I915_WRITE(HWSTAM, 0xffffffff);
2605 for_each_pipe(pipe)
2606 I915_WRITE(PIPESTAT(pipe), 0);
2607 I915_WRITE(IMR, 0xffffffff);
2608 I915_WRITE(IER, 0x0);
2609
2610 for_each_pipe(pipe)
2611 I915_WRITE(PIPESTAT(pipe),
2612 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2613 I915_WRITE(IIR, I915_READ(IIR));
2614}
2615
f71d4af4
JB		 2616void intel_irq_init(struct drm_device *dev)
2617{
8b2e326d
CW		 2618 struct drm_i915_private *dev_priv = dev->dev_private;
2619
2620 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2621 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2622 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
98fd81cd 2623 INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
8b2e326d 2624
f71d4af4
JB		 2625 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2626 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2627 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2628 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2629 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2630 }
2631
c3613de9
KP		 2632 if (drm_core_check_feature(dev, DRIVER_MODESET))
2633 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2634 else
2635 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2636 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2637
7e231dbe
JB		 2638 if (IS_VALLEYVIEW(dev)) {
2639 dev->driver->irq_handler = valleyview_irq_handler;
2640 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2641 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2642 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2643 dev->driver->enable_vblank = valleyview_enable_vblank;
2644 dev->driver->disable_vblank = valleyview_disable_vblank;
2645 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2646 /* Share pre & uninstall handlers with ILK/SNB */
2647 dev->driver->irq_handler = ivybridge_irq_handler;
2648 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2649 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2650 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2651 dev->driver->enable_vblank = ivybridge_enable_vblank;
2652 dev->driver->disable_vblank = ivybridge_disable_vblank;
7d4e146f
ED		 2653 } else if (IS_HASWELL(dev)) {
2654 /* Share interrupts handling with IVB */
2655 dev->driver->irq_handler = ivybridge_irq_handler;
2656 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2657 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2658 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2659 dev->driver->enable_vblank = ivybridge_enable_vblank;
2660 dev->driver->disable_vblank = ivybridge_disable_vblank;
f71d4af4
JB		 2661 } else if (HAS_PCH_SPLIT(dev)) {
2662 dev->driver->irq_handler = ironlake_irq_handler;
2663 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2664 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2665 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2666 dev->driver->enable_vblank = ironlake_enable_vblank;
2667 dev->driver->disable_vblank = ironlake_disable_vblank;
2668 } else {
c2798b19
CW		 2669 if (INTEL_INFO(dev)->gen == 2) {
2670 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2671 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2672 dev->driver->irq_handler = i8xx_irq_handler;
2673 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2674 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2675 /* IIR "flip pending" means done if this bit is set */
2676 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2677
a266c7d5
CW		 2678 dev->driver->irq_preinstall = i915_irq_preinstall;
2679 dev->driver->irq_postinstall = i915_irq_postinstall;
2680 dev->driver->irq_uninstall = i915_irq_uninstall;
2681 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2682 } else {
a266c7d5
CW		 2683 dev->driver->irq_preinstall = i965_irq_preinstall;
2684 dev->driver->irq_postinstall = i965_irq_postinstall;
2685 dev->driver->irq_uninstall = i965_irq_uninstall;
2686 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2687 }
f71d4af4
JB		 2688 dev->driver->enable_vblank = i915_enable_vblank;
2689 dev->driver->disable_vblank = i915_disable_vblank;
2690 }
2691}
Linux kernel - Deliverables
This page took 1.164969 seconds and 5 git commands to generate.