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drm/i915/bdw: Handle context switch events
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
b2c88f5b 33#include <linux/circ_buf.h>
760285e7
DH		 34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
1da177e4 36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
e5868a31
EE		 40static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46};
47
48static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54};
55
56static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63};
64
704cfb87 65static const u32 hpd_status_g4x[] = {
e5868a31
EE		 66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72};
73
e5868a31
EE		 74static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81};
82
5c502442 83/* IIR can theoretically queue up two events. Be paranoid. */
f86f3fb0 84#define GEN8_IRQ_RESET_NDX(type, which) do { \
5c502442
PZ		 85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
92} while (0)
93
f86f3fb0 94#define GEN5_IRQ_RESET(type) do { \
a9d356a6 95 I915_WRITE(type##IMR, 0xffffffff); \
5c502442 96 POSTING_READ(type##IMR); \
a9d356a6 97 I915_WRITE(type##IER, 0); \
5c502442
PZ		 98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
a9d356a6
PZ		 102} while (0)
103
337ba017
PZ		 104/*
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
106 */
107#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
109 if (val) { \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
111 (reg), val); \
112 I915_WRITE((reg), 0xffffffff); \
113 POSTING_READ(reg); \
114 I915_WRITE((reg), 0xffffffff); \
115 POSTING_READ(reg); \
116 } \
117} while (0)
118
35079899 119#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
337ba017 120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
35079899
PZ		 121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
124} while (0)
125
126#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
337ba017 127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
35079899
PZ		 128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
131} while (0)
132
036a4a7d 133/* For display hotplug interrupt */
995b6762 134static void
2d1013dd 135ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 136{
4bc9d430
DV		 137 assert_spin_locked(&dev_priv->irq_lock);
138
9df7575f 139 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 140 return;
c67a470b 141
1ec14ad3
CW		 142 if ((dev_priv->irq_mask & mask) != 0) {
143 dev_priv->irq_mask &= ~mask;
144 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 145 POSTING_READ(DEIMR);
036a4a7d
ZW		 146 }
147}
148
0ff9800a 149static void
2d1013dd 150ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 151{
4bc9d430
DV		 152 assert_spin_locked(&dev_priv->irq_lock);
153
06ffc778 154 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 155 return;
c67a470b 156
1ec14ad3
CW		 157 if ((dev_priv->irq_mask & mask) != mask) {
158 dev_priv->irq_mask |= mask;
159 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 160 POSTING_READ(DEIMR);
036a4a7d
ZW		 161 }
162}
163
43eaea13
PZ		 164/**
165 * ilk_update_gt_irq - update GTIMR
166 * @dev_priv: driver private
167 * @interrupt_mask: mask of interrupt bits to update
168 * @enabled_irq_mask: mask of interrupt bits to enable
169 */
170static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
171 uint32_t interrupt_mask,
172 uint32_t enabled_irq_mask)
173{
174 assert_spin_locked(&dev_priv->irq_lock);
175
9df7575f 176 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 177 return;
c67a470b 178
43eaea13
PZ		 179 dev_priv->gt_irq_mask &= ~interrupt_mask;
180 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
181 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
182 POSTING_READ(GTIMR);
183}
184
480c8033 185void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
43eaea13
PZ		 186{
187 ilk_update_gt_irq(dev_priv, mask, mask);
188}
189
480c8033 190void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
43eaea13
PZ		 191{
192 ilk_update_gt_irq(dev_priv, mask, 0);
193}
194
edbfdb45
PZ		 195/**
196 * snb_update_pm_irq - update GEN6_PMIMR
197 * @dev_priv: driver private
198 * @interrupt_mask: mask of interrupt bits to update
199 * @enabled_irq_mask: mask of interrupt bits to enable
200 */
201static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
202 uint32_t interrupt_mask,
203 uint32_t enabled_irq_mask)
204{
605cd25b 205 uint32_t new_val;
edbfdb45
PZ		 206
207 assert_spin_locked(&dev_priv->irq_lock);
208
9df7575f 209 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 210 return;
c67a470b 211
605cd25b 212 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 213 new_val &= ~interrupt_mask;
214 new_val |= (~enabled_irq_mask & interrupt_mask);
215
605cd25b
PZ		 216 if (new_val != dev_priv->pm_irq_mask) {
217 dev_priv->pm_irq_mask = new_val;
218 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
f52ecbcf
PZ		 219 POSTING_READ(GEN6_PMIMR);
220 }
edbfdb45
PZ		 221}
222
480c8033 223void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
edbfdb45
PZ		 224{
225 snb_update_pm_irq(dev_priv, mask, mask);
226}
227
480c8033 228void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
edbfdb45
PZ		 229{
230 snb_update_pm_irq(dev_priv, mask, 0);
231}
232
8664281b
PZ		 233static bool ivb_can_enable_err_int(struct drm_device *dev)
234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 struct intel_crtc *crtc;
237 enum pipe pipe;
238
4bc9d430
DV		 239 assert_spin_locked(&dev_priv->irq_lock);
240
8664281b
PZ		 241 for_each_pipe(pipe) {
242 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
243
244 if (crtc->cpu_fifo_underrun_disabled)
245 return false;
246 }
247
248 return true;
249}
250
0961021a
BW		 251/**
252 * bdw_update_pm_irq - update GT interrupt 2
253 * @dev_priv: driver private
254 * @interrupt_mask: mask of interrupt bits to update
255 * @enabled_irq_mask: mask of interrupt bits to enable
256 *
257 * Copied from the snb function, updated with relevant register offsets
258 */
259static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
260 uint32_t interrupt_mask,
261 uint32_t enabled_irq_mask)
262{
263 uint32_t new_val;
264
265 assert_spin_locked(&dev_priv->irq_lock);
266
9df7575f 267 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
0961021a
BW		 268 return;
269
270 new_val = dev_priv->pm_irq_mask;
271 new_val &= ~interrupt_mask;
272 new_val |= (~enabled_irq_mask & interrupt_mask);
273
274 if (new_val != dev_priv->pm_irq_mask) {
275 dev_priv->pm_irq_mask = new_val;
276 I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
277 POSTING_READ(GEN8_GT_IMR(2));
278 }
279}
280
480c8033 281void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
0961021a
BW		 282{
283 bdw_update_pm_irq(dev_priv, mask, mask);
284}
285
480c8033 286void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
0961021a
BW		 287{
288 bdw_update_pm_irq(dev_priv, mask, 0);
289}
290
8664281b
PZ		 291static bool cpt_can_enable_serr_int(struct drm_device *dev)
292{
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 enum pipe pipe;
295 struct intel_crtc *crtc;
296
fee884ed
DV		 297 assert_spin_locked(&dev_priv->irq_lock);
298
8664281b
PZ		 299 for_each_pipe(pipe) {
300 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
301
302 if (crtc->pch_fifo_underrun_disabled)
303 return false;
304 }
305
306 return true;
307}
308
56b80e1f
VS		 309void i9xx_check_fifo_underruns(struct drm_device *dev)
310{
311 struct drm_i915_private *dev_priv = dev->dev_private;
312 struct intel_crtc *crtc;
313 unsigned long flags;
314
315 spin_lock_irqsave(&dev_priv->irq_lock, flags);
316
317 for_each_intel_crtc(dev, crtc) {
318 u32 reg = PIPESTAT(crtc->pipe);
319 u32 pipestat;
320
321 if (crtc->cpu_fifo_underrun_disabled)
322 continue;
323
324 pipestat = I915_READ(reg) & 0xffff0000;
325 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
326 continue;
327
328 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
329 POSTING_READ(reg);
330
331 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
332 }
333
334 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
335}
336
e69abff0 337static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
2ae2a50c
DV		 338 enum pipe pipe,
339 bool enable, bool old)
2d9d2b0b
VS		 340{
341 struct drm_i915_private *dev_priv = dev->dev_private;
342 u32 reg = PIPESTAT(pipe);
e69abff0 343 u32 pipestat = I915_READ(reg) & 0xffff0000;
2d9d2b0b
VS		 344
345 assert_spin_locked(&dev_priv->irq_lock);
346
e69abff0
VS		 347 if (enable) {
348 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
349 POSTING_READ(reg);
350 } else {
2ae2a50c 351 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
e69abff0
VS		 352 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
353 }
2d9d2b0b
VS		 354}
355
8664281b
PZ		 356static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
357 enum pipe pipe, bool enable)
358{
359 struct drm_i915_private *dev_priv = dev->dev_private;
360 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
361 DE_PIPEB_FIFO_UNDERRUN;
362
363 if (enable)
364 ironlake_enable_display_irq(dev_priv, bit);
365 else
366 ironlake_disable_display_irq(dev_priv, bit);
367}
368
369static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
2ae2a50c
DV		 370 enum pipe pipe,
371 bool enable, bool old)
8664281b
PZ		 372{
373 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 374 if (enable) {
7336df65
DV		 375 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
376
8664281b
PZ		 377 if (!ivb_can_enable_err_int(dev))
378 return;
379
8664281b
PZ		 380 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
381 } else {
382 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65 383
2ae2a50c
DV		 384 if (old &&
385 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
823c6909
VS		 386 DRM_ERROR("uncleared fifo underrun on pipe %c\n",
387 pipe_name(pipe));
7336df65 388 }
8664281b
PZ		 389 }
390}
391
38d83c96
DV		 392static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
393 enum pipe pipe, bool enable)
394{
395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 assert_spin_locked(&dev_priv->irq_lock);
398
399 if (enable)
400 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
401 else
402 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
403 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
404 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
405}
406
fee884ed
DV		 407/**
408 * ibx_display_interrupt_update - update SDEIMR
409 * @dev_priv: driver private
410 * @interrupt_mask: mask of interrupt bits to update
411 * @enabled_irq_mask: mask of interrupt bits to enable
412 */
413static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
414 uint32_t interrupt_mask,
415 uint32_t enabled_irq_mask)
416{
417 uint32_t sdeimr = I915_READ(SDEIMR);
418 sdeimr &= ~interrupt_mask;
419 sdeimr |= (~enabled_irq_mask & interrupt_mask);
420
421 assert_spin_locked(&dev_priv->irq_lock);
422
9df7575f 423 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 424 return;
c67a470b 425
fee884ed
DV		 426 I915_WRITE(SDEIMR, sdeimr);
427 POSTING_READ(SDEIMR);
428}
429#define ibx_enable_display_interrupt(dev_priv, bits) \
430 ibx_display_interrupt_update((dev_priv), (bits), (bits))
431#define ibx_disable_display_interrupt(dev_priv, bits) \
432 ibx_display_interrupt_update((dev_priv), (bits), 0)
433
de28075d
DV		 434static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
435 enum transcoder pch_transcoder,
8664281b
PZ		 436 bool enable)
437{
8664281b 438 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 439 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
440 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 441
442 if (enable)
fee884ed 443 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 444 else
fee884ed 445 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 446}
447
448static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
449 enum transcoder pch_transcoder,
2ae2a50c 450 bool enable, bool old)
8664281b
PZ		 451{
452 struct drm_i915_private *dev_priv = dev->dev_private;
453
454 if (enable) {
1dd246fb
DV		 455 I915_WRITE(SERR_INT,
456 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
457
8664281b
PZ		 458 if (!cpt_can_enable_serr_int(dev))
459 return;
460
fee884ed 461 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 462 } else {
fee884ed 463 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb 464
2ae2a50c
DV		 465 if (old && I915_READ(SERR_INT) &
466 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
823c6909
VS		 467 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
468 transcoder_name(pch_transcoder));
1dd246fb 469 }
8664281b 470 }
8664281b
PZ		 471}
472
473/**
474 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
475 * @dev: drm device
476 * @pipe: pipe
477 * @enable: true if we want to report FIFO underrun errors, false otherwise
478 *
479 * This function makes us disable or enable CPU fifo underruns for a specific
480 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
481 * reporting for one pipe may also disable all the other CPU error interruts for
482 * the other pipes, due to the fact that there's just one interrupt mask/enable
483 * bit for all the pipes.
484 *
485 * Returns the previous state of underrun reporting.
486 */
c5ab3bc0
DV		 487static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
488 enum pipe pipe, bool enable)
8664281b
PZ		 489{
490 struct drm_i915_private *dev_priv = dev->dev_private;
491 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2ae2a50c 493 bool old;
8664281b 494
77961eb9
ID		 495 assert_spin_locked(&dev_priv->irq_lock);
496
2ae2a50c 497 old = !intel_crtc->cpu_fifo_underrun_disabled;
8664281b
PZ		 498 intel_crtc->cpu_fifo_underrun_disabled = !enable;
499
e69abff0 500 if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2ae2a50c 501 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
2d9d2b0b 502 else if (IS_GEN5(dev) || IS_GEN6(dev))
8664281b
PZ		 503 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
504 else if (IS_GEN7(dev))
2ae2a50c 505 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
38d83c96
DV		 506 else if (IS_GEN8(dev))
507 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b 508
2ae2a50c 509 return old;
f88d42f1
ID		 510}
511
512bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
513 enum pipe pipe, bool enable)
514{
515 struct drm_i915_private *dev_priv = dev->dev_private;
516 unsigned long flags;
517 bool ret;
518
519 spin_lock_irqsave(&dev_priv->irq_lock, flags);
520 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
8664281b 521 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
f88d42f1 522
8664281b
PZ		 523 return ret;
524}
525
91d181dd
ID		 526static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
527 enum pipe pipe)
528{
529 struct drm_i915_private *dev_priv = dev->dev_private;
530 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
532
533 return !intel_crtc->cpu_fifo_underrun_disabled;
534}
535
8664281b
PZ		 536/**
537 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
538 * @dev: drm device
539 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
540 * @enable: true if we want to report FIFO underrun errors, false otherwise
541 *
542 * This function makes us disable or enable PCH fifo underruns for a specific
543 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
544 * underrun reporting for one transcoder may also disable all the other PCH
545 * error interruts for the other transcoders, due to the fact that there's just
546 * one interrupt mask/enable bit for all the transcoders.
547 *
548 * Returns the previous state of underrun reporting.
549 */
550bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
551 enum transcoder pch_transcoder,
552 bool enable)
553{
554 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 555 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b 557 unsigned long flags;
2ae2a50c 558 bool old;
8664281b 559
de28075d
DV		 560 /*
561 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
562 * has only one pch transcoder A that all pipes can use. To avoid racy
563 * pch transcoder -> pipe lookups from interrupt code simply store the
564 * underrun statistics in crtc A. Since we never expose this anywhere
565 * nor use it outside of the fifo underrun code here using the "wrong"
566 * crtc on LPT won't cause issues.
567 */
8664281b
PZ		 568
569 spin_lock_irqsave(&dev_priv->irq_lock, flags);
570
2ae2a50c 571 old = !intel_crtc->pch_fifo_underrun_disabled;
8664281b
PZ		 572 intel_crtc->pch_fifo_underrun_disabled = !enable;
573
574 if (HAS_PCH_IBX(dev))
de28075d 575 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b 576 else
2ae2a50c 577 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);
8664281b 578
8664281b 579 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
2ae2a50c 580 return old;
8664281b
PZ		 581}
582
583
b5ea642a 584static void
755e9019
ID		 585__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
586 u32 enable_mask, u32 status_mask)
7c463586 587{
46c06a30 588 u32 reg = PIPESTAT(pipe);
755e9019 589 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 590
b79480ba
DV		 591 assert_spin_locked(&dev_priv->irq_lock);
592
04feced9
VS		 593 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
594 status_mask & ~PIPESTAT_INT_STATUS_MASK,
595 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
596 pipe_name(pipe), enable_mask, status_mask))
755e9019
ID		 597 return;
598
599 if ((pipestat & enable_mask) == enable_mask)
46c06a30
VS		 600 return;
601
91d181dd
ID		 602 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
603
46c06a30 604 /* Enable the interrupt, clear any pending status */
755e9019 605 pipestat |= enable_mask | status_mask;
46c06a30
VS		 606 I915_WRITE(reg, pipestat);
607 POSTING_READ(reg);
7c463586
KP		 608}
609
b5ea642a 610static void
755e9019
ID		 611__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
612 u32 enable_mask, u32 status_mask)
7c463586 613{
46c06a30 614 u32 reg = PIPESTAT(pipe);
755e9019 615 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 616
b79480ba
DV		 617 assert_spin_locked(&dev_priv->irq_lock);
618
04feced9
VS		 619 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
620 status_mask & ~PIPESTAT_INT_STATUS_MASK,
621 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
622 pipe_name(pipe), enable_mask, status_mask))
46c06a30
VS		 623 return;
624
755e9019
ID		 625 if ((pipestat & enable_mask) == 0)
626 return;
627
91d181dd
ID		 628 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
629
755e9019 630 pipestat &= ~enable_mask;
46c06a30
VS		 631 I915_WRITE(reg, pipestat);
632 POSTING_READ(reg);
7c463586
KP		 633}
634
10c59c51
ID		 635static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
636{
637 u32 enable_mask = status_mask << 16;
638
639 /*
724a6905
VS		 640 * On pipe A we don't support the PSR interrupt yet,
641 * on pipe B and C the same bit MBZ.
10c59c51
ID		 642 */
643 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
644 return 0;
724a6905
VS		 645 /*
646 * On pipe B and C we don't support the PSR interrupt yet, on pipe
647 * A the same bit is for perf counters which we don't use either.
648 */
649 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
650 return 0;
10c59c51
ID		 651
652 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
653 SPRITE0_FLIP_DONE_INT_EN_VLV |
654 SPRITE1_FLIP_DONE_INT_EN_VLV);
655 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
656 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
657 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
658 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
659
660 return enable_mask;
661}
662
755e9019
ID		 663void
664i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
665 u32 status_mask)
666{
667 u32 enable_mask;
668
10c59c51
ID		 669 if (IS_VALLEYVIEW(dev_priv->dev))
670 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
671 status_mask);
672 else
673 enable_mask = status_mask << 16;
755e9019
ID		 674 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
675}
676
677void
678i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
679 u32 status_mask)
680{
681 u32 enable_mask;
682
10c59c51
ID		 683 if (IS_VALLEYVIEW(dev_priv->dev))
684 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
685 status_mask);
686 else
687 enable_mask = status_mask << 16;
755e9019
ID		 688 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
689}
690
01c66889 691/**
f49e38dd 692 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 693 */
f49e38dd 694static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 695{
2d1013dd 696 struct drm_i915_private *dev_priv = dev->dev_private;
1ec14ad3
CW		 697 unsigned long irqflags;
698
f49e38dd
JN		 699 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
700 return;
701
1ec14ad3 702 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 703
755e9019 704 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
f898780b 705 if (INTEL_INFO(dev)->gen >= 4)
3b6c42e8 706 i915_enable_pipestat(dev_priv, PIPE_A,
755e9019 707 PIPE_LEGACY_BLC_EVENT_STATUS);
1ec14ad3
CW		 708
709 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 710}
711
0a3e67a4
JB		 712/**
713 * i915_pipe_enabled - check if a pipe is enabled
714 * @dev: DRM device
715 * @pipe: pipe to check
716 *
717 * Reading certain registers when the pipe is disabled can hang the chip.
718 * Use this routine to make sure the PLL is running and the pipe is active
719 * before reading such registers if unsure.
720 */
721static int
722i915_pipe_enabled(struct drm_device *dev, int pipe)
723{
2d1013dd 724 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56 725
a01025af
DV		 726 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
727 /* Locking is horribly broken here, but whatever. */
728 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 730
a01025af
DV		 731 return intel_crtc->active;
732 } else {
733 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
734 }
0a3e67a4
JB		 735}
736
f75f3746
VS		 737/*
738 * This timing diagram depicts the video signal in and
739 * around the vertical blanking period.
740 *
741 * Assumptions about the fictitious mode used in this example:
742 * vblank_start >= 3
743 * vsync_start = vblank_start + 1
744 * vsync_end = vblank_start + 2
745 * vtotal = vblank_start + 3
746 *
747 * start of vblank:
748 * latch double buffered registers
749 * increment frame counter (ctg+)
750 * generate start of vblank interrupt (gen4+)
751 * |
752 * | frame start:
753 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
754 * | may be shifted forward 1-3 extra lines via PIPECONF
755 * | |
756 * | | start of vsync:
757 * | | generate vsync interrupt
758 * | | |
759 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
760 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
761 * ----va---> <-----------------vb--------------------> <--------va-------------
762 * | | <----vs-----> |
763 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
764 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
765 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
766 * | | |
767 * last visible pixel first visible pixel
768 * | increment frame counter (gen3/4)
769 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
770 *
771 * x = horizontal active
772 * _ = horizontal blanking
773 * hs = horizontal sync
774 * va = vertical active
775 * vb = vertical blanking
776 * vs = vertical sync
777 * vbs = vblank_start (number)
778 *
779 * Summary:
780 * - most events happen at the start of horizontal sync
781 * - frame start happens at the start of horizontal blank, 1-4 lines
782 * (depending on PIPECONF settings) after the start of vblank
783 * - gen3/4 pixel and frame counter are synchronized with the start
784 * of horizontal active on the first line of vertical active
785 */
786
4cdb83ec
VS		 787static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
788{
789 /* Gen2 doesn't have a hardware frame counter */
790 return 0;
791}
792
42f52ef8
KP		 793/* Called from drm generic code, passed a 'crtc', which
794 * we use as a pipe index
795 */
f71d4af4 796static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4 797{
2d1013dd 798 struct drm_i915_private *dev_priv = dev->dev_private;
0a3e67a4
JB		 799 unsigned long high_frame;
800 unsigned long low_frame;
0b2a8e09 801 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
0a3e67a4
JB		 802
803 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 804 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 805 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 806 return 0;
807 }
808
391f75e2
VS		 809 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
810 struct intel_crtc *intel_crtc =
811 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
812 const struct drm_display_mode *mode =
813 &intel_crtc->config.adjusted_mode;
814
0b2a8e09
VS		 815 htotal = mode->crtc_htotal;
816 hsync_start = mode->crtc_hsync_start;
817 vbl_start = mode->crtc_vblank_start;
818 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
819 vbl_start = DIV_ROUND_UP(vbl_start, 2);
391f75e2 820 } else {
a2d213dd 821 enum transcoder cpu_transcoder = (enum transcoder) pipe;
391f75e2
VS		 822
823 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
0b2a8e09 824 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
391f75e2 825 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
0b2a8e09
VS		 826 if ((I915_READ(PIPECONF(cpu_transcoder)) &
827 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
828 vbl_start = DIV_ROUND_UP(vbl_start, 2);
391f75e2
VS		 829 }
830
0b2a8e09
VS		 831 /* Convert to pixel count */
832 vbl_start *= htotal;
833
834 /* Start of vblank event occurs at start of hsync */
835 vbl_start -= htotal - hsync_start;
836
9db4a9c7
JB		 837 high_frame = PIPEFRAME(pipe);
838 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 839
0a3e67a4
JB		 840 /*
841 * High & low register fields aren't synchronized, so make sure
842 * we get a low value that's stable across two reads of the high
843 * register.
844 */
845 do {
5eddb70b 846 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 847 low = I915_READ(low_frame);
5eddb70b 848 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 849 } while (high1 != high2);
850
5eddb70b 851 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 852 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 853 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 854
855 /*
856 * The frame counter increments at beginning of active.
857 * Cook up a vblank counter by also checking the pixel
858 * counter against vblank start.
859 */
edc08d0a 860 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
0a3e67a4
JB		 861}
862
f71d4af4 863static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5 864{
2d1013dd 865 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 866 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 867
868 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 869 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 870 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 871 return 0;
872 }
873
874 return I915_READ(reg);
875}
876
ad3543ed
MK		 877/* raw reads, only for fast reads of display block, no need for forcewake etc. */
878#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
ad3543ed 879
a225f079
VS		 880static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
881{
882 struct drm_device *dev = crtc->base.dev;
883 struct drm_i915_private *dev_priv = dev->dev_private;
884 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
885 enum pipe pipe = crtc->pipe;
80715b2f 886 int position, vtotal;
a225f079 887
80715b2f 888 vtotal = mode->crtc_vtotal;
a225f079
VS		 889 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
890 vtotal /= 2;
891
892 if (IS_GEN2(dev))
893 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
894 else
895 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
896
897 /*
80715b2f
VS		 898 * See update_scanline_offset() for the details on the
899 * scanline_offset adjustment.
a225f079 900 */
80715b2f 901 return (position + crtc->scanline_offset) % vtotal;
a225f079
VS		 902}
903
f71d4af4 904static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
abca9e45
VS		 905 unsigned int flags, int *vpos, int *hpos,
906 ktime_t *stime, ktime_t *etime)
0af7e4df 907{
c2baf4b7
VS		 908 struct drm_i915_private *dev_priv = dev->dev_private;
909 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
911 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
3aa18df8 912 int position;
78e8fc6b 913 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
0af7e4df
MK		 914 bool in_vbl = true;
915 int ret = 0;
ad3543ed 916 unsigned long irqflags;
0af7e4df 917
c2baf4b7 918 if (!intel_crtc->active) {
0af7e4df 919 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 920 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 921 return 0;
922 }
923
c2baf4b7 924 htotal = mode->crtc_htotal;
78e8fc6b 925 hsync_start = mode->crtc_hsync_start;
c2baf4b7
VS		 926 vtotal = mode->crtc_vtotal;
927 vbl_start = mode->crtc_vblank_start;
928 vbl_end = mode->crtc_vblank_end;
0af7e4df 929
d31faf65
VS		 930 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
931 vbl_start = DIV_ROUND_UP(vbl_start, 2);
932 vbl_end /= 2;
933 vtotal /= 2;
934 }
935
c2baf4b7
VS		 936 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
937
ad3543ed
MK		 938 /*
939 * Lock uncore.lock, as we will do multiple timing critical raw
940 * register reads, potentially with preemption disabled, so the
941 * following code must not block on uncore.lock.
942 */
943 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
78e8fc6b 944
ad3543ed
MK		 945 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
946
947 /* Get optional system timestamp before query. */
948 if (stime)
949 *stime = ktime_get();
950
7c06b08a 951 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 952 /* No obvious pixelcount register. Only query vertical
953 * scanout position from Display scan line register.
954 */
a225f079 955 position = __intel_get_crtc_scanline(intel_crtc);
0af7e4df
MK		 956 } else {
957 /* Have access to pixelcount since start of frame.
958 * We can split this into vertical and horizontal
959 * scanout position.
960 */
ad3543ed 961 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
0af7e4df 962
3aa18df8
VS		 963 /* convert to pixel counts */
964 vbl_start *= htotal;
965 vbl_end *= htotal;
966 vtotal *= htotal;
78e8fc6b 967
7e78f1cb
VS		 968 /*
969 * In interlaced modes, the pixel counter counts all pixels,
970 * so one field will have htotal more pixels. In order to avoid
971 * the reported position from jumping backwards when the pixel
972 * counter is beyond the length of the shorter field, just
973 * clamp the position the length of the shorter field. This
974 * matches how the scanline counter based position works since
975 * the scanline counter doesn't count the two half lines.
976 */
977 if (position >= vtotal)
978 position = vtotal - 1;
979
78e8fc6b
VS		 980 /*
981 * Start of vblank interrupt is triggered at start of hsync,
982 * just prior to the first active line of vblank. However we
983 * consider lines to start at the leading edge of horizontal
984 * active. So, should we get here before we've crossed into
985 * the horizontal active of the first line in vblank, we would
986 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
987 * always add htotal-hsync_start to the current pixel position.
988 */
989 position = (position + htotal - hsync_start) % vtotal;
0af7e4df
MK		 990 }
991
ad3543ed
MK		 992 /* Get optional system timestamp after query. */
993 if (etime)
994 *etime = ktime_get();
995
996 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
997
998 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
999
3aa18df8
VS		 1000 in_vbl = position >= vbl_start && position < vbl_end;
1001
1002 /*
1003 * While in vblank, position will be negative
1004 * counting up towards 0 at vbl_end. And outside
1005 * vblank, position will be positive counting
1006 * up since vbl_end.
1007 */
1008 if (position >= vbl_start)
1009 position -= vbl_end;
1010 else
1011 position += vtotal - vbl_end;
0af7e4df 1012
7c06b08a 1013 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3aa18df8
VS		 1014 *vpos = position;
1015 *hpos = 0;
1016 } else {
1017 *vpos = position / htotal;
1018 *hpos = position - (*vpos * htotal);
1019 }
0af7e4df 1020
0af7e4df
MK		 1021 /* In vblank? */
1022 if (in_vbl)
1023 ret |= DRM_SCANOUTPOS_INVBL;
1024
1025 return ret;
1026}
1027
a225f079
VS		 1028int intel_get_crtc_scanline(struct intel_crtc *crtc)
1029{
1030 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1031 unsigned long irqflags;
1032 int position;
1033
1034 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1035 position = __intel_get_crtc_scanline(crtc);
1036 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1037
1038 return position;
1039}
1040
f71d4af4 1041static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 1042 int *max_error,
1043 struct timeval *vblank_time,
1044 unsigned flags)
1045{
4041b853 1046 struct drm_crtc *crtc;
0af7e4df 1047
7eb552ae 1048 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 1049 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 1050 return -EINVAL;
1051 }
1052
1053 /* Get drm_crtc to timestamp: */
4041b853
CW		 1054 crtc = intel_get_crtc_for_pipe(dev, pipe);
1055 if (crtc == NULL) {
1056 DRM_ERROR("Invalid crtc %d\n", pipe);
1057 return -EINVAL;
1058 }
1059
1060 if (!crtc->enabled) {
1061 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1062 return -EBUSY;
1063 }
0af7e4df
MK		 1064
1065 /* Helper routine in DRM core does all the work: */
4041b853
CW		 1066 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
1067 vblank_time, flags,
7da903ef
VS		 1068 crtc,
1069 &to_intel_crtc(crtc)->config.adjusted_mode);
0af7e4df
MK		 1070}
1071
67c347ff
JN		 1072static bool intel_hpd_irq_event(struct drm_device *dev,
1073 struct drm_connector *connector)
321a1b30
EE		 1074{
1075 enum drm_connector_status old_status;
1076
1077 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1078 old_status = connector->status;
1079
1080 connector->status = connector->funcs->detect(connector, false);
67c347ff
JN		 1081 if (old_status == connector->status)
1082 return false;
1083
1084 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
321a1b30 1085 connector->base.id,
c23cc417 1086 connector->name,
67c347ff
JN		 1087 drm_get_connector_status_name(old_status),
1088 drm_get_connector_status_name(connector->status));
1089
1090 return true;
321a1b30
EE		 1091}
1092
13cf5504
DA		 1093static void i915_digport_work_func(struct work_struct *work)
1094{
1095 struct drm_i915_private *dev_priv =
1096 container_of(work, struct drm_i915_private, dig_port_work);
1097 unsigned long irqflags;
1098 u32 long_port_mask, short_port_mask;
1099 struct intel_digital_port *intel_dig_port;
1100 int i, ret;
1101 u32 old_bits = 0;
1102
1103 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1104 long_port_mask = dev_priv->long_hpd_port_mask;
1105 dev_priv->long_hpd_port_mask = 0;
1106 short_port_mask = dev_priv->short_hpd_port_mask;
1107 dev_priv->short_hpd_port_mask = 0;
1108 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1109
1110 for (i = 0; i < I915_MAX_PORTS; i++) {
1111 bool valid = false;
1112 bool long_hpd = false;
1113 intel_dig_port = dev_priv->hpd_irq_port[i];
1114 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
1115 continue;
1116
1117 if (long_port_mask & (1 << i)) {
1118 valid = true;
1119 long_hpd = true;
1120 } else if (short_port_mask & (1 << i))
1121 valid = true;
1122
1123 if (valid) {
1124 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
1125 if (ret == true) {
1126 /* if we get true fallback to old school hpd */
1127 old_bits |= (1 << intel_dig_port->base.hpd_pin);
1128 }
1129 }
1130 }
1131
1132 if (old_bits) {
1133 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1134 dev_priv->hpd_event_bits |= old_bits;
1135 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1136 schedule_work(&dev_priv->hotplug_work);
1137 }
1138}
1139
5ca58282
JB		 1140/*
1141 * Handle hotplug events outside the interrupt handler proper.
1142 */
ac4c16c5
EE		 1143#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
1144
5ca58282
JB		 1145static void i915_hotplug_work_func(struct work_struct *work)
1146{
2d1013dd
JN		 1147 struct drm_i915_private *dev_priv =
1148 container_of(work, struct drm_i915_private, hotplug_work);
5ca58282 1149 struct drm_device *dev = dev_priv->dev;
c31c4ba3 1150 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 1151 struct intel_connector *intel_connector;
1152 struct intel_encoder *intel_encoder;
1153 struct drm_connector *connector;
1154 unsigned long irqflags;
1155 bool hpd_disabled = false;
321a1b30 1156 bool changed = false;
142e2398 1157 u32 hpd_event_bits;
4ef69c7a 1158
a65e34c7 1159 mutex_lock(&mode_config->mutex);
e67189ab
JB		 1160 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1161
cd569aed 1162 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 1163
1164 hpd_event_bits = dev_priv->hpd_event_bits;
1165 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 1166 list_for_each_entry(connector, &mode_config->connector_list, head) {
1167 intel_connector = to_intel_connector(connector);
36cd7444
DA		 1168 if (!intel_connector->encoder)
1169 continue;
cd569aed
EE		 1170 intel_encoder = intel_connector->encoder;
1171 if (intel_encoder->hpd_pin > HPD_NONE &&
1172 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1173 connector->polled == DRM_CONNECTOR_POLL_HPD) {
1174 DRM_INFO("HPD interrupt storm detected on connector %s: "
1175 "switching from hotplug detection to polling\n",
c23cc417 1176 connector->name);
cd569aed
EE		 1177 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1178 connector->polled = DRM_CONNECTOR_POLL_CONNECT
1179 | DRM_CONNECTOR_POLL_DISCONNECT;
1180 hpd_disabled = true;
1181 }
142e2398
EE		 1182 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1183 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
c23cc417 1184 connector->name, intel_encoder->hpd_pin);
142e2398 1185 }
cd569aed
EE		 1186 }
1187 /* if there were no outputs to poll, poll was disabled,
1188 * therefore make sure it's enabled when disabling HPD on
1189 * some connectors */
ac4c16c5 1190 if (hpd_disabled) {
cd569aed 1191 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 1192 mod_timer(&dev_priv->hotplug_reenable_timer,
1193 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1194 }
cd569aed
EE		 1195
1196 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1197
321a1b30
EE		 1198 list_for_each_entry(connector, &mode_config->connector_list, head) {
1199 intel_connector = to_intel_connector(connector);
36cd7444
DA		 1200 if (!intel_connector->encoder)
1201 continue;
321a1b30
EE		 1202 intel_encoder = intel_connector->encoder;
1203 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1204 if (intel_encoder->hot_plug)
1205 intel_encoder->hot_plug(intel_encoder);
1206 if (intel_hpd_irq_event(dev, connector))
1207 changed = true;
1208 }
1209 }
40ee3381
KP		 1210 mutex_unlock(&mode_config->mutex);
1211
321a1b30
EE		 1212 if (changed)
1213 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 1214}
1215
3ca1cced
VS		 1216static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1217{
1218 del_timer_sync(&dev_priv->hotplug_reenable_timer);
1219}
1220
d0ecd7e2 1221static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1 1222{
2d1013dd 1223 struct drm_i915_private *dev_priv = dev->dev_private;
b5b72e89 1224 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 1225 u8 new_delay;
9270388e 1226
d0ecd7e2 1227 spin_lock(&mchdev_lock);
f97108d1 1228
73edd18f
DV		 1229 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1230
20e4d407 1231 new_delay = dev_priv->ips.cur_delay;
9270388e 1232
7648fa99 1233 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 1234 busy_up = I915_READ(RCPREVBSYTUPAVG);
1235 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 1236 max_avg = I915_READ(RCBMAXAVG);
1237 min_avg = I915_READ(RCBMINAVG);
1238
1239 /* Handle RCS change request from hw */
b5b72e89 1240 if (busy_up > max_avg) {
20e4d407
DV		 1241 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1242 new_delay = dev_priv->ips.cur_delay - 1;
1243 if (new_delay < dev_priv->ips.max_delay)
1244 new_delay = dev_priv->ips.max_delay;
b5b72e89 1245 } else if (busy_down < min_avg) {
20e4d407
DV		 1246 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1247 new_delay = dev_priv->ips.cur_delay + 1;
1248 if (new_delay > dev_priv->ips.min_delay)
1249 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 1250 }
1251
7648fa99 1252 if (ironlake_set_drps(dev, new_delay))
20e4d407 1253 dev_priv->ips.cur_delay = new_delay;
f97108d1 1254
d0ecd7e2 1255 spin_unlock(&mchdev_lock);
9270388e 1256
f97108d1
JB		 1257 return;
1258}
1259
549f7365 1260static void notify_ring(struct drm_device *dev,
a4872ba6 1261 struct intel_engine_cs *ring)
549f7365 1262{
93b0a4e0 1263 if (!intel_ring_initialized(ring))
475553de
CW		 1264 return;
1265
814e9b57 1266 trace_i915_gem_request_complete(ring);
9862e600 1267
84c33a64
SG		 1268 if (drm_core_check_feature(dev, DRIVER_MODESET))
1269 intel_notify_mmio_flip(ring);
1270
549f7365 1271 wake_up_all(&ring->irq_queue);
10cd45b6 1272 i915_queue_hangcheck(dev);
549f7365
CW		 1273}
1274
31685c25 1275static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
bf225f20 1276 struct intel_rps_ei *rps_ei)
31685c25
D		 1277{
1278 u32 cz_ts, cz_freq_khz;
1279 u32 render_count, media_count;
1280 u32 elapsed_render, elapsed_media, elapsed_time;
1281 u32 residency = 0;
1282
1283 cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1284 cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
1285
1286 render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1287 media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1288
bf225f20
CW		 1289 if (rps_ei->cz_clock == 0) {
1290 rps_ei->cz_clock = cz_ts;
1291 rps_ei->render_c0 = render_count;
1292 rps_ei->media_c0 = media_count;
31685c25
D		 1293
1294 return dev_priv->rps.cur_freq;
1295 }
1296
bf225f20
CW		 1297 elapsed_time = cz_ts - rps_ei->cz_clock;
1298 rps_ei->cz_clock = cz_ts;
31685c25 1299
bf225f20
CW		 1300 elapsed_render = render_count - rps_ei->render_c0;
1301 rps_ei->render_c0 = render_count;
31685c25 1302
bf225f20
CW		 1303 elapsed_media = media_count - rps_ei->media_c0;
1304 rps_ei->media_c0 = media_count;
31685c25
D		 1305
1306 /* Convert all the counters into common unit of milli sec */
1307 elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1308 elapsed_render /= cz_freq_khz;
1309 elapsed_media /= cz_freq_khz;
1310
1311 /*
1312 * Calculate overall C0 residency percentage
1313 * only if elapsed time is non zero
1314 */
1315 if (elapsed_time) {
1316 residency =
1317 ((max(elapsed_render, elapsed_media) * 100)
1318 / elapsed_time);
1319 }
1320
1321 return residency;
1322}
1323
1324/**
1325 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1326 * busy-ness calculated from C0 counters of render & media power wells
1327 * @dev_priv: DRM device private
1328 *
1329 */
4fa79042 1330static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
31685c25
D		 1331{
1332 u32 residency_C0_up = 0, residency_C0_down = 0;
4fa79042 1333 int new_delay, adj;
31685c25
D		 1334
1335 dev_priv->rps.ei_interrupt_count++;
1336
1337 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1338
1339
bf225f20
CW		 1340 if (dev_priv->rps.up_ei.cz_clock == 0) {
1341 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1342 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
31685c25
D		 1343 return dev_priv->rps.cur_freq;
1344 }
1345
1346
1347 /*
1348 * To down throttle, C0 residency should be less than down threshold
1349 * for continous EI intervals. So calculate down EI counters
1350 * once in VLV_INT_COUNT_FOR_DOWN_EI
1351 */
1352 if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1353
1354 dev_priv->rps.ei_interrupt_count = 0;
1355
1356 residency_C0_down = vlv_c0_residency(dev_priv,
bf225f20 1357 &dev_priv->rps.down_ei);
31685c25
D		 1358 } else {
1359 residency_C0_up = vlv_c0_residency(dev_priv,
bf225f20 1360 &dev_priv->rps.up_ei);
31685c25
D		 1361 }
1362
1363 new_delay = dev_priv->rps.cur_freq;
1364
1365 adj = dev_priv->rps.last_adj;
1366 /* C0 residency is greater than UP threshold. Increase Frequency */
1367 if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1368 if (adj > 0)
1369 adj *= 2;
1370 else
1371 adj = 1;
1372
1373 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1374 new_delay = dev_priv->rps.cur_freq + adj;
1375
1376 /*
1377 * For better performance, jump directly
1378 * to RPe if we're below it.
1379 */
1380 if (new_delay < dev_priv->rps.efficient_freq)
1381 new_delay = dev_priv->rps.efficient_freq;
1382
1383 } else if (!dev_priv->rps.ei_interrupt_count &&
1384 (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1385 if (adj < 0)
1386 adj *= 2;
1387 else
1388 adj = -1;
1389 /*
1390 * This means, C0 residency is less than down threshold over
1391 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1392 */
1393 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1394 new_delay = dev_priv->rps.cur_freq + adj;
1395 }
1396
1397 return new_delay;
1398}
1399
4912d041 1400static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 1401{
2d1013dd
JN		 1402 struct drm_i915_private *dev_priv =
1403 container_of(work, struct drm_i915_private, rps.work);
edbfdb45 1404 u32 pm_iir;
dd75fdc8 1405 int new_delay, adj;
4912d041 1406
59cdb63d 1407 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3
DV		 1408 pm_iir = dev_priv->rps.pm_iir;
1409 dev_priv->rps.pm_iir = 0;
6af257cd 1410 if (INTEL_INFO(dev_priv->dev)->gen >= 8)
480c8033 1411 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
0961021a
BW		 1412 else {
1413 /* Make sure not to corrupt PMIMR state used by ringbuffer */
480c8033 1414 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
0961021a 1415 }
59cdb63d 1416 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 1417
60611c13 1418 /* Make sure we didn't queue anything we're not going to process. */
a6706b45 1419 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
60611c13 1420
a6706b45 1421 if ((pm_iir & dev_priv->pm_rps_events) == 0)
3b8d8d91
JB		 1422 return;
1423
4fc688ce 1424 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 1425
dd75fdc8 1426 adj = dev_priv->rps.last_adj;
7425034a 1427 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 1428 if (adj > 0)
1429 adj *= 2;
13a5660c
D		 1430 else {
1431 /* CHV needs even encode values */
1432 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1433 }
b39fb297 1434 new_delay = dev_priv->rps.cur_freq + adj;
7425034a
VS		 1435
1436 /*
1437 * For better performance, jump directly
1438 * to RPe if we're below it.
1439 */
b39fb297
BW		 1440 if (new_delay < dev_priv->rps.efficient_freq)
1441 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 1442 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
b39fb297
BW		 1443 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1444 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 1445 else
b39fb297 1446 new_delay = dev_priv->rps.min_freq_softlimit;
dd75fdc8 1447 adj = 0;
31685c25
D		 1448 } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1449 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
dd75fdc8
CW		 1450 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1451 if (adj < 0)
1452 adj *= 2;
13a5660c
D		 1453 else {
1454 /* CHV needs even encode values */
1455 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1456 }
b39fb297 1457 new_delay = dev_priv->rps.cur_freq + adj;
dd75fdc8 1458 } else { /* unknown event */
b39fb297 1459 new_delay = dev_priv->rps.cur_freq;
dd75fdc8 1460 }
3b8d8d91 1461
79249636
BW		 1462 /* sysfs frequency interfaces may have snuck in while servicing the
1463 * interrupt
1464 */
1272e7b8 1465 new_delay = clamp_t(int, new_delay,
b39fb297
BW		 1466 dev_priv->rps.min_freq_softlimit,
1467 dev_priv->rps.max_freq_softlimit);
27544369 1468
b39fb297 1469 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
dd75fdc8
CW		 1470
1471 if (IS_VALLEYVIEW(dev_priv->dev))
1472 valleyview_set_rps(dev_priv->dev, new_delay);
1473 else
1474 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 1475
4fc688ce 1476 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 1477}
1478
e3689190
BW		 1479
1480/**
1481 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1482 * occurred.
1483 * @work: workqueue struct
1484 *
1485 * Doesn't actually do anything except notify userspace. As a consequence of
1486 * this event, userspace should try to remap the bad rows since statistically
1487 * it is likely the same row is more likely to go bad again.
1488 */
1489static void ivybridge_parity_work(struct work_struct *work)
1490{
2d1013dd
JN		 1491 struct drm_i915_private *dev_priv =
1492 container_of(work, struct drm_i915_private, l3_parity.error_work);
e3689190 1493 u32 error_status, row, bank, subbank;
35a85ac6 1494 char *parity_event[6];
e3689190
BW		 1495 uint32_t misccpctl;
1496 unsigned long flags;
35a85ac6 1497 uint8_t slice = 0;
e3689190
BW		 1498
1499 /* We must turn off DOP level clock gating to access the L3 registers.
1500 * In order to prevent a get/put style interface, acquire struct mutex
1501 * any time we access those registers.
1502 */
1503 mutex_lock(&dev_priv->dev->struct_mutex);
1504
35a85ac6
BW		 1505 /* If we've screwed up tracking, just let the interrupt fire again */
1506 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1507 goto out;
1508
e3689190
BW		 1509 misccpctl = I915_READ(GEN7_MISCCPCTL);
1510 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1511 POSTING_READ(GEN7_MISCCPCTL);
1512
35a85ac6
BW		 1513 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1514 u32 reg;
e3689190 1515
35a85ac6
BW		 1516 slice--;
1517 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1518 break;
e3689190 1519
35a85ac6 1520 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 1521
35a85ac6 1522 reg = GEN7_L3CDERRST1 + (slice * 0x200);
e3689190 1523
35a85ac6
BW		 1524 error_status = I915_READ(reg);
1525 row = GEN7_PARITY_ERROR_ROW(error_status);
1526 bank = GEN7_PARITY_ERROR_BANK(error_status);
1527 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1528
1529 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1530 POSTING_READ(reg);
1531
1532 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1533 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1534 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1535 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1536 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1537 parity_event[5] = NULL;
1538
5bdebb18 1539 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
35a85ac6 1540 KOBJ_CHANGE, parity_event);
e3689190 1541
35a85ac6
BW		 1542 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1543 slice, row, bank, subbank);
e3689190 1544
35a85ac6
BW		 1545 kfree(parity_event[4]);
1546 kfree(parity_event[3]);
1547 kfree(parity_event[2]);
1548 kfree(parity_event[1]);
1549 }
e3689190 1550
35a85ac6 1551 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 1552
35a85ac6
BW		 1553out:
1554 WARN_ON(dev_priv->l3_parity.which_slice);
1555 spin_lock_irqsave(&dev_priv->irq_lock, flags);
480c8033 1556 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
35a85ac6
BW		 1557 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1558
1559 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 1560}
1561
35a85ac6 1562static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190 1563{
2d1013dd 1564 struct drm_i915_private *dev_priv = dev->dev_private;
e3689190 1565
040d2baa 1566 if (!HAS_L3_DPF(dev))
e3689190
BW		 1567 return;
1568
d0ecd7e2 1569 spin_lock(&dev_priv->irq_lock);
480c8033 1570 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 1571 spin_unlock(&dev_priv->irq_lock);
e3689190 1572
35a85ac6
BW		 1573 iir &= GT_PARITY_ERROR(dev);
1574 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1575 dev_priv->l3_parity.which_slice |= 1 << 1;
1576
1577 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1578 dev_priv->l3_parity.which_slice |= 1 << 0;
1579
a4da4fa4 1580 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1581}
1582
f1af8fc1
PZ		 1583static void ilk_gt_irq_handler(struct drm_device *dev,
1584 struct drm_i915_private *dev_priv,
1585 u32 gt_iir)
1586{
1587 if (gt_iir &
1588 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1589 notify_ring(dev, &dev_priv->ring[RCS]);
1590 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1591 notify_ring(dev, &dev_priv->ring[VCS]);
1592}
1593
e7b4c6b1
DV		 1594static void snb_gt_irq_handler(struct drm_device *dev,
1595 struct drm_i915_private *dev_priv,
1596 u32 gt_iir)
1597{
1598
cc609d5d
BW		 1599 if (gt_iir &
1600 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1601 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1602 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 1603 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 1604 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 1605 notify_ring(dev, &dev_priv->ring[BCS]);
1606
cc609d5d
BW		 1607 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1608 GT_BSD_CS_ERROR_INTERRUPT |
1609 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
58174462
MK		 1610 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1611 gt_iir);
e7b4c6b1 1612 }
e3689190 1613
35a85ac6
BW		 1614 if (gt_iir & GT_PARITY_ERROR(dev))
1615 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1616}
1617
0961021a
BW		 1618static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1619{
1620 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1621 return;
1622
1623 spin_lock(&dev_priv->irq_lock);
1624 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
480c8033 1625 gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
0961021a
BW		 1626 spin_unlock(&dev_priv->irq_lock);
1627
1628 queue_work(dev_priv->wq, &dev_priv->rps.work);
1629}
1630
abd58f01
BW		 1631static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1632 struct drm_i915_private *dev_priv,
1633 u32 master_ctl)
1634{
e981e7b1 1635 struct intel_engine_cs *ring;
abd58f01
BW		 1636 u32 rcs, bcs, vcs;
1637 uint32_t tmp = 0;
1638 irqreturn_t ret = IRQ_NONE;
1639
1640 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1641 tmp = I915_READ(GEN8_GT_IIR(0));
1642 if (tmp) {
38cc46d7 1643 I915_WRITE(GEN8_GT_IIR(0), tmp);
abd58f01 1644 ret = IRQ_HANDLED;
e981e7b1 1645
abd58f01 1646 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
e981e7b1 1647 ring = &dev_priv->ring[RCS];
abd58f01 1648 if (rcs & GT_RENDER_USER_INTERRUPT)
e981e7b1
TD		 1649 notify_ring(dev, ring);
1650 if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1651 intel_execlists_handle_ctx_events(ring);
1652
1653 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1654 ring = &dev_priv->ring[BCS];
abd58f01 1655 if (bcs & GT_RENDER_USER_INTERRUPT)
e981e7b1
TD		 1656 notify_ring(dev, ring);
1657 if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1658 intel_execlists_handle_ctx_events(ring);
abd58f01
BW		 1659 } else
1660 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1661 }
1662
85f9b5f9 1663 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
abd58f01
BW		 1664 tmp = I915_READ(GEN8_GT_IIR(1));
1665 if (tmp) {
38cc46d7 1666 I915_WRITE(GEN8_GT_IIR(1), tmp);
abd58f01 1667 ret = IRQ_HANDLED;
e981e7b1 1668
abd58f01 1669 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
e981e7b1 1670 ring = &dev_priv->ring[VCS];
abd58f01 1671 if (vcs & GT_RENDER_USER_INTERRUPT)
e981e7b1 1672 notify_ring(dev, ring);
73d477f6 1673 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
e981e7b1
TD		 1674 intel_execlists_handle_ctx_events(ring);
1675
85f9b5f9 1676 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
e981e7b1 1677 ring = &dev_priv->ring[VCS2];
85f9b5f9 1678 if (vcs & GT_RENDER_USER_INTERRUPT)
e981e7b1 1679 notify_ring(dev, ring);
73d477f6 1680 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
e981e7b1 1681 intel_execlists_handle_ctx_events(ring);
abd58f01
BW		 1682 } else
1683 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1684 }
1685
0961021a
BW		 1686 if (master_ctl & GEN8_GT_PM_IRQ) {
1687 tmp = I915_READ(GEN8_GT_IIR(2));
1688 if (tmp & dev_priv->pm_rps_events) {
0961021a
BW		 1689 I915_WRITE(GEN8_GT_IIR(2),
1690 tmp & dev_priv->pm_rps_events);
38cc46d7
OM		 1691 ret = IRQ_HANDLED;
1692 gen8_rps_irq_handler(dev_priv, tmp);
0961021a
BW		 1693 } else
1694 DRM_ERROR("The master control interrupt lied (PM)!\n");
1695 }
1696
abd58f01
BW		 1697 if (master_ctl & GEN8_GT_VECS_IRQ) {
1698 tmp = I915_READ(GEN8_GT_IIR(3));
1699 if (tmp) {
38cc46d7 1700 I915_WRITE(GEN8_GT_IIR(3), tmp);
abd58f01 1701 ret = IRQ_HANDLED;
e981e7b1 1702
abd58f01 1703 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
e981e7b1 1704 ring = &dev_priv->ring[VECS];
abd58f01 1705 if (vcs & GT_RENDER_USER_INTERRUPT)
e981e7b1 1706 notify_ring(dev, ring);
73d477f6 1707 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
e981e7b1 1708 intel_execlists_handle_ctx_events(ring);
abd58f01
BW		 1709 } else
1710 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1711 }
1712
1713 return ret;
1714}
1715
b543fb04
EE		 1716#define HPD_STORM_DETECT_PERIOD 1000
1717#define HPD_STORM_THRESHOLD 5
1718
13cf5504
DA		 1719static int ilk_port_to_hotplug_shift(enum port port)
1720{
1721 switch (port) {
1722 case PORT_A:
1723 case PORT_E:
1724 default:
1725 return -1;
1726 case PORT_B:
1727 return 0;
1728 case PORT_C:
1729 return 8;
1730 case PORT_D:
1731 return 16;
1732 }
1733}
1734
1735static int g4x_port_to_hotplug_shift(enum port port)
1736{
1737 switch (port) {
1738 case PORT_A:
1739 case PORT_E:
1740 default:
1741 return -1;
1742 case PORT_B:
1743 return 17;
1744 case PORT_C:
1745 return 19;
1746 case PORT_D:
1747 return 21;
1748 }
1749}
1750
1751static inline enum port get_port_from_pin(enum hpd_pin pin)
1752{
1753 switch (pin) {
1754 case HPD_PORT_B:
1755 return PORT_B;
1756 case HPD_PORT_C:
1757 return PORT_C;
1758 case HPD_PORT_D:
1759 return PORT_D;
1760 default:
1761 return PORT_A; /* no hpd */
1762 }
1763}
1764
10a504de 1765static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba 1766 u32 hotplug_trigger,
13cf5504 1767 u32 dig_hotplug_reg,
22062dba 1768 const u32 *hpd)
b543fb04 1769{
2d1013dd 1770 struct drm_i915_private *dev_priv = dev->dev_private;
b543fb04 1771 int i;
13cf5504 1772 enum port port;
10a504de 1773 bool storm_detected = false;
13cf5504
DA		 1774 bool queue_dig = false, queue_hp = false;
1775 u32 dig_shift;
1776 u32 dig_port_mask = 0;
b543fb04 1777
91d131d2
DV		 1778 if (!hotplug_trigger)
1779 return;
1780
13cf5504
DA		 1781 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1782 hotplug_trigger, dig_hotplug_reg);
cc9bd499 1783
b5ea2d56 1784 spin_lock(&dev_priv->irq_lock);
b543fb04 1785 for (i = 1; i < HPD_NUM_PINS; i++) {
13cf5504
DA		 1786 if (!(hpd[i] & hotplug_trigger))
1787 continue;
1788
1789 port = get_port_from_pin(i);
1790 if (port && dev_priv->hpd_irq_port[port]) {
1791 bool long_hpd;
1792
1793 if (IS_G4X(dev)) {
1794 dig_shift = g4x_port_to_hotplug_shift(port);
1795 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1796 } else {
1797 dig_shift = ilk_port_to_hotplug_shift(port);
1798 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1799 }
1800
26fbb774
VS		 1801 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1802 port_name(port),
1803 long_hpd ? "long" : "short");
13cf5504
DA		 1804 /* for long HPD pulses we want to have the digital queue happen,
1805 but we still want HPD storm detection to function. */
1806 if (long_hpd) {
1807 dev_priv->long_hpd_port_mask |= (1 << port);
1808 dig_port_mask |= hpd[i];
1809 } else {
1810 /* for short HPD just trigger the digital queue */
1811 dev_priv->short_hpd_port_mask |= (1 << port);
1812 hotplug_trigger &= ~hpd[i];
1813 }
1814 queue_dig = true;
1815 }
1816 }
821450c6 1817
13cf5504 1818 for (i = 1; i < HPD_NUM_PINS; i++) {
3ff04a16
DV		 1819 if (hpd[i] & hotplug_trigger &&
1820 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1821 /*
1822 * On GMCH platforms the interrupt mask bits only
1823 * prevent irq generation, not the setting of the
1824 * hotplug bits itself. So only WARN about unexpected
1825 * interrupts on saner platforms.
1826 */
1827 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1828 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1829 hotplug_trigger, i, hpd[i]);
1830
1831 continue;
1832 }
b8f102e8 1833
b543fb04
EE		 1834 if (!(hpd[i] & hotplug_trigger) ||
1835 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1836 continue;
1837
13cf5504
DA		 1838 if (!(dig_port_mask & hpd[i])) {
1839 dev_priv->hpd_event_bits |= (1 << i);
1840 queue_hp = true;
1841 }
1842
b543fb04
EE		 1843 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1844 dev_priv->hpd_stats[i].hpd_last_jiffies
1845 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1846 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1847 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1848 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1849 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1850 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1851 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1852 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1853 storm_detected = true;
b543fb04
EE		 1854 } else {
1855 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1856 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1857 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1858 }
1859 }
1860
10a504de
DV		 1861 if (storm_detected)
1862 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1863 spin_unlock(&dev_priv->irq_lock);
5876fa0d 1864
645416f5
DV		 1865 /*
1866 * Our hotplug handler can grab modeset locks (by calling down into the
1867 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1868 * queue for otherwise the flush_work in the pageflip code will
1869 * deadlock.
1870 */
13cf5504 1871 if (queue_dig)
0e32b39c 1872 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
13cf5504
DA		 1873 if (queue_hp)
1874 schedule_work(&dev_priv->hotplug_work);
b543fb04
EE		 1875}
1876
515ac2bb
DV		 1877static void gmbus_irq_handler(struct drm_device *dev)
1878{
2d1013dd 1879 struct drm_i915_private *dev_priv = dev->dev_private;
28c70f16 1880
28c70f16 1881 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1882}
1883
ce99c256
DV		 1884static void dp_aux_irq_handler(struct drm_device *dev)
1885{
2d1013dd 1886 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 1887
9ee32fea 1888 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1889}
1890
8bf1e9f1 1891#if defined(CONFIG_DEBUG_FS)
277de95e
DV		 1892static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1893 uint32_t crc0, uint32_t crc1,
1894 uint32_t crc2, uint32_t crc3,
1895 uint32_t crc4)
8bf1e9f1
SH		 1896{
1897 struct drm_i915_private *dev_priv = dev->dev_private;
1898 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1899 struct intel_pipe_crc_entry *entry;
ac2300d4 1900 int head, tail;
b2c88f5b 1901
d538bbdf
DL		 1902 spin_lock(&pipe_crc->lock);
1903
0c912c79 1904 if (!pipe_crc->entries) {
d538bbdf 1905 spin_unlock(&pipe_crc->lock);
0c912c79
DL		 1906 DRM_ERROR("spurious interrupt\n");
1907 return;
1908 }
1909
d538bbdf
DL		 1910 head = pipe_crc->head;
1911 tail = pipe_crc->tail;
b2c88f5b
DL		 1912
1913 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
d538bbdf 1914 spin_unlock(&pipe_crc->lock);
b2c88f5b
DL		 1915 DRM_ERROR("CRC buffer overflowing\n");
1916 return;
1917 }
1918
1919 entry = &pipe_crc->entries[head];
8bf1e9f1 1920
8bc5e955 1921 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
eba94eb9
DV		 1922 entry->crc[0] = crc0;
1923 entry->crc[1] = crc1;
1924 entry->crc[2] = crc2;
1925 entry->crc[3] = crc3;
1926 entry->crc[4] = crc4;
b2c88f5b
DL		 1927
1928 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
d538bbdf
DL		 1929 pipe_crc->head = head;
1930
1931 spin_unlock(&pipe_crc->lock);
07144428
DL		 1932
1933 wake_up_interruptible(&pipe_crc->wq);
8bf1e9f1 1934}
277de95e
DV		 1935#else
1936static inline void
1937display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1938 uint32_t crc0, uint32_t crc1,
1939 uint32_t crc2, uint32_t crc3,
1940 uint32_t crc4) {}
1941#endif
1942
eba94eb9 1943
277de95e 1944static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5a69b89f
DV		 1945{
1946 struct drm_i915_private *dev_priv = dev->dev_private;
1947
277de95e
DV		 1948 display_pipe_crc_irq_handler(dev, pipe,
1949 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1950 0, 0, 0, 0);
5a69b89f
DV		 1951}
1952
277de95e 1953static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
eba94eb9
DV		 1954{
1955 struct drm_i915_private *dev_priv = dev->dev_private;
1956
277de95e
DV		 1957 display_pipe_crc_irq_handler(dev, pipe,
1958 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1959 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1960 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1961 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1962 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
eba94eb9 1963}
5b3a856b 1964
277de95e 1965static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5b3a856b
DV		 1966{
1967 struct drm_i915_private *dev_priv = dev->dev_private;
0b5c5ed0
DV		 1968 uint32_t res1, res2;
1969
1970 if (INTEL_INFO(dev)->gen >= 3)
1971 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1972 else
1973 res1 = 0;
1974
1975 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1976 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1977 else
1978 res2 = 0;
5b3a856b 1979
277de95e
DV		 1980 display_pipe_crc_irq_handler(dev, pipe,
1981 I915_READ(PIPE_CRC_RES_RED(pipe)),
1982 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1983 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1984 res1, res2);
5b3a856b 1985}
8bf1e9f1 1986
1403c0d4
PZ		 1987/* The RPS events need forcewake, so we add them to a work queue and mask their
1988 * IMR bits until the work is done. Other interrupts can be processed without
1989 * the work queue. */
1990static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1991{
a6706b45 1992 if (pm_iir & dev_priv->pm_rps_events) {
59cdb63d 1993 spin_lock(&dev_priv->irq_lock);
a6706b45 1994 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
480c8033 1995 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
59cdb63d 1996 spin_unlock(&dev_priv->irq_lock);
2adbee62
DV		 1997
1998 queue_work(dev_priv->wq, &dev_priv->rps.work);
baf02a1f 1999 }
baf02a1f 2000
1403c0d4
PZ		 2001 if (HAS_VEBOX(dev_priv->dev)) {
2002 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
2003 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 2004
1403c0d4 2005 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
58174462
MK		 2006 i915_handle_error(dev_priv->dev, false,
2007 "VEBOX CS error interrupt 0x%08x",
2008 pm_iir);
1403c0d4 2009 }
12638c57 2010 }
baf02a1f
BW		 2011}
2012
8d7849db
VS		 2013static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
2014{
8d7849db
VS		 2015 if (!drm_handle_vblank(dev, pipe))
2016 return false;
2017
8d7849db
VS		 2018 return true;
2019}
2020
c1874ed7
ID		 2021static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
2022{
2023 struct drm_i915_private *dev_priv = dev->dev_private;
91d181dd 2024 u32 pipe_stats[I915_MAX_PIPES] = { };
c1874ed7
ID		 2025 int pipe;
2026
58ead0d7 2027 spin_lock(&dev_priv->irq_lock);
c1874ed7 2028 for_each_pipe(pipe) {
91d181dd 2029 int reg;
bbb5eebf 2030 u32 mask, iir_bit = 0;
91d181dd 2031
bbb5eebf
DV		 2032 /*
2033 * PIPESTAT bits get signalled even when the interrupt is
2034 * disabled with the mask bits, and some of the status bits do
2035 * not generate interrupts at all (like the underrun bit). Hence
2036 * we need to be careful that we only handle what we want to
2037 * handle.
2038 */
2039 mask = 0;
2040 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
2041 mask |= PIPE_FIFO_UNDERRUN_STATUS;
2042
2043 switch (pipe) {
2044 case PIPE_A:
2045 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
2046 break;
2047 case PIPE_B:
2048 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
2049 break;
3278f67f
VS		 2050 case PIPE_C:
2051 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
2052 break;
bbb5eebf
DV		 2053 }
2054 if (iir & iir_bit)
2055 mask |= dev_priv->pipestat_irq_mask[pipe];
2056
2057 if (!mask)
91d181dd
ID		 2058 continue;
2059
2060 reg = PIPESTAT(pipe);
bbb5eebf
DV		 2061 mask |= PIPESTAT_INT_ENABLE_MASK;
2062 pipe_stats[pipe] = I915_READ(reg) & mask;
c1874ed7
ID		 2063
2064 /*
2065 * Clear the PIPE*STAT regs before the IIR
2066 */
91d181dd
ID		 2067 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
2068 PIPESTAT_INT_STATUS_MASK))
c1874ed7
ID		 2069 I915_WRITE(reg, pipe_stats[pipe]);
2070 }
58ead0d7 2071 spin_unlock(&dev_priv->irq_lock);
c1874ed7
ID		 2072
2073 for_each_pipe(pipe) {
2074 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
8d7849db 2075 intel_pipe_handle_vblank(dev, pipe);
c1874ed7 2076
579a9b0e 2077 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
c1874ed7
ID		 2078 intel_prepare_page_flip(dev, pipe);
2079 intel_finish_page_flip(dev, pipe);
2080 }
2081
2082 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2083 i9xx_pipe_crc_irq_handler(dev, pipe);
2084
2085 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
2086 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
2087 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
2088 }
2089
2090 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2091 gmbus_irq_handler(dev);
2092}
2093
16c6c56b
VS		 2094static void i9xx_hpd_irq_handler(struct drm_device *dev)
2095{
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2097 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2098
3ff60f89
OM		 2099 if (hotplug_status) {
2100 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2101 /*
2102 * Make sure hotplug status is cleared before we clear IIR, or else we
2103 * may miss hotplug events.
2104 */
2105 POSTING_READ(PORT_HOTPLUG_STAT);
16c6c56b 2106
3ff60f89
OM		 2107 if (IS_G4X(dev)) {
2108 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
16c6c56b 2109
13cf5504 2110 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
3ff60f89
OM		 2111 } else {
2112 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
16c6c56b 2113
13cf5504 2114 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
3ff60f89 2115 }
16c6c56b 2116
3ff60f89
OM		 2117 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
2118 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
2119 dp_aux_irq_handler(dev);
2120 }
16c6c56b
VS		 2121}
2122
ff1f525e 2123static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe 2124{
45a83f84 2125 struct drm_device *dev = arg;
2d1013dd 2126 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 2127 u32 iir, gt_iir, pm_iir;
2128 irqreturn_t ret = IRQ_NONE;
7e231dbe 2129
7e231dbe 2130 while (true) {
3ff60f89
OM		 2131 /* Find, clear, then process each source of interrupt */
2132
7e231dbe 2133 gt_iir = I915_READ(GTIIR);
3ff60f89
OM		 2134 if (gt_iir)
2135 I915_WRITE(GTIIR, gt_iir);
2136
7e231dbe 2137 pm_iir = I915_READ(GEN6_PMIIR);
3ff60f89
OM		 2138 if (pm_iir)
2139 I915_WRITE(GEN6_PMIIR, pm_iir);
2140
2141 iir = I915_READ(VLV_IIR);
2142 if (iir) {
2143 /* Consume port before clearing IIR or we'll miss events */
2144 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2145 i9xx_hpd_irq_handler(dev);
2146 I915_WRITE(VLV_IIR, iir);
2147 }
7e231dbe
JB		 2148
2149 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
2150 goto out;
2151
2152 ret = IRQ_HANDLED;
2153
3ff60f89
OM		 2154 if (gt_iir)
2155 snb_gt_irq_handler(dev, dev_priv, gt_iir);
60611c13 2156 if (pm_iir)
d0ecd7e2 2157 gen6_rps_irq_handler(dev_priv, pm_iir);
3ff60f89
OM		 2158 /* Call regardless, as some status bits might not be
2159 * signalled in iir */
2160 valleyview_pipestat_irq_handler(dev, iir);
7e231dbe
JB		 2161 }
2162
2163out:
2164 return ret;
2165}
2166
43f328d7
VS		 2167static irqreturn_t cherryview_irq_handler(int irq, void *arg)
2168{
45a83f84 2169 struct drm_device *dev = arg;
43f328d7
VS		 2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 u32 master_ctl, iir;
2172 irqreturn_t ret = IRQ_NONE;
43f328d7 2173
8e5fd599
VS		 2174 for (;;) {
2175 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
2176 iir = I915_READ(VLV_IIR);
43f328d7 2177
8e5fd599
VS		 2178 if (master_ctl == 0 && iir == 0)
2179 break;
43f328d7 2180
27b6c122
OM		 2181 ret = IRQ_HANDLED;
2182
8e5fd599 2183 I915_WRITE(GEN8_MASTER_IRQ, 0);
43f328d7 2184
27b6c122 2185 /* Find, clear, then process each source of interrupt */
43f328d7 2186
27b6c122
OM		 2187 if (iir) {
2188 /* Consume port before clearing IIR or we'll miss events */
2189 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2190 i9xx_hpd_irq_handler(dev);
2191 I915_WRITE(VLV_IIR, iir);
2192 }
43f328d7 2193
27b6c122 2194 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
43f328d7 2195
27b6c122
OM		 2196 /* Call regardless, as some status bits might not be
2197 * signalled in iir */
2198 valleyview_pipestat_irq_handler(dev, iir);
43f328d7 2199
8e5fd599
VS		 2200 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
2201 POSTING_READ(GEN8_MASTER_IRQ);
8e5fd599 2202 }
3278f67f 2203
43f328d7
VS		 2204 return ret;
2205}
2206
23e81d69 2207static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806 2208{
2d1013dd 2209 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 2210 int pipe;
b543fb04 2211 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
13cf5504
DA		 2212 u32 dig_hotplug_reg;
2213
2214 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2215 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
776ad806 2216
13cf5504 2217 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
91d131d2 2218
cfc33bf7
VS		 2219 if (pch_iir & SDE_AUDIO_POWER_MASK) {
2220 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2221 SDE_AUDIO_POWER_SHIFT);
776ad806 2222 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 2223 port_name(port));
2224 }
776ad806 2225
ce99c256
DV		 2226 if (pch_iir & SDE_AUX_MASK)
2227 dp_aux_irq_handler(dev);
2228
776ad806 2229 if (pch_iir & SDE_GMBUS)
515ac2bb 2230 gmbus_irq_handler(dev);
776ad806
JB		 2231
2232 if (pch_iir & SDE_AUDIO_HDCP_MASK)
2233 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2234
2235 if (pch_iir & SDE_AUDIO_TRANS_MASK)
2236 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2237
2238 if (pch_iir & SDE_POISON)
2239 DRM_ERROR("PCH poison interrupt\n");
2240
9db4a9c7
JB		 2241 if (pch_iir & SDE_FDI_MASK)
2242 for_each_pipe(pipe)
2243 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2244 pipe_name(pipe),
2245 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 2246
2247 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2248 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2249
2250 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2251 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2252
776ad806 2253 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 2254 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
2255 false))
fc2c807b 2256 DRM_ERROR("PCH transcoder A FIFO underrun\n");
8664281b
PZ		 2257
2258 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2259 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
2260 false))
fc2c807b 2261 DRM_ERROR("PCH transcoder B FIFO underrun\n");
8664281b
PZ		 2262}
2263
2264static void ivb_err_int_handler(struct drm_device *dev)
2265{
2266 struct drm_i915_private *dev_priv = dev->dev_private;
2267 u32 err_int = I915_READ(GEN7_ERR_INT);
5a69b89f 2268 enum pipe pipe;
8664281b 2269
de032bf4
PZ		 2270 if (err_int & ERR_INT_POISON)
2271 DRM_ERROR("Poison interrupt\n");
2272
5a69b89f
DV		 2273 for_each_pipe(pipe) {
2274 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
2275 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2276 false))
fc2c807b
VS		 2277 DRM_ERROR("Pipe %c FIFO underrun\n",
2278 pipe_name(pipe));
5a69b89f 2279 }
8bf1e9f1 2280
5a69b89f
DV		 2281 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2282 if (IS_IVYBRIDGE(dev))
277de95e 2283 ivb_pipe_crc_irq_handler(dev, pipe);
5a69b89f 2284 else
277de95e 2285 hsw_pipe_crc_irq_handler(dev, pipe);
5a69b89f
DV		 2286 }
2287 }
8bf1e9f1 2288
8664281b
PZ		 2289 I915_WRITE(GEN7_ERR_INT, err_int);
2290}
2291
2292static void cpt_serr_int_handler(struct drm_device *dev)
2293{
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 u32 serr_int = I915_READ(SERR_INT);
2296
de032bf4
PZ		 2297 if (serr_int & SERR_INT_POISON)
2298 DRM_ERROR("PCH poison interrupt\n");
2299
8664281b
PZ		 2300 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2301 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
2302 false))
fc2c807b 2303 DRM_ERROR("PCH transcoder A FIFO underrun\n");
8664281b
PZ		 2304
2305 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2306 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
2307 false))
fc2c807b 2308 DRM_ERROR("PCH transcoder B FIFO underrun\n");
8664281b
PZ		 2309
2310 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2311 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
2312 false))
fc2c807b 2313 DRM_ERROR("PCH transcoder C FIFO underrun\n");
8664281b
PZ		 2314
2315 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 2316}
2317
23e81d69
AJ		 2318static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2319{
2d1013dd 2320 struct drm_i915_private *dev_priv = dev->dev_private;
23e81d69 2321 int pipe;
b543fb04 2322 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
13cf5504
DA		 2323 u32 dig_hotplug_reg;
2324
2325 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2326 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
23e81d69 2327
13cf5504 2328 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
91d131d2 2329
cfc33bf7
VS		 2330 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2331 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2332 SDE_AUDIO_POWER_SHIFT_CPT);
2333 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2334 port_name(port));
2335 }
23e81d69
AJ		 2336
2337 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 2338 dp_aux_irq_handler(dev);
23e81d69
AJ		 2339
2340 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 2341 gmbus_irq_handler(dev);
23e81d69
AJ		 2342
2343 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2344 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2345
2346 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2347 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2348
2349 if (pch_iir & SDE_FDI_MASK_CPT)
2350 for_each_pipe(pipe)
2351 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2352 pipe_name(pipe),
2353 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 2354
2355 if (pch_iir & SDE_ERROR_CPT)
2356 cpt_serr_int_handler(dev);
23e81d69
AJ		 2357}
2358
c008bc6e
PZ		 2359static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2360{
2361 struct drm_i915_private *dev_priv = dev->dev_private;
40da17c2 2362 enum pipe pipe;
c008bc6e
PZ		 2363
2364 if (de_iir & DE_AUX_CHANNEL_A)
2365 dp_aux_irq_handler(dev);
2366
2367 if (de_iir & DE_GSE)
2368 intel_opregion_asle_intr(dev);
2369
c008bc6e
PZ		 2370 if (de_iir & DE_POISON)
2371 DRM_ERROR("Poison interrupt\n");
2372
40da17c2
DV		 2373 for_each_pipe(pipe) {
2374 if (de_iir & DE_PIPE_VBLANK(pipe))
8d7849db 2375 intel_pipe_handle_vblank(dev, pipe);
5b3a856b 2376
40da17c2
DV		 2377 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2378 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b
VS		 2379 DRM_ERROR("Pipe %c FIFO underrun\n",
2380 pipe_name(pipe));
5b3a856b 2381
40da17c2
DV		 2382 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2383 i9xx_pipe_crc_irq_handler(dev, pipe);
c008bc6e 2384
40da17c2
DV		 2385 /* plane/pipes map 1:1 on ilk+ */
2386 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2387 intel_prepare_page_flip(dev, pipe);
2388 intel_finish_page_flip_plane(dev, pipe);
2389 }
c008bc6e
PZ		 2390 }
2391
2392 /* check event from PCH */
2393 if (de_iir & DE_PCH_EVENT) {
2394 u32 pch_iir = I915_READ(SDEIIR);
2395
2396 if (HAS_PCH_CPT(dev))
2397 cpt_irq_handler(dev, pch_iir);
2398 else
2399 ibx_irq_handler(dev, pch_iir);
2400
2401 /* should clear PCH hotplug event before clear CPU irq */
2402 I915_WRITE(SDEIIR, pch_iir);
2403 }
2404
2405 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2406 ironlake_rps_change_irq_handler(dev);
2407}
2408
9719fb98
PZ		 2409static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2410{
2411 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 2412 enum pipe pipe;
9719fb98
PZ		 2413
2414 if (de_iir & DE_ERR_INT_IVB)
2415 ivb_err_int_handler(dev);
2416
2417 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2418 dp_aux_irq_handler(dev);
2419
2420 if (de_iir & DE_GSE_IVB)
2421 intel_opregion_asle_intr(dev);
2422
07d27e20
DL		 2423 for_each_pipe(pipe) {
2424 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
8d7849db 2425 intel_pipe_handle_vblank(dev, pipe);
40da17c2
DV		 2426
2427 /* plane/pipes map 1:1 on ilk+ */
07d27e20
DL		 2428 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2429 intel_prepare_page_flip(dev, pipe);
2430 intel_finish_page_flip_plane(dev, pipe);
9719fb98
PZ		 2431 }
2432 }
2433
2434 /* check event from PCH */
2435 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2436 u32 pch_iir = I915_READ(SDEIIR);
2437
2438 cpt_irq_handler(dev, pch_iir);
2439
2440 /* clear PCH hotplug event before clear CPU irq */
2441 I915_WRITE(SDEIIR, pch_iir);
2442 }
2443}
2444
72c90f62
OM		 2445/*
2446 * To handle irqs with the minimum potential races with fresh interrupts, we:
2447 * 1 - Disable Master Interrupt Control.
2448 * 2 - Find the source(s) of the interrupt.
2449 * 3 - Clear the Interrupt Identity bits (IIR).
2450 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2451 * 5 - Re-enable Master Interrupt Control.
2452 */
f1af8fc1 2453static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0 2454{
45a83f84 2455 struct drm_device *dev = arg;
2d1013dd 2456 struct drm_i915_private *dev_priv = dev->dev_private;
f1af8fc1 2457 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 2458 irqreturn_t ret = IRQ_NONE;
b1f14ad0 2459
8664281b
PZ		 2460 /* We get interrupts on unclaimed registers, so check for this before we
2461 * do any I915_{READ,WRITE}. */
907b28c5 2462 intel_uncore_check_errors(dev);
8664281b 2463
b1f14ad0
JB		 2464 /* disable master interrupt before clearing iir */
2465 de_ier = I915_READ(DEIER);
2466 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 2467 POSTING_READ(DEIER);
b1f14ad0 2468
44498aea
PZ		 2469 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2470 * interrupts will will be stored on its back queue, and then we'll be
2471 * able to process them after we restore SDEIER (as soon as we restore
2472 * it, we'll get an interrupt if SDEIIR still has something to process
2473 * due to its back queue). */
ab5c608b
BW		 2474 if (!HAS_PCH_NOP(dev)) {
2475 sde_ier = I915_READ(SDEIER);
2476 I915_WRITE(SDEIER, 0);
2477 POSTING_READ(SDEIER);
2478 }
44498aea 2479
72c90f62
OM		 2480 /* Find, clear, then process each source of interrupt */
2481
b1f14ad0 2482 gt_iir = I915_READ(GTIIR);
0e43406b 2483 if (gt_iir) {
72c90f62
OM		 2484 I915_WRITE(GTIIR, gt_iir);
2485 ret = IRQ_HANDLED;
d8fc8a47 2486 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 2487 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 2488 else
2489 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 2490 }
2491
0e43406b
CW		 2492 de_iir = I915_READ(DEIIR);
2493 if (de_iir) {
72c90f62
OM		 2494 I915_WRITE(DEIIR, de_iir);
2495 ret = IRQ_HANDLED;
f1af8fc1
PZ		 2496 if (INTEL_INFO(dev)->gen >= 7)
2497 ivb_display_irq_handler(dev, de_iir);
2498 else
2499 ilk_display_irq_handler(dev, de_iir);
b1f14ad0
JB		 2500 }
2501
f1af8fc1
PZ		 2502 if (INTEL_INFO(dev)->gen >= 6) {
2503 u32 pm_iir = I915_READ(GEN6_PMIIR);
2504 if (pm_iir) {
f1af8fc1
PZ		 2505 I915_WRITE(GEN6_PMIIR, pm_iir);
2506 ret = IRQ_HANDLED;
72c90f62 2507 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1 2508 }
0e43406b 2509 }
b1f14ad0 2510
b1f14ad0
JB		 2511 I915_WRITE(DEIER, de_ier);
2512 POSTING_READ(DEIER);
ab5c608b
BW		 2513 if (!HAS_PCH_NOP(dev)) {
2514 I915_WRITE(SDEIER, sde_ier);
2515 POSTING_READ(SDEIER);
2516 }
b1f14ad0
JB		 2517
2518 return ret;
2519}
2520
abd58f01
BW		 2521static irqreturn_t gen8_irq_handler(int irq, void *arg)
2522{
2523 struct drm_device *dev = arg;
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 u32 master_ctl;
2526 irqreturn_t ret = IRQ_NONE;
2527 uint32_t tmp = 0;
c42664cc 2528 enum pipe pipe;
abd58f01 2529
abd58f01
BW		 2530 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2531 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2532 if (!master_ctl)
2533 return IRQ_NONE;
2534
2535 I915_WRITE(GEN8_MASTER_IRQ, 0);
2536 POSTING_READ(GEN8_MASTER_IRQ);
2537
38cc46d7
OM		 2538 /* Find, clear, then process each source of interrupt */
2539
abd58f01
BW		 2540 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2541
2542 if (master_ctl & GEN8_DE_MISC_IRQ) {
2543 tmp = I915_READ(GEN8_DE_MISC_IIR);
abd58f01
BW		 2544 if (tmp) {
2545 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2546 ret = IRQ_HANDLED;
38cc46d7
OM		 2547 if (tmp & GEN8_DE_MISC_GSE)
2548 intel_opregion_asle_intr(dev);
2549 else
2550 DRM_ERROR("Unexpected DE Misc interrupt\n");
abd58f01 2551 }
38cc46d7
OM		 2552 else
2553 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
abd58f01
BW		 2554 }
2555
6d766f02
DV		 2556 if (master_ctl & GEN8_DE_PORT_IRQ) {
2557 tmp = I915_READ(GEN8_DE_PORT_IIR);
6d766f02
DV		 2558 if (tmp) {
2559 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2560 ret = IRQ_HANDLED;
38cc46d7
OM		 2561 if (tmp & GEN8_AUX_CHANNEL_A)
2562 dp_aux_irq_handler(dev);
2563 else
2564 DRM_ERROR("Unexpected DE Port interrupt\n");
6d766f02 2565 }
38cc46d7
OM		 2566 else
2567 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
6d766f02
DV		 2568 }
2569
c42664cc
DV		 2570 for_each_pipe(pipe) {
2571 uint32_t pipe_iir;
abd58f01 2572
c42664cc
DV		 2573 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2574 continue;
abd58f01 2575
c42664cc 2576 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
c42664cc
DV		 2577 if (pipe_iir) {
2578 ret = IRQ_HANDLED;
2579 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
38cc46d7
OM		 2580 if (pipe_iir & GEN8_PIPE_VBLANK)
2581 intel_pipe_handle_vblank(dev, pipe);
2582
2583 if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) {
2584 intel_prepare_page_flip(dev, pipe);
2585 intel_finish_page_flip_plane(dev, pipe);
2586 }
2587
2588 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2589 hsw_pipe_crc_irq_handler(dev, pipe);
2590
2591 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2592 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2593 false))
2594 DRM_ERROR("Pipe %c FIFO underrun\n",
2595 pipe_name(pipe));
2596 }
2597
2598 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2599 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2600 pipe_name(pipe),
2601 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2602 }
c42664cc 2603 } else
abd58f01
BW		 2604 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2605 }
2606
92d03a80
DV		 2607 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2608 /*
2609 * FIXME(BDW): Assume for now that the new interrupt handling
2610 * scheme also closed the SDE interrupt handling race we've seen
2611 * on older pch-split platforms. But this needs testing.
2612 */
2613 u32 pch_iir = I915_READ(SDEIIR);
92d03a80
DV		 2614 if (pch_iir) {
2615 I915_WRITE(SDEIIR, pch_iir);
2616 ret = IRQ_HANDLED;
38cc46d7
OM		 2617 cpt_irq_handler(dev, pch_iir);
2618 } else
2619 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2620
92d03a80
DV		 2621 }
2622
abd58f01
BW		 2623 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2624 POSTING_READ(GEN8_MASTER_IRQ);
2625
2626 return ret;
2627}
2628
17e1df07
DV		 2629static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2630 bool reset_completed)
2631{
a4872ba6 2632 struct intel_engine_cs *ring;
17e1df07
DV		 2633 int i;
2634
2635 /*
2636 * Notify all waiters for GPU completion events that reset state has
2637 * been changed, and that they need to restart their wait after
2638 * checking for potential errors (and bail out to drop locks if there is
2639 * a gpu reset pending so that i915_error_work_func can acquire them).
2640 */
2641
2642 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2643 for_each_ring(ring, dev_priv, i)
2644 wake_up_all(&ring->irq_queue);
2645
2646 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2647 wake_up_all(&dev_priv->pending_flip_queue);
2648
2649 /*
2650 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2651 * reset state is cleared.
2652 */
2653 if (reset_completed)
2654 wake_up_all(&dev_priv->gpu_error.reset_queue);
2655}
2656
8a905236
JB		 2657/**
2658 * i915_error_work_func - do process context error handling work
2659 * @work: work struct
2660 *
2661 * Fire an error uevent so userspace can see that a hang or error
2662 * was detected.
2663 */
2664static void i915_error_work_func(struct work_struct *work)
2665{
1f83fee0
DV		 2666 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2667 work);
2d1013dd
JN		 2668 struct drm_i915_private *dev_priv =
2669 container_of(error, struct drm_i915_private, gpu_error);
8a905236 2670 struct drm_device *dev = dev_priv->dev;
cce723ed
BW		 2671 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2672 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2673 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 2674 int ret;
8a905236 2675
5bdebb18 2676 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
f316a42c 2677
7db0ba24
DV		 2678 /*
2679 * Note that there's only one work item which does gpu resets, so we
2680 * need not worry about concurrent gpu resets potentially incrementing
2681 * error->reset_counter twice. We only need to take care of another
2682 * racing irq/hangcheck declaring the gpu dead for a second time. A
2683 * quick check for that is good enough: schedule_work ensures the
2684 * correct ordering between hang detection and this work item, and since
2685 * the reset in-progress bit is only ever set by code outside of this
2686 * work we don't need to worry about any other races.
2687 */
2688 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 2689 DRM_DEBUG_DRIVER("resetting chip\n");
5bdebb18 2690 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
7db0ba24 2691 reset_event);
1f83fee0 2692
f454c694
ID		 2693 /*
2694 * In most cases it's guaranteed that we get here with an RPM
2695 * reference held, for example because there is a pending GPU
2696 * request that won't finish until the reset is done. This
2697 * isn't the case at least when we get here by doing a
2698 * simulated reset via debugs, so get an RPM reference.
2699 */
2700 intel_runtime_pm_get(dev_priv);
17e1df07
DV		 2701 /*
2702 * All state reset _must_ be completed before we update the
2703 * reset counter, for otherwise waiters might miss the reset
2704 * pending state and not properly drop locks, resulting in
2705 * deadlocks with the reset work.
2706 */
f69061be
DV		 2707 ret = i915_reset(dev);
2708
17e1df07
DV		 2709 intel_display_handle_reset(dev);
2710
f454c694
ID		 2711 intel_runtime_pm_put(dev_priv);
2712
f69061be
DV		 2713 if (ret == 0) {
2714 /*
2715 * After all the gem state is reset, increment the reset
2716 * counter and wake up everyone waiting for the reset to
2717 * complete.
2718 *
2719 * Since unlock operations are a one-sided barrier only,
2720 * we need to insert a barrier here to order any seqno
2721 * updates before
2722 * the counter increment.
2723 */
4e857c58 2724 smp_mb__before_atomic();
f69061be
DV		 2725 atomic_inc(&dev_priv->gpu_error.reset_counter);
2726
5bdebb18 2727 kobject_uevent_env(&dev->primary->kdev->kobj,
f69061be 2728 KOBJ_CHANGE, reset_done_event);
1f83fee0 2729 } else {
2ac0f450 2730 atomic_set_mask(I915_WEDGED, &error->reset_counter);
f316a42c 2731 }
1f83fee0 2732
17e1df07
DV		 2733 /*
2734 * Note: The wake_up also serves as a memory barrier so that
2735 * waiters see the update value of the reset counter atomic_t.
2736 */
2737 i915_error_wake_up(dev_priv, true);
f316a42c 2738 }
8a905236
JB		 2739}
2740
35aed2e6 2741static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2742{
2743 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2744 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2745 u32 eir = I915_READ(EIR);
050ee91f 2746 int pipe, i;
8a905236 2747
35aed2e6
CW		 2748 if (!eir)
2749 return;
8a905236 2750
a70491cc 2751 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2752
bd9854f9
BW		 2753 i915_get_extra_instdone(dev, instdone);
2754
8a905236
JB		 2755 if (IS_G4X(dev)) {
2756 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2757 u32 ipeir = I915_READ(IPEIR_I965);
2758
a70491cc
JP		 2759 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2760 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2761 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2762 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2763 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2764 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2765 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2766 POSTING_READ(IPEIR_I965);
8a905236
JB		 2767 }
2768 if (eir & GM45_ERROR_PAGE_TABLE) {
2769 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2770 pr_err("page table error\n");
2771 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2772 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2773 POSTING_READ(PGTBL_ER);
8a905236
JB		 2774 }
2775 }
2776
a6c45cf0 2777 if (!IS_GEN2(dev)) {
8a905236
JB		 2778 if (eir & I915_ERROR_PAGE_TABLE) {
2779 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2780 pr_err("page table error\n");
2781 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2782 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2783 POSTING_READ(PGTBL_ER);
8a905236
JB		 2784 }
2785 }
2786
2787 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2788 pr_err("memory refresh error:\n");
9db4a9c7 2789 for_each_pipe(pipe)
a70491cc 2790 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2791 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2792 /* pipestat has already been acked */
2793 }
2794 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2795 pr_err("instruction error\n");
2796 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2797 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2798 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2799 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2800 u32 ipeir = I915_READ(IPEIR);
2801
a70491cc
JP		 2802 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2803 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2804 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2805 I915_WRITE(IPEIR, ipeir);
3143a2bf 2806 POSTING_READ(IPEIR);
8a905236
JB		 2807 } else {
2808 u32 ipeir = I915_READ(IPEIR_I965);
2809
a70491cc
JP		 2810 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2811 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2812 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2813 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2814 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2815 POSTING_READ(IPEIR_I965);
8a905236
JB		 2816 }
2817 }
2818
2819 I915_WRITE(EIR, eir);
3143a2bf 2820 POSTING_READ(EIR);
8a905236
JB		 2821 eir = I915_READ(EIR);
2822 if (eir) {
2823 /*
2824 * some errors might have become stuck,
2825 * mask them.
2826 */
2827 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2828 I915_WRITE(EMR, I915_READ(EMR) | eir);
2829 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2830 }
35aed2e6
CW		 2831}
2832
2833/**
2834 * i915_handle_error - handle an error interrupt
2835 * @dev: drm device
2836 *
2837 * Do some basic checking of regsiter state at error interrupt time and
2838 * dump it to the syslog. Also call i915_capture_error_state() to make
2839 * sure we get a record and make it available in debugfs. Fire a uevent
2840 * so userspace knows something bad happened (should trigger collection
2841 * of a ring dump etc.).
2842 */
58174462
MK		 2843void i915_handle_error(struct drm_device *dev, bool wedged,
2844 const char *fmt, ...)
35aed2e6
CW		 2845{
2846 struct drm_i915_private *dev_priv = dev->dev_private;
58174462
MK		 2847 va_list args;
2848 char error_msg[80];
35aed2e6 2849
58174462
MK		 2850 va_start(args, fmt);
2851 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2852 va_end(args);
2853
2854 i915_capture_error_state(dev, wedged, error_msg);
35aed2e6 2855 i915_report_and_clear_eir(dev);
8a905236 2856
ba1234d1 2857 if (wedged) {
f69061be
DV		 2858 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2859 &dev_priv->gpu_error.reset_counter);
ba1234d1 2860
11ed50ec 2861 /*
17e1df07
DV		 2862 * Wakeup waiting processes so that the reset work function
2863 * i915_error_work_func doesn't deadlock trying to grab various
2864 * locks. By bumping the reset counter first, the woken
2865 * processes will see a reset in progress and back off,
2866 * releasing their locks and then wait for the reset completion.
2867 * We must do this for _all_ gpu waiters that might hold locks
2868 * that the reset work needs to acquire.
2869 *
2870 * Note: The wake_up serves as the required memory barrier to
2871 * ensure that the waiters see the updated value of the reset
2872 * counter atomic_t.
11ed50ec 2873 */
17e1df07 2874 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 2875 }
2876
122f46ba
DV		 2877 /*
2878 * Our reset work can grab modeset locks (since it needs to reset the
2879 * state of outstanding pagelips). Hence it must not be run on our own
2880 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2881 * code will deadlock.
2882 */
2883 schedule_work(&dev_priv->gpu_error.work);
8a905236
JB		 2884}
2885
21ad8330 2886static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd 2887{
2d1013dd 2888 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd
SF		 2889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2891 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2892 struct intel_unpin_work *work;
2893 unsigned long flags;
2894 bool stall_detected;
2895
2896 /* Ignore early vblank irqs */
2897 if (intel_crtc == NULL)
2898 return;
2899
2900 spin_lock_irqsave(&dev->event_lock, flags);
2901 work = intel_crtc->unpin_work;
2902
e7d841ca
CW		 2903 if (work == NULL ||
2904 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2905 !work->enable_stall_check) {
4e5359cd
SF		 2906 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2907 spin_unlock_irqrestore(&dev->event_lock, flags);
2908 return;
2909 }
2910
2911 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2912 obj = work->pending_flip_obj;
a6c45cf0 2913 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2914 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 2915 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 2916 i915_gem_obj_ggtt_offset(obj);
4e5359cd 2917 } else {
9db4a9c7 2918 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 2919 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
f4510a27
MR		 2920 crtc->y * crtc->primary->fb->pitches[0] +
2921 crtc->x * crtc->primary->fb->bits_per_pixel/8);
4e5359cd
SF		 2922 }
2923
2924 spin_unlock_irqrestore(&dev->event_lock, flags);
2925
2926 if (stall_detected) {
2927 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2928 intel_prepare_page_flip(dev, intel_crtc->plane);
2929 }
2930}
2931
42f52ef8
KP		 2932/* Called from drm generic code, passed 'crtc' which
2933 * we use as a pipe index
2934 */
f71d4af4 2935static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2936{
2d1013dd 2937 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2938 unsigned long irqflags;
71e0ffa5 2939
5eddb70b 2940 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2941 return -EINVAL;
0a3e67a4 2942
1ec14ad3 2943 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2944 if (INTEL_INFO(dev)->gen >= 4)
7c463586 2945 i915_enable_pipestat(dev_priv, pipe,
755e9019 2946 PIPE_START_VBLANK_INTERRUPT_STATUS);
e9d21d7f 2947 else
7c463586 2948 i915_enable_pipestat(dev_priv, pipe,
755e9019 2949 PIPE_VBLANK_INTERRUPT_STATUS);
1ec14ad3 2950 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2951
0a3e67a4
JB		 2952 return 0;
2953}
2954
f71d4af4 2955static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2956{
2d1013dd 2957 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2958 unsigned long irqflags;
b518421f 2959 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2960 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2961
2962 if (!i915_pipe_enabled(dev, pipe))
2963 return -EINVAL;
2964
2965 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2966 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2967 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2968
2969 return 0;
2970}
2971
7e231dbe
JB		 2972static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2973{
2d1013dd 2974 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2975 unsigned long irqflags;
7e231dbe
JB		 2976
2977 if (!i915_pipe_enabled(dev, pipe))
2978 return -EINVAL;
2979
2980 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2981 i915_enable_pipestat(dev_priv, pipe,
755e9019 2982 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2983 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2984
2985 return 0;
2986}
2987
abd58f01
BW		 2988static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2989{
2990 struct drm_i915_private *dev_priv = dev->dev_private;
2991 unsigned long irqflags;
abd58f01
BW		 2992
2993 if (!i915_pipe_enabled(dev, pipe))
2994 return -EINVAL;
2995
2996 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2997 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2998 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2999 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 3000 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3001 return 0;
3002}
3003
42f52ef8
KP		 3004/* Called from drm generic code, passed 'crtc' which
3005 * we use as a pipe index
3006 */
f71d4af4 3007static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 3008{
2d1013dd 3009 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 3010 unsigned long irqflags;
0a3e67a4 3011
1ec14ad3 3012 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 3013 i915_disable_pipestat(dev_priv, pipe,
755e9019
ID		 3014 PIPE_VBLANK_INTERRUPT_STATUS |
3015 PIPE_START_VBLANK_INTERRUPT_STATUS);
f796cf8f
JB		 3016 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3017}
3018
f71d4af4 3019static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f 3020{
2d1013dd 3021 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 3022 unsigned long irqflags;
b518421f 3023 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 3024 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 3025
3026 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 3027 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 3028 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3029}
3030
7e231dbe
JB		 3031static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
3032{
2d1013dd 3033 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 3034 unsigned long irqflags;
7e231dbe
JB		 3035
3036 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 3037 i915_disable_pipestat(dev_priv, pipe,
755e9019 3038 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 3039 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3040}
3041
abd58f01
BW		 3042static void gen8_disable_vblank(struct drm_device *dev, int pipe)
3043{
3044 struct drm_i915_private *dev_priv = dev->dev_private;
3045 unsigned long irqflags;
abd58f01
BW		 3046
3047 if (!i915_pipe_enabled(dev, pipe))
3048 return;
3049
3050 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 3051 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
3052 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
3053 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 3054 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3055}
3056
893eead0 3057static u32
a4872ba6 3058ring_last_seqno(struct intel_engine_cs *ring)
852835f3 3059{
893eead0
CW		 3060 return list_entry(ring->request_list.prev,
3061 struct drm_i915_gem_request, list)->seqno;
3062}
3063
9107e9d2 3064static bool
a4872ba6 3065ring_idle(struct intel_engine_cs *ring, u32 seqno)
9107e9d2
CW		 3066{
3067 return (list_empty(&ring->request_list) ||
3068 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 3069}
3070
a028c4b0
DV		 3071static bool
3072ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
3073{
3074 if (INTEL_INFO(dev)->gen >= 8) {
a6cdb93a 3075 return (ipehr >> 23) == 0x1c;
a028c4b0
DV		 3076 } else {
3077 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
3078 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
3079 MI_SEMAPHORE_REGISTER);
3080 }
3081}
3082
a4872ba6 3083static struct intel_engine_cs *
a6cdb93a 3084semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
921d42ea
DV		 3085{
3086 struct drm_i915_private *dev_priv = ring->dev->dev_private;
a4872ba6 3087 struct intel_engine_cs *signaller;
921d42ea
DV		 3088 int i;
3089
3090 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
a6cdb93a
RV		 3091 for_each_ring(signaller, dev_priv, i) {
3092 if (ring == signaller)
3093 continue;
3094
3095 if (offset == signaller->semaphore.signal_ggtt[ring->id])
3096 return signaller;
3097 }
921d42ea
DV		 3098 } else {
3099 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
3100
3101 for_each_ring(signaller, dev_priv, i) {
3102 if(ring == signaller)
3103 continue;
3104
ebc348b2 3105 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
921d42ea
DV		 3106 return signaller;
3107 }
3108 }
3109
a6cdb93a
RV		 3110 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
3111 ring->id, ipehr, offset);
921d42ea
DV		 3112
3113 return NULL;
3114}
3115
a4872ba6
OM		 3116static struct intel_engine_cs *
3117semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
a24a11e6
CW		 3118{
3119 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88fe429d 3120 u32 cmd, ipehr, head;
a6cdb93a
RV		 3121 u64 offset = 0;
3122 int i, backwards;
a24a11e6
CW		 3123
3124 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
a028c4b0 3125 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
6274f212 3126 return NULL;
a24a11e6 3127
88fe429d
DV		 3128 /*
3129 * HEAD is likely pointing to the dword after the actual command,
3130 * so scan backwards until we find the MBOX. But limit it to just 3
a6cdb93a
RV		 3131 * or 4 dwords depending on the semaphore wait command size.
3132 * Note that we don't care about ACTHD here since that might
88fe429d
DV		 3133 * point at at batch, and semaphores are always emitted into the
3134 * ringbuffer itself.
a24a11e6 3135 */
88fe429d 3136 head = I915_READ_HEAD(ring) & HEAD_ADDR;
a6cdb93a 3137 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
88fe429d 3138
a6cdb93a 3139 for (i = backwards; i; --i) {
88fe429d
DV		 3140 /*
3141 * Be paranoid and presume the hw has gone off into the wild -
3142 * our ring is smaller than what the hardware (and hence
3143 * HEAD_ADDR) allows. Also handles wrap-around.
3144 */
ee1b1e5e 3145 head &= ring->buffer->size - 1;
88fe429d
DV		 3146
3147 /* This here seems to blow up */
ee1b1e5e 3148 cmd = ioread32(ring->buffer->virtual_start + head);
a24a11e6
CW		 3149 if (cmd == ipehr)
3150 break;
3151
88fe429d
DV		 3152 head -= 4;
3153 }
a24a11e6 3154
88fe429d
DV		 3155 if (!i)
3156 return NULL;
a24a11e6 3157
ee1b1e5e 3158 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
a6cdb93a
RV		 3159 if (INTEL_INFO(ring->dev)->gen >= 8) {
3160 offset = ioread32(ring->buffer->virtual_start + head + 12);
3161 offset <<= 32;
3162 offset = ioread32(ring->buffer->virtual_start + head + 8);
3163 }
3164 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
a24a11e6
CW		 3165}
3166
a4872ba6 3167static int semaphore_passed(struct intel_engine_cs *ring)
6274f212
CW		 3168{
3169 struct drm_i915_private *dev_priv = ring->dev->dev_private;
a4872ba6 3170 struct intel_engine_cs *signaller;
a0d036b0 3171 u32 seqno;
6274f212 3172
4be17381 3173 ring->hangcheck.deadlock++;
6274f212
CW		 3174
3175 signaller = semaphore_waits_for(ring, &seqno);
4be17381
CW		 3176 if (signaller == NULL)
3177 return -1;
3178
3179 /* Prevent pathological recursion due to driver bugs */
3180 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
6274f212
CW		 3181 return -1;
3182
4be17381
CW		 3183 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
3184 return 1;
3185
a0d036b0
CW		 3186 /* cursory check for an unkickable deadlock */
3187 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
3188 semaphore_passed(signaller) < 0)
4be17381
CW		 3189 return -1;
3190
3191 return 0;
6274f212
CW		 3192}
3193
3194static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
3195{
a4872ba6 3196 struct intel_engine_cs *ring;
6274f212
CW		 3197 int i;
3198
3199 for_each_ring(ring, dev_priv, i)
4be17381 3200 ring->hangcheck.deadlock = 0;
6274f212
CW		 3201}
3202
ad8beaea 3203static enum intel_ring_hangcheck_action
a4872ba6 3204ring_stuck(struct intel_engine_cs *ring, u64 acthd)
1ec14ad3
CW		 3205{
3206 struct drm_device *dev = ring->dev;
3207 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 3208 u32 tmp;
3209
f260fe7b
MK		 3210 if (acthd != ring->hangcheck.acthd) {
3211 if (acthd > ring->hangcheck.max_acthd) {
3212 ring->hangcheck.max_acthd = acthd;
3213 return HANGCHECK_ACTIVE;
3214 }
3215
3216 return HANGCHECK_ACTIVE_LOOP;
3217 }
6274f212 3218
9107e9d2 3219 if (IS_GEN2(dev))
f2f4d82f 3220 return HANGCHECK_HUNG;
9107e9d2
CW		 3221
3222 /* Is the chip hanging on a WAIT_FOR_EVENT?
3223 * If so we can simply poke the RB_WAIT bit
3224 * and break the hang. This should work on
3225 * all but the second generation chipsets.
3226 */
3227 tmp = I915_READ_CTL(ring);
1ec14ad3 3228 if (tmp & RING_WAIT) {
58174462
MK		 3229 i915_handle_error(dev, false,
3230 "Kicking stuck wait on %s",
3231 ring->name);
1ec14ad3 3232 I915_WRITE_CTL(ring, tmp);
f2f4d82f 3233 return HANGCHECK_KICK;
6274f212
CW		 3234 }
3235
3236 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3237 switch (semaphore_passed(ring)) {
3238 default:
f2f4d82f 3239 return HANGCHECK_HUNG;
6274f212 3240 case 1:
58174462
MK		 3241 i915_handle_error(dev, false,
3242 "Kicking stuck semaphore on %s",
3243 ring->name);
6274f212 3244 I915_WRITE_CTL(ring, tmp);
f2f4d82f 3245 return HANGCHECK_KICK;
6274f212 3246 case 0:
f2f4d82f 3247 return HANGCHECK_WAIT;
6274f212 3248 }
9107e9d2 3249 }
ed5cbb03 3250
f2f4d82f 3251 return HANGCHECK_HUNG;
ed5cbb03
MK		 3252}
3253
f65d9421
BG		 3254/**
3255 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 3256 * batchbuffers in a long time. We keep track per ring seqno progress and
3257 * if there are no progress, hangcheck score for that ring is increased.
3258 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3259 * we kick the ring. If we see no progress on three subsequent calls
3260 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 3261 */
a658b5d2 3262static void i915_hangcheck_elapsed(unsigned long data)
f65d9421
BG		 3263{
3264 struct drm_device *dev = (struct drm_device *)data;
2d1013dd 3265 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3266 struct intel_engine_cs *ring;
b4519513 3267 int i;
05407ff8 3268 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 3269 bool stuck[I915_NUM_RINGS] = { 0 };
3270#define BUSY 1
3271#define KICK 5
3272#define HUNG 20
893eead0 3273
d330a953 3274 if (!i915.enable_hangcheck)
3e0dc6b0
BW		 3275 return;
3276
b4519513 3277 for_each_ring(ring, dev_priv, i) {
50877445
CW		 3278 u64 acthd;
3279 u32 seqno;
9107e9d2 3280 bool busy = true;
05407ff8 3281
6274f212
CW		 3282 semaphore_clear_deadlocks(dev_priv);
3283
05407ff8
MK		 3284 seqno = ring->get_seqno(ring, false);
3285 acthd = intel_ring_get_active_head(ring);
b4519513 3286
9107e9d2
CW		 3287 if (ring->hangcheck.seqno == seqno) {
3288 if (ring_idle(ring, seqno)) {
da661464
MK		 3289 ring->hangcheck.action = HANGCHECK_IDLE;
3290
9107e9d2
CW		 3291 if (waitqueue_active(&ring->irq_queue)) {
3292 /* Issue a wake-up to catch stuck h/w. */
094f9a54 3293 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
f4adcd24
DV		 3294 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
3295 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3296 ring->name);
3297 else
3298 DRM_INFO("Fake missed irq on %s\n",
3299 ring->name);
094f9a54
CW		 3300 wake_up_all(&ring->irq_queue);
3301 }
3302 /* Safeguard against driver failure */
3303 ring->hangcheck.score += BUSY;
9107e9d2
CW		 3304 } else
3305 busy = false;
05407ff8 3306 } else {
6274f212
CW		 3307 /* We always increment the hangcheck score
3308 * if the ring is busy and still processing
3309 * the same request, so that no single request
3310 * can run indefinitely (such as a chain of
3311 * batches). The only time we do not increment
3312 * the hangcheck score on this ring, if this
3313 * ring is in a legitimate wait for another
3314 * ring. In that case the waiting ring is a
3315 * victim and we want to be sure we catch the
3316 * right culprit. Then every time we do kick
3317 * the ring, add a small increment to the
3318 * score so that we can catch a batch that is
3319 * being repeatedly kicked and so responsible
3320 * for stalling the machine.
3321 */
ad8beaea
MK		 3322 ring->hangcheck.action = ring_stuck(ring,
3323 acthd);
3324
3325 switch (ring->hangcheck.action) {
da661464 3326 case HANGCHECK_IDLE:
f2f4d82f 3327 case HANGCHECK_WAIT:
f2f4d82f 3328 case HANGCHECK_ACTIVE:
f260fe7b
MK		 3329 break;
3330 case HANGCHECK_ACTIVE_LOOP:
ea04cb31 3331 ring->hangcheck.score += BUSY;
6274f212 3332 break;
f2f4d82f 3333 case HANGCHECK_KICK:
ea04cb31 3334 ring->hangcheck.score += KICK;
6274f212 3335 break;
f2f4d82f 3336 case HANGCHECK_HUNG:
ea04cb31 3337 ring->hangcheck.score += HUNG;
6274f212
CW		 3338 stuck[i] = true;
3339 break;
3340 }
05407ff8 3341 }
9107e9d2 3342 } else {
da661464
MK		 3343 ring->hangcheck.action = HANGCHECK_ACTIVE;
3344
9107e9d2
CW		 3345 /* Gradually reduce the count so that we catch DoS
3346 * attempts across multiple batches.
3347 */
3348 if (ring->hangcheck.score > 0)
3349 ring->hangcheck.score--;
f260fe7b
MK		 3350
3351 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
d1e61e7f
CW		 3352 }
3353
05407ff8
MK		 3354 ring->hangcheck.seqno = seqno;
3355 ring->hangcheck.acthd = acthd;
9107e9d2 3356 busy_count += busy;
893eead0 3357 }
b9201c14 3358
92cab734 3359 for_each_ring(ring, dev_priv, i) {
b6b0fac0 3360 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
b8d88d1d
DV		 3361 DRM_INFO("%s on %s\n",
3362 stuck[i] ? "stuck" : "no progress",
3363 ring->name);
a43adf07 3364 rings_hung++;
92cab734
MK		 3365 }
3366 }
3367
05407ff8 3368 if (rings_hung)
58174462 3369 return i915_handle_error(dev, true, "Ring hung");
f65d9421 3370
05407ff8
MK		 3371 if (busy_count)
3372 /* Reset timer case chip hangs without another request
3373 * being added */
10cd45b6
MK		 3374 i915_queue_hangcheck(dev);
3375}
3376
3377void i915_queue_hangcheck(struct drm_device *dev)
3378{
3379 struct drm_i915_private *dev_priv = dev->dev_private;
d330a953 3380 if (!i915.enable_hangcheck)
10cd45b6
MK		 3381 return;
3382
3383 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
3384 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 3385}
3386
1c69eb42 3387static void ibx_irq_reset(struct drm_device *dev)
91738a95
PZ		 3388{
3389 struct drm_i915_private *dev_priv = dev->dev_private;
3390
3391 if (HAS_PCH_NOP(dev))
3392 return;
3393
f86f3fb0 3394 GEN5_IRQ_RESET(SDE);
105b122e
PZ		 3395
3396 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3397 I915_WRITE(SERR_INT, 0xffffffff);
622364b6 3398}
105b122e 3399
622364b6
PZ		 3400/*
3401 * SDEIER is also touched by the interrupt handler to work around missed PCH
3402 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3403 * instead we unconditionally enable all PCH interrupt sources here, but then
3404 * only unmask them as needed with SDEIMR.
3405 *
3406 * This function needs to be called before interrupts are enabled.
3407 */
3408static void ibx_irq_pre_postinstall(struct drm_device *dev)
3409{
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3411
3412 if (HAS_PCH_NOP(dev))
3413 return;
3414
3415 WARN_ON(I915_READ(SDEIER) != 0);
91738a95
PZ		 3416 I915_WRITE(SDEIER, 0xffffffff);
3417 POSTING_READ(SDEIER);
3418}
3419
7c4d664e 3420static void gen5_gt_irq_reset(struct drm_device *dev)
d18ea1b5
DV		 3421{
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423
f86f3fb0 3424 GEN5_IRQ_RESET(GT);
a9d356a6 3425 if (INTEL_INFO(dev)->gen >= 6)
f86f3fb0 3426 GEN5_IRQ_RESET(GEN6_PM);
d18ea1b5
DV		 3427}
3428
1da177e4
LT		 3429/* drm_dma.h hooks
3430*/
be30b29f 3431static void ironlake_irq_reset(struct drm_device *dev)
036a4a7d 3432{
2d1013dd 3433 struct drm_i915_private *dev_priv = dev->dev_private;
036a4a7d 3434
0c841212 3435 I915_WRITE(HWSTAM, 0xffffffff);
bdfcdb63 3436
f86f3fb0 3437 GEN5_IRQ_RESET(DE);
c6d954c1
PZ		 3438 if (IS_GEN7(dev))
3439 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
036a4a7d 3440
7c4d664e 3441 gen5_gt_irq_reset(dev);
c650156a 3442
1c69eb42 3443 ibx_irq_reset(dev);
7d99163d 3444}
c650156a 3445
7e231dbe
JB		 3446static void valleyview_irq_preinstall(struct drm_device *dev)
3447{
2d1013dd 3448 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 3449 int pipe;
3450
7e231dbe
JB		 3451 /* VLV magic */
3452 I915_WRITE(VLV_IMR, 0);
3453 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3454 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3455 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3456
7e231dbe
JB		 3457 /* and GT */
3458 I915_WRITE(GTIIR, I915_READ(GTIIR));
3459 I915_WRITE(GTIIR, I915_READ(GTIIR));
d18ea1b5 3460
7c4d664e 3461 gen5_gt_irq_reset(dev);
7e231dbe
JB		 3462
3463 I915_WRITE(DPINVGTT, 0xff);
3464
3465 I915_WRITE(PORT_HOTPLUG_EN, 0);
3466 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3467 for_each_pipe(pipe)
3468 I915_WRITE(PIPESTAT(pipe), 0xffff);
3469 I915_WRITE(VLV_IIR, 0xffffffff);
3470 I915_WRITE(VLV_IMR, 0xffffffff);
3471 I915_WRITE(VLV_IER, 0x0);
3472 POSTING_READ(VLV_IER);
3473}
3474
d6e3cca3
DV		 3475static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3476{
3477 GEN8_IRQ_RESET_NDX(GT, 0);
3478 GEN8_IRQ_RESET_NDX(GT, 1);
3479 GEN8_IRQ_RESET_NDX(GT, 2);
3480 GEN8_IRQ_RESET_NDX(GT, 3);
3481}
3482
823f6b38 3483static void gen8_irq_reset(struct drm_device *dev)
abd58f01
BW		 3484{
3485 struct drm_i915_private *dev_priv = dev->dev_private;
3486 int pipe;
3487
abd58f01
BW		 3488 I915_WRITE(GEN8_MASTER_IRQ, 0);
3489 POSTING_READ(GEN8_MASTER_IRQ);
3490
d6e3cca3 3491 gen8_gt_irq_reset(dev_priv);
abd58f01 3492
823f6b38 3493 for_each_pipe(pipe)
813bde43
PZ		 3494 if (intel_display_power_enabled(dev_priv,
3495 POWER_DOMAIN_PIPE(pipe)))
3496 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
abd58f01 3497
f86f3fb0
PZ		 3498 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3499 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3500 GEN5_IRQ_RESET(GEN8_PCU_);
abd58f01 3501
1c69eb42 3502 ibx_irq_reset(dev);
abd58f01 3503}
09f2344d 3504
d49bdb0e
PZ		 3505void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3506{
3507 unsigned long irqflags;
3508
3509 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3510 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3511 ~dev_priv->de_irq_mask[PIPE_B]);
3512 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3513 ~dev_priv->de_irq_mask[PIPE_C]);
3514 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3515}
3516
43f328d7
VS		 3517static void cherryview_irq_preinstall(struct drm_device *dev)
3518{
3519 struct drm_i915_private *dev_priv = dev->dev_private;
3520 int pipe;
3521
3522 I915_WRITE(GEN8_MASTER_IRQ, 0);
3523 POSTING_READ(GEN8_MASTER_IRQ);
3524
d6e3cca3 3525 gen8_gt_irq_reset(dev_priv);
43f328d7
VS		 3526
3527 GEN5_IRQ_RESET(GEN8_PCU_);
3528
3529 POSTING_READ(GEN8_PCU_IIR);
3530
3531 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3532
3533 I915_WRITE(PORT_HOTPLUG_EN, 0);
3534 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3535
3536 for_each_pipe(pipe)
3537 I915_WRITE(PIPESTAT(pipe), 0xffff);
3538
3539 I915_WRITE(VLV_IMR, 0xffffffff);
3540 I915_WRITE(VLV_IER, 0x0);
3541 I915_WRITE(VLV_IIR, 0xffffffff);
3542 POSTING_READ(VLV_IIR);
3543}
3544
82a28bcf 3545static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973 3546{
2d1013dd 3547 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 3548 struct intel_encoder *intel_encoder;
fee884ed 3549 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 3550
3551 if (HAS_PCH_IBX(dev)) {
fee884ed 3552 hotplug_irqs = SDE_HOTPLUG_MASK;
b2784e15 3553 for_each_intel_encoder(dev, intel_encoder)
cd569aed 3554 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 3555 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 3556 } else {
fee884ed 3557 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
b2784e15 3558 for_each_intel_encoder(dev, intel_encoder)
cd569aed 3559 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 3560 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 3561 }
7fe0b973 3562
fee884ed 3563 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 3564
3565 /*
3566 * Enable digital hotplug on the PCH, and configure the DP short pulse
3567 * duration to 2ms (which is the minimum in the Display Port spec)
3568 *
3569 * This register is the same on all known PCH chips.
3570 */
7fe0b973
KP		 3571 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3572 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3573 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3574 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3575 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3576 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3577}
3578
d46da437
PZ		 3579static void ibx_irq_postinstall(struct drm_device *dev)
3580{
2d1013dd 3581 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 3582 u32 mask;
e5868a31 3583
692a04cf
DV		 3584 if (HAS_PCH_NOP(dev))
3585 return;
3586
105b122e 3587 if (HAS_PCH_IBX(dev))
5c673b60 3588 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
105b122e 3589 else
5c673b60 3590 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
8664281b 3591
337ba017 3592 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
d46da437 3593 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 3594}
3595
0a9a8c91
DV		 3596static void gen5_gt_irq_postinstall(struct drm_device *dev)
3597{
3598 struct drm_i915_private *dev_priv = dev->dev_private;
3599 u32 pm_irqs, gt_irqs;
3600
3601 pm_irqs = gt_irqs = 0;
3602
3603 dev_priv->gt_irq_mask = ~0;
040d2baa 3604 if (HAS_L3_DPF(dev)) {
0a9a8c91 3605 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 3606 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3607 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 3608 }
3609
3610 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3611 if (IS_GEN5(dev)) {
3612 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3613 ILK_BSD_USER_INTERRUPT;
3614 } else {
3615 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3616 }
3617
35079899 3618 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
0a9a8c91
DV		 3619
3620 if (INTEL_INFO(dev)->gen >= 6) {
a6706b45 3621 pm_irqs |= dev_priv->pm_rps_events;
0a9a8c91
DV		 3622
3623 if (HAS_VEBOX(dev))
3624 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3625
605cd25b 3626 dev_priv->pm_irq_mask = 0xffffffff;
35079899 3627 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
0a9a8c91
DV		 3628 }
3629}
3630
f71d4af4 3631static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 3632{
4bc9d430 3633 unsigned long irqflags;
2d1013dd 3634 struct drm_i915_private *dev_priv = dev->dev_private;
8e76f8dc
PZ		 3635 u32 display_mask, extra_mask;
3636
3637 if (INTEL_INFO(dev)->gen >= 7) {
3638 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3639 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3640 DE_PLANEB_FLIP_DONE_IVB |
5c673b60 3641 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
8e76f8dc 3642 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
5c673b60 3643 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
8e76f8dc
PZ		 3644 } else {
3645 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3646 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
5b3a856b 3647 DE_AUX_CHANNEL_A |
5b3a856b
DV		 3648 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3649 DE_POISON);
5c673b60
DV		 3650 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3651 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
8e76f8dc 3652 }
036a4a7d 3653
1ec14ad3 3654 dev_priv->irq_mask = ~display_mask;
036a4a7d 3655
0c841212
PZ		 3656 I915_WRITE(HWSTAM, 0xeffe);
3657
622364b6
PZ		 3658 ibx_irq_pre_postinstall(dev);
3659
35079899 3660 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
036a4a7d 3661
0a9a8c91 3662 gen5_gt_irq_postinstall(dev);
036a4a7d 3663
d46da437 3664 ibx_irq_postinstall(dev);
7fe0b973 3665
f97108d1 3666 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 3667 /* Enable PCU event interrupts
3668 *
3669 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 3670 * setup is guaranteed to run in single-threaded context. But we
3671 * need it to make the assert_spin_locked happy. */
3672 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 3673 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 3674 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 3675 }
3676
036a4a7d
ZW		 3677 return 0;
3678}
3679
f8b79e58
ID		 3680static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3681{
3682 u32 pipestat_mask;
3683 u32 iir_mask;
3684
3685 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3686 PIPE_FIFO_UNDERRUN_STATUS;
3687
3688 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3689 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3690 POSTING_READ(PIPESTAT(PIPE_A));
3691
3692 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3693 PIPE_CRC_DONE_INTERRUPT_STATUS;
3694
3695 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3696 PIPE_GMBUS_INTERRUPT_STATUS);
3697 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3698
3699 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3700 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3701 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3702 dev_priv->irq_mask &= ~iir_mask;
3703
3704 I915_WRITE(VLV_IIR, iir_mask);
3705 I915_WRITE(VLV_IIR, iir_mask);
3706 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3707 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3708 POSTING_READ(VLV_IER);
3709}
3710
3711static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3712{
3713 u32 pipestat_mask;
3714 u32 iir_mask;
3715
3716 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3717 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
6c7fba04 3718 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
f8b79e58
ID		 3719
3720 dev_priv->irq_mask |= iir_mask;
3721 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3722 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3723 I915_WRITE(VLV_IIR, iir_mask);
3724 I915_WRITE(VLV_IIR, iir_mask);
3725 POSTING_READ(VLV_IIR);
3726
3727 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3728 PIPE_CRC_DONE_INTERRUPT_STATUS;
3729
3730 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3731 PIPE_GMBUS_INTERRUPT_STATUS);
3732 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3733
3734 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3735 PIPE_FIFO_UNDERRUN_STATUS;
3736 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3737 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3738 POSTING_READ(PIPESTAT(PIPE_A));
3739}
3740
3741void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3742{
3743 assert_spin_locked(&dev_priv->irq_lock);
3744
3745 if (dev_priv->display_irqs_enabled)
3746 return;
3747
3748 dev_priv->display_irqs_enabled = true;
3749
3750 if (dev_priv->dev->irq_enabled)
3751 valleyview_display_irqs_install(dev_priv);
3752}
3753
3754void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3755{
3756 assert_spin_locked(&dev_priv->irq_lock);
3757
3758 if (!dev_priv->display_irqs_enabled)
3759 return;
3760
3761 dev_priv->display_irqs_enabled = false;
3762
3763 if (dev_priv->dev->irq_enabled)
3764 valleyview_display_irqs_uninstall(dev_priv);
3765}
3766
7e231dbe
JB		 3767static int valleyview_irq_postinstall(struct drm_device *dev)
3768{
2d1013dd 3769 struct drm_i915_private *dev_priv = dev->dev_private;
b79480ba 3770 unsigned long irqflags;
7e231dbe 3771
f8b79e58 3772 dev_priv->irq_mask = ~0;
7e231dbe 3773
20afbda2
DV		 3774 I915_WRITE(PORT_HOTPLUG_EN, 0);
3775 POSTING_READ(PORT_HOTPLUG_EN);
3776
7e231dbe 3777 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
f8b79e58 3778 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
7e231dbe 3779 I915_WRITE(VLV_IIR, 0xffffffff);
7e231dbe
JB		 3780 POSTING_READ(VLV_IER);
3781
b79480ba
DV		 3782 /* Interrupt setup is already guaranteed to be single-threaded, this is
3783 * just to make the assert_spin_locked check happy. */
3784 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f8b79e58
ID		 3785 if (dev_priv->display_irqs_enabled)
3786 valleyview_display_irqs_install(dev_priv);
b79480ba 3787 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 3788
7e231dbe
JB		 3789 I915_WRITE(VLV_IIR, 0xffffffff);
3790 I915_WRITE(VLV_IIR, 0xffffffff);
3791
0a9a8c91 3792 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 3793
3794 /* ack & enable invalid PTE error interrupts */
3795#if 0 /* FIXME: add support to irq handler for checking these bits */
3796 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3797 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3798#endif
3799
3800 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 3801
3802 return 0;
3803}
3804
abd58f01
BW		 3805static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3806{
3807 int i;
3808
3809 /* These are interrupts we'll toggle with the ring mask register */
3810 uint32_t gt_interrupts[] = {
3811 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
73d477f6 3812 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
abd58f01 3813 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
73d477f6
OM		 3814 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3815 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
abd58f01 3816 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
73d477f6
OM		 3817 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3818 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3819 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
abd58f01 3820 0,
73d477f6
OM		 3821 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3822 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
abd58f01
BW		 3823 };
3824
337ba017 3825 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
35079899 3826 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
0961021a
BW		 3827
3828 dev_priv->pm_irq_mask = 0xffffffff;
abd58f01
BW		 3829}
3830
3831static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3832{
3833 struct drm_device *dev = dev_priv->dev;
d0e1f1cb 3834 uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE |
13b3a0a7 3835 GEN8_PIPE_CDCLK_CRC_DONE |
13b3a0a7 3836 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
5c673b60
DV		 3837 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3838 GEN8_PIPE_FIFO_UNDERRUN;
abd58f01 3839 int pipe;
13b3a0a7
DV		 3840 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3841 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3842 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
abd58f01 3843
337ba017 3844 for_each_pipe(pipe)
813bde43
PZ		 3845 if (intel_display_power_enabled(dev_priv,
3846 POWER_DOMAIN_PIPE(pipe)))
3847 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3848 dev_priv->de_irq_mask[pipe],
3849 de_pipe_enables);
abd58f01 3850
35079899 3851 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
abd58f01
BW		 3852}
3853
3854static int gen8_irq_postinstall(struct drm_device *dev)
3855{
3856 struct drm_i915_private *dev_priv = dev->dev_private;
3857
622364b6
PZ		 3858 ibx_irq_pre_postinstall(dev);
3859
abd58f01
BW		 3860 gen8_gt_irq_postinstall(dev_priv);
3861 gen8_de_irq_postinstall(dev_priv);
3862
3863 ibx_irq_postinstall(dev);
3864
3865 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3866 POSTING_READ(GEN8_MASTER_IRQ);
3867
3868 return 0;
3869}
3870
43f328d7
VS		 3871static int cherryview_irq_postinstall(struct drm_device *dev)
3872{
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3875 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
43f328d7 3876 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3278f67f
VS		 3877 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3878 u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3879 PIPE_CRC_DONE_INTERRUPT_STATUS;
43f328d7
VS		 3880 unsigned long irqflags;
3881 int pipe;
3882
3883 /*
3884 * Leave vblank interrupts masked initially. enable/disable will
3885 * toggle them based on usage.
3886 */
3278f67f 3887 dev_priv->irq_mask = ~enable_mask;
43f328d7
VS		 3888
3889 for_each_pipe(pipe)
3890 I915_WRITE(PIPESTAT(pipe), 0xffff);
3891
3892 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3278f67f 3893 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
43f328d7
VS		 3894 for_each_pipe(pipe)
3895 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3896 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3897
3898 I915_WRITE(VLV_IIR, 0xffffffff);
3899 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3900 I915_WRITE(VLV_IER, enable_mask);
3901
3902 gen8_gt_irq_postinstall(dev_priv);
3903
3904 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3905 POSTING_READ(GEN8_MASTER_IRQ);
3906
3907 return 0;
3908}
3909
abd58f01
BW		 3910static void gen8_irq_uninstall(struct drm_device *dev)
3911{
3912 struct drm_i915_private *dev_priv = dev->dev_private;
abd58f01
BW		 3913
3914 if (!dev_priv)
3915 return;
3916
d4eb6b10 3917 intel_hpd_irq_uninstall(dev_priv);
abd58f01 3918
823f6b38 3919 gen8_irq_reset(dev);
abd58f01
BW		 3920}
3921
7e231dbe
JB		 3922static void valleyview_irq_uninstall(struct drm_device *dev)
3923{
2d1013dd 3924 struct drm_i915_private *dev_priv = dev->dev_private;
f8b79e58 3925 unsigned long irqflags;
7e231dbe
JB		 3926 int pipe;
3927
3928 if (!dev_priv)
3929 return;
3930
843d0e7d
ID		 3931 I915_WRITE(VLV_MASTER_IER, 0);
3932
3ca1cced 3933 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3934
7e231dbe
JB		 3935 for_each_pipe(pipe)
3936 I915_WRITE(PIPESTAT(pipe), 0xffff);
3937
3938 I915_WRITE(HWSTAM, 0xffffffff);
3939 I915_WRITE(PORT_HOTPLUG_EN, 0);
3940 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
f8b79e58
ID		 3941
3942 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3943 if (dev_priv->display_irqs_enabled)
3944 valleyview_display_irqs_uninstall(dev_priv);
3945 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3946
3947 dev_priv->irq_mask = 0;
3948
7e231dbe
JB		 3949 I915_WRITE(VLV_IIR, 0xffffffff);
3950 I915_WRITE(VLV_IMR, 0xffffffff);
3951 I915_WRITE(VLV_IER, 0x0);
3952 POSTING_READ(VLV_IER);
3953}
3954
43f328d7
VS		 3955static void cherryview_irq_uninstall(struct drm_device *dev)
3956{
3957 struct drm_i915_private *dev_priv = dev->dev_private;
3958 int pipe;
3959
3960 if (!dev_priv)
3961 return;
3962
3963 I915_WRITE(GEN8_MASTER_IRQ, 0);
3964 POSTING_READ(GEN8_MASTER_IRQ);
3965
3966#define GEN8_IRQ_FINI_NDX(type, which) \
3967do { \
3968 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3969 I915_WRITE(GEN8_##type##_IER(which), 0); \
3970 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3971 POSTING_READ(GEN8_##type##_IIR(which)); \
3972 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3973} while (0)
3974
3975#define GEN8_IRQ_FINI(type) \
3976do { \
3977 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3978 I915_WRITE(GEN8_##type##_IER, 0); \
3979 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3980 POSTING_READ(GEN8_##type##_IIR); \
3981 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3982} while (0)
3983
3984 GEN8_IRQ_FINI_NDX(GT, 0);
3985 GEN8_IRQ_FINI_NDX(GT, 1);
3986 GEN8_IRQ_FINI_NDX(GT, 2);
3987 GEN8_IRQ_FINI_NDX(GT, 3);
3988
3989 GEN8_IRQ_FINI(PCU);
3990
3991#undef GEN8_IRQ_FINI
3992#undef GEN8_IRQ_FINI_NDX
3993
3994 I915_WRITE(PORT_HOTPLUG_EN, 0);
3995 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3996
3997 for_each_pipe(pipe)
3998 I915_WRITE(PIPESTAT(pipe), 0xffff);
3999
4000 I915_WRITE(VLV_IMR, 0xffffffff);
4001 I915_WRITE(VLV_IER, 0x0);
4002 I915_WRITE(VLV_IIR, 0xffffffff);
4003 POSTING_READ(VLV_IIR);
4004}
4005
f71d4af4 4006static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d 4007{
2d1013dd 4008 struct drm_i915_private *dev_priv = dev->dev_private;
4697995b
JB		 4009
4010 if (!dev_priv)
4011 return;
4012
3ca1cced 4013 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 4014
be30b29f 4015 ironlake_irq_reset(dev);
036a4a7d
ZW		 4016}
4017
a266c7d5 4018static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4 4019{
2d1013dd 4020 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 4021 int pipe;
91e3738e 4022
9db4a9c7
JB		 4023 for_each_pipe(pipe)
4024 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 4025 I915_WRITE16(IMR, 0xffff);
4026 I915_WRITE16(IER, 0x0);
4027 POSTING_READ16(IER);
c2798b19
CW		 4028}
4029
4030static int i8xx_irq_postinstall(struct drm_device *dev)
4031{
2d1013dd 4032 struct drm_i915_private *dev_priv = dev->dev_private;
379ef82d 4033 unsigned long irqflags;
c2798b19 4034
c2798b19
CW		 4035 I915_WRITE16(EMR,
4036 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4037
4038 /* Unmask the interrupts that we always want on. */
4039 dev_priv->irq_mask =
4040 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4041 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4042 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4043 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4044 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4045 I915_WRITE16(IMR, dev_priv->irq_mask);
4046
4047 I915_WRITE16(IER,
4048 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4049 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4050 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
4051 I915_USER_INTERRUPT);
4052 POSTING_READ16(IER);
4053
379ef82d
DV		 4054 /* Interrupt setup is already guaranteed to be single-threaded, this is
4055 * just to make the assert_spin_locked check happy. */
4056 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
755e9019
ID		 4057 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4058 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
379ef82d
DV		 4059 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4060
c2798b19
CW		 4061 return 0;
4062}
4063
90a72f87
VS		 4064/*
4065 * Returns true when a page flip has completed.
4066 */
4067static bool i8xx_handle_vblank(struct drm_device *dev,
1f1c2e24 4068 int plane, int pipe, u32 iir)
90a72f87 4069{
2d1013dd 4070 struct drm_i915_private *dev_priv = dev->dev_private;
1f1c2e24 4071 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
90a72f87 4072
8d7849db 4073 if (!intel_pipe_handle_vblank(dev, pipe))
90a72f87
VS		 4074 return false;
4075
4076 if ((iir & flip_pending) == 0)
4077 return false;
4078
1f1c2e24 4079 intel_prepare_page_flip(dev, plane);
90a72f87
VS		 4080
4081 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4082 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4083 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4084 * the flip is completed (no longer pending). Since this doesn't raise
4085 * an interrupt per se, we watch for the change at vblank.
4086 */
4087 if (I915_READ16(ISR) & flip_pending)
4088 return false;
4089
4090 intel_finish_page_flip(dev, pipe);
4091
4092 return true;
4093}
4094
ff1f525e 4095static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19 4096{
45a83f84 4097 struct drm_device *dev = arg;
2d1013dd 4098 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 4099 u16 iir, new_iir;
4100 u32 pipe_stats[2];
4101 unsigned long irqflags;
c2798b19
CW		 4102 int pipe;
4103 u16 flip_mask =
4104 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4105 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4106
c2798b19
CW		 4107 iir = I915_READ16(IIR);
4108 if (iir == 0)
4109 return IRQ_NONE;
4110
4111 while (iir & ~flip_mask) {
4112 /* Can't rely on pipestat interrupt bit in iir as it might
4113 * have been cleared after the pipestat interrupt was received.
4114 * It doesn't set the bit in iir again, but it still produces
4115 * interrupts (for non-MSI).
4116 */
4117 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4118 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
58174462
MK		 4119 i915_handle_error(dev, false,
4120 "Command parser error, iir 0x%08x",
4121 iir);
c2798b19
CW		 4122
4123 for_each_pipe(pipe) {
4124 int reg = PIPESTAT(pipe);
4125 pipe_stats[pipe] = I915_READ(reg);
4126
4127 /*
4128 * Clear the PIPE*STAT regs before the IIR
4129 */
2d9d2b0b 4130 if (pipe_stats[pipe] & 0x8000ffff)
c2798b19 4131 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19
CW		 4132 }
4133 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4134
4135 I915_WRITE16(IIR, iir & ~flip_mask);
4136 new_iir = I915_READ16(IIR); /* Flush posted writes */
4137
d05c617e 4138 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 4139
4140 if (iir & I915_USER_INTERRUPT)
4141 notify_ring(dev, &dev_priv->ring[RCS]);
4142
4356d586 4143 for_each_pipe(pipe) {
1f1c2e24 4144 int plane = pipe;
3a77c4c4 4145 if (HAS_FBC(dev))
1f1c2e24
VS		 4146 plane = !plane;
4147
4356d586 4148 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
1f1c2e24
VS		 4149 i8xx_handle_vblank(dev, plane, pipe, iir))
4150 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
c2798b19 4151
4356d586 4152 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 4153 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b
VS		 4154
4155 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4156 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b 4157 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4356d586 4158 }
c2798b19
CW		 4159
4160 iir = new_iir;
4161 }
4162
4163 return IRQ_HANDLED;
4164}
4165
4166static void i8xx_irq_uninstall(struct drm_device * dev)
4167{
2d1013dd 4168 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 4169 int pipe;
4170
c2798b19
CW		 4171 for_each_pipe(pipe) {
4172 /* Clear enable bits; then clear status bits */
4173 I915_WRITE(PIPESTAT(pipe), 0);
4174 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4175 }
4176 I915_WRITE16(IMR, 0xffff);
4177 I915_WRITE16(IER, 0x0);
4178 I915_WRITE16(IIR, I915_READ16(IIR));
4179}
4180
a266c7d5
CW		 4181static void i915_irq_preinstall(struct drm_device * dev)
4182{
2d1013dd 4183 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4184 int pipe;
4185
a266c7d5
CW		 4186 if (I915_HAS_HOTPLUG(dev)) {
4187 I915_WRITE(PORT_HOTPLUG_EN, 0);
4188 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4189 }
4190
00d98ebd 4191 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 4192 for_each_pipe(pipe)
4193 I915_WRITE(PIPESTAT(pipe), 0);
4194 I915_WRITE(IMR, 0xffffffff);
4195 I915_WRITE(IER, 0x0);
4196 POSTING_READ(IER);
4197}
4198
4199static int i915_irq_postinstall(struct drm_device *dev)
4200{
2d1013dd 4201 struct drm_i915_private *dev_priv = dev->dev_private;
38bde180 4202 u32 enable_mask;
379ef82d 4203 unsigned long irqflags;
a266c7d5 4204
38bde180
CW		 4205 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4206
4207 /* Unmask the interrupts that we always want on. */
4208 dev_priv->irq_mask =
4209 ~(I915_ASLE_INTERRUPT |
4210 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4211 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4212 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4213 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4214 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4215
4216 enable_mask =
4217 I915_ASLE_INTERRUPT |
4218 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4219 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4220 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
4221 I915_USER_INTERRUPT;
4222
a266c7d5 4223 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 4224 I915_WRITE(PORT_HOTPLUG_EN, 0);
4225 POSTING_READ(PORT_HOTPLUG_EN);
4226
a266c7d5
CW		 4227 /* Enable in IER... */
4228 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4229 /* and unmask in IMR */
4230 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4231 }
4232
a266c7d5
CW		 4233 I915_WRITE(IMR, dev_priv->irq_mask);
4234 I915_WRITE(IER, enable_mask);
4235 POSTING_READ(IER);
4236
f49e38dd 4237 i915_enable_asle_pipestat(dev);
20afbda2 4238
379ef82d
DV		 4239 /* Interrupt setup is already guaranteed to be single-threaded, this is
4240 * just to make the assert_spin_locked check happy. */
4241 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
755e9019
ID		 4242 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4243 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
379ef82d
DV		 4244 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4245
20afbda2
DV		 4246 return 0;
4247}
4248
90a72f87
VS		 4249/*
4250 * Returns true when a page flip has completed.
4251 */
4252static bool i915_handle_vblank(struct drm_device *dev,
4253 int plane, int pipe, u32 iir)
4254{
2d1013dd 4255 struct drm_i915_private *dev_priv = dev->dev_private;
90a72f87
VS		 4256 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4257
8d7849db 4258 if (!intel_pipe_handle_vblank(dev, pipe))
90a72f87
VS		 4259 return false;
4260
4261 if ((iir & flip_pending) == 0)
4262 return false;
4263
4264 intel_prepare_page_flip(dev, plane);
4265
4266 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4267 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4268 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4269 * the flip is completed (no longer pending). Since this doesn't raise
4270 * an interrupt per se, we watch for the change at vblank.
4271 */
4272 if (I915_READ(ISR) & flip_pending)
4273 return false;
4274
4275 intel_finish_page_flip(dev, pipe);
4276
4277 return true;
4278}
4279
ff1f525e 4280static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5 4281{
45a83f84 4282 struct drm_device *dev = arg;
2d1013dd 4283 struct drm_i915_private *dev_priv = dev->dev_private;
8291ee90 4284 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 4285 unsigned long irqflags;
38bde180
CW		 4286 u32 flip_mask =
4287 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4288 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 4289 int pipe, ret = IRQ_NONE;
a266c7d5 4290
a266c7d5 4291 iir = I915_READ(IIR);
38bde180
CW		 4292 do {
4293 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 4294 bool blc_event = false;
a266c7d5
CW		 4295
4296 /* Can't rely on pipestat interrupt bit in iir as it might
4297 * have been cleared after the pipestat interrupt was received.
4298 * It doesn't set the bit in iir again, but it still produces
4299 * interrupts (for non-MSI).
4300 */
4301 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4302 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
58174462
MK		 4303 i915_handle_error(dev, false,
4304 "Command parser error, iir 0x%08x",
4305 iir);
a266c7d5
CW		 4306
4307 for_each_pipe(pipe) {
4308 int reg = PIPESTAT(pipe);
4309 pipe_stats[pipe] = I915_READ(reg);
4310
38bde180 4311 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5 4312 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 4313 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 4314 irq_received = true;
a266c7d5
CW		 4315 }
4316 }
4317 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4318
4319 if (!irq_received)
4320 break;
4321
a266c7d5 4322 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 4323 if (I915_HAS_HOTPLUG(dev) &&
4324 iir & I915_DISPLAY_PORT_INTERRUPT)
4325 i9xx_hpd_irq_handler(dev);
a266c7d5 4326
38bde180 4327 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 4328 new_iir = I915_READ(IIR); /* Flush posted writes */
4329
a266c7d5
CW		 4330 if (iir & I915_USER_INTERRUPT)
4331 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 4332
a266c7d5 4333 for_each_pipe(pipe) {
38bde180 4334 int plane = pipe;
3a77c4c4 4335 if (HAS_FBC(dev))
38bde180 4336 plane = !plane;
90a72f87 4337
8291ee90 4338 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 4339 i915_handle_vblank(dev, plane, pipe, iir))
4340 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 4341
4342 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4343 blc_event = true;
4356d586
DV		 4344
4345 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 4346 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b
VS		 4347
4348 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4349 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b 4350 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
a266c7d5
CW		 4351 }
4352
a266c7d5
CW		 4353 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4354 intel_opregion_asle_intr(dev);
4355
4356 /* With MSI, interrupts are only generated when iir
4357 * transitions from zero to nonzero. If another bit got
4358 * set while we were handling the existing iir bits, then
4359 * we would never get another interrupt.
4360 *
4361 * This is fine on non-MSI as well, as if we hit this path
4362 * we avoid exiting the interrupt handler only to generate
4363 * another one.
4364 *
4365 * Note that for MSI this could cause a stray interrupt report
4366 * if an interrupt landed in the time between writing IIR and
4367 * the posting read. This should be rare enough to never
4368 * trigger the 99% of 100,000 interrupts test for disabling
4369 * stray interrupts.
4370 */
38bde180 4371 ret = IRQ_HANDLED;
a266c7d5 4372 iir = new_iir;
38bde180 4373 } while (iir & ~flip_mask);
a266c7d5 4374
d05c617e 4375 i915_update_dri1_breadcrumb(dev);
8291ee90 4376
a266c7d5
CW		 4377 return ret;
4378}
4379
4380static void i915_irq_uninstall(struct drm_device * dev)
4381{
2d1013dd 4382 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4383 int pipe;
4384
3ca1cced 4385 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 4386
a266c7d5
CW		 4387 if (I915_HAS_HOTPLUG(dev)) {
4388 I915_WRITE(PORT_HOTPLUG_EN, 0);
4389 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4390 }
4391
00d98ebd 4392 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 4393 for_each_pipe(pipe) {
4394 /* Clear enable bits; then clear status bits */
a266c7d5 4395 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 4396 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4397 }
a266c7d5
CW		 4398 I915_WRITE(IMR, 0xffffffff);
4399 I915_WRITE(IER, 0x0);
4400
a266c7d5
CW		 4401 I915_WRITE(IIR, I915_READ(IIR));
4402}
4403
4404static void i965_irq_preinstall(struct drm_device * dev)
4405{
2d1013dd 4406 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4407 int pipe;
4408
adca4730
CW		 4409 I915_WRITE(PORT_HOTPLUG_EN, 0);
4410 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 4411
4412 I915_WRITE(HWSTAM, 0xeffe);
4413 for_each_pipe(pipe)
4414 I915_WRITE(PIPESTAT(pipe), 0);
4415 I915_WRITE(IMR, 0xffffffff);
4416 I915_WRITE(IER, 0x0);
4417 POSTING_READ(IER);
4418}
4419
4420static int i965_irq_postinstall(struct drm_device *dev)
4421{
2d1013dd 4422 struct drm_i915_private *dev_priv = dev->dev_private;
bbba0a97 4423 u32 enable_mask;
a266c7d5 4424 u32 error_mask;
b79480ba 4425 unsigned long irqflags;
a266c7d5 4426
a266c7d5 4427 /* Unmask the interrupts that we always want on. */
bbba0a97 4428 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 4429 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 4430 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4431 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4432 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4433 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4434 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4435
4436 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 4437 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4438 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 4439 enable_mask |= I915_USER_INTERRUPT;
4440
4441 if (IS_G4X(dev))
4442 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 4443
b79480ba
DV		 4444 /* Interrupt setup is already guaranteed to be single-threaded, this is
4445 * just to make the assert_spin_locked check happy. */
4446 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
755e9019
ID		 4447 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4448 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4449 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
b79480ba 4450 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 4451
a266c7d5
CW		 4452 /*
4453 * Enable some error detection, note the instruction error mask
4454 * bit is reserved, so we leave it masked.
4455 */
4456 if (IS_G4X(dev)) {
4457 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4458 GM45_ERROR_MEM_PRIV |
4459 GM45_ERROR_CP_PRIV |
4460 I915_ERROR_MEMORY_REFRESH);
4461 } else {
4462 error_mask = ~(I915_ERROR_PAGE_TABLE |
4463 I915_ERROR_MEMORY_REFRESH);
4464 }
4465 I915_WRITE(EMR, error_mask);
4466
4467 I915_WRITE(IMR, dev_priv->irq_mask);
4468 I915_WRITE(IER, enable_mask);
4469 POSTING_READ(IER);
4470
20afbda2
DV		 4471 I915_WRITE(PORT_HOTPLUG_EN, 0);
4472 POSTING_READ(PORT_HOTPLUG_EN);
4473
f49e38dd 4474 i915_enable_asle_pipestat(dev);
20afbda2
DV		 4475
4476 return 0;
4477}
4478
bac56d5b 4479static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2 4480{
2d1013dd 4481 struct drm_i915_private *dev_priv = dev->dev_private;
cd569aed 4482 struct intel_encoder *intel_encoder;
20afbda2
DV		 4483 u32 hotplug_en;
4484
b5ea2d56
DV		 4485 assert_spin_locked(&dev_priv->irq_lock);
4486
bac56d5b
EE		 4487 if (I915_HAS_HOTPLUG(dev)) {
4488 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4489 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4490 /* Note HDMI and DP share hotplug bits */
e5868a31 4491 /* enable bits are the same for all generations */
b2784e15 4492 for_each_intel_encoder(dev, intel_encoder)
cd569aed
EE		 4493 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4494 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 4495 /* Programming the CRT detection parameters tends
4496 to generate a spurious hotplug event about three
4497 seconds later. So just do it once.
4498 */
4499 if (IS_G4X(dev))
4500 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 4501 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 4502 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 4503
bac56d5b
EE		 4504 /* Ignore TV since it's buggy */
4505 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4506 }
a266c7d5
CW		 4507}
4508
ff1f525e 4509static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5 4510{
45a83f84 4511 struct drm_device *dev = arg;
2d1013dd 4512 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4513 u32 iir, new_iir;
4514 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5 4515 unsigned long irqflags;
a266c7d5 4516 int ret = IRQ_NONE, pipe;
21ad8330
VS		 4517 u32 flip_mask =
4518 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4519 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5 4520
a266c7d5
CW		 4521 iir = I915_READ(IIR);
4522
a266c7d5 4523 for (;;) {
501e01d7 4524 bool irq_received = (iir & ~flip_mask) != 0;
2c8ba29f
CW		 4525 bool blc_event = false;
4526
a266c7d5
CW		 4527 /* Can't rely on pipestat interrupt bit in iir as it might
4528 * have been cleared after the pipestat interrupt was received.
4529 * It doesn't set the bit in iir again, but it still produces
4530 * interrupts (for non-MSI).
4531 */
4532 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4533 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
58174462
MK		 4534 i915_handle_error(dev, false,
4535 "Command parser error, iir 0x%08x",
4536 iir);
a266c7d5
CW		 4537
4538 for_each_pipe(pipe) {
4539 int reg = PIPESTAT(pipe);
4540 pipe_stats[pipe] = I915_READ(reg);
4541
4542 /*
4543 * Clear the PIPE*STAT regs before the IIR
4544 */
4545 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 4546 I915_WRITE(reg, pipe_stats[pipe]);
501e01d7 4547 irq_received = true;
a266c7d5
CW		 4548 }
4549 }
4550 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4551
4552 if (!irq_received)
4553 break;
4554
4555 ret = IRQ_HANDLED;
4556
4557 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 4558 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4559 i9xx_hpd_irq_handler(dev);
a266c7d5 4560
21ad8330 4561 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 4562 new_iir = I915_READ(IIR); /* Flush posted writes */
4563
a266c7d5
CW		 4564 if (iir & I915_USER_INTERRUPT)
4565 notify_ring(dev, &dev_priv->ring[RCS]);
4566 if (iir & I915_BSD_USER_INTERRUPT)
4567 notify_ring(dev, &dev_priv->ring[VCS]);
4568
a266c7d5 4569 for_each_pipe(pipe) {
2c8ba29f 4570 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 4571 i915_handle_vblank(dev, pipe, pipe, iir))
4572 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 4573
4574 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4575 blc_event = true;
4356d586
DV		 4576
4577 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 4578 i9xx_pipe_crc_irq_handler(dev, pipe);
a266c7d5 4579
2d9d2b0b
VS		 4580 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4581 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b 4582 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
2d9d2b0b 4583 }
a266c7d5
CW		 4584
4585 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4586 intel_opregion_asle_intr(dev);
4587
515ac2bb
DV		 4588 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4589 gmbus_irq_handler(dev);
4590
a266c7d5
CW		 4591 /* With MSI, interrupts are only generated when iir
4592 * transitions from zero to nonzero. If another bit got
4593 * set while we were handling the existing iir bits, then
4594 * we would never get another interrupt.
4595 *
4596 * This is fine on non-MSI as well, as if we hit this path
4597 * we avoid exiting the interrupt handler only to generate
4598 * another one.
4599 *
4600 * Note that for MSI this could cause a stray interrupt report
4601 * if an interrupt landed in the time between writing IIR and
4602 * the posting read. This should be rare enough to never
4603 * trigger the 99% of 100,000 interrupts test for disabling
4604 * stray interrupts.
4605 */
4606 iir = new_iir;
4607 }
4608
d05c617e 4609 i915_update_dri1_breadcrumb(dev);
2c8ba29f 4610
a266c7d5
CW		 4611 return ret;
4612}
4613
4614static void i965_irq_uninstall(struct drm_device * dev)
4615{
2d1013dd 4616 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4617 int pipe;
4618
4619 if (!dev_priv)
4620 return;
4621
3ca1cced 4622 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 4623
adca4730
CW		 4624 I915_WRITE(PORT_HOTPLUG_EN, 0);
4625 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 4626
4627 I915_WRITE(HWSTAM, 0xffffffff);
4628 for_each_pipe(pipe)
4629 I915_WRITE(PIPESTAT(pipe), 0);
4630 I915_WRITE(IMR, 0xffffffff);
4631 I915_WRITE(IER, 0x0);
4632
4633 for_each_pipe(pipe)
4634 I915_WRITE(PIPESTAT(pipe),
4635 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4636 I915_WRITE(IIR, I915_READ(IIR));
4637}
4638
3ca1cced 4639static void intel_hpd_irq_reenable(unsigned long data)
ac4c16c5 4640{
2d1013dd 4641 struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
ac4c16c5
EE		 4642 struct drm_device *dev = dev_priv->dev;
4643 struct drm_mode_config *mode_config = &dev->mode_config;
4644 unsigned long irqflags;
4645 int i;
4646
4647 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4648 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4649 struct drm_connector *connector;
4650
4651 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4652 continue;
4653
4654 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4655
4656 list_for_each_entry(connector, &mode_config->connector_list, head) {
4657 struct intel_connector *intel_connector = to_intel_connector(connector);
4658
4659 if (intel_connector->encoder->hpd_pin == i) {
4660 if (connector->polled != intel_connector->polled)
4661 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
c23cc417 4662 connector->name);
ac4c16c5
EE		 4663 connector->polled = intel_connector->polled;
4664 if (!connector->polled)
4665 connector->polled = DRM_CONNECTOR_POLL_HPD;
4666 }
4667 }
4668 }
4669 if (dev_priv->display.hpd_irq_setup)
4670 dev_priv->display.hpd_irq_setup(dev);
4671 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4672}
4673
f71d4af4
JB		 4674void intel_irq_init(struct drm_device *dev)
4675{
8b2e326d
CW		 4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677
4678 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
13cf5504 4679 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
99584db3 4680 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 4681 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 4682 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 4683
a6706b45 4684 /* Let's track the enabled rps events */
31685c25
D		 4685 if (IS_VALLEYVIEW(dev))
4686 /* WaGsvRC0ResidenncyMethod:VLV */
4687 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4688 else
4689 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
a6706b45 4690
99584db3
DV		 4691 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4692 i915_hangcheck_elapsed,
61bac78e 4693 (unsigned long) dev);
3ca1cced 4694 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
ac4c16c5 4695 (unsigned long) dev_priv);
61bac78e 4696
97a19a24 4697 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 4698
95f25bed
JB		 4699 /* Haven't installed the IRQ handler yet */
4700 dev_priv->pm._irqs_disabled = true;
4701
4cdb83ec
VS		 4702 if (IS_GEN2(dev)) {
4703 dev->max_vblank_count = 0;
4704 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4705 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 4706 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4707 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
391f75e2
VS		 4708 } else {
4709 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4710 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 4711 }
4712
c2baf4b7 4713 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
c3613de9 4714 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
c2baf4b7
VS		 4715 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4716 }
f71d4af4 4717
43f328d7
VS		 4718 if (IS_CHERRYVIEW(dev)) {
4719 dev->driver->irq_handler = cherryview_irq_handler;
4720 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4721 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4722 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4723 dev->driver->enable_vblank = valleyview_enable_vblank;
4724 dev->driver->disable_vblank = valleyview_disable_vblank;
4725 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4726 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 4727 dev->driver->irq_handler = valleyview_irq_handler;
4728 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4729 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4730 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4731 dev->driver->enable_vblank = valleyview_enable_vblank;
4732 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 4733 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
abd58f01
BW		 4734 } else if (IS_GEN8(dev)) {
4735 dev->driver->irq_handler = gen8_irq_handler;
723761b8 4736 dev->driver->irq_preinstall = gen8_irq_reset;
abd58f01
BW		 4737 dev->driver->irq_postinstall = gen8_irq_postinstall;
4738 dev->driver->irq_uninstall = gen8_irq_uninstall;
4739 dev->driver->enable_vblank = gen8_enable_vblank;
4740 dev->driver->disable_vblank = gen8_disable_vblank;
4741 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 4742 } else if (HAS_PCH_SPLIT(dev)) {
4743 dev->driver->irq_handler = ironlake_irq_handler;
723761b8 4744 dev->driver->irq_preinstall = ironlake_irq_reset;
f71d4af4
JB		 4745 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4746 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4747 dev->driver->enable_vblank = ironlake_enable_vblank;
4748 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 4749 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 4750 } else {
c2798b19
CW		 4751 if (INTEL_INFO(dev)->gen == 2) {
4752 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4753 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4754 dev->driver->irq_handler = i8xx_irq_handler;
4755 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 4756 } else if (INTEL_INFO(dev)->gen == 3) {
4757 dev->driver->irq_preinstall = i915_irq_preinstall;
4758 dev->driver->irq_postinstall = i915_irq_postinstall;
4759 dev->driver->irq_uninstall = i915_irq_uninstall;
4760 dev->driver->irq_handler = i915_irq_handler;
20afbda2 4761 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 4762 } else {
a266c7d5
CW		 4763 dev->driver->irq_preinstall = i965_irq_preinstall;
4764 dev->driver->irq_postinstall = i965_irq_postinstall;
4765 dev->driver->irq_uninstall = i965_irq_uninstall;
4766 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 4767 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 4768 }
f71d4af4
JB		 4769 dev->driver->enable_vblank = i915_enable_vblank;
4770 dev->driver->disable_vblank = i915_disable_vblank;
4771 }
4772}
20afbda2
DV		 4773
4774void intel_hpd_init(struct drm_device *dev)
4775{
4776 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 4777 struct drm_mode_config *mode_config = &dev->mode_config;
4778 struct drm_connector *connector;
b5ea2d56 4779 unsigned long irqflags;
821450c6 4780 int i;
20afbda2 4781
821450c6
EE		 4782 for (i = 1; i < HPD_NUM_PINS; i++) {
4783 dev_priv->hpd_stats[i].hpd_cnt = 0;
4784 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4785 }
4786 list_for_each_entry(connector, &mode_config->connector_list, head) {
4787 struct intel_connector *intel_connector = to_intel_connector(connector);
4788 connector->polled = intel_connector->polled;
0e32b39c
DA		 4789 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4790 connector->polled = DRM_CONNECTOR_POLL_HPD;
4791 if (intel_connector->mst_port)
821450c6
EE		 4792 connector->polled = DRM_CONNECTOR_POLL_HPD;
4793 }
b5ea2d56
DV		 4794
4795 /* Interrupt setup is already guaranteed to be single-threaded, this is
4796 * just to make the assert_spin_locked checks happy. */
4797 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 4798 if (dev_priv->display.hpd_irq_setup)
4799 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 4800 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 4801}
c67a470b 4802
5d584b2e 4803/* Disable interrupts so we can allow runtime PM. */
730488b2 4804void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
c67a470b
PZ		 4805{
4806 struct drm_i915_private *dev_priv = dev->dev_private;
c67a470b 4807
730488b2 4808 dev->driver->irq_uninstall(dev);
9df7575f 4809 dev_priv->pm._irqs_disabled = true;
c67a470b
PZ		 4810}
4811
5d584b2e 4812/* Restore interrupts so we can recover from runtime PM. */
730488b2 4813void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
c67a470b
PZ		 4814{
4815 struct drm_i915_private *dev_priv = dev->dev_private;
c67a470b 4816
9df7575f 4817 dev_priv->pm._irqs_disabled = false;
730488b2
PZ		 4818 dev->driver->irq_preinstall(dev);
4819 dev->driver->irq_postinstall(dev);
c67a470b 4820}
Linux kernel - Deliverables
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