Commit | Line | Data |
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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | ||
1da177e4 | 34 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 35 | |
7c463586 KP |
36 | /** |
37 | * Interrupts that are always left unmasked. | |
38 | * | |
39 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
40 | * we leave them always unmasked in IMR and then control enabling them through | |
41 | * PIPESTAT alone. | |
42 | */ | |
43 | #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ | |
44 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
45 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) | |
46 | ||
47 | /** Interrupts that we mask and unmask at runtime. */ | |
48 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) | |
49 | ||
50 | /** These are all of the interrupts used by the driver */ | |
51 | #define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \ | |
52 | I915_INTERRUPT_ENABLE_VAR) | |
ed4cb414 | 53 | |
8ee1c3db | 54 | void |
ed4cb414 EA |
55 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
56 | { | |
57 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
58 | dev_priv->irq_mask_reg &= ~mask; | |
59 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
60 | (void) I915_READ(IMR); | |
61 | } | |
62 | } | |
63 | ||
64 | static inline void | |
65 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
66 | { | |
67 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
68 | dev_priv->irq_mask_reg |= mask; | |
69 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
70 | (void) I915_READ(IMR); | |
71 | } | |
72 | } | |
73 | ||
7c463586 KP |
74 | static inline u32 |
75 | i915_pipestat(int pipe) | |
76 | { | |
77 | if (pipe == 0) | |
78 | return PIPEASTAT; | |
79 | if (pipe == 1) | |
80 | return PIPEBSTAT; | |
9c84ba4e | 81 | BUG(); |
7c463586 KP |
82 | } |
83 | ||
84 | void | |
85 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
86 | { | |
87 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
88 | u32 reg = i915_pipestat(pipe); | |
89 | ||
90 | dev_priv->pipestat[pipe] |= mask; | |
91 | /* Enable the interrupt, clear any pending status */ | |
92 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
93 | (void) I915_READ(reg); | |
94 | } | |
95 | } | |
96 | ||
97 | void | |
98 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
99 | { | |
100 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
101 | u32 reg = i915_pipestat(pipe); | |
102 | ||
103 | dev_priv->pipestat[pipe] &= ~mask; | |
104 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
105 | (void) I915_READ(reg); | |
106 | } | |
107 | } | |
108 | ||
0a3e67a4 JB |
109 | /** |
110 | * i915_pipe_enabled - check if a pipe is enabled | |
111 | * @dev: DRM device | |
112 | * @pipe: pipe to check | |
113 | * | |
114 | * Reading certain registers when the pipe is disabled can hang the chip. | |
115 | * Use this routine to make sure the PLL is running and the pipe is active | |
116 | * before reading such registers if unsure. | |
117 | */ | |
118 | static int | |
119 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
120 | { | |
121 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
122 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; | |
123 | ||
124 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) | |
125 | return 1; | |
126 | ||
127 | return 0; | |
128 | } | |
129 | ||
42f52ef8 KP |
130 | /* Called from drm generic code, passed a 'crtc', which |
131 | * we use as a pipe index | |
132 | */ | |
133 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
134 | { |
135 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
136 | unsigned long high_frame; | |
137 | unsigned long low_frame; | |
138 | u32 high1, high2, low, count; | |
0a3e67a4 | 139 | |
0a3e67a4 JB |
140 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
141 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
142 | ||
143 | if (!i915_pipe_enabled(dev, pipe)) { | |
144 | DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); | |
145 | return 0; | |
146 | } | |
147 | ||
148 | /* | |
149 | * High & low register fields aren't synchronized, so make sure | |
150 | * we get a low value that's stable across two reads of the high | |
151 | * register. | |
152 | */ | |
153 | do { | |
154 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
155 | PIPE_FRAME_HIGH_SHIFT); | |
156 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> | |
157 | PIPE_FRAME_LOW_SHIFT); | |
158 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
159 | PIPE_FRAME_HIGH_SHIFT); | |
160 | } while (high1 != high2); | |
161 | ||
162 | count = (high1 << 8) | low; | |
163 | ||
164 | return count; | |
165 | } | |
166 | ||
1da177e4 LT |
167 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
168 | { | |
84b1fd10 | 169 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 170 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 171 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
172 | u32 iir, new_iir; |
173 | u32 pipea_stats, pipeb_stats; | |
05eff845 KP |
174 | u32 vblank_status; |
175 | u32 vblank_enable; | |
0a3e67a4 | 176 | int vblank = 0; |
7c463586 | 177 | unsigned long irqflags; |
05eff845 KP |
178 | int irq_received; |
179 | int ret = IRQ_NONE; | |
6e5fca53 | 180 | |
630681d9 EA |
181 | atomic_inc(&dev_priv->irq_received); |
182 | ||
ed4cb414 | 183 | iir = I915_READ(IIR); |
a6b54f3f | 184 | |
05eff845 KP |
185 | if (IS_I965G(dev)) { |
186 | vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; | |
187 | vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; | |
188 | } else { | |
189 | vblank_status = I915_VBLANK_INTERRUPT_STATUS; | |
190 | vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; | |
191 | } | |
af6061af | 192 | |
05eff845 KP |
193 | for (;;) { |
194 | irq_received = iir != 0; | |
195 | ||
196 | /* Can't rely on pipestat interrupt bit in iir as it might | |
197 | * have been cleared after the pipestat interrupt was received. | |
198 | * It doesn't set the bit in iir again, but it still produces | |
199 | * interrupts (for non-MSI). | |
200 | */ | |
201 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
202 | pipea_stats = I915_READ(PIPEASTAT); | |
203 | pipeb_stats = I915_READ(PIPEBSTAT); | |
cdfbc41f EA |
204 | /* |
205 | * Clear the PIPE(A|B)STAT regs before the IIR | |
206 | */ | |
05eff845 | 207 | if (pipea_stats & 0x8000ffff) { |
cdfbc41f | 208 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 209 | irq_received = 1; |
cdfbc41f | 210 | } |
1da177e4 | 211 | |
05eff845 | 212 | if (pipeb_stats & 0x8000ffff) { |
cdfbc41f | 213 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 214 | irq_received = 1; |
cdfbc41f | 215 | } |
05eff845 KP |
216 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
217 | ||
218 | if (!irq_received) | |
219 | break; | |
220 | ||
221 | ret = IRQ_HANDLED; | |
8ee1c3db | 222 | |
cdfbc41f EA |
223 | I915_WRITE(IIR, iir); |
224 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 225 | |
7c1c2871 DA |
226 | if (dev->primary->master) { |
227 | master_priv = dev->primary->master->driver_priv; | |
228 | if (master_priv->sarea_priv) | |
229 | master_priv->sarea_priv->last_dispatch = | |
230 | READ_BREADCRUMB(dev_priv); | |
231 | } | |
0a3e67a4 | 232 | |
cdfbc41f EA |
233 | if (iir & I915_USER_INTERRUPT) { |
234 | dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); | |
235 | DRM_WAKEUP(&dev_priv->irq_queue); | |
236 | } | |
673a394b | 237 | |
05eff845 | 238 | if (pipea_stats & vblank_status) { |
cdfbc41f EA |
239 | vblank++; |
240 | drm_handle_vblank(dev, 0); | |
241 | } | |
7c463586 | 242 | |
05eff845 | 243 | if (pipeb_stats & vblank_status) { |
cdfbc41f EA |
244 | vblank++; |
245 | drm_handle_vblank(dev, 1); | |
246 | } | |
7c463586 | 247 | |
cdfbc41f EA |
248 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || |
249 | (iir & I915_ASLE_INTERRUPT)) | |
250 | opregion_asle_intr(dev); | |
251 | ||
252 | /* With MSI, interrupts are only generated when iir | |
253 | * transitions from zero to nonzero. If another bit got | |
254 | * set while we were handling the existing iir bits, then | |
255 | * we would never get another interrupt. | |
256 | * | |
257 | * This is fine on non-MSI as well, as if we hit this path | |
258 | * we avoid exiting the interrupt handler only to generate | |
259 | * another one. | |
260 | * | |
261 | * Note that for MSI this could cause a stray interrupt report | |
262 | * if an interrupt landed in the time between writing IIR and | |
263 | * the posting read. This should be rare enough to never | |
264 | * trigger the 99% of 100,000 interrupts test for disabling | |
265 | * stray interrupts. | |
266 | */ | |
267 | iir = new_iir; | |
05eff845 | 268 | } |
0a3e67a4 | 269 | |
05eff845 | 270 | return ret; |
1da177e4 LT |
271 | } |
272 | ||
af6061af | 273 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
274 | { |
275 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 276 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
277 | RING_LOCALS; |
278 | ||
279 | i915_kernel_lost_context(dev); | |
280 | ||
3e684eae | 281 | DRM_DEBUG("\n"); |
1da177e4 | 282 | |
c99b058f | 283 | dev_priv->counter++; |
c29b669c | 284 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 285 | dev_priv->counter = 1; |
7c1c2871 DA |
286 | if (master_priv->sarea_priv) |
287 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 288 | |
0baf823a | 289 | BEGIN_LP_RING(4); |
585fb111 | 290 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 291 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
c29b669c | 292 | OUT_RING(dev_priv->counter); |
585fb111 | 293 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 294 | ADVANCE_LP_RING(); |
bc5f4523 | 295 | |
c29b669c | 296 | return dev_priv->counter; |
1da177e4 LT |
297 | } |
298 | ||
673a394b | 299 | void i915_user_irq_get(struct drm_device *dev) |
ed4cb414 EA |
300 | { |
301 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 302 | unsigned long irqflags; |
ed4cb414 | 303 | |
e9d21d7f | 304 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
305 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) |
306 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
e9d21d7f | 307 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
308 | } |
309 | ||
0a3e67a4 | 310 | void i915_user_irq_put(struct drm_device *dev) |
ed4cb414 EA |
311 | { |
312 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 313 | unsigned long irqflags; |
ed4cb414 | 314 | |
e9d21d7f | 315 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
316 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
317 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) | |
318 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
e9d21d7f | 319 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
320 | } |
321 | ||
84b1fd10 | 322 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
323 | { |
324 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 325 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
326 | int ret = 0; |
327 | ||
3e684eae | 328 | DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
329 | READ_BREADCRUMB(dev_priv)); |
330 | ||
ed4cb414 | 331 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
332 | if (master_priv->sarea_priv) |
333 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 334 | return 0; |
ed4cb414 | 335 | } |
1da177e4 | 336 | |
7c1c2871 DA |
337 | if (master_priv->sarea_priv) |
338 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 339 | |
ed4cb414 | 340 | i915_user_irq_get(dev); |
1da177e4 LT |
341 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
342 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
ed4cb414 | 343 | i915_user_irq_put(dev); |
1da177e4 | 344 | |
20caafa6 | 345 | if (ret == -EBUSY) { |
3e684eae | 346 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
347 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
348 | } | |
349 | ||
af6061af DA |
350 | return ret; |
351 | } | |
352 | ||
1da177e4 LT |
353 | /* Needs the lock as it touches the ring. |
354 | */ | |
c153f45f EA |
355 | int i915_irq_emit(struct drm_device *dev, void *data, |
356 | struct drm_file *file_priv) | |
1da177e4 | 357 | { |
1da177e4 | 358 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 359 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
360 | int result; |
361 | ||
546b0974 | 362 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 LT |
363 | |
364 | if (!dev_priv) { | |
3e684eae | 365 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 366 | return -EINVAL; |
1da177e4 | 367 | } |
546b0974 | 368 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 369 | result = i915_emit_irq(dev); |
546b0974 | 370 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 371 | |
c153f45f | 372 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 373 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 374 | return -EFAULT; |
1da177e4 LT |
375 | } |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
380 | /* Doesn't need the hardware lock. | |
381 | */ | |
c153f45f EA |
382 | int i915_irq_wait(struct drm_device *dev, void *data, |
383 | struct drm_file *file_priv) | |
1da177e4 | 384 | { |
1da177e4 | 385 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 386 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
387 | |
388 | if (!dev_priv) { | |
3e684eae | 389 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 390 | return -EINVAL; |
1da177e4 LT |
391 | } |
392 | ||
c153f45f | 393 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
394 | } |
395 | ||
42f52ef8 KP |
396 | /* Called from drm generic code, passed 'crtc' which |
397 | * we use as a pipe index | |
398 | */ | |
399 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
400 | { |
401 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 402 | unsigned long irqflags; |
0a3e67a4 | 403 | |
e9d21d7f | 404 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
e9d21d7f | 405 | if (IS_I965G(dev)) |
7c463586 KP |
406 | i915_enable_pipestat(dev_priv, pipe, |
407 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 408 | else |
7c463586 KP |
409 | i915_enable_pipestat(dev_priv, pipe, |
410 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 411 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
412 | return 0; |
413 | } | |
414 | ||
42f52ef8 KP |
415 | /* Called from drm generic code, passed 'crtc' which |
416 | * we use as a pipe index | |
417 | */ | |
418 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
419 | { |
420 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 421 | unsigned long irqflags; |
0a3e67a4 | 422 | |
e9d21d7f | 423 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
7c463586 KP |
424 | i915_disable_pipestat(dev_priv, pipe, |
425 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
426 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 427 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
428 | } |
429 | ||
702880f2 DA |
430 | /* Set the vblank monitor pipe |
431 | */ | |
c153f45f EA |
432 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
433 | struct drm_file *file_priv) | |
702880f2 | 434 | { |
702880f2 | 435 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
436 | |
437 | if (!dev_priv) { | |
3e684eae | 438 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 439 | return -EINVAL; |
702880f2 DA |
440 | } |
441 | ||
5b51694a | 442 | return 0; |
702880f2 DA |
443 | } |
444 | ||
c153f45f EA |
445 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
446 | struct drm_file *file_priv) | |
702880f2 | 447 | { |
702880f2 | 448 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 449 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
450 | |
451 | if (!dev_priv) { | |
3e684eae | 452 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 453 | return -EINVAL; |
702880f2 DA |
454 | } |
455 | ||
0a3e67a4 | 456 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 457 | |
702880f2 DA |
458 | return 0; |
459 | } | |
460 | ||
a6b54f3f MCA |
461 | /** |
462 | * Schedule buffer swap at given vertical blank. | |
463 | */ | |
c153f45f EA |
464 | int i915_vblank_swap(struct drm_device *dev, void *data, |
465 | struct drm_file *file_priv) | |
a6b54f3f | 466 | { |
bd95e0a4 EA |
467 | /* The delayed swap mechanism was fundamentally racy, and has been |
468 | * removed. The model was that the client requested a delayed flip/swap | |
469 | * from the kernel, then waited for vblank before continuing to perform | |
470 | * rendering. The problem was that the kernel might wake the client | |
471 | * up before it dispatched the vblank swap (since the lock has to be | |
472 | * held while touching the ringbuffer), in which case the client would | |
473 | * clear and start the next frame before the swap occurred, and | |
474 | * flicker would occur in addition to likely missing the vblank. | |
475 | * | |
476 | * In the absence of this ioctl, userland falls back to a correct path | |
477 | * of waiting for a vblank, then dispatching the swap on its own. | |
478 | * Context switching to userland and back is plenty fast enough for | |
479 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 480 | */ |
bd95e0a4 | 481 | return -EINVAL; |
a6b54f3f MCA |
482 | } |
483 | ||
1da177e4 LT |
484 | /* drm_dma.h hooks |
485 | */ | |
84b1fd10 | 486 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
487 | { |
488 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
489 | ||
0a3e67a4 | 490 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
491 | I915_WRITE(PIPEASTAT, 0); |
492 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 493 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 494 | I915_WRITE(IER, 0x0); |
7c463586 | 495 | (void) I915_READ(IER); |
1da177e4 LT |
496 | } |
497 | ||
0a3e67a4 | 498 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
499 | { |
500 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
0a3e67a4 JB |
501 | |
502 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
0a3e67a4 JB |
503 | |
504 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
ed4cb414 | 505 | |
7c463586 KP |
506 | /* Unmask the interrupts that we always want on. */ |
507 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
508 | ||
509 | dev_priv->pipestat[0] = 0; | |
510 | dev_priv->pipestat[1] = 0; | |
511 | ||
512 | /* Disable pipe interrupt enables, clear pending pipe status */ | |
513 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); | |
514 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
515 | /* Clear pending interrupt status */ | |
516 | I915_WRITE(IIR, I915_READ(IIR)); | |
8ee1c3db | 517 | |
ed4cb414 | 518 | I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK); |
7c463586 | 519 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
ed4cb414 EA |
520 | (void) I915_READ(IER); |
521 | ||
8ee1c3db | 522 | opregion_enable_asle(dev); |
1da177e4 | 523 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
0a3e67a4 JB |
524 | |
525 | return 0; | |
1da177e4 LT |
526 | } |
527 | ||
84b1fd10 | 528 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
529 | { |
530 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 531 | |
1da177e4 LT |
532 | if (!dev_priv) |
533 | return; | |
534 | ||
0a3e67a4 JB |
535 | dev_priv->vblank_pipe = 0; |
536 | ||
537 | I915_WRITE(HWSTAM, 0xffffffff); | |
7c463586 KP |
538 | I915_WRITE(PIPEASTAT, 0); |
539 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 540 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 541 | I915_WRITE(IER, 0x0); |
af6061af | 542 | |
7c463586 KP |
543 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
544 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
545 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 546 | } |