projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: get a runtime PM ref for the deferred GPU reset work
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
b2c88f5b 33#include <linux/circ_buf.h>
760285e7
DH		 34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
1da177e4 36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
e5868a31
EE		 40static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46};
47
48static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54};
55
56static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63};
64
704cfb87 65static const u32 hpd_status_g4x[] = {
e5868a31
EE		 66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72};
73
e5868a31
EE		 74static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81};
82
5c502442 83/* IIR can theoretically queue up two events. Be paranoid. */
f86f3fb0 84#define GEN8_IRQ_RESET_NDX(type, which) do { \
5c502442
PZ		 85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
92} while (0)
93
f86f3fb0 94#define GEN5_IRQ_RESET(type) do { \
a9d356a6 95 I915_WRITE(type##IMR, 0xffffffff); \
5c502442 96 POSTING_READ(type##IMR); \
a9d356a6 97 I915_WRITE(type##IER, 0); \
5c502442
PZ		 98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
a9d356a6
PZ		 102} while (0)
103
337ba017
PZ		 104/*
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
106 */
107#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
109 if (val) { \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
111 (reg), val); \
112 I915_WRITE((reg), 0xffffffff); \
113 POSTING_READ(reg); \
114 I915_WRITE((reg), 0xffffffff); \
115 POSTING_READ(reg); \
116 } \
117} while (0)
118
35079899 119#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
337ba017 120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
35079899
PZ		 121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
124} while (0)
125
126#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
337ba017 127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
35079899
PZ		 128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
131} while (0)
132
036a4a7d 133/* For display hotplug interrupt */
995b6762 134static void
2d1013dd 135ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 136{
4bc9d430
DV		 137 assert_spin_locked(&dev_priv->irq_lock);
138
730488b2 139 if (WARN_ON(dev_priv->pm.irqs_disabled))
c67a470b 140 return;
c67a470b 141
1ec14ad3
CW		 142 if ((dev_priv->irq_mask & mask) != 0) {
143 dev_priv->irq_mask &= ~mask;
144 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 145 POSTING_READ(DEIMR);
036a4a7d
ZW		 146 }
147}
148
0ff9800a 149static void
2d1013dd 150ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 151{
4bc9d430
DV		 152 assert_spin_locked(&dev_priv->irq_lock);
153
730488b2 154 if (WARN_ON(dev_priv->pm.irqs_disabled))
c67a470b 155 return;
c67a470b 156
1ec14ad3
CW		 157 if ((dev_priv->irq_mask & mask) != mask) {
158 dev_priv->irq_mask |= mask;
159 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 160 POSTING_READ(DEIMR);
036a4a7d
ZW		 161 }
162}
163
43eaea13
PZ		 164/**
165 * ilk_update_gt_irq - update GTIMR
166 * @dev_priv: driver private
167 * @interrupt_mask: mask of interrupt bits to update
168 * @enabled_irq_mask: mask of interrupt bits to enable
169 */
170static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
171 uint32_t interrupt_mask,
172 uint32_t enabled_irq_mask)
173{
174 assert_spin_locked(&dev_priv->irq_lock);
175
730488b2 176 if (WARN_ON(dev_priv->pm.irqs_disabled))
c67a470b 177 return;
c67a470b 178
43eaea13
PZ		 179 dev_priv->gt_irq_mask &= ~interrupt_mask;
180 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
181 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
182 POSTING_READ(GTIMR);
183}
184
185void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
186{
187 ilk_update_gt_irq(dev_priv, mask, mask);
188}
189
190void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
191{
192 ilk_update_gt_irq(dev_priv, mask, 0);
193}
194
edbfdb45
PZ		 195/**
196 * snb_update_pm_irq - update GEN6_PMIMR
197 * @dev_priv: driver private
198 * @interrupt_mask: mask of interrupt bits to update
199 * @enabled_irq_mask: mask of interrupt bits to enable
200 */
201static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
202 uint32_t interrupt_mask,
203 uint32_t enabled_irq_mask)
204{
605cd25b 205 uint32_t new_val;
edbfdb45
PZ		 206
207 assert_spin_locked(&dev_priv->irq_lock);
208
730488b2 209 if (WARN_ON(dev_priv->pm.irqs_disabled))
c67a470b 210 return;
c67a470b 211
605cd25b 212 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 213 new_val &= ~interrupt_mask;
214 new_val |= (~enabled_irq_mask & interrupt_mask);
215
605cd25b
PZ		 216 if (new_val != dev_priv->pm_irq_mask) {
217 dev_priv->pm_irq_mask = new_val;
218 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
f52ecbcf
PZ		 219 POSTING_READ(GEN6_PMIMR);
220 }
edbfdb45
PZ		 221}
222
223void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
224{
225 snb_update_pm_irq(dev_priv, mask, mask);
226}
227
228void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
229{
230 snb_update_pm_irq(dev_priv, mask, 0);
231}
232
8664281b
PZ		 233static bool ivb_can_enable_err_int(struct drm_device *dev)
234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 struct intel_crtc *crtc;
237 enum pipe pipe;
238
4bc9d430
DV		 239 assert_spin_locked(&dev_priv->irq_lock);
240
8664281b
PZ		 241 for_each_pipe(pipe) {
242 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
243
244 if (crtc->cpu_fifo_underrun_disabled)
245 return false;
246 }
247
248 return true;
249}
250
251static bool cpt_can_enable_serr_int(struct drm_device *dev)
252{
253 struct drm_i915_private *dev_priv = dev->dev_private;
254 enum pipe pipe;
255 struct intel_crtc *crtc;
256
fee884ed
DV		 257 assert_spin_locked(&dev_priv->irq_lock);
258
8664281b
PZ		 259 for_each_pipe(pipe) {
260 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
261
262 if (crtc->pch_fifo_underrun_disabled)
263 return false;
264 }
265
266 return true;
267}
268
2d9d2b0b
VS		 269static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
270{
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 u32 reg = PIPESTAT(pipe);
273 u32 pipestat = I915_READ(reg) & 0x7fff0000;
274
275 assert_spin_locked(&dev_priv->irq_lock);
276
277 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
278 POSTING_READ(reg);
279}
280
8664281b
PZ		 281static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
282 enum pipe pipe, bool enable)
283{
284 struct drm_i915_private *dev_priv = dev->dev_private;
285 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
286 DE_PIPEB_FIFO_UNDERRUN;
287
288 if (enable)
289 ironlake_enable_display_irq(dev_priv, bit);
290 else
291 ironlake_disable_display_irq(dev_priv, bit);
292}
293
294static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
7336df65 295 enum pipe pipe, bool enable)
8664281b
PZ		 296{
297 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 298 if (enable) {
7336df65
DV		 299 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
300
8664281b
PZ		 301 if (!ivb_can_enable_err_int(dev))
302 return;
303
8664281b
PZ		 304 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
305 } else {
7336df65
DV		 306 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
307
308 /* Change the state _after_ we've read out the current one. */
8664281b 309 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65
DV		 310
311 if (!was_enabled &&
312 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
313 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
314 pipe_name(pipe));
315 }
8664281b
PZ		 316 }
317}
318
38d83c96
DV		 319static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
320 enum pipe pipe, bool enable)
321{
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 assert_spin_locked(&dev_priv->irq_lock);
325
326 if (enable)
327 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
328 else
329 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
330 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
331 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
332}
333
fee884ed
DV		 334/**
335 * ibx_display_interrupt_update - update SDEIMR
336 * @dev_priv: driver private
337 * @interrupt_mask: mask of interrupt bits to update
338 * @enabled_irq_mask: mask of interrupt bits to enable
339 */
340static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
341 uint32_t interrupt_mask,
342 uint32_t enabled_irq_mask)
343{
344 uint32_t sdeimr = I915_READ(SDEIMR);
345 sdeimr &= ~interrupt_mask;
346 sdeimr |= (~enabled_irq_mask & interrupt_mask);
347
348 assert_spin_locked(&dev_priv->irq_lock);
349
730488b2 350 if (WARN_ON(dev_priv->pm.irqs_disabled))
c67a470b 351 return;
c67a470b 352
fee884ed
DV		 353 I915_WRITE(SDEIMR, sdeimr);
354 POSTING_READ(SDEIMR);
355}
356#define ibx_enable_display_interrupt(dev_priv, bits) \
357 ibx_display_interrupt_update((dev_priv), (bits), (bits))
358#define ibx_disable_display_interrupt(dev_priv, bits) \
359 ibx_display_interrupt_update((dev_priv), (bits), 0)
360
de28075d
DV		 361static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
362 enum transcoder pch_transcoder,
8664281b
PZ		 363 bool enable)
364{
8664281b 365 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 366 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
367 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 368
369 if (enable)
fee884ed 370 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 371 else
fee884ed 372 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 373}
374
375static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
376 enum transcoder pch_transcoder,
377 bool enable)
378{
379 struct drm_i915_private *dev_priv = dev->dev_private;
380
381 if (enable) {
1dd246fb
DV		 382 I915_WRITE(SERR_INT,
383 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
384
8664281b
PZ		 385 if (!cpt_can_enable_serr_int(dev))
386 return;
387
fee884ed 388 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 389 } else {
1dd246fb
DV		 390 uint32_t tmp = I915_READ(SERR_INT);
391 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
392
393 /* Change the state _after_ we've read out the current one. */
fee884ed 394 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb
DV		 395
396 if (!was_enabled &&
397 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
398 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
399 transcoder_name(pch_transcoder));
400 }
8664281b 401 }
8664281b
PZ		 402}
403
404/**
405 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
406 * @dev: drm device
407 * @pipe: pipe
408 * @enable: true if we want to report FIFO underrun errors, false otherwise
409 *
410 * This function makes us disable or enable CPU fifo underruns for a specific
411 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
412 * reporting for one pipe may also disable all the other CPU error interruts for
413 * the other pipes, due to the fact that there's just one interrupt mask/enable
414 * bit for all the pipes.
415 *
416 * Returns the previous state of underrun reporting.
417 */
f88d42f1
ID		 418bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
419 enum pipe pipe, bool enable)
8664281b
PZ		 420{
421 struct drm_i915_private *dev_priv = dev->dev_private;
422 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 424 bool ret;
425
77961eb9
ID		 426 assert_spin_locked(&dev_priv->irq_lock);
427
8664281b
PZ		 428 ret = !intel_crtc->cpu_fifo_underrun_disabled;
429
430 if (enable == ret)
431 goto done;
432
433 intel_crtc->cpu_fifo_underrun_disabled = !enable;
434
2d9d2b0b
VS		 435 if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
436 i9xx_clear_fifo_underrun(dev, pipe);
437 else if (IS_GEN5(dev) || IS_GEN6(dev))
8664281b
PZ		 438 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
439 else if (IS_GEN7(dev))
7336df65 440 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
38d83c96
DV		 441 else if (IS_GEN8(dev))
442 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b
PZ		 443
444done:
f88d42f1
ID		 445 return ret;
446}
447
448bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
449 enum pipe pipe, bool enable)
450{
451 struct drm_i915_private *dev_priv = dev->dev_private;
452 unsigned long flags;
453 bool ret;
454
455 spin_lock_irqsave(&dev_priv->irq_lock, flags);
456 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
8664281b 457 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
f88d42f1 458
8664281b
PZ		 459 return ret;
460}
461
91d181dd
ID		 462static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
463 enum pipe pipe)
464{
465 struct drm_i915_private *dev_priv = dev->dev_private;
466 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
468
469 return !intel_crtc->cpu_fifo_underrun_disabled;
470}
471
8664281b
PZ		 472/**
473 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
474 * @dev: drm device
475 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
476 * @enable: true if we want to report FIFO underrun errors, false otherwise
477 *
478 * This function makes us disable or enable PCH fifo underruns for a specific
479 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
480 * underrun reporting for one transcoder may also disable all the other PCH
481 * error interruts for the other transcoders, due to the fact that there's just
482 * one interrupt mask/enable bit for all the transcoders.
483 *
484 * Returns the previous state of underrun reporting.
485 */
486bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
487 enum transcoder pch_transcoder,
488 bool enable)
489{
490 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 491 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 493 unsigned long flags;
494 bool ret;
495
de28075d
DV		 496 /*
497 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
498 * has only one pch transcoder A that all pipes can use. To avoid racy
499 * pch transcoder -> pipe lookups from interrupt code simply store the
500 * underrun statistics in crtc A. Since we never expose this anywhere
501 * nor use it outside of the fifo underrun code here using the "wrong"
502 * crtc on LPT won't cause issues.
503 */
8664281b
PZ		 504
505 spin_lock_irqsave(&dev_priv->irq_lock, flags);
506
507 ret = !intel_crtc->pch_fifo_underrun_disabled;
508
509 if (enable == ret)
510 goto done;
511
512 intel_crtc->pch_fifo_underrun_disabled = !enable;
513
514 if (HAS_PCH_IBX(dev))
de28075d 515 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b
PZ		 516 else
517 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
518
519done:
520 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
521 return ret;
522}
523
524
b5ea642a 525static void
755e9019
ID		 526__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
527 u32 enable_mask, u32 status_mask)
7c463586 528{
46c06a30 529 u32 reg = PIPESTAT(pipe);
755e9019 530 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 531
b79480ba
DV		 532 assert_spin_locked(&dev_priv->irq_lock);
533
04feced9
VS		 534 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
535 status_mask & ~PIPESTAT_INT_STATUS_MASK,
536 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
537 pipe_name(pipe), enable_mask, status_mask))
755e9019
ID		 538 return;
539
540 if ((pipestat & enable_mask) == enable_mask)
46c06a30
VS		 541 return;
542
91d181dd
ID		 543 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
544
46c06a30 545 /* Enable the interrupt, clear any pending status */
755e9019 546 pipestat |= enable_mask | status_mask;
46c06a30
VS		 547 I915_WRITE(reg, pipestat);
548 POSTING_READ(reg);
7c463586
KP		 549}
550
b5ea642a 551static void
755e9019
ID		 552__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
553 u32 enable_mask, u32 status_mask)
7c463586 554{
46c06a30 555 u32 reg = PIPESTAT(pipe);
755e9019 556 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 557
b79480ba
DV		 558 assert_spin_locked(&dev_priv->irq_lock);
559
04feced9
VS		 560 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
561 status_mask & ~PIPESTAT_INT_STATUS_MASK,
562 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
563 pipe_name(pipe), enable_mask, status_mask))
46c06a30
VS		 564 return;
565
755e9019
ID		 566 if ((pipestat & enable_mask) == 0)
567 return;
568
91d181dd
ID		 569 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
570
755e9019 571 pipestat &= ~enable_mask;
46c06a30
VS		 572 I915_WRITE(reg, pipestat);
573 POSTING_READ(reg);
7c463586
KP		 574}
575
10c59c51
ID		 576static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
577{
578 u32 enable_mask = status_mask << 16;
579
580 /*
581 * On pipe A we don't support the PSR interrupt yet, on pipe B the
582 * same bit MBZ.
583 */
584 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
585 return 0;
586
587 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
588 SPRITE0_FLIP_DONE_INT_EN_VLV |
589 SPRITE1_FLIP_DONE_INT_EN_VLV);
590 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
591 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
592 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
593 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
594
595 return enable_mask;
596}
597
755e9019
ID		 598void
599i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
600 u32 status_mask)
601{
602 u32 enable_mask;
603
10c59c51
ID		 604 if (IS_VALLEYVIEW(dev_priv->dev))
605 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
606 status_mask);
607 else
608 enable_mask = status_mask << 16;
755e9019
ID		 609 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
610}
611
612void
613i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
614 u32 status_mask)
615{
616 u32 enable_mask;
617
10c59c51
ID		 618 if (IS_VALLEYVIEW(dev_priv->dev))
619 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
620 status_mask);
621 else
622 enable_mask = status_mask << 16;
755e9019
ID		 623 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
624}
625
01c66889 626/**
f49e38dd 627 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 628 */
f49e38dd 629static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 630{
2d1013dd 631 struct drm_i915_private *dev_priv = dev->dev_private;
1ec14ad3
CW		 632 unsigned long irqflags;
633
f49e38dd
JN		 634 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
635 return;
636
1ec14ad3 637 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 638
755e9019 639 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
f898780b 640 if (INTEL_INFO(dev)->gen >= 4)
3b6c42e8 641 i915_enable_pipestat(dev_priv, PIPE_A,
755e9019 642 PIPE_LEGACY_BLC_EVENT_STATUS);
1ec14ad3
CW		 643
644 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 645}
646
0a3e67a4
JB		 647/**
648 * i915_pipe_enabled - check if a pipe is enabled
649 * @dev: DRM device
650 * @pipe: pipe to check
651 *
652 * Reading certain registers when the pipe is disabled can hang the chip.
653 * Use this routine to make sure the PLL is running and the pipe is active
654 * before reading such registers if unsure.
655 */
656static int
657i915_pipe_enabled(struct drm_device *dev, int pipe)
658{
2d1013dd 659 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56 660
a01025af
DV		 661 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
662 /* Locking is horribly broken here, but whatever. */
663 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 665
a01025af
DV		 666 return intel_crtc->active;
667 } else {
668 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
669 }
0a3e67a4
JB		 670}
671
4cdb83ec
VS		 672static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
673{
674 /* Gen2 doesn't have a hardware frame counter */
675 return 0;
676}
677
42f52ef8
KP		 678/* Called from drm generic code, passed a 'crtc', which
679 * we use as a pipe index
680 */
f71d4af4 681static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4 682{
2d1013dd 683 struct drm_i915_private *dev_priv = dev->dev_private;
0a3e67a4
JB		 684 unsigned long high_frame;
685 unsigned long low_frame;
391f75e2 686 u32 high1, high2, low, pixel, vbl_start;
0a3e67a4
JB		 687
688 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 689 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 690 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 691 return 0;
692 }
693
391f75e2
VS		 694 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
695 struct intel_crtc *intel_crtc =
696 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
697 const struct drm_display_mode *mode =
698 &intel_crtc->config.adjusted_mode;
699
700 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
701 } else {
a2d213dd 702 enum transcoder cpu_transcoder = (enum transcoder) pipe;
391f75e2
VS		 703 u32 htotal;
704
705 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
706 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
707
708 vbl_start *= htotal;
709 }
710
9db4a9c7
JB		 711 high_frame = PIPEFRAME(pipe);
712 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 713
0a3e67a4
JB		 714 /*
715 * High & low register fields aren't synchronized, so make sure
716 * we get a low value that's stable across two reads of the high
717 * register.
718 */
719 do {
5eddb70b 720 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 721 low = I915_READ(low_frame);
5eddb70b 722 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 723 } while (high1 != high2);
724
5eddb70b 725 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 726 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 727 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 728
729 /*
730 * The frame counter increments at beginning of active.
731 * Cook up a vblank counter by also checking the pixel
732 * counter against vblank start.
733 */
edc08d0a 734 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
0a3e67a4
JB		 735}
736
f71d4af4 737static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5 738{
2d1013dd 739 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 740 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 741
742 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 743 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 744 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 745 return 0;
746 }
747
748 return I915_READ(reg);
749}
750
ad3543ed
MK		 751/* raw reads, only for fast reads of display block, no need for forcewake etc. */
752#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
ad3543ed 753
095163ba 754static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
54ddcbd2
VS		 755{
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 uint32_t status;
24302624
VS		 758 int reg;
759
760 if (INTEL_INFO(dev)->gen >= 8) {
761 status = GEN8_PIPE_VBLANK;
762 reg = GEN8_DE_PIPE_ISR(pipe);
763 } else if (INTEL_INFO(dev)->gen >= 7) {
764 status = DE_PIPE_VBLANK_IVB(pipe);
765 reg = DEISR;
54ddcbd2 766 } else {
24302624
VS		 767 status = DE_PIPE_VBLANK(pipe);
768 reg = DEISR;
54ddcbd2 769 }
ad3543ed 770
24302624 771 return __raw_i915_read32(dev_priv, reg) & status;
54ddcbd2
VS		 772}
773
f71d4af4 774static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
abca9e45
VS		 775 unsigned int flags, int *vpos, int *hpos,
776 ktime_t *stime, ktime_t *etime)
0af7e4df 777{
c2baf4b7
VS		 778 struct drm_i915_private *dev_priv = dev->dev_private;
779 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
781 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
3aa18df8 782 int position;
0af7e4df
MK		 783 int vbl_start, vbl_end, htotal, vtotal;
784 bool in_vbl = true;
785 int ret = 0;
ad3543ed 786 unsigned long irqflags;
0af7e4df 787
c2baf4b7 788 if (!intel_crtc->active) {
0af7e4df 789 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 790 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 791 return 0;
792 }
793
c2baf4b7
VS		 794 htotal = mode->crtc_htotal;
795 vtotal = mode->crtc_vtotal;
796 vbl_start = mode->crtc_vblank_start;
797 vbl_end = mode->crtc_vblank_end;
0af7e4df 798
d31faf65
VS		 799 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
800 vbl_start = DIV_ROUND_UP(vbl_start, 2);
801 vbl_end /= 2;
802 vtotal /= 2;
803 }
804
c2baf4b7
VS		 805 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
806
ad3543ed
MK		 807 /*
808 * Lock uncore.lock, as we will do multiple timing critical raw
809 * register reads, potentially with preemption disabled, so the
810 * following code must not block on uncore.lock.
811 */
812 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
813
814 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
815
816 /* Get optional system timestamp before query. */
817 if (stime)
818 *stime = ktime_get();
819
7c06b08a 820 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 821 /* No obvious pixelcount register. Only query vertical
822 * scanout position from Display scan line register.
823 */
7c06b08a 824 if (IS_GEN2(dev))
ad3543ed 825 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
7c06b08a 826 else
ad3543ed 827 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
54ddcbd2 828
fcb81823
VS		 829 if (HAS_DDI(dev)) {
830 /*
831 * On HSW HDMI outputs there seems to be a 2 line
832 * difference, whereas eDP has the normal 1 line
833 * difference that earlier platforms have. External
834 * DP is unknown. For now just check for the 2 line
835 * difference case on all output types on HSW+.
836 *
837 * This might misinterpret the scanline counter being
838 * one line too far along on eDP, but that's less
839 * dangerous than the alternative since that would lead
840 * the vblank timestamp code astray when it sees a
841 * scanline count before vblank_start during a vblank
842 * interrupt.
843 */
844 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
845 if ((in_vbl && (position == vbl_start - 2 ||
846 position == vbl_start - 1)) ||
847 (!in_vbl && (position == vbl_end - 2 ||
848 position == vbl_end - 1)))
849 position = (position + 2) % vtotal;
850 } else if (HAS_PCH_SPLIT(dev)) {
095163ba
VS		 851 /*
852 * The scanline counter increments at the leading edge
853 * of hsync, ie. it completely misses the active portion
854 * of the line. Fix up the counter at both edges of vblank
855 * to get a more accurate picture whether we're in vblank
856 * or not.
857 */
858 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
859 if ((in_vbl && position == vbl_start - 1) ||
860 (!in_vbl && position == vbl_end - 1))
861 position = (position + 1) % vtotal;
862 } else {
863 /*
864 * ISR vblank status bits don't work the way we'd want
865 * them to work on non-PCH platforms (for
866 * ilk_pipe_in_vblank_locked()), and there doesn't
867 * appear any other way to determine if we're currently
868 * in vblank.
869 *
870 * Instead let's assume that we're already in vblank if
871 * we got called from the vblank interrupt and the
872 * scanline counter value indicates that we're on the
873 * line just prior to vblank start. This should result
874 * in the correct answer, unless the vblank interrupt
875 * delivery really got delayed for almost exactly one
876 * full frame/field.
877 */
878 if (flags & DRM_CALLED_FROM_VBLIRQ &&
879 position == vbl_start - 1) {
880 position = (position + 1) % vtotal;
881
882 /* Signal this correction as "applied". */
883 ret |= 0x8;
884 }
885 }
0af7e4df
MK		 886 } else {
887 /* Have access to pixelcount since start of frame.
888 * We can split this into vertical and horizontal
889 * scanout position.
890 */
ad3543ed 891 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
0af7e4df 892
3aa18df8
VS		 893 /* convert to pixel counts */
894 vbl_start *= htotal;
895 vbl_end *= htotal;
896 vtotal *= htotal;
0af7e4df
MK		 897 }
898
ad3543ed
MK		 899 /* Get optional system timestamp after query. */
900 if (etime)
901 *etime = ktime_get();
902
903 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
904
905 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
906
3aa18df8
VS		 907 in_vbl = position >= vbl_start && position < vbl_end;
908
909 /*
910 * While in vblank, position will be negative
911 * counting up towards 0 at vbl_end. And outside
912 * vblank, position will be positive counting
913 * up since vbl_end.
914 */
915 if (position >= vbl_start)
916 position -= vbl_end;
917 else
918 position += vtotal - vbl_end;
0af7e4df 919
7c06b08a 920 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3aa18df8
VS		 921 *vpos = position;
922 *hpos = 0;
923 } else {
924 *vpos = position / htotal;
925 *hpos = position - (*vpos * htotal);
926 }
0af7e4df 927
0af7e4df
MK		 928 /* In vblank? */
929 if (in_vbl)
930 ret |= DRM_SCANOUTPOS_INVBL;
931
932 return ret;
933}
934
f71d4af4 935static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 936 int *max_error,
937 struct timeval *vblank_time,
938 unsigned flags)
939{
4041b853 940 struct drm_crtc *crtc;
0af7e4df 941
7eb552ae 942 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 943 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 944 return -EINVAL;
945 }
946
947 /* Get drm_crtc to timestamp: */
4041b853
CW		 948 crtc = intel_get_crtc_for_pipe(dev, pipe);
949 if (crtc == NULL) {
950 DRM_ERROR("Invalid crtc %d\n", pipe);
951 return -EINVAL;
952 }
953
954 if (!crtc->enabled) {
955 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
956 return -EBUSY;
957 }
0af7e4df
MK		 958
959 /* Helper routine in DRM core does all the work: */
4041b853
CW		 960 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
961 vblank_time, flags,
7da903ef
VS		 962 crtc,
963 &to_intel_crtc(crtc)->config.adjusted_mode);
0af7e4df
MK		 964}
965
67c347ff
JN		 966static bool intel_hpd_irq_event(struct drm_device *dev,
967 struct drm_connector *connector)
321a1b30
EE		 968{
969 enum drm_connector_status old_status;
970
971 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
972 old_status = connector->status;
973
974 connector->status = connector->funcs->detect(connector, false);
67c347ff
JN		 975 if (old_status == connector->status)
976 return false;
977
978 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
321a1b30
EE		 979 connector->base.id,
980 drm_get_connector_name(connector),
67c347ff
JN		 981 drm_get_connector_status_name(old_status),
982 drm_get_connector_status_name(connector->status));
983
984 return true;
321a1b30
EE		 985}
986
5ca58282
JB		 987/*
988 * Handle hotplug events outside the interrupt handler proper.
989 */
ac4c16c5
EE		 990#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
991
5ca58282
JB		 992static void i915_hotplug_work_func(struct work_struct *work)
993{
2d1013dd
JN		 994 struct drm_i915_private *dev_priv =
995 container_of(work, struct drm_i915_private, hotplug_work);
5ca58282 996 struct drm_device *dev = dev_priv->dev;
c31c4ba3 997 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 998 struct intel_connector *intel_connector;
999 struct intel_encoder *intel_encoder;
1000 struct drm_connector *connector;
1001 unsigned long irqflags;
1002 bool hpd_disabled = false;
321a1b30 1003 bool changed = false;
142e2398 1004 u32 hpd_event_bits;
4ef69c7a 1005
52d7eced
DV		 1006 /* HPD irq before everything is fully set up. */
1007 if (!dev_priv->enable_hotplug_processing)
1008 return;
1009
a65e34c7 1010 mutex_lock(&mode_config->mutex);
e67189ab
JB		 1011 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1012
cd569aed 1013 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 1014
1015 hpd_event_bits = dev_priv->hpd_event_bits;
1016 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 1017 list_for_each_entry(connector, &mode_config->connector_list, head) {
1018 intel_connector = to_intel_connector(connector);
1019 intel_encoder = intel_connector->encoder;
1020 if (intel_encoder->hpd_pin > HPD_NONE &&
1021 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1022 connector->polled == DRM_CONNECTOR_POLL_HPD) {
1023 DRM_INFO("HPD interrupt storm detected on connector %s: "
1024 "switching from hotplug detection to polling\n",
1025 drm_get_connector_name(connector));
1026 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1027 connector->polled = DRM_CONNECTOR_POLL_CONNECT
1028 | DRM_CONNECTOR_POLL_DISCONNECT;
1029 hpd_disabled = true;
1030 }
142e2398
EE		 1031 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1032 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1033 drm_get_connector_name(connector), intel_encoder->hpd_pin);
1034 }
cd569aed
EE		 1035 }
1036 /* if there were no outputs to poll, poll was disabled,
1037 * therefore make sure it's enabled when disabling HPD on
1038 * some connectors */
ac4c16c5 1039 if (hpd_disabled) {
cd569aed 1040 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 1041 mod_timer(&dev_priv->hotplug_reenable_timer,
1042 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1043 }
cd569aed
EE		 1044
1045 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1046
321a1b30
EE		 1047 list_for_each_entry(connector, &mode_config->connector_list, head) {
1048 intel_connector = to_intel_connector(connector);
1049 intel_encoder = intel_connector->encoder;
1050 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1051 if (intel_encoder->hot_plug)
1052 intel_encoder->hot_plug(intel_encoder);
1053 if (intel_hpd_irq_event(dev, connector))
1054 changed = true;
1055 }
1056 }
40ee3381
KP		 1057 mutex_unlock(&mode_config->mutex);
1058
321a1b30
EE		 1059 if (changed)
1060 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 1061}
1062
3ca1cced
VS		 1063static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1064{
1065 del_timer_sync(&dev_priv->hotplug_reenable_timer);
1066}
1067
d0ecd7e2 1068static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1 1069{
2d1013dd 1070 struct drm_i915_private *dev_priv = dev->dev_private;
b5b72e89 1071 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 1072 u8 new_delay;
9270388e 1073
d0ecd7e2 1074 spin_lock(&mchdev_lock);
f97108d1 1075
73edd18f
DV		 1076 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1077
20e4d407 1078 new_delay = dev_priv->ips.cur_delay;
9270388e 1079
7648fa99 1080 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 1081 busy_up = I915_READ(RCPREVBSYTUPAVG);
1082 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 1083 max_avg = I915_READ(RCBMAXAVG);
1084 min_avg = I915_READ(RCBMINAVG);
1085
1086 /* Handle RCS change request from hw */
b5b72e89 1087 if (busy_up > max_avg) {
20e4d407
DV		 1088 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1089 new_delay = dev_priv->ips.cur_delay - 1;
1090 if (new_delay < dev_priv->ips.max_delay)
1091 new_delay = dev_priv->ips.max_delay;
b5b72e89 1092 } else if (busy_down < min_avg) {
20e4d407
DV		 1093 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1094 new_delay = dev_priv->ips.cur_delay + 1;
1095 if (new_delay > dev_priv->ips.min_delay)
1096 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 1097 }
1098
7648fa99 1099 if (ironlake_set_drps(dev, new_delay))
20e4d407 1100 dev_priv->ips.cur_delay = new_delay;
f97108d1 1101
d0ecd7e2 1102 spin_unlock(&mchdev_lock);
9270388e 1103
f97108d1
JB		 1104 return;
1105}
1106
549f7365
CW		 1107static void notify_ring(struct drm_device *dev,
1108 struct intel_ring_buffer *ring)
1109{
475553de
CW		 1110 if (ring->obj == NULL)
1111 return;
1112
814e9b57 1113 trace_i915_gem_request_complete(ring);
9862e600 1114
549f7365 1115 wake_up_all(&ring->irq_queue);
10cd45b6 1116 i915_queue_hangcheck(dev);
549f7365
CW		 1117}
1118
4912d041 1119static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 1120{
2d1013dd
JN		 1121 struct drm_i915_private *dev_priv =
1122 container_of(work, struct drm_i915_private, rps.work);
edbfdb45 1123 u32 pm_iir;
dd75fdc8 1124 int new_delay, adj;
4912d041 1125
59cdb63d 1126 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3
DV		 1127 pm_iir = dev_priv->rps.pm_iir;
1128 dev_priv->rps.pm_iir = 0;
4848405c 1129 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
a6706b45 1130 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
59cdb63d 1131 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 1132
60611c13 1133 /* Make sure we didn't queue anything we're not going to process. */
a6706b45 1134 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
60611c13 1135
a6706b45 1136 if ((pm_iir & dev_priv->pm_rps_events) == 0)
3b8d8d91
JB		 1137 return;
1138
4fc688ce 1139 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 1140
dd75fdc8 1141 adj = dev_priv->rps.last_adj;
7425034a 1142 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 1143 if (adj > 0)
1144 adj *= 2;
1145 else
1146 adj = 1;
b39fb297 1147 new_delay = dev_priv->rps.cur_freq + adj;
7425034a
VS		 1148
1149 /*
1150 * For better performance, jump directly
1151 * to RPe if we're below it.
1152 */
b39fb297
BW		 1153 if (new_delay < dev_priv->rps.efficient_freq)
1154 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 1155 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
b39fb297
BW		 1156 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1157 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 1158 else
b39fb297 1159 new_delay = dev_priv->rps.min_freq_softlimit;
dd75fdc8
CW		 1160 adj = 0;
1161 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1162 if (adj < 0)
1163 adj *= 2;
1164 else
1165 adj = -1;
b39fb297 1166 new_delay = dev_priv->rps.cur_freq + adj;
dd75fdc8 1167 } else { /* unknown event */
b39fb297 1168 new_delay = dev_priv->rps.cur_freq;
dd75fdc8 1169 }
3b8d8d91 1170
79249636
BW		 1171 /* sysfs frequency interfaces may have snuck in while servicing the
1172 * interrupt
1173 */
1272e7b8 1174 new_delay = clamp_t(int, new_delay,
b39fb297
BW		 1175 dev_priv->rps.min_freq_softlimit,
1176 dev_priv->rps.max_freq_softlimit);
27544369 1177
b39fb297 1178 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
dd75fdc8
CW		 1179
1180 if (IS_VALLEYVIEW(dev_priv->dev))
1181 valleyview_set_rps(dev_priv->dev, new_delay);
1182 else
1183 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 1184
4fc688ce 1185 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 1186}
1187
e3689190
BW		 1188
1189/**
1190 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1191 * occurred.
1192 * @work: workqueue struct
1193 *
1194 * Doesn't actually do anything except notify userspace. As a consequence of
1195 * this event, userspace should try to remap the bad rows since statistically
1196 * it is likely the same row is more likely to go bad again.
1197 */
1198static void ivybridge_parity_work(struct work_struct *work)
1199{
2d1013dd
JN		 1200 struct drm_i915_private *dev_priv =
1201 container_of(work, struct drm_i915_private, l3_parity.error_work);
e3689190 1202 u32 error_status, row, bank, subbank;
35a85ac6 1203 char *parity_event[6];
e3689190
BW		 1204 uint32_t misccpctl;
1205 unsigned long flags;
35a85ac6 1206 uint8_t slice = 0;
e3689190
BW		 1207
1208 /* We must turn off DOP level clock gating to access the L3 registers.
1209 * In order to prevent a get/put style interface, acquire struct mutex
1210 * any time we access those registers.
1211 */
1212 mutex_lock(&dev_priv->dev->struct_mutex);
1213
35a85ac6
BW		 1214 /* If we've screwed up tracking, just let the interrupt fire again */
1215 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1216 goto out;
1217
e3689190
BW		 1218 misccpctl = I915_READ(GEN7_MISCCPCTL);
1219 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1220 POSTING_READ(GEN7_MISCCPCTL);
1221
35a85ac6
BW		 1222 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1223 u32 reg;
e3689190 1224
35a85ac6
BW		 1225 slice--;
1226 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1227 break;
e3689190 1228
35a85ac6 1229 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 1230
35a85ac6 1231 reg = GEN7_L3CDERRST1 + (slice * 0x200);
e3689190 1232
35a85ac6
BW		 1233 error_status = I915_READ(reg);
1234 row = GEN7_PARITY_ERROR_ROW(error_status);
1235 bank = GEN7_PARITY_ERROR_BANK(error_status);
1236 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1237
1238 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1239 POSTING_READ(reg);
1240
1241 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1242 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1243 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1244 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1245 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1246 parity_event[5] = NULL;
1247
5bdebb18 1248 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
35a85ac6 1249 KOBJ_CHANGE, parity_event);
e3689190 1250
35a85ac6
BW		 1251 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1252 slice, row, bank, subbank);
e3689190 1253
35a85ac6
BW		 1254 kfree(parity_event[4]);
1255 kfree(parity_event[3]);
1256 kfree(parity_event[2]);
1257 kfree(parity_event[1]);
1258 }
e3689190 1259
35a85ac6 1260 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 1261
35a85ac6
BW		 1262out:
1263 WARN_ON(dev_priv->l3_parity.which_slice);
1264 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1265 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1266 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1267
1268 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 1269}
1270
35a85ac6 1271static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190 1272{
2d1013dd 1273 struct drm_i915_private *dev_priv = dev->dev_private;
e3689190 1274
040d2baa 1275 if (!HAS_L3_DPF(dev))
e3689190
BW		 1276 return;
1277
d0ecd7e2 1278 spin_lock(&dev_priv->irq_lock);
35a85ac6 1279 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 1280 spin_unlock(&dev_priv->irq_lock);
e3689190 1281
35a85ac6
BW		 1282 iir &= GT_PARITY_ERROR(dev);
1283 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1284 dev_priv->l3_parity.which_slice |= 1 << 1;
1285
1286 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1287 dev_priv->l3_parity.which_slice |= 1 << 0;
1288
a4da4fa4 1289 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1290}
1291
f1af8fc1
PZ		 1292static void ilk_gt_irq_handler(struct drm_device *dev,
1293 struct drm_i915_private *dev_priv,
1294 u32 gt_iir)
1295{
1296 if (gt_iir &
1297 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1298 notify_ring(dev, &dev_priv->ring[RCS]);
1299 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1300 notify_ring(dev, &dev_priv->ring[VCS]);
1301}
1302
e7b4c6b1
DV		 1303static void snb_gt_irq_handler(struct drm_device *dev,
1304 struct drm_i915_private *dev_priv,
1305 u32 gt_iir)
1306{
1307
cc609d5d
BW		 1308 if (gt_iir &
1309 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1310 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1311 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 1312 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 1313 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 1314 notify_ring(dev, &dev_priv->ring[BCS]);
1315
cc609d5d
BW		 1316 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1317 GT_BSD_CS_ERROR_INTERRUPT |
1318 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
58174462
MK		 1319 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1320 gt_iir);
e7b4c6b1 1321 }
e3689190 1322
35a85ac6
BW		 1323 if (gt_iir & GT_PARITY_ERROR(dev))
1324 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1325}
1326
abd58f01
BW		 1327static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1328 struct drm_i915_private *dev_priv,
1329 u32 master_ctl)
1330{
1331 u32 rcs, bcs, vcs;
1332 uint32_t tmp = 0;
1333 irqreturn_t ret = IRQ_NONE;
1334
1335 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1336 tmp = I915_READ(GEN8_GT_IIR(0));
1337 if (tmp) {
1338 ret = IRQ_HANDLED;
1339 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1340 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1341 if (rcs & GT_RENDER_USER_INTERRUPT)
1342 notify_ring(dev, &dev_priv->ring[RCS]);
1343 if (bcs & GT_RENDER_USER_INTERRUPT)
1344 notify_ring(dev, &dev_priv->ring[BCS]);
1345 I915_WRITE(GEN8_GT_IIR(0), tmp);
1346 } else
1347 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1348 }
1349
85f9b5f9 1350 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
abd58f01
BW		 1351 tmp = I915_READ(GEN8_GT_IIR(1));
1352 if (tmp) {
1353 ret = IRQ_HANDLED;
1354 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1355 if (vcs & GT_RENDER_USER_INTERRUPT)
1356 notify_ring(dev, &dev_priv->ring[VCS]);
85f9b5f9
ZY		 1357 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1358 if (vcs & GT_RENDER_USER_INTERRUPT)
1359 notify_ring(dev, &dev_priv->ring[VCS2]);
abd58f01
BW		 1360 I915_WRITE(GEN8_GT_IIR(1), tmp);
1361 } else
1362 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1363 }
1364
1365 if (master_ctl & GEN8_GT_VECS_IRQ) {
1366 tmp = I915_READ(GEN8_GT_IIR(3));
1367 if (tmp) {
1368 ret = IRQ_HANDLED;
1369 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1370 if (vcs & GT_RENDER_USER_INTERRUPT)
1371 notify_ring(dev, &dev_priv->ring[VECS]);
1372 I915_WRITE(GEN8_GT_IIR(3), tmp);
1373 } else
1374 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1375 }
1376
1377 return ret;
1378}
1379
b543fb04
EE		 1380#define HPD_STORM_DETECT_PERIOD 1000
1381#define HPD_STORM_THRESHOLD 5
1382
10a504de 1383static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 1384 u32 hotplug_trigger,
1385 const u32 *hpd)
b543fb04 1386{
2d1013dd 1387 struct drm_i915_private *dev_priv = dev->dev_private;
b543fb04 1388 int i;
10a504de 1389 bool storm_detected = false;
b543fb04 1390
91d131d2
DV		 1391 if (!hotplug_trigger)
1392 return;
1393
cc9bd499
ID		 1394 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1395 hotplug_trigger);
1396
b5ea2d56 1397 spin_lock(&dev_priv->irq_lock);
b543fb04 1398 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 1399
3ff04a16
DV		 1400 if (hpd[i] & hotplug_trigger &&
1401 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1402 /*
1403 * On GMCH platforms the interrupt mask bits only
1404 * prevent irq generation, not the setting of the
1405 * hotplug bits itself. So only WARN about unexpected
1406 * interrupts on saner platforms.
1407 */
1408 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1409 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1410 hotplug_trigger, i, hpd[i]);
1411
1412 continue;
1413 }
b8f102e8 1414
b543fb04
EE		 1415 if (!(hpd[i] & hotplug_trigger) ||
1416 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1417 continue;
1418
bc5ead8c 1419 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 1420 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1421 dev_priv->hpd_stats[i].hpd_last_jiffies
1422 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1423 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1424 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1425 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1426 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1427 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1428 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1429 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1430 storm_detected = true;
b543fb04
EE		 1431 } else {
1432 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1433 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1434 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1435 }
1436 }
1437
10a504de
DV		 1438 if (storm_detected)
1439 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1440 spin_unlock(&dev_priv->irq_lock);
5876fa0d 1441
645416f5
DV		 1442 /*
1443 * Our hotplug handler can grab modeset locks (by calling down into the
1444 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1445 * queue for otherwise the flush_work in the pageflip code will
1446 * deadlock.
1447 */
1448 schedule_work(&dev_priv->hotplug_work);
b543fb04
EE		 1449}
1450
515ac2bb
DV		 1451static void gmbus_irq_handler(struct drm_device *dev)
1452{
2d1013dd 1453 struct drm_i915_private *dev_priv = dev->dev_private;
28c70f16 1454
28c70f16 1455 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1456}
1457
ce99c256
DV		 1458static void dp_aux_irq_handler(struct drm_device *dev)
1459{
2d1013dd 1460 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 1461
9ee32fea 1462 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1463}
1464
8bf1e9f1 1465#if defined(CONFIG_DEBUG_FS)
277de95e
DV		 1466static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1467 uint32_t crc0, uint32_t crc1,
1468 uint32_t crc2, uint32_t crc3,
1469 uint32_t crc4)
8bf1e9f1
SH		 1470{
1471 struct drm_i915_private *dev_priv = dev->dev_private;
1472 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1473 struct intel_pipe_crc_entry *entry;
ac2300d4 1474 int head, tail;
b2c88f5b 1475
d538bbdf
DL		 1476 spin_lock(&pipe_crc->lock);
1477
0c912c79 1478 if (!pipe_crc->entries) {
d538bbdf 1479 spin_unlock(&pipe_crc->lock);
0c912c79
DL		 1480 DRM_ERROR("spurious interrupt\n");
1481 return;
1482 }
1483
d538bbdf
DL		 1484 head = pipe_crc->head;
1485 tail = pipe_crc->tail;
b2c88f5b
DL		 1486
1487 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
d538bbdf 1488 spin_unlock(&pipe_crc->lock);
b2c88f5b
DL		 1489 DRM_ERROR("CRC buffer overflowing\n");
1490 return;
1491 }
1492
1493 entry = &pipe_crc->entries[head];
8bf1e9f1 1494
8bc5e955 1495 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
eba94eb9
DV		 1496 entry->crc[0] = crc0;
1497 entry->crc[1] = crc1;
1498 entry->crc[2] = crc2;
1499 entry->crc[3] = crc3;
1500 entry->crc[4] = crc4;
b2c88f5b
DL		 1501
1502 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
d538bbdf
DL		 1503 pipe_crc->head = head;
1504
1505 spin_unlock(&pipe_crc->lock);
07144428
DL		 1506
1507 wake_up_interruptible(&pipe_crc->wq);
8bf1e9f1 1508}
277de95e
DV		 1509#else
1510static inline void
1511display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1512 uint32_t crc0, uint32_t crc1,
1513 uint32_t crc2, uint32_t crc3,
1514 uint32_t crc4) {}
1515#endif
1516
eba94eb9 1517
277de95e 1518static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5a69b89f
DV		 1519{
1520 struct drm_i915_private *dev_priv = dev->dev_private;
1521
277de95e
DV		 1522 display_pipe_crc_irq_handler(dev, pipe,
1523 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1524 0, 0, 0, 0);
5a69b89f
DV		 1525}
1526
277de95e 1527static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
eba94eb9
DV		 1528{
1529 struct drm_i915_private *dev_priv = dev->dev_private;
1530
277de95e
DV		 1531 display_pipe_crc_irq_handler(dev, pipe,
1532 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1533 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1534 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1535 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1536 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
eba94eb9 1537}
5b3a856b 1538
277de95e 1539static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5b3a856b
DV		 1540{
1541 struct drm_i915_private *dev_priv = dev->dev_private;
0b5c5ed0
DV		 1542 uint32_t res1, res2;
1543
1544 if (INTEL_INFO(dev)->gen >= 3)
1545 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1546 else
1547 res1 = 0;
1548
1549 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1550 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1551 else
1552 res2 = 0;
5b3a856b 1553
277de95e
DV		 1554 display_pipe_crc_irq_handler(dev, pipe,
1555 I915_READ(PIPE_CRC_RES_RED(pipe)),
1556 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1557 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1558 res1, res2);
5b3a856b 1559}
8bf1e9f1 1560
1403c0d4
PZ		 1561/* The RPS events need forcewake, so we add them to a work queue and mask their
1562 * IMR bits until the work is done. Other interrupts can be processed without
1563 * the work queue. */
1564static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1565{
a6706b45 1566 if (pm_iir & dev_priv->pm_rps_events) {
59cdb63d 1567 spin_lock(&dev_priv->irq_lock);
a6706b45
D		 1568 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1569 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
59cdb63d 1570 spin_unlock(&dev_priv->irq_lock);
2adbee62
DV		 1571
1572 queue_work(dev_priv->wq, &dev_priv->rps.work);
baf02a1f 1573 }
baf02a1f 1574
1403c0d4
PZ		 1575 if (HAS_VEBOX(dev_priv->dev)) {
1576 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1577 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 1578
1403c0d4 1579 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
58174462
MK		 1580 i915_handle_error(dev_priv->dev, false,
1581 "VEBOX CS error interrupt 0x%08x",
1582 pm_iir);
1403c0d4 1583 }
12638c57 1584 }
baf02a1f
BW		 1585}
1586
c1874ed7
ID		 1587static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1588{
1589 struct drm_i915_private *dev_priv = dev->dev_private;
91d181dd 1590 u32 pipe_stats[I915_MAX_PIPES] = { };
c1874ed7
ID		 1591 int pipe;
1592
58ead0d7 1593 spin_lock(&dev_priv->irq_lock);
c1874ed7 1594 for_each_pipe(pipe) {
91d181dd 1595 int reg;
bbb5eebf 1596 u32 mask, iir_bit = 0;
91d181dd 1597
bbb5eebf
DV		 1598 /*
1599 * PIPESTAT bits get signalled even when the interrupt is
1600 * disabled with the mask bits, and some of the status bits do
1601 * not generate interrupts at all (like the underrun bit). Hence
1602 * we need to be careful that we only handle what we want to
1603 * handle.
1604 */
1605 mask = 0;
1606 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1607 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1608
1609 switch (pipe) {
1610 case PIPE_A:
1611 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1612 break;
1613 case PIPE_B:
1614 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1615 break;
1616 }
1617 if (iir & iir_bit)
1618 mask |= dev_priv->pipestat_irq_mask[pipe];
1619
1620 if (!mask)
91d181dd
ID		 1621 continue;
1622
1623 reg = PIPESTAT(pipe);
bbb5eebf
DV		 1624 mask |= PIPESTAT_INT_ENABLE_MASK;
1625 pipe_stats[pipe] = I915_READ(reg) & mask;
c1874ed7
ID		 1626
1627 /*
1628 * Clear the PIPE*STAT regs before the IIR
1629 */
91d181dd
ID		 1630 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1631 PIPESTAT_INT_STATUS_MASK))
c1874ed7
ID		 1632 I915_WRITE(reg, pipe_stats[pipe]);
1633 }
58ead0d7 1634 spin_unlock(&dev_priv->irq_lock);
c1874ed7
ID		 1635
1636 for_each_pipe(pipe) {
1637 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1638 drm_handle_vblank(dev, pipe);
1639
579a9b0e 1640 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
c1874ed7
ID		 1641 intel_prepare_page_flip(dev, pipe);
1642 intel_finish_page_flip(dev, pipe);
1643 }
1644
1645 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1646 i9xx_pipe_crc_irq_handler(dev, pipe);
1647
1648 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1649 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1650 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1651 }
1652
1653 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1654 gmbus_irq_handler(dev);
1655}
1656
16c6c56b
VS		 1657static void i9xx_hpd_irq_handler(struct drm_device *dev)
1658{
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1661
1662 if (IS_G4X(dev)) {
1663 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1664
1665 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
1666 } else {
1667 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1668
1669 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1670 }
1671
1672 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1673 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1674 dp_aux_irq_handler(dev);
1675
1676 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1677 /*
1678 * Make sure hotplug status is cleared before we clear IIR, or else we
1679 * may miss hotplug events.
1680 */
1681 POSTING_READ(PORT_HOTPLUG_STAT);
1682}
1683
ff1f525e 1684static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 1685{
1686 struct drm_device *dev = (struct drm_device *) arg;
2d1013dd 1687 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 1688 u32 iir, gt_iir, pm_iir;
1689 irqreturn_t ret = IRQ_NONE;
7e231dbe 1690
7e231dbe
JB		 1691 while (true) {
1692 iir = I915_READ(VLV_IIR);
1693 gt_iir = I915_READ(GTIIR);
1694 pm_iir = I915_READ(GEN6_PMIIR);
1695
1696 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1697 goto out;
1698
1699 ret = IRQ_HANDLED;
1700
e7b4c6b1 1701 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe 1702
c1874ed7 1703 valleyview_pipestat_irq_handler(dev, iir);
31acc7f5 1704
7e231dbe 1705 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 1706 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1707 i9xx_hpd_irq_handler(dev);
7e231dbe 1708
60611c13 1709 if (pm_iir)
d0ecd7e2 1710 gen6_rps_irq_handler(dev_priv, pm_iir);
7e231dbe
JB		 1711
1712 I915_WRITE(GTIIR, gt_iir);
1713 I915_WRITE(GEN6_PMIIR, pm_iir);
1714 I915_WRITE(VLV_IIR, iir);
1715 }
1716
1717out:
1718 return ret;
1719}
1720
23e81d69 1721static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806 1722{
2d1013dd 1723 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 1724 int pipe;
b543fb04 1725 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1726
91d131d2
DV		 1727 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1728
cfc33bf7
VS		 1729 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1730 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1731 SDE_AUDIO_POWER_SHIFT);
776ad806 1732 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1733 port_name(port));
1734 }
776ad806 1735
ce99c256
DV		 1736 if (pch_iir & SDE_AUX_MASK)
1737 dp_aux_irq_handler(dev);
1738
776ad806 1739 if (pch_iir & SDE_GMBUS)
515ac2bb 1740 gmbus_irq_handler(dev);
776ad806
JB		 1741
1742 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1743 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1744
1745 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1746 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1747
1748 if (pch_iir & SDE_POISON)
1749 DRM_ERROR("PCH poison interrupt\n");
1750
9db4a9c7
JB		 1751 if (pch_iir & SDE_FDI_MASK)
1752 for_each_pipe(pipe)
1753 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1754 pipe_name(pipe),
1755 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1756
1757 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1758 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1759
1760 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1761 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1762
776ad806 1763 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1764 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1765 false))
fc2c807b 1766 DRM_ERROR("PCH transcoder A FIFO underrun\n");
8664281b
PZ		 1767
1768 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1769 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1770 false))
fc2c807b 1771 DRM_ERROR("PCH transcoder B FIFO underrun\n");
8664281b
PZ		 1772}
1773
1774static void ivb_err_int_handler(struct drm_device *dev)
1775{
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 u32 err_int = I915_READ(GEN7_ERR_INT);
5a69b89f 1778 enum pipe pipe;
8664281b 1779
de032bf4
PZ		 1780 if (err_int & ERR_INT_POISON)
1781 DRM_ERROR("Poison interrupt\n");
1782
5a69b89f
DV		 1783 for_each_pipe(pipe) {
1784 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1785 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1786 false))
fc2c807b
VS		 1787 DRM_ERROR("Pipe %c FIFO underrun\n",
1788 pipe_name(pipe));
5a69b89f 1789 }
8bf1e9f1 1790
5a69b89f
DV		 1791 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1792 if (IS_IVYBRIDGE(dev))
277de95e 1793 ivb_pipe_crc_irq_handler(dev, pipe);
5a69b89f 1794 else
277de95e 1795 hsw_pipe_crc_irq_handler(dev, pipe);
5a69b89f
DV		 1796 }
1797 }
8bf1e9f1 1798
8664281b
PZ		 1799 I915_WRITE(GEN7_ERR_INT, err_int);
1800}
1801
1802static void cpt_serr_int_handler(struct drm_device *dev)
1803{
1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805 u32 serr_int = I915_READ(SERR_INT);
1806
de032bf4
PZ		 1807 if (serr_int & SERR_INT_POISON)
1808 DRM_ERROR("PCH poison interrupt\n");
1809
8664281b
PZ		 1810 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1811 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1812 false))
fc2c807b 1813 DRM_ERROR("PCH transcoder A FIFO underrun\n");
8664281b
PZ		 1814
1815 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1816 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1817 false))
fc2c807b 1818 DRM_ERROR("PCH transcoder B FIFO underrun\n");
8664281b
PZ		 1819
1820 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1821 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1822 false))
fc2c807b 1823 DRM_ERROR("PCH transcoder C FIFO underrun\n");
8664281b
PZ		 1824
1825 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1826}
1827
23e81d69
AJ		 1828static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1829{
2d1013dd 1830 struct drm_i915_private *dev_priv = dev->dev_private;
23e81d69 1831 int pipe;
b543fb04 1832 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1833
91d131d2
DV		 1834 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1835
cfc33bf7
VS		 1836 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1837 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1838 SDE_AUDIO_POWER_SHIFT_CPT);
1839 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1840 port_name(port));
1841 }
23e81d69
AJ		 1842
1843 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1844 dp_aux_irq_handler(dev);
23e81d69
AJ		 1845
1846 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1847 gmbus_irq_handler(dev);
23e81d69
AJ		 1848
1849 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1850 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1851
1852 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1853 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1854
1855 if (pch_iir & SDE_FDI_MASK_CPT)
1856 for_each_pipe(pipe)
1857 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1858 pipe_name(pipe),
1859 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1860
1861 if (pch_iir & SDE_ERROR_CPT)
1862 cpt_serr_int_handler(dev);
23e81d69
AJ		 1863}
1864
c008bc6e
PZ		 1865static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1866{
1867 struct drm_i915_private *dev_priv = dev->dev_private;
40da17c2 1868 enum pipe pipe;
c008bc6e
PZ		 1869
1870 if (de_iir & DE_AUX_CHANNEL_A)
1871 dp_aux_irq_handler(dev);
1872
1873 if (de_iir & DE_GSE)
1874 intel_opregion_asle_intr(dev);
1875
c008bc6e
PZ		 1876 if (de_iir & DE_POISON)
1877 DRM_ERROR("Poison interrupt\n");
1878
40da17c2
DV		 1879 for_each_pipe(pipe) {
1880 if (de_iir & DE_PIPE_VBLANK(pipe))
1881 drm_handle_vblank(dev, pipe);
5b3a856b 1882
40da17c2
DV		 1883 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1884 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b
VS		 1885 DRM_ERROR("Pipe %c FIFO underrun\n",
1886 pipe_name(pipe));
5b3a856b 1887
40da17c2
DV		 1888 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1889 i9xx_pipe_crc_irq_handler(dev, pipe);
c008bc6e 1890
40da17c2
DV		 1891 /* plane/pipes map 1:1 on ilk+ */
1892 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1893 intel_prepare_page_flip(dev, pipe);
1894 intel_finish_page_flip_plane(dev, pipe);
1895 }
c008bc6e
PZ		 1896 }
1897
1898 /* check event from PCH */
1899 if (de_iir & DE_PCH_EVENT) {
1900 u32 pch_iir = I915_READ(SDEIIR);
1901
1902 if (HAS_PCH_CPT(dev))
1903 cpt_irq_handler(dev, pch_iir);
1904 else
1905 ibx_irq_handler(dev, pch_iir);
1906
1907 /* should clear PCH hotplug event before clear CPU irq */
1908 I915_WRITE(SDEIIR, pch_iir);
1909 }
1910
1911 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1912 ironlake_rps_change_irq_handler(dev);
1913}
1914
9719fb98
PZ		 1915static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1916{
1917 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 1918 enum pipe pipe;
9719fb98
PZ		 1919
1920 if (de_iir & DE_ERR_INT_IVB)
1921 ivb_err_int_handler(dev);
1922
1923 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1924 dp_aux_irq_handler(dev);
1925
1926 if (de_iir & DE_GSE_IVB)
1927 intel_opregion_asle_intr(dev);
1928
07d27e20
DL		 1929 for_each_pipe(pipe) {
1930 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
1931 drm_handle_vblank(dev, pipe);
40da17c2
DV		 1932
1933 /* plane/pipes map 1:1 on ilk+ */
07d27e20
DL		 1934 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
1935 intel_prepare_page_flip(dev, pipe);
1936 intel_finish_page_flip_plane(dev, pipe);
9719fb98
PZ		 1937 }
1938 }
1939
1940 /* check event from PCH */
1941 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1942 u32 pch_iir = I915_READ(SDEIIR);
1943
1944 cpt_irq_handler(dev, pch_iir);
1945
1946 /* clear PCH hotplug event before clear CPU irq */
1947 I915_WRITE(SDEIIR, pch_iir);
1948 }
1949}
1950
f1af8fc1 1951static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1952{
1953 struct drm_device *dev = (struct drm_device *) arg;
2d1013dd 1954 struct drm_i915_private *dev_priv = dev->dev_private;
f1af8fc1 1955 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 1956 irqreturn_t ret = IRQ_NONE;
b1f14ad0 1957
8664281b
PZ		 1958 /* We get interrupts on unclaimed registers, so check for this before we
1959 * do any I915_{READ,WRITE}. */
907b28c5 1960 intel_uncore_check_errors(dev);
8664281b 1961
b1f14ad0
JB		 1962 /* disable master interrupt before clearing iir */
1963 de_ier = I915_READ(DEIER);
1964 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 1965 POSTING_READ(DEIER);
b1f14ad0 1966
44498aea
PZ		 1967 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1968 * interrupts will will be stored on its back queue, and then we'll be
1969 * able to process them after we restore SDEIER (as soon as we restore
1970 * it, we'll get an interrupt if SDEIIR still has something to process
1971 * due to its back queue). */
ab5c608b
BW		 1972 if (!HAS_PCH_NOP(dev)) {
1973 sde_ier = I915_READ(SDEIER);
1974 I915_WRITE(SDEIER, 0);
1975 POSTING_READ(SDEIER);
1976 }
44498aea 1977
b1f14ad0 1978 gt_iir = I915_READ(GTIIR);
0e43406b 1979 if (gt_iir) {
d8fc8a47 1980 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 1981 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 1982 else
1983 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
0e43406b
CW		 1984 I915_WRITE(GTIIR, gt_iir);
1985 ret = IRQ_HANDLED;
b1f14ad0
JB		 1986 }
1987
0e43406b
CW		 1988 de_iir = I915_READ(DEIIR);
1989 if (de_iir) {
f1af8fc1
PZ		 1990 if (INTEL_INFO(dev)->gen >= 7)
1991 ivb_display_irq_handler(dev, de_iir);
1992 else
1993 ilk_display_irq_handler(dev, de_iir);
0e43406b
CW		 1994 I915_WRITE(DEIIR, de_iir);
1995 ret = IRQ_HANDLED;
b1f14ad0
JB		 1996 }
1997
f1af8fc1
PZ		 1998 if (INTEL_INFO(dev)->gen >= 6) {
1999 u32 pm_iir = I915_READ(GEN6_PMIIR);
2000 if (pm_iir) {
1403c0d4 2001 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1
PZ		 2002 I915_WRITE(GEN6_PMIIR, pm_iir);
2003 ret = IRQ_HANDLED;
2004 }
0e43406b 2005 }
b1f14ad0 2006
b1f14ad0
JB		 2007 I915_WRITE(DEIER, de_ier);
2008 POSTING_READ(DEIER);
ab5c608b
BW		 2009 if (!HAS_PCH_NOP(dev)) {
2010 I915_WRITE(SDEIER, sde_ier);
2011 POSTING_READ(SDEIER);
2012 }
b1f14ad0
JB		 2013
2014 return ret;
2015}
2016
abd58f01
BW		 2017static irqreturn_t gen8_irq_handler(int irq, void *arg)
2018{
2019 struct drm_device *dev = arg;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 u32 master_ctl;
2022 irqreturn_t ret = IRQ_NONE;
2023 uint32_t tmp = 0;
c42664cc 2024 enum pipe pipe;
abd58f01 2025
abd58f01
BW		 2026 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2027 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2028 if (!master_ctl)
2029 return IRQ_NONE;
2030
2031 I915_WRITE(GEN8_MASTER_IRQ, 0);
2032 POSTING_READ(GEN8_MASTER_IRQ);
2033
2034 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2035
2036 if (master_ctl & GEN8_DE_MISC_IRQ) {
2037 tmp = I915_READ(GEN8_DE_MISC_IIR);
2038 if (tmp & GEN8_DE_MISC_GSE)
2039 intel_opregion_asle_intr(dev);
2040 else if (tmp)
2041 DRM_ERROR("Unexpected DE Misc interrupt\n");
2042 else
2043 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2044
2045 if (tmp) {
2046 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2047 ret = IRQ_HANDLED;
2048 }
2049 }
2050
6d766f02
DV		 2051 if (master_ctl & GEN8_DE_PORT_IRQ) {
2052 tmp = I915_READ(GEN8_DE_PORT_IIR);
2053 if (tmp & GEN8_AUX_CHANNEL_A)
2054 dp_aux_irq_handler(dev);
2055 else if (tmp)
2056 DRM_ERROR("Unexpected DE Port interrupt\n");
2057 else
2058 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2059
2060 if (tmp) {
2061 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2062 ret = IRQ_HANDLED;
2063 }
2064 }
2065
c42664cc
DV		 2066 for_each_pipe(pipe) {
2067 uint32_t pipe_iir;
abd58f01 2068
c42664cc
DV		 2069 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2070 continue;
abd58f01 2071
c42664cc
DV		 2072 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2073 if (pipe_iir & GEN8_PIPE_VBLANK)
2074 drm_handle_vblank(dev, pipe);
abd58f01 2075
d0e1f1cb 2076 if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) {
c42664cc
DV		 2077 intel_prepare_page_flip(dev, pipe);
2078 intel_finish_page_flip_plane(dev, pipe);
abd58f01 2079 }
c42664cc 2080
0fbe7870
DV		 2081 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2082 hsw_pipe_crc_irq_handler(dev, pipe);
2083
38d83c96
DV		 2084 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2085 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2086 false))
fc2c807b
VS		 2087 DRM_ERROR("Pipe %c FIFO underrun\n",
2088 pipe_name(pipe));
38d83c96
DV		 2089 }
2090
30100f2b
DV		 2091 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2092 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2093 pipe_name(pipe),
2094 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2095 }
c42664cc
DV		 2096
2097 if (pipe_iir) {
2098 ret = IRQ_HANDLED;
2099 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2100 } else
abd58f01
BW		 2101 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2102 }
2103
92d03a80
DV		 2104 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2105 /*
2106 * FIXME(BDW): Assume for now that the new interrupt handling
2107 * scheme also closed the SDE interrupt handling race we've seen
2108 * on older pch-split platforms. But this needs testing.
2109 */
2110 u32 pch_iir = I915_READ(SDEIIR);
2111
2112 cpt_irq_handler(dev, pch_iir);
2113
2114 if (pch_iir) {
2115 I915_WRITE(SDEIIR, pch_iir);
2116 ret = IRQ_HANDLED;
2117 }
2118 }
2119
abd58f01
BW		 2120 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2121 POSTING_READ(GEN8_MASTER_IRQ);
2122
2123 return ret;
2124}
2125
17e1df07
DV		 2126static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2127 bool reset_completed)
2128{
2129 struct intel_ring_buffer *ring;
2130 int i;
2131
2132 /*
2133 * Notify all waiters for GPU completion events that reset state has
2134 * been changed, and that they need to restart their wait after
2135 * checking for potential errors (and bail out to drop locks if there is
2136 * a gpu reset pending so that i915_error_work_func can acquire them).
2137 */
2138
2139 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2140 for_each_ring(ring, dev_priv, i)
2141 wake_up_all(&ring->irq_queue);
2142
2143 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2144 wake_up_all(&dev_priv->pending_flip_queue);
2145
2146 /*
2147 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2148 * reset state is cleared.
2149 */
2150 if (reset_completed)
2151 wake_up_all(&dev_priv->gpu_error.reset_queue);
2152}
2153
8a905236
JB		 2154/**
2155 * i915_error_work_func - do process context error handling work
2156 * @work: work struct
2157 *
2158 * Fire an error uevent so userspace can see that a hang or error
2159 * was detected.
2160 */
2161static void i915_error_work_func(struct work_struct *work)
2162{
1f83fee0
DV		 2163 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2164 work);
2d1013dd
JN		 2165 struct drm_i915_private *dev_priv =
2166 container_of(error, struct drm_i915_private, gpu_error);
8a905236 2167 struct drm_device *dev = dev_priv->dev;
cce723ed
BW		 2168 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2169 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2170 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 2171 int ret;
8a905236 2172
5bdebb18 2173 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
f316a42c 2174
7db0ba24
DV		 2175 /*
2176 * Note that there's only one work item which does gpu resets, so we
2177 * need not worry about concurrent gpu resets potentially incrementing
2178 * error->reset_counter twice. We only need to take care of another
2179 * racing irq/hangcheck declaring the gpu dead for a second time. A
2180 * quick check for that is good enough: schedule_work ensures the
2181 * correct ordering between hang detection and this work item, and since
2182 * the reset in-progress bit is only ever set by code outside of this
2183 * work we don't need to worry about any other races.
2184 */
2185 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 2186 DRM_DEBUG_DRIVER("resetting chip\n");
5bdebb18 2187 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
7db0ba24 2188 reset_event);
1f83fee0 2189
f454c694
ID		 2190 /*
2191 * In most cases it's guaranteed that we get here with an RPM
2192 * reference held, for example because there is a pending GPU
2193 * request that won't finish until the reset is done. This
2194 * isn't the case at least when we get here by doing a
2195 * simulated reset via debugs, so get an RPM reference.
2196 */
2197 intel_runtime_pm_get(dev_priv);
17e1df07
DV		 2198 /*
2199 * All state reset _must_ be completed before we update the
2200 * reset counter, for otherwise waiters might miss the reset
2201 * pending state and not properly drop locks, resulting in
2202 * deadlocks with the reset work.
2203 */
f69061be
DV		 2204 ret = i915_reset(dev);
2205
17e1df07
DV		 2206 intel_display_handle_reset(dev);
2207
f454c694
ID		 2208 intel_runtime_pm_put(dev_priv);
2209
f69061be
DV		 2210 if (ret == 0) {
2211 /*
2212 * After all the gem state is reset, increment the reset
2213 * counter and wake up everyone waiting for the reset to
2214 * complete.
2215 *
2216 * Since unlock operations are a one-sided barrier only,
2217 * we need to insert a barrier here to order any seqno
2218 * updates before
2219 * the counter increment.
2220 */
2221 smp_mb__before_atomic_inc();
2222 atomic_inc(&dev_priv->gpu_error.reset_counter);
2223
5bdebb18 2224 kobject_uevent_env(&dev->primary->kdev->kobj,
f69061be 2225 KOBJ_CHANGE, reset_done_event);
1f83fee0 2226 } else {
2ac0f450 2227 atomic_set_mask(I915_WEDGED, &error->reset_counter);
f316a42c 2228 }
1f83fee0 2229
17e1df07
DV		 2230 /*
2231 * Note: The wake_up also serves as a memory barrier so that
2232 * waiters see the update value of the reset counter atomic_t.
2233 */
2234 i915_error_wake_up(dev_priv, true);
f316a42c 2235 }
8a905236
JB		 2236}
2237
35aed2e6 2238static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2239{
2240 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2241 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2242 u32 eir = I915_READ(EIR);
050ee91f 2243 int pipe, i;
8a905236 2244
35aed2e6
CW		 2245 if (!eir)
2246 return;
8a905236 2247
a70491cc 2248 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2249
bd9854f9
BW		 2250 i915_get_extra_instdone(dev, instdone);
2251
8a905236
JB		 2252 if (IS_G4X(dev)) {
2253 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2254 u32 ipeir = I915_READ(IPEIR_I965);
2255
a70491cc
JP		 2256 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2257 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2258 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2259 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2260 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2261 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2262 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2263 POSTING_READ(IPEIR_I965);
8a905236
JB		 2264 }
2265 if (eir & GM45_ERROR_PAGE_TABLE) {
2266 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2267 pr_err("page table error\n");
2268 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2269 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2270 POSTING_READ(PGTBL_ER);
8a905236
JB		 2271 }
2272 }
2273
a6c45cf0 2274 if (!IS_GEN2(dev)) {
8a905236
JB		 2275 if (eir & I915_ERROR_PAGE_TABLE) {
2276 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2277 pr_err("page table error\n");
2278 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2279 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2280 POSTING_READ(PGTBL_ER);
8a905236
JB		 2281 }
2282 }
2283
2284 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2285 pr_err("memory refresh error:\n");
9db4a9c7 2286 for_each_pipe(pipe)
a70491cc 2287 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2288 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2289 /* pipestat has already been acked */
2290 }
2291 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2292 pr_err("instruction error\n");
2293 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2294 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2295 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2296 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2297 u32 ipeir = I915_READ(IPEIR);
2298
a70491cc
JP		 2299 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2300 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2301 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2302 I915_WRITE(IPEIR, ipeir);
3143a2bf 2303 POSTING_READ(IPEIR);
8a905236
JB		 2304 } else {
2305 u32 ipeir = I915_READ(IPEIR_I965);
2306
a70491cc
JP		 2307 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2308 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2309 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2310 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2311 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2312 POSTING_READ(IPEIR_I965);
8a905236
JB		 2313 }
2314 }
2315
2316 I915_WRITE(EIR, eir);
3143a2bf 2317 POSTING_READ(EIR);
8a905236
JB		 2318 eir = I915_READ(EIR);
2319 if (eir) {
2320 /*
2321 * some errors might have become stuck,
2322 * mask them.
2323 */
2324 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2325 I915_WRITE(EMR, I915_READ(EMR) | eir);
2326 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2327 }
35aed2e6
CW		 2328}
2329
2330/**
2331 * i915_handle_error - handle an error interrupt
2332 * @dev: drm device
2333 *
2334 * Do some basic checking of regsiter state at error interrupt time and
2335 * dump it to the syslog. Also call i915_capture_error_state() to make
2336 * sure we get a record and make it available in debugfs. Fire a uevent
2337 * so userspace knows something bad happened (should trigger collection
2338 * of a ring dump etc.).
2339 */
58174462
MK		 2340void i915_handle_error(struct drm_device *dev, bool wedged,
2341 const char *fmt, ...)
35aed2e6
CW		 2342{
2343 struct drm_i915_private *dev_priv = dev->dev_private;
58174462
MK		 2344 va_list args;
2345 char error_msg[80];
35aed2e6 2346
58174462
MK		 2347 va_start(args, fmt);
2348 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2349 va_end(args);
2350
2351 i915_capture_error_state(dev, wedged, error_msg);
35aed2e6 2352 i915_report_and_clear_eir(dev);
8a905236 2353
ba1234d1 2354 if (wedged) {
f69061be
DV		 2355 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2356 &dev_priv->gpu_error.reset_counter);
ba1234d1 2357
11ed50ec 2358 /*
17e1df07
DV		 2359 * Wakeup waiting processes so that the reset work function
2360 * i915_error_work_func doesn't deadlock trying to grab various
2361 * locks. By bumping the reset counter first, the woken
2362 * processes will see a reset in progress and back off,
2363 * releasing their locks and then wait for the reset completion.
2364 * We must do this for _all_ gpu waiters that might hold locks
2365 * that the reset work needs to acquire.
2366 *
2367 * Note: The wake_up serves as the required memory barrier to
2368 * ensure that the waiters see the updated value of the reset
2369 * counter atomic_t.
11ed50ec 2370 */
17e1df07 2371 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 2372 }
2373
122f46ba
DV		 2374 /*
2375 * Our reset work can grab modeset locks (since it needs to reset the
2376 * state of outstanding pagelips). Hence it must not be run on our own
2377 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2378 * code will deadlock.
2379 */
2380 schedule_work(&dev_priv->gpu_error.work);
8a905236
JB		 2381}
2382
21ad8330 2383static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd 2384{
2d1013dd 2385 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd
SF		 2386 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2388 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2389 struct intel_unpin_work *work;
2390 unsigned long flags;
2391 bool stall_detected;
2392
2393 /* Ignore early vblank irqs */
2394 if (intel_crtc == NULL)
2395 return;
2396
2397 spin_lock_irqsave(&dev->event_lock, flags);
2398 work = intel_crtc->unpin_work;
2399
e7d841ca
CW		 2400 if (work == NULL ||
2401 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2402 !work->enable_stall_check) {
4e5359cd
SF		 2403 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2404 spin_unlock_irqrestore(&dev->event_lock, flags);
2405 return;
2406 }
2407
2408 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2409 obj = work->pending_flip_obj;
a6c45cf0 2410 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2411 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 2412 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 2413 i915_gem_obj_ggtt_offset(obj);
4e5359cd 2414 } else {
9db4a9c7 2415 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 2416 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
f4510a27
MR		 2417 crtc->y * crtc->primary->fb->pitches[0] +
2418 crtc->x * crtc->primary->fb->bits_per_pixel/8);
4e5359cd
SF		 2419 }
2420
2421 spin_unlock_irqrestore(&dev->event_lock, flags);
2422
2423 if (stall_detected) {
2424 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2425 intel_prepare_page_flip(dev, intel_crtc->plane);
2426 }
2427}
2428
42f52ef8
KP		 2429/* Called from drm generic code, passed 'crtc' which
2430 * we use as a pipe index
2431 */
f71d4af4 2432static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2433{
2d1013dd 2434 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2435 unsigned long irqflags;
71e0ffa5 2436
5eddb70b 2437 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2438 return -EINVAL;
0a3e67a4 2439
1ec14ad3 2440 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2441 if (INTEL_INFO(dev)->gen >= 4)
7c463586 2442 i915_enable_pipestat(dev_priv, pipe,
755e9019 2443 PIPE_START_VBLANK_INTERRUPT_STATUS);
e9d21d7f 2444 else
7c463586 2445 i915_enable_pipestat(dev_priv, pipe,
755e9019 2446 PIPE_VBLANK_INTERRUPT_STATUS);
8692d00e
CW		 2447
2448 /* maintain vblank delivery even in deep C-states */
3d13ef2e 2449 if (INTEL_INFO(dev)->gen == 3)
6b26c86d 2450 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 2451 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2452
0a3e67a4
JB		 2453 return 0;
2454}
2455
f71d4af4 2456static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2457{
2d1013dd 2458 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2459 unsigned long irqflags;
b518421f 2460 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2461 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2462
2463 if (!i915_pipe_enabled(dev, pipe))
2464 return -EINVAL;
2465
2466 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2467 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2468 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2469
2470 return 0;
2471}
2472
7e231dbe
JB		 2473static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2474{
2d1013dd 2475 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2476 unsigned long irqflags;
7e231dbe
JB		 2477
2478 if (!i915_pipe_enabled(dev, pipe))
2479 return -EINVAL;
2480
2481 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2482 i915_enable_pipestat(dev_priv, pipe,
755e9019 2483 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2484 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2485
2486 return 0;
2487}
2488
abd58f01
BW		 2489static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2490{
2491 struct drm_i915_private *dev_priv = dev->dev_private;
2492 unsigned long irqflags;
abd58f01
BW		 2493
2494 if (!i915_pipe_enabled(dev, pipe))
2495 return -EINVAL;
2496
2497 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2498 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2499 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2500 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2501 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2502 return 0;
2503}
2504
42f52ef8
KP		 2505/* Called from drm generic code, passed 'crtc' which
2506 * we use as a pipe index
2507 */
f71d4af4 2508static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2509{
2d1013dd 2510 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2511 unsigned long irqflags;
0a3e67a4 2512
1ec14ad3 2513 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3d13ef2e 2514 if (INTEL_INFO(dev)->gen == 3)
6b26c86d 2515 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2516
f796cf8f 2517 i915_disable_pipestat(dev_priv, pipe,
755e9019
ID		 2518 PIPE_VBLANK_INTERRUPT_STATUS |
2519 PIPE_START_VBLANK_INTERRUPT_STATUS);
f796cf8f
JB		 2520 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2521}
2522
f71d4af4 2523static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2524{
2d1013dd 2525 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2526 unsigned long irqflags;
b518421f 2527 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2528 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2529
2530 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2531 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2532 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2533}
2534
7e231dbe
JB		 2535static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2536{
2d1013dd 2537 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2538 unsigned long irqflags;
7e231dbe
JB		 2539
2540 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2541 i915_disable_pipestat(dev_priv, pipe,
755e9019 2542 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2543 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2544}
2545
abd58f01
BW		 2546static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2547{
2548 struct drm_i915_private *dev_priv = dev->dev_private;
2549 unsigned long irqflags;
abd58f01
BW		 2550
2551 if (!i915_pipe_enabled(dev, pipe))
2552 return;
2553
2554 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2555 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2556 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2557 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2558 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2559}
2560
893eead0
CW		 2561static u32
2562ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2563{
893eead0
CW		 2564 return list_entry(ring->request_list.prev,
2565 struct drm_i915_gem_request, list)->seqno;
2566}
2567
9107e9d2
CW		 2568static bool
2569ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2570{
2571 return (list_empty(&ring->request_list) ||
2572 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 2573}
2574
a028c4b0
DV		 2575static bool
2576ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2577{
2578 if (INTEL_INFO(dev)->gen >= 8) {
2579 /*
2580 * FIXME: gen8 semaphore support - currently we don't emit
2581 * semaphores on bdw anyway, but this needs to be addressed when
2582 * we merge that code.
2583 */
2584 return false;
2585 } else {
2586 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2587 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2588 MI_SEMAPHORE_REGISTER);
2589 }
2590}
2591
921d42ea
DV		 2592static struct intel_ring_buffer *
2593semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr)
2594{
2595 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2596 struct intel_ring_buffer *signaller;
2597 int i;
2598
2599 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2600 /*
2601 * FIXME: gen8 semaphore support - currently we don't emit
2602 * semaphores on bdw anyway, but this needs to be addressed when
2603 * we merge that code.
2604 */
2605 return NULL;
2606 } else {
2607 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2608
2609 for_each_ring(signaller, dev_priv, i) {
2610 if(ring == signaller)
2611 continue;
2612
2613 if (sync_bits ==
2614 signaller->semaphore_register[ring->id])
2615 return signaller;
2616 }
2617 }
2618
2619 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2620 ring->id, ipehr);
2621
2622 return NULL;
2623}
2624
6274f212
CW		 2625static struct intel_ring_buffer *
2626semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 2627{
2628 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88fe429d
DV		 2629 u32 cmd, ipehr, head;
2630 int i;
a24a11e6
CW		 2631
2632 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
a028c4b0 2633 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
6274f212 2634 return NULL;
a24a11e6 2635
88fe429d
DV		 2636 /*
2637 * HEAD is likely pointing to the dword after the actual command,
2638 * so scan backwards until we find the MBOX. But limit it to just 3
2639 * dwords. Note that we don't care about ACTHD here since that might
2640 * point at at batch, and semaphores are always emitted into the
2641 * ringbuffer itself.
a24a11e6 2642 */
88fe429d
DV		 2643 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2644
2645 for (i = 4; i; --i) {
2646 /*
2647 * Be paranoid and presume the hw has gone off into the wild -
2648 * our ring is smaller than what the hardware (and hence
2649 * HEAD_ADDR) allows. Also handles wrap-around.
2650 */
2651 head &= ring->size - 1;
2652
2653 /* This here seems to blow up */
2654 cmd = ioread32(ring->virtual_start + head);
a24a11e6
CW		 2655 if (cmd == ipehr)
2656 break;
2657
88fe429d
DV		 2658 head -= 4;
2659 }
a24a11e6 2660
88fe429d
DV		 2661 if (!i)
2662 return NULL;
a24a11e6 2663
88fe429d 2664 *seqno = ioread32(ring->virtual_start + head + 4) + 1;
921d42ea 2665 return semaphore_wait_to_signaller_ring(ring, ipehr);
a24a11e6
CW		 2666}
2667
6274f212
CW		 2668static int semaphore_passed(struct intel_ring_buffer *ring)
2669{
2670 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2671 struct intel_ring_buffer *signaller;
2672 u32 seqno, ctl;
2673
2674 ring->hangcheck.deadlock = true;
2675
2676 signaller = semaphore_waits_for(ring, &seqno);
2677 if (signaller == NULL || signaller->hangcheck.deadlock)
2678 return -1;
2679
2680 /* cursory check for an unkickable deadlock */
2681 ctl = I915_READ_CTL(signaller);
2682 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2683 return -1;
2684
2685 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2686}
2687
2688static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2689{
2690 struct intel_ring_buffer *ring;
2691 int i;
2692
2693 for_each_ring(ring, dev_priv, i)
2694 ring->hangcheck.deadlock = false;
2695}
2696
ad8beaea 2697static enum intel_ring_hangcheck_action
50877445 2698ring_stuck(struct intel_ring_buffer *ring, u64 acthd)
1ec14ad3
CW		 2699{
2700 struct drm_device *dev = ring->dev;
2701 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2702 u32 tmp;
2703
6274f212 2704 if (ring->hangcheck.acthd != acthd)
f2f4d82f 2705 return HANGCHECK_ACTIVE;
6274f212 2706
9107e9d2 2707 if (IS_GEN2(dev))
f2f4d82f 2708 return HANGCHECK_HUNG;
9107e9d2
CW		 2709
2710 /* Is the chip hanging on a WAIT_FOR_EVENT?
2711 * If so we can simply poke the RB_WAIT bit
2712 * and break the hang. This should work on
2713 * all but the second generation chipsets.
2714 */
2715 tmp = I915_READ_CTL(ring);
1ec14ad3 2716 if (tmp & RING_WAIT) {
58174462
MK		 2717 i915_handle_error(dev, false,
2718 "Kicking stuck wait on %s",
2719 ring->name);
1ec14ad3 2720 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2721 return HANGCHECK_KICK;
6274f212
CW		 2722 }
2723
2724 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2725 switch (semaphore_passed(ring)) {
2726 default:
f2f4d82f 2727 return HANGCHECK_HUNG;
6274f212 2728 case 1:
58174462
MK		 2729 i915_handle_error(dev, false,
2730 "Kicking stuck semaphore on %s",
2731 ring->name);
6274f212 2732 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2733 return HANGCHECK_KICK;
6274f212 2734 case 0:
f2f4d82f 2735 return HANGCHECK_WAIT;
6274f212 2736 }
9107e9d2 2737 }
ed5cbb03 2738
f2f4d82f 2739 return HANGCHECK_HUNG;
ed5cbb03
MK		 2740}
2741
f65d9421
BG		 2742/**
2743 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2744 * batchbuffers in a long time. We keep track per ring seqno progress and
2745 * if there are no progress, hangcheck score for that ring is increased.
2746 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2747 * we kick the ring. If we see no progress on three subsequent calls
2748 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 2749 */
a658b5d2 2750static void i915_hangcheck_elapsed(unsigned long data)
f65d9421
BG		 2751{
2752 struct drm_device *dev = (struct drm_device *)data;
2d1013dd 2753 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 2754 struct intel_ring_buffer *ring;
b4519513 2755 int i;
05407ff8 2756 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2757 bool stuck[I915_NUM_RINGS] = { 0 };
2758#define BUSY 1
2759#define KICK 5
2760#define HUNG 20
893eead0 2761
d330a953 2762 if (!i915.enable_hangcheck)
3e0dc6b0
BW		 2763 return;
2764
b4519513 2765 for_each_ring(ring, dev_priv, i) {
50877445
CW		 2766 u64 acthd;
2767 u32 seqno;
9107e9d2 2768 bool busy = true;
05407ff8 2769
6274f212
CW		 2770 semaphore_clear_deadlocks(dev_priv);
2771
05407ff8
MK		 2772 seqno = ring->get_seqno(ring, false);
2773 acthd = intel_ring_get_active_head(ring);
b4519513 2774
9107e9d2
CW		 2775 if (ring->hangcheck.seqno == seqno) {
2776 if (ring_idle(ring, seqno)) {
da661464
MK		 2777 ring->hangcheck.action = HANGCHECK_IDLE;
2778
9107e9d2
CW		 2779 if (waitqueue_active(&ring->irq_queue)) {
2780 /* Issue a wake-up to catch stuck h/w. */
094f9a54 2781 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
f4adcd24
DV		 2782 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2783 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2784 ring->name);
2785 else
2786 DRM_INFO("Fake missed irq on %s\n",
2787 ring->name);
094f9a54
CW		 2788 wake_up_all(&ring->irq_queue);
2789 }
2790 /* Safeguard against driver failure */
2791 ring->hangcheck.score += BUSY;
9107e9d2
CW		 2792 } else
2793 busy = false;
05407ff8 2794 } else {
6274f212
CW		 2795 /* We always increment the hangcheck score
2796 * if the ring is busy and still processing
2797 * the same request, so that no single request
2798 * can run indefinitely (such as a chain of
2799 * batches). The only time we do not increment
2800 * the hangcheck score on this ring, if this
2801 * ring is in a legitimate wait for another
2802 * ring. In that case the waiting ring is a
2803 * victim and we want to be sure we catch the
2804 * right culprit. Then every time we do kick
2805 * the ring, add a small increment to the
2806 * score so that we can catch a batch that is
2807 * being repeatedly kicked and so responsible
2808 * for stalling the machine.
2809 */
ad8beaea
MK		 2810 ring->hangcheck.action = ring_stuck(ring,
2811 acthd);
2812
2813 switch (ring->hangcheck.action) {
da661464 2814 case HANGCHECK_IDLE:
f2f4d82f 2815 case HANGCHECK_WAIT:
6274f212 2816 break;
f2f4d82f 2817 case HANGCHECK_ACTIVE:
ea04cb31 2818 ring->hangcheck.score += BUSY;
6274f212 2819 break;
f2f4d82f 2820 case HANGCHECK_KICK:
ea04cb31 2821 ring->hangcheck.score += KICK;
6274f212 2822 break;
f2f4d82f 2823 case HANGCHECK_HUNG:
ea04cb31 2824 ring->hangcheck.score += HUNG;
6274f212
CW		 2825 stuck[i] = true;
2826 break;
2827 }
05407ff8 2828 }
9107e9d2 2829 } else {
da661464
MK		 2830 ring->hangcheck.action = HANGCHECK_ACTIVE;
2831
9107e9d2
CW		 2832 /* Gradually reduce the count so that we catch DoS
2833 * attempts across multiple batches.
2834 */
2835 if (ring->hangcheck.score > 0)
2836 ring->hangcheck.score--;
d1e61e7f
CW		 2837 }
2838
05407ff8
MK		 2839 ring->hangcheck.seqno = seqno;
2840 ring->hangcheck.acthd = acthd;
9107e9d2 2841 busy_count += busy;
893eead0 2842 }
b9201c14 2843
92cab734 2844 for_each_ring(ring, dev_priv, i) {
b6b0fac0 2845 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
b8d88d1d
DV		 2846 DRM_INFO("%s on %s\n",
2847 stuck[i] ? "stuck" : "no progress",
2848 ring->name);
a43adf07 2849 rings_hung++;
92cab734
MK		 2850 }
2851 }
2852
05407ff8 2853 if (rings_hung)
58174462 2854 return i915_handle_error(dev, true, "Ring hung");
f65d9421 2855
05407ff8
MK		 2856 if (busy_count)
2857 /* Reset timer case chip hangs without another request
2858 * being added */
10cd45b6
MK		 2859 i915_queue_hangcheck(dev);
2860}
2861
2862void i915_queue_hangcheck(struct drm_device *dev)
2863{
2864 struct drm_i915_private *dev_priv = dev->dev_private;
d330a953 2865 if (!i915.enable_hangcheck)
10cd45b6
MK		 2866 return;
2867
2868 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2869 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2870}
2871
1c69eb42 2872static void ibx_irq_reset(struct drm_device *dev)
91738a95
PZ		 2873{
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875
2876 if (HAS_PCH_NOP(dev))
2877 return;
2878
f86f3fb0 2879 GEN5_IRQ_RESET(SDE);
105b122e
PZ		 2880
2881 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2882 I915_WRITE(SERR_INT, 0xffffffff);
622364b6 2883}
105b122e 2884
622364b6
PZ		 2885/*
2886 * SDEIER is also touched by the interrupt handler to work around missed PCH
2887 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2888 * instead we unconditionally enable all PCH interrupt sources here, but then
2889 * only unmask them as needed with SDEIMR.
2890 *
2891 * This function needs to be called before interrupts are enabled.
2892 */
2893static void ibx_irq_pre_postinstall(struct drm_device *dev)
2894{
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896
2897 if (HAS_PCH_NOP(dev))
2898 return;
2899
2900 WARN_ON(I915_READ(SDEIER) != 0);
91738a95
PZ		 2901 I915_WRITE(SDEIER, 0xffffffff);
2902 POSTING_READ(SDEIER);
2903}
2904
7c4d664e 2905static void gen5_gt_irq_reset(struct drm_device *dev)
d18ea1b5
DV		 2906{
2907 struct drm_i915_private *dev_priv = dev->dev_private;
2908
f86f3fb0 2909 GEN5_IRQ_RESET(GT);
a9d356a6 2910 if (INTEL_INFO(dev)->gen >= 6)
f86f3fb0 2911 GEN5_IRQ_RESET(GEN6_PM);
d18ea1b5
DV		 2912}
2913
1da177e4
LT		 2914/* drm_dma.h hooks
2915*/
be30b29f 2916static void ironlake_irq_reset(struct drm_device *dev)
036a4a7d 2917{
2d1013dd 2918 struct drm_i915_private *dev_priv = dev->dev_private;
036a4a7d 2919
0c841212 2920 I915_WRITE(HWSTAM, 0xffffffff);
bdfcdb63 2921
f86f3fb0 2922 GEN5_IRQ_RESET(DE);
c6d954c1
PZ		 2923 if (IS_GEN7(dev))
2924 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
036a4a7d 2925
7c4d664e 2926 gen5_gt_irq_reset(dev);
c650156a 2927
1c69eb42 2928 ibx_irq_reset(dev);
7d99163d 2929}
c650156a 2930
be30b29f
PZ		 2931static void ironlake_irq_preinstall(struct drm_device *dev)
2932{
be30b29f 2933 ironlake_irq_reset(dev);
7d99163d
BW		 2934}
2935
7e231dbe
JB		 2936static void valleyview_irq_preinstall(struct drm_device *dev)
2937{
2d1013dd 2938 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 2939 int pipe;
2940
7e231dbe
JB		 2941 /* VLV magic */
2942 I915_WRITE(VLV_IMR, 0);
2943 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2944 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2945 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2946
7e231dbe
JB		 2947 /* and GT */
2948 I915_WRITE(GTIIR, I915_READ(GTIIR));
2949 I915_WRITE(GTIIR, I915_READ(GTIIR));
d18ea1b5 2950
7c4d664e 2951 gen5_gt_irq_reset(dev);
7e231dbe
JB		 2952
2953 I915_WRITE(DPINVGTT, 0xff);
2954
2955 I915_WRITE(PORT_HOTPLUG_EN, 0);
2956 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2957 for_each_pipe(pipe)
2958 I915_WRITE(PIPESTAT(pipe), 0xffff);
2959 I915_WRITE(VLV_IIR, 0xffffffff);
2960 I915_WRITE(VLV_IMR, 0xffffffff);
2961 I915_WRITE(VLV_IER, 0x0);
2962 POSTING_READ(VLV_IER);
2963}
2964
823f6b38 2965static void gen8_irq_reset(struct drm_device *dev)
abd58f01
BW		 2966{
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 int pipe;
2969
abd58f01
BW		 2970 I915_WRITE(GEN8_MASTER_IRQ, 0);
2971 POSTING_READ(GEN8_MASTER_IRQ);
2972
f86f3fb0
PZ		 2973 GEN8_IRQ_RESET_NDX(GT, 0);
2974 GEN8_IRQ_RESET_NDX(GT, 1);
2975 GEN8_IRQ_RESET_NDX(GT, 2);
2976 GEN8_IRQ_RESET_NDX(GT, 3);
abd58f01 2977
823f6b38 2978 for_each_pipe(pipe)
f86f3fb0 2979 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
abd58f01 2980
f86f3fb0
PZ		 2981 GEN5_IRQ_RESET(GEN8_DE_PORT_);
2982 GEN5_IRQ_RESET(GEN8_DE_MISC_);
2983 GEN5_IRQ_RESET(GEN8_PCU_);
abd58f01 2984
1c69eb42 2985 ibx_irq_reset(dev);
abd58f01 2986}
09f2344d 2987
823f6b38
PZ		 2988static void gen8_irq_preinstall(struct drm_device *dev)
2989{
2990 gen8_irq_reset(dev);
abd58f01
BW		 2991}
2992
82a28bcf 2993static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973 2994{
2d1013dd 2995 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf
DV		 2996 struct drm_mode_config *mode_config = &dev->mode_config;
2997 struct intel_encoder *intel_encoder;
fee884ed 2998 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2999
3000 if (HAS_PCH_IBX(dev)) {
fee884ed 3001 hotplug_irqs = SDE_HOTPLUG_MASK;
82a28bcf 3002 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 3003 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 3004 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 3005 } else {
fee884ed 3006 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
82a28bcf 3007 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 3008 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 3009 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 3010 }
7fe0b973 3011
fee884ed 3012 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 3013
3014 /*
3015 * Enable digital hotplug on the PCH, and configure the DP short pulse
3016 * duration to 2ms (which is the minimum in the Display Port spec)
3017 *
3018 * This register is the same on all known PCH chips.
3019 */
7fe0b973
KP		 3020 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3021 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3022 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3023 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3024 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3025 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3026}
3027
d46da437
PZ		 3028static void ibx_irq_postinstall(struct drm_device *dev)
3029{
2d1013dd 3030 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 3031 u32 mask;
e5868a31 3032
692a04cf
DV		 3033 if (HAS_PCH_NOP(dev))
3034 return;
3035
105b122e 3036 if (HAS_PCH_IBX(dev))
5c673b60 3037 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
105b122e 3038 else
5c673b60 3039 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
8664281b 3040
337ba017 3041 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
d46da437 3042 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 3043}
3044
0a9a8c91
DV		 3045static void gen5_gt_irq_postinstall(struct drm_device *dev)
3046{
3047 struct drm_i915_private *dev_priv = dev->dev_private;
3048 u32 pm_irqs, gt_irqs;
3049
3050 pm_irqs = gt_irqs = 0;
3051
3052 dev_priv->gt_irq_mask = ~0;
040d2baa 3053 if (HAS_L3_DPF(dev)) {
0a9a8c91 3054 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 3055 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3056 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 3057 }
3058
3059 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3060 if (IS_GEN5(dev)) {
3061 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3062 ILK_BSD_USER_INTERRUPT;
3063 } else {
3064 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3065 }
3066
35079899 3067 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
0a9a8c91
DV		 3068
3069 if (INTEL_INFO(dev)->gen >= 6) {
a6706b45 3070 pm_irqs |= dev_priv->pm_rps_events;
0a9a8c91
DV		 3071
3072 if (HAS_VEBOX(dev))
3073 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3074
605cd25b 3075 dev_priv->pm_irq_mask = 0xffffffff;
35079899 3076 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
0a9a8c91
DV		 3077 }
3078}
3079
f71d4af4 3080static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 3081{
4bc9d430 3082 unsigned long irqflags;
2d1013dd 3083 struct drm_i915_private *dev_priv = dev->dev_private;
8e76f8dc
PZ		 3084 u32 display_mask, extra_mask;
3085
3086 if (INTEL_INFO(dev)->gen >= 7) {
3087 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3088 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3089 DE_PLANEB_FLIP_DONE_IVB |
5c673b60 3090 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
8e76f8dc 3091 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
5c673b60 3092 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
8e76f8dc
PZ		 3093 } else {
3094 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3095 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
5b3a856b 3096 DE_AUX_CHANNEL_A |
5b3a856b
DV		 3097 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3098 DE_POISON);
5c673b60
DV		 3099 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3100 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
8e76f8dc 3101 }
036a4a7d 3102
1ec14ad3 3103 dev_priv->irq_mask = ~display_mask;
036a4a7d 3104
0c841212
PZ		 3105 I915_WRITE(HWSTAM, 0xeffe);
3106
622364b6
PZ		 3107 ibx_irq_pre_postinstall(dev);
3108
35079899 3109 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
036a4a7d 3110
0a9a8c91 3111 gen5_gt_irq_postinstall(dev);
036a4a7d 3112
d46da437 3113 ibx_irq_postinstall(dev);
7fe0b973 3114
f97108d1 3115 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 3116 /* Enable PCU event interrupts
3117 *
3118 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 3119 * setup is guaranteed to run in single-threaded context. But we
3120 * need it to make the assert_spin_locked happy. */
3121 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 3122 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 3123 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 3124 }
3125
036a4a7d
ZW		 3126 return 0;
3127}
3128
f8b79e58
ID		 3129static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3130{
3131 u32 pipestat_mask;
3132 u32 iir_mask;
3133
3134 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3135 PIPE_FIFO_UNDERRUN_STATUS;
3136
3137 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3138 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3139 POSTING_READ(PIPESTAT(PIPE_A));
3140
3141 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3142 PIPE_CRC_DONE_INTERRUPT_STATUS;
3143
3144 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3145 PIPE_GMBUS_INTERRUPT_STATUS);
3146 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3147
3148 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3149 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3150 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3151 dev_priv->irq_mask &= ~iir_mask;
3152
3153 I915_WRITE(VLV_IIR, iir_mask);
3154 I915_WRITE(VLV_IIR, iir_mask);
3155 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3156 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3157 POSTING_READ(VLV_IER);
3158}
3159
3160static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3161{
3162 u32 pipestat_mask;
3163 u32 iir_mask;
3164
3165 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3166 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
6c7fba04 3167 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
f8b79e58
ID		 3168
3169 dev_priv->irq_mask |= iir_mask;
3170 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3171 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3172 I915_WRITE(VLV_IIR, iir_mask);
3173 I915_WRITE(VLV_IIR, iir_mask);
3174 POSTING_READ(VLV_IIR);
3175
3176 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3177 PIPE_CRC_DONE_INTERRUPT_STATUS;
3178
3179 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3180 PIPE_GMBUS_INTERRUPT_STATUS);
3181 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3182
3183 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3184 PIPE_FIFO_UNDERRUN_STATUS;
3185 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3186 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3187 POSTING_READ(PIPESTAT(PIPE_A));
3188}
3189
3190void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3191{
3192 assert_spin_locked(&dev_priv->irq_lock);
3193
3194 if (dev_priv->display_irqs_enabled)
3195 return;
3196
3197 dev_priv->display_irqs_enabled = true;
3198
3199 if (dev_priv->dev->irq_enabled)
3200 valleyview_display_irqs_install(dev_priv);
3201}
3202
3203void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3204{
3205 assert_spin_locked(&dev_priv->irq_lock);
3206
3207 if (!dev_priv->display_irqs_enabled)
3208 return;
3209
3210 dev_priv->display_irqs_enabled = false;
3211
3212 if (dev_priv->dev->irq_enabled)
3213 valleyview_display_irqs_uninstall(dev_priv);
3214}
3215
7e231dbe
JB		 3216static int valleyview_irq_postinstall(struct drm_device *dev)
3217{
2d1013dd 3218 struct drm_i915_private *dev_priv = dev->dev_private;
b79480ba 3219 unsigned long irqflags;
7e231dbe 3220
f8b79e58 3221 dev_priv->irq_mask = ~0;
7e231dbe 3222
20afbda2
DV		 3223 I915_WRITE(PORT_HOTPLUG_EN, 0);
3224 POSTING_READ(PORT_HOTPLUG_EN);
3225
7e231dbe 3226 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
f8b79e58 3227 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
7e231dbe 3228 I915_WRITE(VLV_IIR, 0xffffffff);
7e231dbe
JB		 3229 POSTING_READ(VLV_IER);
3230
b79480ba
DV		 3231 /* Interrupt setup is already guaranteed to be single-threaded, this is
3232 * just to make the assert_spin_locked check happy. */
3233 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f8b79e58
ID		 3234 if (dev_priv->display_irqs_enabled)
3235 valleyview_display_irqs_install(dev_priv);
b79480ba 3236 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 3237
7e231dbe
JB		 3238 I915_WRITE(VLV_IIR, 0xffffffff);
3239 I915_WRITE(VLV_IIR, 0xffffffff);
3240
0a9a8c91 3241 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 3242
3243 /* ack & enable invalid PTE error interrupts */
3244#if 0 /* FIXME: add support to irq handler for checking these bits */
3245 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3246 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3247#endif
3248
3249 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 3250
3251 return 0;
3252}
3253
abd58f01
BW		 3254static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3255{
3256 int i;
3257
3258 /* These are interrupts we'll toggle with the ring mask register */
3259 uint32_t gt_interrupts[] = {
3260 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3261 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3262 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3263 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3264 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3265 0,
3266 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3267 };
3268
337ba017 3269 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
35079899 3270 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
abd58f01
BW		 3271}
3272
3273static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3274{
3275 struct drm_device *dev = dev_priv->dev;
d0e1f1cb 3276 uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE |
13b3a0a7 3277 GEN8_PIPE_CDCLK_CRC_DONE |
13b3a0a7 3278 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
5c673b60
DV		 3279 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3280 GEN8_PIPE_FIFO_UNDERRUN;
abd58f01 3281 int pipe;
13b3a0a7
DV		 3282 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3283 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3284 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
abd58f01 3285
337ba017 3286 for_each_pipe(pipe)
35079899
PZ		 3287 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],
3288 de_pipe_enables);
abd58f01 3289
35079899 3290 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
abd58f01
BW		 3291}
3292
3293static int gen8_irq_postinstall(struct drm_device *dev)
3294{
3295 struct drm_i915_private *dev_priv = dev->dev_private;
3296
622364b6
PZ		 3297 ibx_irq_pre_postinstall(dev);
3298
abd58f01
BW		 3299 gen8_gt_irq_postinstall(dev_priv);
3300 gen8_de_irq_postinstall(dev_priv);
3301
3302 ibx_irq_postinstall(dev);
3303
3304 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3305 POSTING_READ(GEN8_MASTER_IRQ);
3306
3307 return 0;
3308}
3309
3310static void gen8_irq_uninstall(struct drm_device *dev)
3311{
3312 struct drm_i915_private *dev_priv = dev->dev_private;
abd58f01
BW		 3313
3314 if (!dev_priv)
3315 return;
3316
d4eb6b10 3317 intel_hpd_irq_uninstall(dev_priv);
abd58f01 3318
823f6b38 3319 gen8_irq_reset(dev);
abd58f01
BW		 3320}
3321
7e231dbe
JB		 3322static void valleyview_irq_uninstall(struct drm_device *dev)
3323{
2d1013dd 3324 struct drm_i915_private *dev_priv = dev->dev_private;
f8b79e58 3325 unsigned long irqflags;
7e231dbe
JB		 3326 int pipe;
3327
3328 if (!dev_priv)
3329 return;
3330
843d0e7d
ID		 3331 I915_WRITE(VLV_MASTER_IER, 0);
3332
3ca1cced 3333 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3334
7e231dbe
JB		 3335 for_each_pipe(pipe)
3336 I915_WRITE(PIPESTAT(pipe), 0xffff);
3337
3338 I915_WRITE(HWSTAM, 0xffffffff);
3339 I915_WRITE(PORT_HOTPLUG_EN, 0);
3340 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
f8b79e58
ID		 3341
3342 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3343 if (dev_priv->display_irqs_enabled)
3344 valleyview_display_irqs_uninstall(dev_priv);
3345 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3346
3347 dev_priv->irq_mask = 0;
3348
7e231dbe
JB		 3349 I915_WRITE(VLV_IIR, 0xffffffff);
3350 I915_WRITE(VLV_IMR, 0xffffffff);
3351 I915_WRITE(VLV_IER, 0x0);
3352 POSTING_READ(VLV_IER);
3353}
3354
f71d4af4 3355static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d 3356{
2d1013dd 3357 struct drm_i915_private *dev_priv = dev->dev_private;
4697995b
JB		 3358
3359 if (!dev_priv)
3360 return;
3361
3ca1cced 3362 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3363
be30b29f 3364 ironlake_irq_reset(dev);
036a4a7d
ZW		 3365}
3366
a266c7d5 3367static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4 3368{
2d1013dd 3369 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 3370 int pipe;
91e3738e 3371
9db4a9c7
JB		 3372 for_each_pipe(pipe)
3373 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 3374 I915_WRITE16(IMR, 0xffff);
3375 I915_WRITE16(IER, 0x0);
3376 POSTING_READ16(IER);
c2798b19
CW		 3377}
3378
3379static int i8xx_irq_postinstall(struct drm_device *dev)
3380{
2d1013dd 3381 struct drm_i915_private *dev_priv = dev->dev_private;
379ef82d 3382 unsigned long irqflags;
c2798b19 3383
c2798b19
CW		 3384 I915_WRITE16(EMR,
3385 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3386
3387 /* Unmask the interrupts that we always want on. */
3388 dev_priv->irq_mask =
3389 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3390 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3391 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3392 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3393 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3394 I915_WRITE16(IMR, dev_priv->irq_mask);
3395
3396 I915_WRITE16(IER,
3397 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3398 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3399 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3400 I915_USER_INTERRUPT);
3401 POSTING_READ16(IER);
3402
379ef82d
DV		 3403 /* Interrupt setup is already guaranteed to be single-threaded, this is
3404 * just to make the assert_spin_locked check happy. */
3405 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
755e9019
ID		 3406 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3407 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
379ef82d
DV		 3408 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3409
c2798b19
CW		 3410 return 0;
3411}
3412
90a72f87
VS		 3413/*
3414 * Returns true when a page flip has completed.
3415 */
3416static bool i8xx_handle_vblank(struct drm_device *dev,
1f1c2e24 3417 int plane, int pipe, u32 iir)
90a72f87 3418{
2d1013dd 3419 struct drm_i915_private *dev_priv = dev->dev_private;
1f1c2e24 3420 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
90a72f87
VS		 3421
3422 if (!drm_handle_vblank(dev, pipe))
3423 return false;
3424
3425 if ((iir & flip_pending) == 0)
3426 return false;
3427
1f1c2e24 3428 intel_prepare_page_flip(dev, plane);
90a72f87
VS		 3429
3430 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3431 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3432 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3433 * the flip is completed (no longer pending). Since this doesn't raise
3434 * an interrupt per se, we watch for the change at vblank.
3435 */
3436 if (I915_READ16(ISR) & flip_pending)
3437 return false;
3438
3439 intel_finish_page_flip(dev, pipe);
3440
3441 return true;
3442}
3443
ff1f525e 3444static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 3445{
3446 struct drm_device *dev = (struct drm_device *) arg;
2d1013dd 3447 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3448 u16 iir, new_iir;
3449 u32 pipe_stats[2];
3450 unsigned long irqflags;
c2798b19
CW		 3451 int pipe;
3452 u16 flip_mask =
3453 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3454 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3455
c2798b19
CW		 3456 iir = I915_READ16(IIR);
3457 if (iir == 0)
3458 return IRQ_NONE;
3459
3460 while (iir & ~flip_mask) {
3461 /* Can't rely on pipestat interrupt bit in iir as it might
3462 * have been cleared after the pipestat interrupt was received.
3463 * It doesn't set the bit in iir again, but it still produces
3464 * interrupts (for non-MSI).
3465 */
3466 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3467 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
58174462
MK		 3468 i915_handle_error(dev, false,
3469 "Command parser error, iir 0x%08x",
3470 iir);
c2798b19
CW		 3471
3472 for_each_pipe(pipe) {
3473 int reg = PIPESTAT(pipe);
3474 pipe_stats[pipe] = I915_READ(reg);
3475
3476 /*
3477 * Clear the PIPE*STAT regs before the IIR
3478 */
2d9d2b0b 3479 if (pipe_stats[pipe] & 0x8000ffff)
c2798b19 3480 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19
CW		 3481 }
3482 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3483
3484 I915_WRITE16(IIR, iir & ~flip_mask);
3485 new_iir = I915_READ16(IIR); /* Flush posted writes */
3486
d05c617e 3487 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 3488
3489 if (iir & I915_USER_INTERRUPT)
3490 notify_ring(dev, &dev_priv->ring[RCS]);
3491
4356d586 3492 for_each_pipe(pipe) {
1f1c2e24 3493 int plane = pipe;
3a77c4c4 3494 if (HAS_FBC(dev))
1f1c2e24
VS		 3495 plane = !plane;
3496
4356d586 3497 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
1f1c2e24
VS		 3498 i8xx_handle_vblank(dev, plane, pipe, iir))
3499 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
c2798b19 3500
4356d586 3501 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3502 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b
VS		 3503
3504 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3505 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b 3506 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4356d586 3507 }
c2798b19
CW		 3508
3509 iir = new_iir;
3510 }
3511
3512 return IRQ_HANDLED;
3513}
3514
3515static void i8xx_irq_uninstall(struct drm_device * dev)
3516{
2d1013dd 3517 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3518 int pipe;
3519
c2798b19
CW		 3520 for_each_pipe(pipe) {
3521 /* Clear enable bits; then clear status bits */
3522 I915_WRITE(PIPESTAT(pipe), 0);
3523 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3524 }
3525 I915_WRITE16(IMR, 0xffff);
3526 I915_WRITE16(IER, 0x0);
3527 I915_WRITE16(IIR, I915_READ16(IIR));
3528}
3529
a266c7d5
CW		 3530static void i915_irq_preinstall(struct drm_device * dev)
3531{
2d1013dd 3532 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3533 int pipe;
3534
a266c7d5
CW		 3535 if (I915_HAS_HOTPLUG(dev)) {
3536 I915_WRITE(PORT_HOTPLUG_EN, 0);
3537 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3538 }
3539
00d98ebd 3540 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 3541 for_each_pipe(pipe)
3542 I915_WRITE(PIPESTAT(pipe), 0);
3543 I915_WRITE(IMR, 0xffffffff);
3544 I915_WRITE(IER, 0x0);
3545 POSTING_READ(IER);
3546}
3547
3548static int i915_irq_postinstall(struct drm_device *dev)
3549{
2d1013dd 3550 struct drm_i915_private *dev_priv = dev->dev_private;
38bde180 3551 u32 enable_mask;
379ef82d 3552 unsigned long irqflags;
a266c7d5 3553
38bde180
CW		 3554 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3555
3556 /* Unmask the interrupts that we always want on. */
3557 dev_priv->irq_mask =
3558 ~(I915_ASLE_INTERRUPT |
3559 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3560 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3561 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3562 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3563 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3564
3565 enable_mask =
3566 I915_ASLE_INTERRUPT |
3567 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3568 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3569 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3570 I915_USER_INTERRUPT;
3571
a266c7d5 3572 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3573 I915_WRITE(PORT_HOTPLUG_EN, 0);
3574 POSTING_READ(PORT_HOTPLUG_EN);
3575
a266c7d5
CW		 3576 /* Enable in IER... */
3577 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3578 /* and unmask in IMR */
3579 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3580 }
3581
a266c7d5
CW		 3582 I915_WRITE(IMR, dev_priv->irq_mask);
3583 I915_WRITE(IER, enable_mask);
3584 POSTING_READ(IER);
3585
f49e38dd 3586 i915_enable_asle_pipestat(dev);
20afbda2 3587
379ef82d
DV		 3588 /* Interrupt setup is already guaranteed to be single-threaded, this is
3589 * just to make the assert_spin_locked check happy. */
3590 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
755e9019
ID		 3591 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3592 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
379ef82d
DV		 3593 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3594
20afbda2
DV		 3595 return 0;
3596}
3597
90a72f87
VS		 3598/*
3599 * Returns true when a page flip has completed.
3600 */
3601static bool i915_handle_vblank(struct drm_device *dev,
3602 int plane, int pipe, u32 iir)
3603{
2d1013dd 3604 struct drm_i915_private *dev_priv = dev->dev_private;
90a72f87
VS		 3605 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3606
3607 if (!drm_handle_vblank(dev, pipe))
3608 return false;
3609
3610 if ((iir & flip_pending) == 0)
3611 return false;
3612
3613 intel_prepare_page_flip(dev, plane);
3614
3615 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3616 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3617 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3618 * the flip is completed (no longer pending). Since this doesn't raise
3619 * an interrupt per se, we watch for the change at vblank.
3620 */
3621 if (I915_READ(ISR) & flip_pending)
3622 return false;
3623
3624 intel_finish_page_flip(dev, pipe);
3625
3626 return true;
3627}
3628
ff1f525e 3629static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 3630{
3631 struct drm_device *dev = (struct drm_device *) arg;
2d1013dd 3632 struct drm_i915_private *dev_priv = dev->dev_private;
8291ee90 3633 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 3634 unsigned long irqflags;
38bde180
CW		 3635 u32 flip_mask =
3636 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3637 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3638 int pipe, ret = IRQ_NONE;
a266c7d5 3639
a266c7d5 3640 iir = I915_READ(IIR);
38bde180
CW		 3641 do {
3642 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3643 bool blc_event = false;
a266c7d5
CW		 3644
3645 /* Can't rely on pipestat interrupt bit in iir as it might
3646 * have been cleared after the pipestat interrupt was received.
3647 * It doesn't set the bit in iir again, but it still produces
3648 * interrupts (for non-MSI).
3649 */
3650 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3651 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
58174462
MK		 3652 i915_handle_error(dev, false,
3653 "Command parser error, iir 0x%08x",
3654 iir);
a266c7d5
CW		 3655
3656 for_each_pipe(pipe) {
3657 int reg = PIPESTAT(pipe);
3658 pipe_stats[pipe] = I915_READ(reg);
3659
38bde180 3660 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5 3661 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3662 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3663 irq_received = true;
a266c7d5
CW		 3664 }
3665 }
3666 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3667
3668 if (!irq_received)
3669 break;
3670
a266c7d5 3671 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 3672 if (I915_HAS_HOTPLUG(dev) &&
3673 iir & I915_DISPLAY_PORT_INTERRUPT)
3674 i9xx_hpd_irq_handler(dev);
a266c7d5 3675
38bde180 3676 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3677 new_iir = I915_READ(IIR); /* Flush posted writes */
3678
a266c7d5
CW		 3679 if (iir & I915_USER_INTERRUPT)
3680 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3681
a266c7d5 3682 for_each_pipe(pipe) {
38bde180 3683 int plane = pipe;
3a77c4c4 3684 if (HAS_FBC(dev))
38bde180 3685 plane = !plane;
90a72f87 3686
8291ee90 3687 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3688 i915_handle_vblank(dev, plane, pipe, iir))
3689 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3690
3691 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3692 blc_event = true;
4356d586
DV		 3693
3694 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3695 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b
VS		 3696
3697 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3698 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b 3699 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
a266c7d5
CW		 3700 }
3701
a266c7d5
CW		 3702 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3703 intel_opregion_asle_intr(dev);
3704
3705 /* With MSI, interrupts are only generated when iir
3706 * transitions from zero to nonzero. If another bit got
3707 * set while we were handling the existing iir bits, then
3708 * we would never get another interrupt.
3709 *
3710 * This is fine on non-MSI as well, as if we hit this path
3711 * we avoid exiting the interrupt handler only to generate
3712 * another one.
3713 *
3714 * Note that for MSI this could cause a stray interrupt report
3715 * if an interrupt landed in the time between writing IIR and
3716 * the posting read. This should be rare enough to never
3717 * trigger the 99% of 100,000 interrupts test for disabling
3718 * stray interrupts.
3719 */
38bde180 3720 ret = IRQ_HANDLED;
a266c7d5 3721 iir = new_iir;
38bde180 3722 } while (iir & ~flip_mask);
a266c7d5 3723
d05c617e 3724 i915_update_dri1_breadcrumb(dev);
8291ee90 3725
a266c7d5
CW		 3726 return ret;
3727}
3728
3729static void i915_irq_uninstall(struct drm_device * dev)
3730{
2d1013dd 3731 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3732 int pipe;
3733
3ca1cced 3734 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3735
a266c7d5
CW		 3736 if (I915_HAS_HOTPLUG(dev)) {
3737 I915_WRITE(PORT_HOTPLUG_EN, 0);
3738 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3739 }
3740
00d98ebd 3741 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3742 for_each_pipe(pipe) {
3743 /* Clear enable bits; then clear status bits */
a266c7d5 3744 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3745 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3746 }
a266c7d5
CW		 3747 I915_WRITE(IMR, 0xffffffff);
3748 I915_WRITE(IER, 0x0);
3749
a266c7d5
CW		 3750 I915_WRITE(IIR, I915_READ(IIR));
3751}
3752
3753static void i965_irq_preinstall(struct drm_device * dev)
3754{
2d1013dd 3755 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3756 int pipe;
3757
adca4730
CW		 3758 I915_WRITE(PORT_HOTPLUG_EN, 0);
3759 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3760
3761 I915_WRITE(HWSTAM, 0xeffe);
3762 for_each_pipe(pipe)
3763 I915_WRITE(PIPESTAT(pipe), 0);
3764 I915_WRITE(IMR, 0xffffffff);
3765 I915_WRITE(IER, 0x0);
3766 POSTING_READ(IER);
3767}
3768
3769static int i965_irq_postinstall(struct drm_device *dev)
3770{
2d1013dd 3771 struct drm_i915_private *dev_priv = dev->dev_private;
bbba0a97 3772 u32 enable_mask;
a266c7d5 3773 u32 error_mask;
b79480ba 3774 unsigned long irqflags;
a266c7d5 3775
a266c7d5 3776 /* Unmask the interrupts that we always want on. */
bbba0a97 3777 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3778 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3779 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3780 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3781 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3782 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3783 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3784
3785 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3786 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3787 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3788 enable_mask |= I915_USER_INTERRUPT;
3789
3790 if (IS_G4X(dev))
3791 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3792
b79480ba
DV		 3793 /* Interrupt setup is already guaranteed to be single-threaded, this is
3794 * just to make the assert_spin_locked check happy. */
3795 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
755e9019
ID		 3796 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3797 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3798 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
b79480ba 3799 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 3800
a266c7d5
CW		 3801 /*
3802 * Enable some error detection, note the instruction error mask
3803 * bit is reserved, so we leave it masked.
3804 */
3805 if (IS_G4X(dev)) {
3806 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3807 GM45_ERROR_MEM_PRIV |
3808 GM45_ERROR_CP_PRIV |
3809 I915_ERROR_MEMORY_REFRESH);
3810 } else {
3811 error_mask = ~(I915_ERROR_PAGE_TABLE |
3812 I915_ERROR_MEMORY_REFRESH);
3813 }
3814 I915_WRITE(EMR, error_mask);
3815
3816 I915_WRITE(IMR, dev_priv->irq_mask);
3817 I915_WRITE(IER, enable_mask);
3818 POSTING_READ(IER);
3819
20afbda2
DV		 3820 I915_WRITE(PORT_HOTPLUG_EN, 0);
3821 POSTING_READ(PORT_HOTPLUG_EN);
3822
f49e38dd 3823 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3824
3825 return 0;
3826}
3827
bac56d5b 3828static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2 3829{
2d1013dd 3830 struct drm_i915_private *dev_priv = dev->dev_private;
e5868a31 3831 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3832 struct intel_encoder *intel_encoder;
20afbda2
DV		 3833 u32 hotplug_en;
3834
b5ea2d56
DV		 3835 assert_spin_locked(&dev_priv->irq_lock);
3836
bac56d5b
EE		 3837 if (I915_HAS_HOTPLUG(dev)) {
3838 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3839 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3840 /* Note HDMI and DP share hotplug bits */
e5868a31 3841 /* enable bits are the same for all generations */
cd569aed
EE		 3842 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3843 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3844 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3845 /* Programming the CRT detection parameters tends
3846 to generate a spurious hotplug event about three
3847 seconds later. So just do it once.
3848 */
3849 if (IS_G4X(dev))
3850 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3851 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3852 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3853
bac56d5b
EE		 3854 /* Ignore TV since it's buggy */
3855 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3856 }
a266c7d5
CW		 3857}
3858
ff1f525e 3859static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3860{
3861 struct drm_device *dev = (struct drm_device *) arg;
2d1013dd 3862 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3863 u32 iir, new_iir;
3864 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5 3865 unsigned long irqflags;
a266c7d5 3866 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3867 u32 flip_mask =
3868 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3869 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5 3870
a266c7d5
CW		 3871 iir = I915_READ(IIR);
3872
a266c7d5 3873 for (;;) {
501e01d7 3874 bool irq_received = (iir & ~flip_mask) != 0;
2c8ba29f
CW		 3875 bool blc_event = false;
3876
a266c7d5
CW		 3877 /* Can't rely on pipestat interrupt bit in iir as it might
3878 * have been cleared after the pipestat interrupt was received.
3879 * It doesn't set the bit in iir again, but it still produces
3880 * interrupts (for non-MSI).
3881 */
3882 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3883 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
58174462
MK		 3884 i915_handle_error(dev, false,
3885 "Command parser error, iir 0x%08x",
3886 iir);
a266c7d5
CW		 3887
3888 for_each_pipe(pipe) {
3889 int reg = PIPESTAT(pipe);
3890 pipe_stats[pipe] = I915_READ(reg);
3891
3892 /*
3893 * Clear the PIPE*STAT regs before the IIR
3894 */
3895 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3896 I915_WRITE(reg, pipe_stats[pipe]);
501e01d7 3897 irq_received = true;
a266c7d5
CW		 3898 }
3899 }
3900 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3901
3902 if (!irq_received)
3903 break;
3904
3905 ret = IRQ_HANDLED;
3906
3907 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 3908 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3909 i9xx_hpd_irq_handler(dev);
a266c7d5 3910
21ad8330 3911 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3912 new_iir = I915_READ(IIR); /* Flush posted writes */
3913
a266c7d5
CW		 3914 if (iir & I915_USER_INTERRUPT)
3915 notify_ring(dev, &dev_priv->ring[RCS]);
3916 if (iir & I915_BSD_USER_INTERRUPT)
3917 notify_ring(dev, &dev_priv->ring[VCS]);
3918
a266c7d5 3919 for_each_pipe(pipe) {
2c8ba29f 3920 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3921 i915_handle_vblank(dev, pipe, pipe, iir))
3922 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3923
3924 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3925 blc_event = true;
4356d586
DV		 3926
3927 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3928 i9xx_pipe_crc_irq_handler(dev, pipe);
a266c7d5 3929
2d9d2b0b
VS		 3930 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3931 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b 3932 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
2d9d2b0b 3933 }
a266c7d5
CW		 3934
3935 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3936 intel_opregion_asle_intr(dev);
3937
515ac2bb
DV		 3938 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3939 gmbus_irq_handler(dev);
3940
a266c7d5
CW		 3941 /* With MSI, interrupts are only generated when iir
3942 * transitions from zero to nonzero. If another bit got
3943 * set while we were handling the existing iir bits, then
3944 * we would never get another interrupt.
3945 *
3946 * This is fine on non-MSI as well, as if we hit this path
3947 * we avoid exiting the interrupt handler only to generate
3948 * another one.
3949 *
3950 * Note that for MSI this could cause a stray interrupt report
3951 * if an interrupt landed in the time between writing IIR and
3952 * the posting read. This should be rare enough to never
3953 * trigger the 99% of 100,000 interrupts test for disabling
3954 * stray interrupts.
3955 */
3956 iir = new_iir;
3957 }
3958
d05c617e 3959 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3960
a266c7d5
CW		 3961 return ret;
3962}
3963
3964static void i965_irq_uninstall(struct drm_device * dev)
3965{
2d1013dd 3966 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3967 int pipe;
3968
3969 if (!dev_priv)
3970 return;
3971
3ca1cced 3972 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3973
adca4730
CW		 3974 I915_WRITE(PORT_HOTPLUG_EN, 0);
3975 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3976
3977 I915_WRITE(HWSTAM, 0xffffffff);
3978 for_each_pipe(pipe)
3979 I915_WRITE(PIPESTAT(pipe), 0);
3980 I915_WRITE(IMR, 0xffffffff);
3981 I915_WRITE(IER, 0x0);
3982
3983 for_each_pipe(pipe)
3984 I915_WRITE(PIPESTAT(pipe),
3985 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3986 I915_WRITE(IIR, I915_READ(IIR));
3987}
3988
3ca1cced 3989static void intel_hpd_irq_reenable(unsigned long data)
ac4c16c5 3990{
2d1013dd 3991 struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
ac4c16c5
EE		 3992 struct drm_device *dev = dev_priv->dev;
3993 struct drm_mode_config *mode_config = &dev->mode_config;
3994 unsigned long irqflags;
3995 int i;
3996
3997 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3998 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3999 struct drm_connector *connector;
4000
4001 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4002 continue;
4003
4004 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4005
4006 list_for_each_entry(connector, &mode_config->connector_list, head) {
4007 struct intel_connector *intel_connector = to_intel_connector(connector);
4008
4009 if (intel_connector->encoder->hpd_pin == i) {
4010 if (connector->polled != intel_connector->polled)
4011 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4012 drm_get_connector_name(connector));
4013 connector->polled = intel_connector->polled;
4014 if (!connector->polled)
4015 connector->polled = DRM_CONNECTOR_POLL_HPD;
4016 }
4017 }
4018 }
4019 if (dev_priv->display.hpd_irq_setup)
4020 dev_priv->display.hpd_irq_setup(dev);
4021 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4022}
4023
f71d4af4
JB		 4024void intel_irq_init(struct drm_device *dev)
4025{
8b2e326d
CW		 4026 struct drm_i915_private *dev_priv = dev->dev_private;
4027
4028 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 4029 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 4030 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 4031 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 4032
a6706b45
D		 4033 /* Let's track the enabled rps events */
4034 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4035
99584db3
DV		 4036 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4037 i915_hangcheck_elapsed,
61bac78e 4038 (unsigned long) dev);
3ca1cced 4039 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
ac4c16c5 4040 (unsigned long) dev_priv);
61bac78e 4041
97a19a24 4042 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 4043
4cdb83ec
VS		 4044 if (IS_GEN2(dev)) {
4045 dev->max_vblank_count = 0;
4046 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4047 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 4048 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4049 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
391f75e2
VS		 4050 } else {
4051 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4052 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 4053 }
4054
c2baf4b7 4055 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
c3613de9 4056 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
c2baf4b7
VS		 4057 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4058 }
f71d4af4 4059
7e231dbe
JB		 4060 if (IS_VALLEYVIEW(dev)) {
4061 dev->driver->irq_handler = valleyview_irq_handler;
4062 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4063 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4064 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4065 dev->driver->enable_vblank = valleyview_enable_vblank;
4066 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 4067 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
abd58f01
BW		 4068 } else if (IS_GEN8(dev)) {
4069 dev->driver->irq_handler = gen8_irq_handler;
4070 dev->driver->irq_preinstall = gen8_irq_preinstall;
4071 dev->driver->irq_postinstall = gen8_irq_postinstall;
4072 dev->driver->irq_uninstall = gen8_irq_uninstall;
4073 dev->driver->enable_vblank = gen8_enable_vblank;
4074 dev->driver->disable_vblank = gen8_disable_vblank;
4075 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 4076 } else if (HAS_PCH_SPLIT(dev)) {
4077 dev->driver->irq_handler = ironlake_irq_handler;
4078 dev->driver->irq_preinstall = ironlake_irq_preinstall;
4079 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4080 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4081 dev->driver->enable_vblank = ironlake_enable_vblank;
4082 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 4083 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 4084 } else {
c2798b19
CW		 4085 if (INTEL_INFO(dev)->gen == 2) {
4086 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4087 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4088 dev->driver->irq_handler = i8xx_irq_handler;
4089 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 4090 } else if (INTEL_INFO(dev)->gen == 3) {
4091 dev->driver->irq_preinstall = i915_irq_preinstall;
4092 dev->driver->irq_postinstall = i915_irq_postinstall;
4093 dev->driver->irq_uninstall = i915_irq_uninstall;
4094 dev->driver->irq_handler = i915_irq_handler;
20afbda2 4095 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 4096 } else {
a266c7d5
CW		 4097 dev->driver->irq_preinstall = i965_irq_preinstall;
4098 dev->driver->irq_postinstall = i965_irq_postinstall;
4099 dev->driver->irq_uninstall = i965_irq_uninstall;
4100 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 4101 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 4102 }
f71d4af4
JB		 4103 dev->driver->enable_vblank = i915_enable_vblank;
4104 dev->driver->disable_vblank = i915_disable_vblank;
4105 }
4106}
20afbda2
DV		 4107
4108void intel_hpd_init(struct drm_device *dev)
4109{
4110 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 4111 struct drm_mode_config *mode_config = &dev->mode_config;
4112 struct drm_connector *connector;
b5ea2d56 4113 unsigned long irqflags;
821450c6 4114 int i;
20afbda2 4115
821450c6
EE		 4116 for (i = 1; i < HPD_NUM_PINS; i++) {
4117 dev_priv->hpd_stats[i].hpd_cnt = 0;
4118 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4119 }
4120 list_for_each_entry(connector, &mode_config->connector_list, head) {
4121 struct intel_connector *intel_connector = to_intel_connector(connector);
4122 connector->polled = intel_connector->polled;
4123 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4124 connector->polled = DRM_CONNECTOR_POLL_HPD;
4125 }
b5ea2d56
DV		 4126
4127 /* Interrupt setup is already guaranteed to be single-threaded, this is
4128 * just to make the assert_spin_locked checks happy. */
4129 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 4130 if (dev_priv->display.hpd_irq_setup)
4131 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 4132 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 4133}
c67a470b 4134
5d584b2e 4135/* Disable interrupts so we can allow runtime PM. */
730488b2 4136void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
c67a470b
PZ		 4137{
4138 struct drm_i915_private *dev_priv = dev->dev_private;
c67a470b 4139
730488b2 4140 dev->driver->irq_uninstall(dev);
5d584b2e 4141 dev_priv->pm.irqs_disabled = true;
c67a470b
PZ		 4142}
4143
5d584b2e 4144/* Restore interrupts so we can recover from runtime PM. */
730488b2 4145void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
c67a470b
PZ		 4146{
4147 struct drm_i915_private *dev_priv = dev->dev_private;
c67a470b 4148
5d584b2e 4149 dev_priv->pm.irqs_disabled = false;
730488b2
PZ		 4150 dev->driver->irq_preinstall(dev);
4151 dev->driver->irq_postinstall(dev);
c67a470b 4152}
Linux kernel - Deliverables
This page took 1.009274 seconds and 5 git commands to generate.