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drm/i915: Introduce an HAS_IPS() macro
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
73static const u32 hpd_status_i965[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
82static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89};
90
cd569aed
EE		 91static void ibx_hpd_irq_setup(struct drm_device *dev);
92static void i915_hpd_irq_setup(struct drm_device *dev);
e5868a31 93
036a4a7d 94/* For display hotplug interrupt */
995b6762 95static void
f2b115e6 96ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 97{
1ec14ad3
CW		 98 if ((dev_priv->irq_mask & mask) != 0) {
99 dev_priv->irq_mask &= ~mask;
100 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 101 POSTING_READ(DEIMR);
036a4a7d
ZW		 102 }
103}
104
0ff9800a 105static void
f2b115e6 106ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 107{
1ec14ad3
CW		 108 if ((dev_priv->irq_mask & mask) != mask) {
109 dev_priv->irq_mask |= mask;
110 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 111 POSTING_READ(DEIMR);
036a4a7d
ZW		 112 }
113}
114
8664281b
PZ		 115static bool ivb_can_enable_err_int(struct drm_device *dev)
116{
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 struct intel_crtc *crtc;
119 enum pipe pipe;
120
121 for_each_pipe(pipe) {
122 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
123
124 if (crtc->cpu_fifo_underrun_disabled)
125 return false;
126 }
127
128 return true;
129}
130
131static bool cpt_can_enable_serr_int(struct drm_device *dev)
132{
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 enum pipe pipe;
135 struct intel_crtc *crtc;
136
137 for_each_pipe(pipe) {
138 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
139
140 if (crtc->pch_fifo_underrun_disabled)
141 return false;
142 }
143
144 return true;
145}
146
147static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
148 enum pipe pipe, bool enable)
149{
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
152 DE_PIPEB_FIFO_UNDERRUN;
153
154 if (enable)
155 ironlake_enable_display_irq(dev_priv, bit);
156 else
157 ironlake_disable_display_irq(dev_priv, bit);
158}
159
160static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
161 bool enable)
162{
163 struct drm_i915_private *dev_priv = dev->dev_private;
164
165 if (enable) {
166 if (!ivb_can_enable_err_int(dev))
167 return;
168
169 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
170 ERR_INT_FIFO_UNDERRUN_B |
171 ERR_INT_FIFO_UNDERRUN_C);
172
173 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
174 } else {
175 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
176 }
177}
178
179static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
180 bool enable)
181{
182 struct drm_device *dev = crtc->base.dev;
183 struct drm_i915_private *dev_priv = dev->dev_private;
184 uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
185 SDE_TRANSB_FIFO_UNDER;
186
187 if (enable)
188 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
189 else
190 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
191
192 POSTING_READ(SDEIMR);
193}
194
195static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
196 enum transcoder pch_transcoder,
197 bool enable)
198{
199 struct drm_i915_private *dev_priv = dev->dev_private;
200
201 if (enable) {
202 if (!cpt_can_enable_serr_int(dev))
203 return;
204
205 I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
206 SERR_INT_TRANS_B_FIFO_UNDERRUN |
207 SERR_INT_TRANS_C_FIFO_UNDERRUN);
208
209 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
210 } else {
211 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
212 }
213
214 POSTING_READ(SDEIMR);
215}
216
217/**
218 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
219 * @dev: drm device
220 * @pipe: pipe
221 * @enable: true if we want to report FIFO underrun errors, false otherwise
222 *
223 * This function makes us disable or enable CPU fifo underruns for a specific
224 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
225 * reporting for one pipe may also disable all the other CPU error interruts for
226 * the other pipes, due to the fact that there's just one interrupt mask/enable
227 * bit for all the pipes.
228 *
229 * Returns the previous state of underrun reporting.
230 */
231bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
232 enum pipe pipe, bool enable)
233{
234 struct drm_i915_private *dev_priv = dev->dev_private;
235 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
237 unsigned long flags;
238 bool ret;
239
240 spin_lock_irqsave(&dev_priv->irq_lock, flags);
241
242 ret = !intel_crtc->cpu_fifo_underrun_disabled;
243
244 if (enable == ret)
245 goto done;
246
247 intel_crtc->cpu_fifo_underrun_disabled = !enable;
248
249 if (IS_GEN5(dev) || IS_GEN6(dev))
250 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
251 else if (IS_GEN7(dev))
252 ivybridge_set_fifo_underrun_reporting(dev, enable);
253
254done:
255 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
256 return ret;
257}
258
259/**
260 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
261 * @dev: drm device
262 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
263 * @enable: true if we want to report FIFO underrun errors, false otherwise
264 *
265 * This function makes us disable or enable PCH fifo underruns for a specific
266 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
267 * underrun reporting for one transcoder may also disable all the other PCH
268 * error interruts for the other transcoders, due to the fact that there's just
269 * one interrupt mask/enable bit for all the transcoders.
270 *
271 * Returns the previous state of underrun reporting.
272 */
273bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
274 enum transcoder pch_transcoder,
275 bool enable)
276{
277 struct drm_i915_private *dev_priv = dev->dev_private;
278 enum pipe p;
279 struct drm_crtc *crtc;
280 struct intel_crtc *intel_crtc;
281 unsigned long flags;
282 bool ret;
283
284 if (HAS_PCH_LPT(dev)) {
285 crtc = NULL;
286 for_each_pipe(p) {
287 struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
288 if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
289 crtc = c;
290 break;
291 }
292 }
293 if (!crtc) {
294 DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
295 return false;
296 }
297 } else {
298 crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
299 }
300 intel_crtc = to_intel_crtc(crtc);
301
302 spin_lock_irqsave(&dev_priv->irq_lock, flags);
303
304 ret = !intel_crtc->pch_fifo_underrun_disabled;
305
306 if (enable == ret)
307 goto done;
308
309 intel_crtc->pch_fifo_underrun_disabled = !enable;
310
311 if (HAS_PCH_IBX(dev))
312 ibx_set_fifo_underrun_reporting(intel_crtc, enable);
313 else
314 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
315
316done:
317 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
318 return ret;
319}
320
321
7c463586
KP		 322void
323i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
324{
46c06a30
VS		 325 u32 reg = PIPESTAT(pipe);
326 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 327
46c06a30
VS		 328 if ((pipestat & mask) == mask)
329 return;
330
331 /* Enable the interrupt, clear any pending status */
332 pipestat |= mask | (mask >> 16);
333 I915_WRITE(reg, pipestat);
334 POSTING_READ(reg);
7c463586
KP		 335}
336
337void
338i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
339{
46c06a30
VS		 340 u32 reg = PIPESTAT(pipe);
341 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 342
46c06a30
VS		 343 if ((pipestat & mask) == 0)
344 return;
345
346 pipestat &= ~mask;
347 I915_WRITE(reg, pipestat);
348 POSTING_READ(reg);
7c463586
KP		 349}
350
01c66889 351/**
f49e38dd 352 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 353 */
f49e38dd 354static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 355{
1ec14ad3
CW		 356 drm_i915_private_t *dev_priv = dev->dev_private;
357 unsigned long irqflags;
358
f49e38dd
JN		 359 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
360 return;
361
1ec14ad3 362 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 363
f898780b
JN		 364 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
365 if (INTEL_INFO(dev)->gen >= 4)
366 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 367
368 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 369}
370
0a3e67a4
JB		 371/**
372 * i915_pipe_enabled - check if a pipe is enabled
373 * @dev: DRM device
374 * @pipe: pipe to check
375 *
376 * Reading certain registers when the pipe is disabled can hang the chip.
377 * Use this routine to make sure the PLL is running and the pipe is active
378 * before reading such registers if unsure.
379 */
380static int
381i915_pipe_enabled(struct drm_device *dev, int pipe)
382{
383 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 384
a01025af
DV		 385 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
386 /* Locking is horribly broken here, but whatever. */
387 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 389
a01025af
DV		 390 return intel_crtc->active;
391 } else {
392 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
393 }
0a3e67a4
JB		 394}
395
42f52ef8
KP		 396/* Called from drm generic code, passed a 'crtc', which
397 * we use as a pipe index
398 */
f71d4af4 399static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 400{
401 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
402 unsigned long high_frame;
403 unsigned long low_frame;
5eddb70b 404 u32 high1, high2, low;
0a3e67a4
JB		 405
406 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 407 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 408 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 409 return 0;
410 }
411
9db4a9c7
JB		 412 high_frame = PIPEFRAME(pipe);
413 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 414
0a3e67a4
JB		 415 /*
416 * High & low register fields aren't synchronized, so make sure
417 * we get a low value that's stable across two reads of the high
418 * register.
419 */
420 do {
5eddb70b
CW		 421 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
422 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
423 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 424 } while (high1 != high2);
425
5eddb70b
CW		 426 high1 >>= PIPE_FRAME_HIGH_SHIFT;
427 low >>= PIPE_FRAME_LOW_SHIFT;
428 return (high1 << 8) | low;
0a3e67a4
JB		 429}
430
f71d4af4 431static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 432{
433 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 434 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 435
436 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 437 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 438 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 439 return 0;
440 }
441
442 return I915_READ(reg);
443}
444
f71d4af4 445static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 446 int *vpos, int *hpos)
447{
448 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
449 u32 vbl = 0, position = 0;
450 int vbl_start, vbl_end, htotal, vtotal;
451 bool in_vbl = true;
452 int ret = 0;
fe2b8f9d
PZ		 453 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
454 pipe);
0af7e4df
MK		 455
456 if (!i915_pipe_enabled(dev, pipe)) {
457 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 458 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 459 return 0;
460 }
461
462 /* Get vtotal. */
fe2b8f9d 463 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 464
465 if (INTEL_INFO(dev)->gen >= 4) {
466 /* No obvious pixelcount register. Only query vertical
467 * scanout position from Display scan line register.
468 */
469 position = I915_READ(PIPEDSL(pipe));
470
471 /* Decode into vertical scanout position. Don't have
472 * horizontal scanout position.
473 */
474 *vpos = position & 0x1fff;
475 *hpos = 0;
476 } else {
477 /* Have access to pixelcount since start of frame.
478 * We can split this into vertical and horizontal
479 * scanout position.
480 */
481 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
482
fe2b8f9d 483 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 484 *vpos = position / htotal;
485 *hpos = position - (*vpos * htotal);
486 }
487
488 /* Query vblank area. */
fe2b8f9d 489 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 490
491 /* Test position against vblank region. */
492 vbl_start = vbl & 0x1fff;
493 vbl_end = (vbl >> 16) & 0x1fff;
494
495 if ((*vpos < vbl_start) || (*vpos > vbl_end))
496 in_vbl = false;
497
498 /* Inside "upper part" of vblank area? Apply corrective offset: */
499 if (in_vbl && (*vpos >= vbl_start))
500 *vpos = *vpos - vtotal;
501
502 /* Readouts valid? */
503 if (vbl > 0)
504 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
505
506 /* In vblank? */
507 if (in_vbl)
508 ret |= DRM_SCANOUTPOS_INVBL;
509
510 return ret;
511}
512
f71d4af4 513static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 514 int *max_error,
515 struct timeval *vblank_time,
516 unsigned flags)
517{
4041b853 518 struct drm_crtc *crtc;
0af7e4df 519
7eb552ae 520 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 521 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 522 return -EINVAL;
523 }
524
525 /* Get drm_crtc to timestamp: */
4041b853
CW		 526 crtc = intel_get_crtc_for_pipe(dev, pipe);
527 if (crtc == NULL) {
528 DRM_ERROR("Invalid crtc %d\n", pipe);
529 return -EINVAL;
530 }
531
532 if (!crtc->enabled) {
533 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
534 return -EBUSY;
535 }
0af7e4df
MK		 536
537 /* Helper routine in DRM core does all the work: */
4041b853
CW		 538 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
539 vblank_time, flags,
540 crtc);
0af7e4df
MK		 541}
542
321a1b30
EE		 543static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
544{
545 enum drm_connector_status old_status;
546
547 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
548 old_status = connector->status;
549
550 connector->status = connector->funcs->detect(connector, false);
551 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
552 connector->base.id,
553 drm_get_connector_name(connector),
554 old_status, connector->status);
555 return (old_status != connector->status);
556}
557
5ca58282
JB		 558/*
559 * Handle hotplug events outside the interrupt handler proper.
560 */
ac4c16c5
EE		 561#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
562
5ca58282
JB		 563static void i915_hotplug_work_func(struct work_struct *work)
564{
565 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
566 hotplug_work);
567 struct drm_device *dev = dev_priv->dev;
c31c4ba3 568 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 569 struct intel_connector *intel_connector;
570 struct intel_encoder *intel_encoder;
571 struct drm_connector *connector;
572 unsigned long irqflags;
573 bool hpd_disabled = false;
321a1b30 574 bool changed = false;
142e2398 575 u32 hpd_event_bits;
4ef69c7a 576
52d7eced
DV		 577 /* HPD irq before everything is fully set up. */
578 if (!dev_priv->enable_hotplug_processing)
579 return;
580
a65e34c7 581 mutex_lock(&mode_config->mutex);
e67189ab
JB		 582 DRM_DEBUG_KMS("running encoder hotplug functions\n");
583
cd569aed 584 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 585
586 hpd_event_bits = dev_priv->hpd_event_bits;
587 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 588 list_for_each_entry(connector, &mode_config->connector_list, head) {
589 intel_connector = to_intel_connector(connector);
590 intel_encoder = intel_connector->encoder;
591 if (intel_encoder->hpd_pin > HPD_NONE &&
592 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
593 connector->polled == DRM_CONNECTOR_POLL_HPD) {
594 DRM_INFO("HPD interrupt storm detected on connector %s: "
595 "switching from hotplug detection to polling\n",
596 drm_get_connector_name(connector));
597 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
598 connector->polled = DRM_CONNECTOR_POLL_CONNECT
599 | DRM_CONNECTOR_POLL_DISCONNECT;
600 hpd_disabled = true;
601 }
142e2398
EE		 602 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
603 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
604 drm_get_connector_name(connector), intel_encoder->hpd_pin);
605 }
cd569aed
EE		 606 }
607 /* if there were no outputs to poll, poll was disabled,
608 * therefore make sure it's enabled when disabling HPD on
609 * some connectors */
ac4c16c5 610 if (hpd_disabled) {
cd569aed 611 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 612 mod_timer(&dev_priv->hotplug_reenable_timer,
613 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
614 }
cd569aed
EE		 615
616 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
617
321a1b30
EE		 618 list_for_each_entry(connector, &mode_config->connector_list, head) {
619 intel_connector = to_intel_connector(connector);
620 intel_encoder = intel_connector->encoder;
621 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
622 if (intel_encoder->hot_plug)
623 intel_encoder->hot_plug(intel_encoder);
624 if (intel_hpd_irq_event(dev, connector))
625 changed = true;
626 }
627 }
40ee3381
KP		 628 mutex_unlock(&mode_config->mutex);
629
321a1b30
EE		 630 if (changed)
631 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 632}
633
73edd18f 634static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 635{
636 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 637 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 638 u8 new_delay;
639 unsigned long flags;
640
641 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 642
73edd18f
DV		 643 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
644
20e4d407 645 new_delay = dev_priv->ips.cur_delay;
9270388e 646
7648fa99 647 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 648 busy_up = I915_READ(RCPREVBSYTUPAVG);
649 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 650 max_avg = I915_READ(RCBMAXAVG);
651 min_avg = I915_READ(RCBMINAVG);
652
653 /* Handle RCS change request from hw */
b5b72e89 654 if (busy_up > max_avg) {
20e4d407
DV		 655 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
656 new_delay = dev_priv->ips.cur_delay - 1;
657 if (new_delay < dev_priv->ips.max_delay)
658 new_delay = dev_priv->ips.max_delay;
b5b72e89 659 } else if (busy_down < min_avg) {
20e4d407
DV		 660 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
661 new_delay = dev_priv->ips.cur_delay + 1;
662 if (new_delay > dev_priv->ips.min_delay)
663 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 664 }
665
7648fa99 666 if (ironlake_set_drps(dev, new_delay))
20e4d407 667 dev_priv->ips.cur_delay = new_delay;
f97108d1 668
9270388e
DV		 669 spin_unlock_irqrestore(&mchdev_lock, flags);
670
f97108d1
JB		 671 return;
672}
673
549f7365
CW		 674static void notify_ring(struct drm_device *dev,
675 struct intel_ring_buffer *ring)
676{
677 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 678
475553de
CW		 679 if (ring->obj == NULL)
680 return;
681
b2eadbc8 682 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 683
549f7365 684 wake_up_all(&ring->irq_queue);
3e0dc6b0 685 if (i915_enable_hangcheck) {
99584db3 686 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 687 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 688 }
549f7365
CW		 689}
690
4912d041 691static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 692{
4912d041 693 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 694 rps.work);
4912d041 695 u32 pm_iir, pm_imr;
7b9e0ae6 696 u8 new_delay;
4912d041 697
c6a828d3
DV		 698 spin_lock_irq(&dev_priv->rps.lock);
699 pm_iir = dev_priv->rps.pm_iir;
700 dev_priv->rps.pm_iir = 0;
4912d041 701 pm_imr = I915_READ(GEN6_PMIMR);
4848405c
BW		 702 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
703 I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
c6a828d3 704 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 705
4848405c 706 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 707 return;
708
4fc688ce 709 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6
CW		 710
711 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 712 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 713 else
c6a828d3 714 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 715
79249636
BW		 716 /* sysfs frequency interfaces may have snuck in while servicing the
717 * interrupt
718 */
719 if (!(new_delay > dev_priv->rps.max_delay ||
720 new_delay < dev_priv->rps.min_delay)) {
0a073b84
JB		 721 if (IS_VALLEYVIEW(dev_priv->dev))
722 valleyview_set_rps(dev_priv->dev, new_delay);
723 else
724 gen6_set_rps(dev_priv->dev, new_delay);
79249636 725 }
3b8d8d91 726
52ceb908
JB		 727 if (IS_VALLEYVIEW(dev_priv->dev)) {
728 /*
729 * On VLV, when we enter RC6 we may not be at the minimum
730 * voltage level, so arm a timer to check. It should only
731 * fire when there's activity or once after we've entered
732 * RC6, and then won't be re-armed until the next RPS interrupt.
733 */
734 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
735 msecs_to_jiffies(100));
736 }
737
4fc688ce 738 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 739}
740
e3689190
BW		 741
742/**
743 * ivybridge_parity_work - Workqueue called when a parity error interrupt
744 * occurred.
745 * @work: workqueue struct
746 *
747 * Doesn't actually do anything except notify userspace. As a consequence of
748 * this event, userspace should try to remap the bad rows since statistically
749 * it is likely the same row is more likely to go bad again.
750 */
751static void ivybridge_parity_work(struct work_struct *work)
752{
753 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 754 l3_parity.error_work);
e3689190
BW		 755 u32 error_status, row, bank, subbank;
756 char *parity_event[5];
757 uint32_t misccpctl;
758 unsigned long flags;
759
760 /* We must turn off DOP level clock gating to access the L3 registers.
761 * In order to prevent a get/put style interface, acquire struct mutex
762 * any time we access those registers.
763 */
764 mutex_lock(&dev_priv->dev->struct_mutex);
765
766 misccpctl = I915_READ(GEN7_MISCCPCTL);
767 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
768 POSTING_READ(GEN7_MISCCPCTL);
769
770 error_status = I915_READ(GEN7_L3CDERRST1);
771 row = GEN7_PARITY_ERROR_ROW(error_status);
772 bank = GEN7_PARITY_ERROR_BANK(error_status);
773 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
774
775 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
776 GEN7_L3CDERRST1_ENABLE);
777 POSTING_READ(GEN7_L3CDERRST1);
778
779 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
780
781 spin_lock_irqsave(&dev_priv->irq_lock, flags);
cc609d5d 782 dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
e3689190
BW		 783 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
784 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
785
786 mutex_unlock(&dev_priv->dev->struct_mutex);
787
788 parity_event[0] = "L3_PARITY_ERROR=1";
789 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
790 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
791 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
792 parity_event[4] = NULL;
793
794 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
795 KOBJ_CHANGE, parity_event);
796
797 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
798 row, bank, subbank);
799
800 kfree(parity_event[3]);
801 kfree(parity_event[2]);
802 kfree(parity_event[1]);
803}
804
d2ba8470 805static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 806{
807 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
808 unsigned long flags;
809
e1ef7cc2 810 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 811 return;
812
813 spin_lock_irqsave(&dev_priv->irq_lock, flags);
cc609d5d 814 dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
e3689190
BW		 815 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
816 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
817
a4da4fa4 818 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 819}
820
e7b4c6b1
DV		 821static void snb_gt_irq_handler(struct drm_device *dev,
822 struct drm_i915_private *dev_priv,
823 u32 gt_iir)
824{
825
cc609d5d
BW		 826 if (gt_iir &
827 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 828 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 829 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 830 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 831 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 832 notify_ring(dev, &dev_priv->ring[BCS]);
833
cc609d5d
BW		 834 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
835 GT_BSD_CS_ERROR_INTERRUPT |
836 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 837 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
838 i915_handle_error(dev, false);
839 }
e3689190 840
cc609d5d 841 if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
e3689190 842 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 843}
844
baf02a1f 845/* Legacy way of handling PM interrupts */
fc6826d1
CW		 846static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
847 u32 pm_iir)
848{
849 unsigned long flags;
850
851 /*
852 * IIR bits should never already be set because IMR should
853 * prevent an interrupt from being shown in IIR. The warning
854 * displays a case where we've unsafely cleared
c6a828d3 855 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 856 * type is not a problem, it displays a problem in the logic.
857 *
c6a828d3 858 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 859 */
860
c6a828d3 861 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 862 dev_priv->rps.pm_iir |= pm_iir;
863 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 864 POSTING_READ(GEN6_PMIMR);
c6a828d3 865 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 866
c6a828d3 867 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 868}
869
b543fb04
EE		 870#define HPD_STORM_DETECT_PERIOD 1000
871#define HPD_STORM_THRESHOLD 5
872
cd569aed 873static inline bool hotplug_irq_storm_detect(struct drm_device *dev,
b543fb04
EE		 874 u32 hotplug_trigger,
875 const u32 *hpd)
876{
877 drm_i915_private_t *dev_priv = dev->dev_private;
878 unsigned long irqflags;
879 int i;
cd569aed 880 bool ret = false;
b543fb04
EE		 881
882 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
883
884 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 885
b543fb04
EE		 886 if (!(hpd[i] & hotplug_trigger) ||
887 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
888 continue;
889
bc5ead8c 890 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 891 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
892 dev_priv->hpd_stats[i].hpd_last_jiffies
893 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
894 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
895 dev_priv->hpd_stats[i].hpd_cnt = 0;
896 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
897 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 898 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 899 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
cd569aed 900 ret = true;
b543fb04
EE		 901 } else {
902 dev_priv->hpd_stats[i].hpd_cnt++;
903 }
904 }
905
906 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
cd569aed
EE		 907
908 return ret;
b543fb04
EE		 909}
910
515ac2bb
DV		 911static void gmbus_irq_handler(struct drm_device *dev)
912{
28c70f16
DV		 913 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
914
28c70f16 915 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 916}
917
ce99c256
DV		 918static void dp_aux_irq_handler(struct drm_device *dev)
919{
9ee32fea
DV		 920 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
921
9ee32fea 922 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 923}
924
baf02a1f
BW		 925/* Unlike gen6_queue_rps_work() from which this function is originally derived,
926 * we must be able to deal with other PM interrupts. This is complicated because
927 * of the way in which we use the masks to defer the RPS work (which for
928 * posterity is necessary because of forcewake).
929 */
930static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
931 u32 pm_iir)
932{
933 unsigned long flags;
934
935 spin_lock_irqsave(&dev_priv->rps.lock, flags);
4848405c 936 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
baf02a1f
BW		 937 if (dev_priv->rps.pm_iir) {
938 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
939 /* never want to mask useful interrupts. (also posting read) */
4848405c 940 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
baf02a1f
BW		 941 /* TODO: if queue_work is slow, move it out of the spinlock */
942 queue_work(dev_priv->wq, &dev_priv->rps.work);
943 }
944 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
945
12638c57
BW		 946 if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
947 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
948 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
949
950 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
951 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
952 i915_handle_error(dev_priv->dev, false);
953 }
954 }
baf02a1f
BW		 955}
956
ff1f525e 957static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 958{
959 struct drm_device *dev = (struct drm_device *) arg;
960 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
961 u32 iir, gt_iir, pm_iir;
962 irqreturn_t ret = IRQ_NONE;
963 unsigned long irqflags;
964 int pipe;
965 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 966
967 atomic_inc(&dev_priv->irq_received);
968
7e231dbe
JB		 969 while (true) {
970 iir = I915_READ(VLV_IIR);
971 gt_iir = I915_READ(GTIIR);
972 pm_iir = I915_READ(GEN6_PMIIR);
973
974 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
975 goto out;
976
977 ret = IRQ_HANDLED;
978
e7b4c6b1 979 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 980
981 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
982 for_each_pipe(pipe) {
983 int reg = PIPESTAT(pipe);
984 pipe_stats[pipe] = I915_READ(reg);
985
986 /*
987 * Clear the PIPE*STAT regs before the IIR
988 */
989 if (pipe_stats[pipe] & 0x8000ffff) {
990 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
991 DRM_DEBUG_DRIVER("pipe %c underrun\n",
992 pipe_name(pipe));
993 I915_WRITE(reg, pipe_stats[pipe]);
994 }
995 }
996 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
997
31acc7f5
JB		 998 for_each_pipe(pipe) {
999 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1000 drm_handle_vblank(dev, pipe);
1001
1002 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1003 intel_prepare_page_flip(dev, pipe);
1004 intel_finish_page_flip(dev, pipe);
1005 }
1006 }
1007
7e231dbe
JB		 1008 /* Consume port. Then clear IIR or we'll miss events */
1009 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1010 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1011 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 1012
1013 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1014 hotplug_status);
b543fb04 1015 if (hotplug_trigger) {
cd569aed
EE		 1016 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
1017 i915_hpd_irq_setup(dev);
7e231dbe
JB		 1018 queue_work(dev_priv->wq,
1019 &dev_priv->hotplug_work);
b543fb04 1020 }
7e231dbe
JB		 1021 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1022 I915_READ(PORT_HOTPLUG_STAT);
1023 }
1024
515ac2bb
DV		 1025 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1026 gmbus_irq_handler(dev);
7e231dbe 1027
4848405c 1028 if (pm_iir & GEN6_PM_RPS_EVENTS)
fc6826d1 1029 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 1030
1031 I915_WRITE(GTIIR, gt_iir);
1032 I915_WRITE(GEN6_PMIIR, pm_iir);
1033 I915_WRITE(VLV_IIR, iir);
1034 }
1035
1036out:
1037 return ret;
1038}
1039
23e81d69 1040static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1041{
1042 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1043 int pipe;
b543fb04 1044 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1045
b543fb04 1046 if (hotplug_trigger) {
cd569aed
EE		 1047 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx))
1048 ibx_hpd_irq_setup(dev);
76e43830 1049 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
b543fb04 1050 }
cfc33bf7
VS		 1051 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1052 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1053 SDE_AUDIO_POWER_SHIFT);
776ad806 1054 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1055 port_name(port));
1056 }
776ad806 1057
ce99c256
DV		 1058 if (pch_iir & SDE_AUX_MASK)
1059 dp_aux_irq_handler(dev);
1060
776ad806 1061 if (pch_iir & SDE_GMBUS)
515ac2bb 1062 gmbus_irq_handler(dev);
776ad806
JB		 1063
1064 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1065 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1066
1067 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1068 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1069
1070 if (pch_iir & SDE_POISON)
1071 DRM_ERROR("PCH poison interrupt\n");
1072
9db4a9c7
JB		 1073 if (pch_iir & SDE_FDI_MASK)
1074 for_each_pipe(pipe)
1075 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1076 pipe_name(pipe),
1077 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1078
1079 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1080 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1081
1082 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1083 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1084
776ad806 1085 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1086 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1087 false))
1088 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1089
1090 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1091 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1092 false))
1093 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1094}
1095
1096static void ivb_err_int_handler(struct drm_device *dev)
1097{
1098 struct drm_i915_private *dev_priv = dev->dev_private;
1099 u32 err_int = I915_READ(GEN7_ERR_INT);
1100
de032bf4
PZ		 1101 if (err_int & ERR_INT_POISON)
1102 DRM_ERROR("Poison interrupt\n");
1103
8664281b
PZ		 1104 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1105 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1106 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1107
1108 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1109 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1110 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1111
1112 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1113 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1114 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1115
1116 I915_WRITE(GEN7_ERR_INT, err_int);
1117}
1118
1119static void cpt_serr_int_handler(struct drm_device *dev)
1120{
1121 struct drm_i915_private *dev_priv = dev->dev_private;
1122 u32 serr_int = I915_READ(SERR_INT);
1123
de032bf4
PZ		 1124 if (serr_int & SERR_INT_POISON)
1125 DRM_ERROR("PCH poison interrupt\n");
1126
8664281b
PZ		 1127 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1128 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1129 false))
1130 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1131
1132 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1133 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1134 false))
1135 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1136
1137 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1138 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1139 false))
1140 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1141
1142 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1143}
1144
23e81d69
AJ		 1145static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1146{
1147 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1148 int pipe;
b543fb04 1149 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1150
b543fb04 1151 if (hotplug_trigger) {
cd569aed
EE		 1152 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt))
1153 ibx_hpd_irq_setup(dev);
76e43830 1154 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
b543fb04 1155 }
cfc33bf7
VS		 1156 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1157 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1158 SDE_AUDIO_POWER_SHIFT_CPT);
1159 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1160 port_name(port));
1161 }
23e81d69
AJ		 1162
1163 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1164 dp_aux_irq_handler(dev);
23e81d69
AJ		 1165
1166 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1167 gmbus_irq_handler(dev);
23e81d69
AJ		 1168
1169 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1170 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1171
1172 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1173 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1174
1175 if (pch_iir & SDE_FDI_MASK_CPT)
1176 for_each_pipe(pipe)
1177 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1178 pipe_name(pipe),
1179 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1180
1181 if (pch_iir & SDE_ERROR_CPT)
1182 cpt_serr_int_handler(dev);
23e81d69
AJ		 1183}
1184
ff1f525e 1185static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1186{
1187 struct drm_device *dev = (struct drm_device *) arg;
1188 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
ab5c608b 1189 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
0e43406b
CW		 1190 irqreturn_t ret = IRQ_NONE;
1191 int i;
b1f14ad0
JB		 1192
1193 atomic_inc(&dev_priv->irq_received);
1194
8664281b
PZ		 1195 /* We get interrupts on unclaimed registers, so check for this before we
1196 * do any I915_{READ,WRITE}. */
1197 if (IS_HASWELL(dev) &&
1198 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1199 DRM_ERROR("Unclaimed register before interrupt\n");
1200 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1201 }
1202
b1f14ad0
JB		 1203 /* disable master interrupt before clearing iir */
1204 de_ier = I915_READ(DEIER);
1205 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 1206
44498aea
PZ		 1207 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1208 * interrupts will will be stored on its back queue, and then we'll be
1209 * able to process them after we restore SDEIER (as soon as we restore
1210 * it, we'll get an interrupt if SDEIIR still has something to process
1211 * due to its back queue). */
ab5c608b
BW		 1212 if (!HAS_PCH_NOP(dev)) {
1213 sde_ier = I915_READ(SDEIER);
1214 I915_WRITE(SDEIER, 0);
1215 POSTING_READ(SDEIER);
1216 }
44498aea 1217
8664281b
PZ		 1218 /* On Haswell, also mask ERR_INT because we don't want to risk
1219 * generating "unclaimed register" interrupts from inside the interrupt
1220 * handler. */
1221 if (IS_HASWELL(dev))
1222 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
1223
b1f14ad0 1224 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 1225 if (gt_iir) {
1226 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1227 I915_WRITE(GTIIR, gt_iir);
1228 ret = IRQ_HANDLED;
b1f14ad0
JB		 1229 }
1230
0e43406b
CW		 1231 de_iir = I915_READ(DEIIR);
1232 if (de_iir) {
8664281b
PZ		 1233 if (de_iir & DE_ERR_INT_IVB)
1234 ivb_err_int_handler(dev);
1235
ce99c256
DV		 1236 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1237 dp_aux_irq_handler(dev);
1238
0e43406b 1239 if (de_iir & DE_GSE_IVB)
81a07809 1240 intel_opregion_asle_intr(dev);
0e43406b
CW		 1241
1242 for (i = 0; i < 3; i++) {
74d44445
DV		 1243 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1244 drm_handle_vblank(dev, i);
0e43406b
CW		 1245 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1246 intel_prepare_page_flip(dev, i);
1247 intel_finish_page_flip_plane(dev, i);
1248 }
0e43406b 1249 }
b615b57a 1250
0e43406b 1251 /* check event from PCH */
ab5c608b 1252 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
0e43406b 1253 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 1254
23e81d69 1255 cpt_irq_handler(dev, pch_iir);
b1f14ad0 1256
0e43406b
CW		 1257 /* clear PCH hotplug event before clear CPU irq */
1258 I915_WRITE(SDEIIR, pch_iir);
1259 }
b615b57a 1260
0e43406b
CW		 1261 I915_WRITE(DEIIR, de_iir);
1262 ret = IRQ_HANDLED;
b1f14ad0
JB		 1263 }
1264
0e43406b
CW		 1265 pm_iir = I915_READ(GEN6_PMIIR);
1266 if (pm_iir) {
baf02a1f
BW		 1267 if (IS_HASWELL(dev))
1268 hsw_pm_irq_handler(dev_priv, pm_iir);
4848405c 1269 else if (pm_iir & GEN6_PM_RPS_EVENTS)
0e43406b
CW		 1270 gen6_queue_rps_work(dev_priv, pm_iir);
1271 I915_WRITE(GEN6_PMIIR, pm_iir);
1272 ret = IRQ_HANDLED;
1273 }
b1f14ad0 1274
8664281b
PZ		 1275 if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev))
1276 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1277
b1f14ad0
JB		 1278 I915_WRITE(DEIER, de_ier);
1279 POSTING_READ(DEIER);
ab5c608b
BW		 1280 if (!HAS_PCH_NOP(dev)) {
1281 I915_WRITE(SDEIER, sde_ier);
1282 POSTING_READ(SDEIER);
1283 }
b1f14ad0
JB		 1284
1285 return ret;
1286}
1287
e7b4c6b1
DV		 1288static void ilk_gt_irq_handler(struct drm_device *dev,
1289 struct drm_i915_private *dev_priv,
1290 u32 gt_iir)
1291{
cc609d5d
BW		 1292 if (gt_iir &
1293 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1294 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1295 if (gt_iir & ILK_BSD_USER_INTERRUPT)
e7b4c6b1
DV		 1296 notify_ring(dev, &dev_priv->ring[VCS]);
1297}
1298
ff1f525e 1299static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 1300{
4697995b 1301 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 1302 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1303 int ret = IRQ_NONE;
44498aea 1304 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
881f47b6 1305
4697995b
JB		 1306 atomic_inc(&dev_priv->irq_received);
1307
2d109a84
ZN		 1308 /* disable master interrupt before clearing iir */
1309 de_ier = I915_READ(DEIER);
1310 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 1311 POSTING_READ(DEIER);
2d109a84 1312
44498aea
PZ		 1313 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1314 * interrupts will will be stored on its back queue, and then we'll be
1315 * able to process them after we restore SDEIER (as soon as we restore
1316 * it, we'll get an interrupt if SDEIIR still has something to process
1317 * due to its back queue). */
1318 sde_ier = I915_READ(SDEIER);
1319 I915_WRITE(SDEIER, 0);
1320 POSTING_READ(SDEIER);
1321
036a4a7d
ZW		 1322 de_iir = I915_READ(DEIIR);
1323 gt_iir = I915_READ(GTIIR);
3b8d8d91 1324 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 1325
acd15b6c 1326 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 1327 goto done;
036a4a7d 1328
c7c85101 1329 ret = IRQ_HANDLED;
036a4a7d 1330
e7b4c6b1
DV		 1331 if (IS_GEN5(dev))
1332 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1333 else
1334 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 1335
ce99c256
DV		 1336 if (de_iir & DE_AUX_CHANNEL_A)
1337 dp_aux_irq_handler(dev);
1338
c7c85101 1339 if (de_iir & DE_GSE)
81a07809 1340 intel_opregion_asle_intr(dev);
c650156a 1341
74d44445
DV		 1342 if (de_iir & DE_PIPEA_VBLANK)
1343 drm_handle_vblank(dev, 0);
1344
1345 if (de_iir & DE_PIPEB_VBLANK)
1346 drm_handle_vblank(dev, 1);
1347
de032bf4
PZ		 1348 if (de_iir & DE_POISON)
1349 DRM_ERROR("Poison interrupt\n");
1350
8664281b
PZ		 1351 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1352 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1353 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1354
1355 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1356 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1357 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1358
f072d2e7 1359 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 1360 intel_prepare_page_flip(dev, 0);
2bbda389 1361 intel_finish_page_flip_plane(dev, 0);
f072d2e7 1362 }
013d5aa2 1363
f072d2e7 1364 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 1365 intel_prepare_page_flip(dev, 1);
2bbda389 1366 intel_finish_page_flip_plane(dev, 1);
f072d2e7 1367 }
013d5aa2 1368
c7c85101 1369 /* check event from PCH */
776ad806 1370 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 1371 u32 pch_iir = I915_READ(SDEIIR);
1372
23e81d69
AJ		 1373 if (HAS_PCH_CPT(dev))
1374 cpt_irq_handler(dev, pch_iir);
1375 else
1376 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 1377
1378 /* should clear PCH hotplug event before clear CPU irq */
1379 I915_WRITE(SDEIIR, pch_iir);
776ad806 1380 }
036a4a7d 1381
73edd18f
DV		 1382 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1383 ironlake_handle_rps_change(dev);
f97108d1 1384
4848405c 1385 if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
fc6826d1 1386 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 1387
c7c85101
ZN		 1388 I915_WRITE(GTIIR, gt_iir);
1389 I915_WRITE(DEIIR, de_iir);
4912d041 1390 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 1391
1392done:
2d109a84 1393 I915_WRITE(DEIER, de_ier);
3143a2bf 1394 POSTING_READ(DEIER);
44498aea
PZ		 1395 I915_WRITE(SDEIER, sde_ier);
1396 POSTING_READ(SDEIER);
2d109a84 1397
036a4a7d
ZW		 1398 return ret;
1399}
1400
8a905236
JB		 1401/**
1402 * i915_error_work_func - do process context error handling work
1403 * @work: work struct
1404 *
1405 * Fire an error uevent so userspace can see that a hang or error
1406 * was detected.
1407 */
1408static void i915_error_work_func(struct work_struct *work)
1409{
1f83fee0
DV		 1410 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1411 work);
1412 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1413 gpu_error);
8a905236 1414 struct drm_device *dev = dev_priv->dev;
f69061be 1415 struct intel_ring_buffer *ring;
f316a42c
BG		 1416 char *error_event[] = { "ERROR=1", NULL };
1417 char *reset_event[] = { "RESET=1", NULL };
1418 char *reset_done_event[] = { "ERROR=0", NULL };
f69061be 1419 int i, ret;
8a905236 1420
f316a42c
BG		 1421 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1422
7db0ba24
DV		 1423 /*
1424 * Note that there's only one work item which does gpu resets, so we
1425 * need not worry about concurrent gpu resets potentially incrementing
1426 * error->reset_counter twice. We only need to take care of another
1427 * racing irq/hangcheck declaring the gpu dead for a second time. A
1428 * quick check for that is good enough: schedule_work ensures the
1429 * correct ordering between hang detection and this work item, and since
1430 * the reset in-progress bit is only ever set by code outside of this
1431 * work we don't need to worry about any other races.
1432 */
1433 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1434 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1435 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1436 reset_event);
1f83fee0 1437
f69061be
DV		 1438 ret = i915_reset(dev);
1439
1440 if (ret == 0) {
1441 /*
1442 * After all the gem state is reset, increment the reset
1443 * counter and wake up everyone waiting for the reset to
1444 * complete.
1445 *
1446 * Since unlock operations are a one-sided barrier only,
1447 * we need to insert a barrier here to order any seqno
1448 * updates before
1449 * the counter increment.
1450 */
1451 smp_mb__before_atomic_inc();
1452 atomic_inc(&dev_priv->gpu_error.reset_counter);
1453
1454 kobject_uevent_env(&dev->primary->kdev.kobj,
1455 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1456 } else {
1457 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1458 }
1f83fee0 1459
f69061be
DV		 1460 for_each_ring(ring, dev_priv, i)
1461 wake_up_all(&ring->irq_queue);
1462
96a02917
VS		 1463 intel_display_handle_reset(dev);
1464
1f83fee0 1465 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 1466 }
8a905236
JB		 1467}
1468
85f9e50d
DV		 1469/* NB: please notice the memset */
1470static void i915_get_extra_instdone(struct drm_device *dev,
1471 uint32_t *instdone)
1472{
1473 struct drm_i915_private *dev_priv = dev->dev_private;
1474 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1475
1476 switch(INTEL_INFO(dev)->gen) {
1477 case 2:
1478 case 3:
1479 instdone[0] = I915_READ(INSTDONE);
1480 break;
1481 case 4:
1482 case 5:
1483 case 6:
1484 instdone[0] = I915_READ(INSTDONE_I965);
1485 instdone[1] = I915_READ(INSTDONE1);
1486 break;
1487 default:
1488 WARN_ONCE(1, "Unsupported platform\n");
1489 case 7:
1490 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1491 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1492 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1493 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1494 break;
1495 }
1496}
1497
3bd3c932 1498#ifdef CONFIG_DEBUG_FS
9df30794 1499static struct drm_i915_error_object *
d0d045e8
BW		 1500i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1501 struct drm_i915_gem_object *src,
1502 const int num_pages)
9df30794
CW		 1503{
1504 struct drm_i915_error_object *dst;
d0d045e8 1505 int i;
e56660dd 1506 u32 reloc_offset;
9df30794 1507
05394f39 1508 if (src == NULL || src->pages == NULL)
9df30794
CW		 1509 return NULL;
1510
d0d045e8 1511 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 1512 if (dst == NULL)
1513 return NULL;
1514
05394f39 1515 reloc_offset = src->gtt_offset;
d0d045e8 1516 for (i = 0; i < num_pages; i++) {
788885ae 1517 unsigned long flags;
e56660dd 1518 void *d;
788885ae 1519
e56660dd 1520 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 1521 if (d == NULL)
1522 goto unwind;
e56660dd 1523
788885ae 1524 local_irq_save(flags);
5d4545ae 1525 if (reloc_offset < dev_priv->gtt.mappable_end &&
74898d7e 1526 src->has_global_gtt_mapping) {
172975aa
CW		 1527 void __iomem *s;
1528
1529 /* Simply ignore tiling or any overlapping fence.
1530 * It's part of the error state, and this hopefully
1531 * captures what the GPU read.
1532 */
1533
5d4545ae 1534 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
172975aa
CW		 1535 reloc_offset);
1536 memcpy_fromio(d, s, PAGE_SIZE);
1537 io_mapping_unmap_atomic(s);
960e3564
CW		 1538 } else if (src->stolen) {
1539 unsigned long offset;
1540
1541 offset = dev_priv->mm.stolen_base;
1542 offset += src->stolen->start;
1543 offset += i << PAGE_SHIFT;
1544
1a240d4d 1545 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 1546 } else {
9da3da66 1547 struct page *page;
172975aa
CW		 1548 void *s;
1549
9da3da66 1550 page = i915_gem_object_get_page(src, i);
172975aa 1551
9da3da66
CW		 1552 drm_clflush_pages(&page, 1);
1553
1554 s = kmap_atomic(page);
172975aa
CW		 1555 memcpy(d, s, PAGE_SIZE);
1556 kunmap_atomic(s);
1557
9da3da66 1558 drm_clflush_pages(&page, 1);
172975aa 1559 }
788885ae 1560 local_irq_restore(flags);
e56660dd 1561
9da3da66 1562 dst->pages[i] = d;
e56660dd
CW		 1563
1564 reloc_offset += PAGE_SIZE;
9df30794 1565 }
d0d045e8 1566 dst->page_count = num_pages;
05394f39 1567 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 1568
1569 return dst;
1570
1571unwind:
9da3da66
CW		 1572 while (i--)
1573 kfree(dst->pages[i]);
9df30794
CW		 1574 kfree(dst);
1575 return NULL;
1576}
d0d045e8
BW		 1577#define i915_error_object_create(dev_priv, src) \
1578 i915_error_object_create_sized((dev_priv), (src), \
1579 (src)->base.size>>PAGE_SHIFT)
9df30794
CW		 1580
1581static void
1582i915_error_object_free(struct drm_i915_error_object *obj)
1583{
1584 int page;
1585
1586 if (obj == NULL)
1587 return;
1588
1589 for (page = 0; page < obj->page_count; page++)
1590 kfree(obj->pages[page]);
1591
1592 kfree(obj);
1593}
1594
742cbee8
DV		 1595void
1596i915_error_state_free(struct kref *error_ref)
9df30794 1597{
742cbee8
DV		 1598 struct drm_i915_error_state *error = container_of(error_ref,
1599 typeof(*error), ref);
e2f973d5
CW		 1600 int i;
1601
52d39a21
CW		 1602 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1603 i915_error_object_free(error->ring[i].batchbuffer);
1604 i915_error_object_free(error->ring[i].ringbuffer);
7ed73da0 1605 i915_error_object_free(error->ring[i].ctx);
52d39a21
CW		 1606 kfree(error->ring[i].requests);
1607 }
e2f973d5 1608
9df30794 1609 kfree(error->active_bo);
6ef3d427 1610 kfree(error->overlay);
7ed73da0 1611 kfree(error->display);
9df30794
CW		 1612 kfree(error);
1613}
1b50247a
CW		 1614static void capture_bo(struct drm_i915_error_buffer *err,
1615 struct drm_i915_gem_object *obj)
1616{
1617 err->size = obj->base.size;
1618 err->name = obj->base.name;
0201f1ec
CW		 1619 err->rseqno = obj->last_read_seqno;
1620 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1621 err->gtt_offset = obj->gtt_offset;
1622 err->read_domains = obj->base.read_domains;
1623 err->write_domain = obj->base.write_domain;
1624 err->fence_reg = obj->fence_reg;
1625 err->pinned = 0;
1626 if (obj->pin_count > 0)
1627 err->pinned = 1;
1628 if (obj->user_pin_count > 0)
1629 err->pinned = -1;
1630 err->tiling = obj->tiling_mode;
1631 err->dirty = obj->dirty;
1632 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1633 err->ring = obj->ring ? obj->ring->id : -1;
1634 err->cache_level = obj->cache_level;
1635}
9df30794 1636
1b50247a
CW		 1637static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1638 int count, struct list_head *head)
c724e8a9
CW		 1639{
1640 struct drm_i915_gem_object *obj;
1641 int i = 0;
1642
1643 list_for_each_entry(obj, head, mm_list) {
1b50247a 1644 capture_bo(err++, obj);
c724e8a9
CW		 1645 if (++i == count)
1646 break;
1b50247a
CW		 1647 }
1648
1649 return i;
1650}
1651
1652static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1653 int count, struct list_head *head)
1654{
1655 struct drm_i915_gem_object *obj;
1656 int i = 0;
1657
35c20a60 1658 list_for_each_entry(obj, head, global_list) {
1b50247a
CW		 1659 if (obj->pin_count == 0)
1660 continue;
c724e8a9 1661
1b50247a
CW		 1662 capture_bo(err++, obj);
1663 if (++i == count)
1664 break;
c724e8a9
CW		 1665 }
1666
1667 return i;
1668}
1669
748ebc60
CW		 1670static void i915_gem_record_fences(struct drm_device *dev,
1671 struct drm_i915_error_state *error)
1672{
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 int i;
1675
1676 /* Fences */
1677 switch (INTEL_INFO(dev)->gen) {
775d17b6 1678 case 7:
748ebc60 1679 case 6:
42b5aeab 1680 for (i = 0; i < dev_priv->num_fence_regs; i++)
748ebc60
CW		 1681 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1682 break;
1683 case 5:
1684 case 4:
1685 for (i = 0; i < 16; i++)
1686 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1687 break;
1688 case 3:
1689 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1690 for (i = 0; i < 8; i++)
1691 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1692 case 2:
1693 for (i = 0; i < 8; i++)
1694 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1695 break;
1696
7dbf9d6e
BW		 1697 default:
1698 BUG();
748ebc60
CW		 1699 }
1700}
1701
bcfb2e28
CW		 1702static struct drm_i915_error_object *
1703i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1704 struct intel_ring_buffer *ring)
1705{
1706 struct drm_i915_gem_object *obj;
1707 u32 seqno;
1708
1709 if (!ring->get_seqno)
1710 return NULL;
1711
b45305fc
DV		 1712 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1713 u32 acthd = I915_READ(ACTHD);
1714
1715 if (WARN_ON(ring->id != RCS))
1716 return NULL;
1717
1718 obj = ring->private;
1719 if (acthd >= obj->gtt_offset &&
1720 acthd < obj->gtt_offset + obj->base.size)
1721 return i915_error_object_create(dev_priv, obj);
1722 }
1723
b2eadbc8 1724 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1725 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1726 if (obj->ring != ring)
1727 continue;
1728
0201f1ec 1729 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1730 continue;
1731
1732 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1733 continue;
1734
1735 /* We need to copy these to an anonymous buffer as the simplest
1736 * method to avoid being overwritten by userspace.
1737 */
1738 return i915_error_object_create(dev_priv, obj);
1739 }
1740
1741 return NULL;
1742}
1743
d27b1e0e
DV		 1744static void i915_record_ring_state(struct drm_device *dev,
1745 struct drm_i915_error_state *error,
1746 struct intel_ring_buffer *ring)
1747{
1748 struct drm_i915_private *dev_priv = dev->dev_private;
1749
33f3f518 1750 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1751 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1752 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1753 error->semaphore_mboxes[ring->id][0]
1754 = I915_READ(RING_SYNC_0(ring->mmio_base));
1755 error->semaphore_mboxes[ring->id][1]
1756 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1757 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1758 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1759 }
c1cd90ed 1760
d27b1e0e 1761 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1762 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1763 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1764 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1765 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1766 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1767 if (ring->id == RCS)
d27b1e0e 1768 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1769 } else {
9d2f41fa 1770 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1771 error->ipeir[ring->id] = I915_READ(IPEIR);
1772 error->ipehr[ring->id] = I915_READ(IPEHR);
1773 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1774 }
1775
9574b3fe 1776 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1777 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1778 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1779 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1780 error->head[ring->id] = I915_READ_HEAD(ring);
1781 error->tail[ring->id] = I915_READ_TAIL(ring);
0f3b6849 1782 error->ctl[ring->id] = I915_READ_CTL(ring);
7e3b8737
DV		 1783
1784 error->cpu_ring_head[ring->id] = ring->head;
1785 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1786}
1787
8c123e54
BW		 1788
1789static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1790 struct drm_i915_error_state *error,
1791 struct drm_i915_error_ring *ering)
1792{
1793 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1794 struct drm_i915_gem_object *obj;
1795
1796 /* Currently render ring is the only HW context user */
1797 if (ring->id != RCS || !error->ccid)
1798 return;
1799
35c20a60 1800 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
8c123e54
BW		 1801 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1802 ering->ctx = i915_error_object_create_sized(dev_priv,
1803 obj, 1);
1804 }
1805 }
1806}
1807
52d39a21
CW		 1808static void i915_gem_record_rings(struct drm_device *dev,
1809 struct drm_i915_error_state *error)
1810{
1811 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1812 struct intel_ring_buffer *ring;
52d39a21
CW		 1813 struct drm_i915_gem_request *request;
1814 int i, count;
1815
b4519513 1816 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1817 i915_record_ring_state(dev, error, ring);
1818
1819 error->ring[i].batchbuffer =
1820 i915_error_first_batchbuffer(dev_priv, ring);
1821
1822 error->ring[i].ringbuffer =
1823 i915_error_object_create(dev_priv, ring->obj);
1824
8c123e54
BW		 1825
1826 i915_gem_record_active_context(ring, error, &error->ring[i]);
1827
52d39a21
CW		 1828 count = 0;
1829 list_for_each_entry(request, &ring->request_list, list)
1830 count++;
1831
1832 error->ring[i].num_requests = count;
1833 error->ring[i].requests =
1834 kmalloc(count*sizeof(struct drm_i915_error_request),
1835 GFP_ATOMIC);
1836 if (error->ring[i].requests == NULL) {
1837 error->ring[i].num_requests = 0;
1838 continue;
1839 }
1840
1841 count = 0;
1842 list_for_each_entry(request, &ring->request_list, list) {
1843 struct drm_i915_error_request *erq;
1844
1845 erq = &error->ring[i].requests[count++];
1846 erq->seqno = request->seqno;
1847 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1848 erq->tail = request->tail;
52d39a21
CW		 1849 }
1850 }
1851}
1852
8a905236
JB		 1853/**
1854 * i915_capture_error_state - capture an error record for later analysis
1855 * @dev: drm device
1856 *
1857 * Should be called when an error is detected (either a hang or an error
1858 * interrupt) to capture error state from the time of the error. Fills
1859 * out a structure which becomes available in debugfs for user level tools
1860 * to pick up.
1861 */
63eeaf38
JB		 1862static void i915_capture_error_state(struct drm_device *dev)
1863{
1864 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1865 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1866 struct drm_i915_error_state *error;
1867 unsigned long flags;
9db4a9c7 1868 int i, pipe;
63eeaf38 1869
99584db3
DV		 1870 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1871 error = dev_priv->gpu_error.first_error;
1872 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1873 if (error)
1874 return;
63eeaf38 1875
9db4a9c7 1876 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1877 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1878 if (!error) {
9df30794
CW		 1879 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1880 return;
63eeaf38
JB		 1881 }
1882
5d83d294 1883 DRM_INFO("capturing error event; look for more information in "
2f86f191 1884 "/sys/kernel/debug/dri/%d/i915_error_state\n",
b6f7833b 1885 dev->primary->index);
2fa772f3 1886
742cbee8 1887 kref_init(&error->ref);
63eeaf38
JB		 1888 error->eir = I915_READ(EIR);
1889 error->pgtbl_er = I915_READ(PGTBL_ER);
211816ec
BW		 1890 if (HAS_HW_CONTEXTS(dev))
1891 error->ccid = I915_READ(CCID);
be998e2e
BW		 1892
1893 if (HAS_PCH_SPLIT(dev))
1894 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1895 else if (IS_VALLEYVIEW(dev))
1896 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1897 else if (IS_GEN2(dev))
1898 error->ier = I915_READ16(IER);
1899 else
1900 error->ier = I915_READ(IER);
1901
0f3b6849
CW		 1902 if (INTEL_INFO(dev)->gen >= 6)
1903 error->derrmr = I915_READ(DERRMR);
1904
1905 if (IS_VALLEYVIEW(dev))
1906 error->forcewake = I915_READ(FORCEWAKE_VLV);
1907 else if (INTEL_INFO(dev)->gen >= 7)
1908 error->forcewake = I915_READ(FORCEWAKE_MT);
1909 else if (INTEL_INFO(dev)->gen == 6)
1910 error->forcewake = I915_READ(FORCEWAKE);
1911
4f3308b9
PZ		 1912 if (!HAS_PCH_SPLIT(dev))
1913 for_each_pipe(pipe)
1914 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1915
33f3f518 1916 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1917 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1918 error->done_reg = I915_READ(DONE_REG);
1919 }
d27b1e0e 1920
71e172e8
BW		 1921 if (INTEL_INFO(dev)->gen == 7)
1922 error->err_int = I915_READ(GEN7_ERR_INT);
1923
050ee91f
BW		 1924 i915_get_extra_instdone(dev, error->extra_instdone);
1925
748ebc60 1926 i915_gem_record_fences(dev, error);
52d39a21 1927 i915_gem_record_rings(dev, error);
9df30794 1928
c724e8a9 1929 /* Record buffers on the active and pinned lists. */
9df30794 1930 error->active_bo = NULL;
c724e8a9 1931 error->pinned_bo = NULL;
9df30794 1932
bcfb2e28
CW		 1933 i = 0;
1934 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1935 i++;
1936 error->active_bo_count = i;
35c20a60 1937 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1b50247a
CW		 1938 if (obj->pin_count)
1939 i++;
bcfb2e28 1940 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1941
8e934dbf
CW		 1942 error->active_bo = NULL;
1943 error->pinned_bo = NULL;
bcfb2e28
CW		 1944 if (i) {
1945 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1946 GFP_ATOMIC);
c724e8a9
CW		 1947 if (error->active_bo)
1948 error->pinned_bo =
1949 error->active_bo + error->active_bo_count;
9df30794
CW		 1950 }
1951
c724e8a9
CW		 1952 if (error->active_bo)
1953 error->active_bo_count =
1b50247a
CW		 1954 capture_active_bo(error->active_bo,
1955 error->active_bo_count,
1956 &dev_priv->mm.active_list);
c724e8a9
CW		 1957
1958 if (error->pinned_bo)
1959 error->pinned_bo_count =
1b50247a
CW		 1960 capture_pinned_bo(error->pinned_bo,
1961 error->pinned_bo_count,
6c085a72 1962 &dev_priv->mm.bound_list);
c724e8a9 1963
9df30794
CW		 1964 do_gettimeofday(&error->time);
1965
6ef3d427 1966 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1967 error->display = intel_display_capture_error_state(dev);
6ef3d427 1968
99584db3
DV		 1969 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1970 if (dev_priv->gpu_error.first_error == NULL) {
1971 dev_priv->gpu_error.first_error = error;
9df30794
CW		 1972 error = NULL;
1973 }
99584db3 1974 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1975
1976 if (error)
742cbee8 1977 i915_error_state_free(&error->ref);
9df30794
CW		 1978}
1979
1980void i915_destroy_error_state(struct drm_device *dev)
1981{
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 struct drm_i915_error_state *error;
6dc0e816 1984 unsigned long flags;
9df30794 1985
99584db3
DV		 1986 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1987 error = dev_priv->gpu_error.first_error;
1988 dev_priv->gpu_error.first_error = NULL;
1989 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1990
1991 if (error)
742cbee8 1992 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1993}
3bd3c932
CW		 1994#else
1995#define i915_capture_error_state(x)
1996#endif
63eeaf38 1997
35aed2e6 1998static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1999{
2000 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2001 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2002 u32 eir = I915_READ(EIR);
050ee91f 2003 int pipe, i;
8a905236 2004
35aed2e6
CW		 2005 if (!eir)
2006 return;
8a905236 2007
a70491cc 2008 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2009
bd9854f9
BW		 2010 i915_get_extra_instdone(dev, instdone);
2011
8a905236
JB		 2012 if (IS_G4X(dev)) {
2013 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2014 u32 ipeir = I915_READ(IPEIR_I965);
2015
a70491cc
JP		 2016 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2017 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2018 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2019 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2020 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2021 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2022 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2023 POSTING_READ(IPEIR_I965);
8a905236
JB		 2024 }
2025 if (eir & GM45_ERROR_PAGE_TABLE) {
2026 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2027 pr_err("page table error\n");
2028 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2029 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2030 POSTING_READ(PGTBL_ER);
8a905236
JB		 2031 }
2032 }
2033
a6c45cf0 2034 if (!IS_GEN2(dev)) {
8a905236
JB		 2035 if (eir & I915_ERROR_PAGE_TABLE) {
2036 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2037 pr_err("page table error\n");
2038 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2039 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2040 POSTING_READ(PGTBL_ER);
8a905236
JB		 2041 }
2042 }
2043
2044 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2045 pr_err("memory refresh error:\n");
9db4a9c7 2046 for_each_pipe(pipe)
a70491cc 2047 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2048 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2049 /* pipestat has already been acked */
2050 }
2051 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2052 pr_err("instruction error\n");
2053 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2054 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2055 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2056 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2057 u32 ipeir = I915_READ(IPEIR);
2058
a70491cc
JP		 2059 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2060 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2061 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2062 I915_WRITE(IPEIR, ipeir);
3143a2bf 2063 POSTING_READ(IPEIR);
8a905236
JB		 2064 } else {
2065 u32 ipeir = I915_READ(IPEIR_I965);
2066
a70491cc
JP		 2067 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2068 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2069 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2070 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2071 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2072 POSTING_READ(IPEIR_I965);
8a905236
JB		 2073 }
2074 }
2075
2076 I915_WRITE(EIR, eir);
3143a2bf 2077 POSTING_READ(EIR);
8a905236
JB		 2078 eir = I915_READ(EIR);
2079 if (eir) {
2080 /*
2081 * some errors might have become stuck,
2082 * mask them.
2083 */
2084 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2085 I915_WRITE(EMR, I915_READ(EMR) | eir);
2086 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2087 }
35aed2e6
CW		 2088}
2089
2090/**
2091 * i915_handle_error - handle an error interrupt
2092 * @dev: drm device
2093 *
2094 * Do some basic checking of regsiter state at error interrupt time and
2095 * dump it to the syslog. Also call i915_capture_error_state() to make
2096 * sure we get a record and make it available in debugfs. Fire a uevent
2097 * so userspace knows something bad happened (should trigger collection
2098 * of a ring dump etc.).
2099 */
527f9e90 2100void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 2101{
2102 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 2103 struct intel_ring_buffer *ring;
2104 int i;
35aed2e6
CW		 2105
2106 i915_capture_error_state(dev);
2107 i915_report_and_clear_eir(dev);
8a905236 2108
ba1234d1 2109 if (wedged) {
f69061be
DV		 2110 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2111 &dev_priv->gpu_error.reset_counter);
ba1234d1 2112
11ed50ec 2113 /*
1f83fee0
DV		 2114 * Wakeup waiting processes so that the reset work item
2115 * doesn't deadlock trying to grab various locks.
11ed50ec 2116 */
b4519513
CW		 2117 for_each_ring(ring, dev_priv, i)
2118 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 2119 }
2120
99584db3 2121 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 2122}
2123
21ad8330 2124static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 2125{
2126 drm_i915_private_t *dev_priv = dev->dev_private;
2127 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2129 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2130 struct intel_unpin_work *work;
2131 unsigned long flags;
2132 bool stall_detected;
2133
2134 /* Ignore early vblank irqs */
2135 if (intel_crtc == NULL)
2136 return;
2137
2138 spin_lock_irqsave(&dev->event_lock, flags);
2139 work = intel_crtc->unpin_work;
2140
e7d841ca
CW		 2141 if (work == NULL ||
2142 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2143 !work->enable_stall_check) {
4e5359cd
SF		 2144 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2145 spin_unlock_irqrestore(&dev->event_lock, flags);
2146 return;
2147 }
2148
2149 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2150 obj = work->pending_flip_obj;
a6c45cf0 2151 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2152 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 2153 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2154 obj->gtt_offset;
4e5359cd 2155 } else {
9db4a9c7 2156 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 2157 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 2158 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 2159 crtc->x * crtc->fb->bits_per_pixel/8);
2160 }
2161
2162 spin_unlock_irqrestore(&dev->event_lock, flags);
2163
2164 if (stall_detected) {
2165 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2166 intel_prepare_page_flip(dev, intel_crtc->plane);
2167 }
2168}
2169
42f52ef8
KP		 2170/* Called from drm generic code, passed 'crtc' which
2171 * we use as a pipe index
2172 */
f71d4af4 2173static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2174{
2175 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2176 unsigned long irqflags;
71e0ffa5 2177
5eddb70b 2178 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2179 return -EINVAL;
0a3e67a4 2180
1ec14ad3 2181 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2182 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 2183 i915_enable_pipestat(dev_priv, pipe,
2184 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 2185 else
7c463586
KP		 2186 i915_enable_pipestat(dev_priv, pipe,
2187 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 2188
2189 /* maintain vblank delivery even in deep C-states */
2190 if (dev_priv->info->gen == 3)
6b26c86d 2191 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 2192 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2193
0a3e67a4
JB		 2194 return 0;
2195}
2196
f71d4af4 2197static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2198{
2199 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2200 unsigned long irqflags;
2201
2202 if (!i915_pipe_enabled(dev, pipe))
2203 return -EINVAL;
2204
2205 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2206 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2207 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 2208 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2209
2210 return 0;
2211}
2212
f71d4af4 2213static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2214{
2215 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2216 unsigned long irqflags;
2217
2218 if (!i915_pipe_enabled(dev, pipe))
2219 return -EINVAL;
2220
2221 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2222 ironlake_enable_display_irq(dev_priv,
2223 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 2224 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2225
2226 return 0;
2227}
2228
7e231dbe
JB		 2229static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2230{
2231 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2232 unsigned long irqflags;
31acc7f5 2233 u32 imr;
7e231dbe
JB		 2234
2235 if (!i915_pipe_enabled(dev, pipe))
2236 return -EINVAL;
2237
2238 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 2239 imr = I915_READ(VLV_IMR);
31acc7f5 2240 if (pipe == 0)
7e231dbe 2241 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2242 else
7e231dbe 2243 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2244 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 2245 i915_enable_pipestat(dev_priv, pipe,
2246 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 2247 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2248
2249 return 0;
2250}
2251
42f52ef8
KP		 2252/* Called from drm generic code, passed 'crtc' which
2253 * we use as a pipe index
2254 */
f71d4af4 2255static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2256{
2257 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2258 unsigned long irqflags;
0a3e67a4 2259
1ec14ad3 2260 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 2261 if (dev_priv->info->gen == 3)
6b26c86d 2262 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2263
f796cf8f
JB		 2264 i915_disable_pipestat(dev_priv, pipe,
2265 PIPE_VBLANK_INTERRUPT_ENABLE |
2266 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2267 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2268}
2269
f71d4af4 2270static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2271{
2272 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2273 unsigned long irqflags;
2274
2275 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2276 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2277 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 2278 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 2279}
2280
f71d4af4 2281static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2282{
2283 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2284 unsigned long irqflags;
2285
2286 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2287 ironlake_disable_display_irq(dev_priv,
2288 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 2289 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2290}
2291
7e231dbe
JB		 2292static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2293{
2294 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2295 unsigned long irqflags;
31acc7f5 2296 u32 imr;
7e231dbe
JB		 2297
2298 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2299 i915_disable_pipestat(dev_priv, pipe,
2300 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 2301 imr = I915_READ(VLV_IMR);
31acc7f5 2302 if (pipe == 0)
7e231dbe 2303 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2304 else
7e231dbe 2305 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2306 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 2307 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2308}
2309
893eead0
CW		 2310static u32
2311ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2312{
893eead0
CW		 2313 return list_entry(ring->request_list.prev,
2314 struct drm_i915_gem_request, list)->seqno;
2315}
2316
9107e9d2
CW		 2317static bool
2318ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2319{
2320 return (list_empty(&ring->request_list) ||
2321 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 2322}
2323
6274f212
CW		 2324static struct intel_ring_buffer *
2325semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 2326{
2327 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 2328 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 2329
2330 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2331 if ((ipehr & ~(0x3 << 16)) !=
2332 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 2333 return NULL;
a24a11e6
CW		 2334
2335 /* ACTHD is likely pointing to the dword after the actual command,
2336 * so scan backwards until we find the MBOX.
2337 */
6274f212 2338 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 2339 acthd_min = max((int)acthd - 3 * 4, 0);
2340 do {
2341 cmd = ioread32(ring->virtual_start + acthd);
2342 if (cmd == ipehr)
2343 break;
2344
2345 acthd -= 4;
2346 if (acthd < acthd_min)
6274f212 2347 return NULL;
a24a11e6
CW		 2348 } while (1);
2349
6274f212
CW		 2350 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2351 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 2352}
2353
6274f212
CW		 2354static int semaphore_passed(struct intel_ring_buffer *ring)
2355{
2356 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2357 struct intel_ring_buffer *signaller;
2358 u32 seqno, ctl;
2359
2360 ring->hangcheck.deadlock = true;
2361
2362 signaller = semaphore_waits_for(ring, &seqno);
2363 if (signaller == NULL || signaller->hangcheck.deadlock)
2364 return -1;
2365
2366 /* cursory check for an unkickable deadlock */
2367 ctl = I915_READ_CTL(signaller);
2368 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2369 return -1;
2370
2371 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2372}
2373
2374static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2375{
2376 struct intel_ring_buffer *ring;
2377 int i;
2378
2379 for_each_ring(ring, dev_priv, i)
2380 ring->hangcheck.deadlock = false;
2381}
2382
ad8beaea
MK		 2383static enum intel_ring_hangcheck_action
2384ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 2385{
2386 struct drm_device *dev = ring->dev;
2387 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2388 u32 tmp;
2389
6274f212
CW		 2390 if (ring->hangcheck.acthd != acthd)
2391 return active;
2392
9107e9d2 2393 if (IS_GEN2(dev))
6274f212 2394 return hung;
9107e9d2
CW		 2395
2396 /* Is the chip hanging on a WAIT_FOR_EVENT?
2397 * If so we can simply poke the RB_WAIT bit
2398 * and break the hang. This should work on
2399 * all but the second generation chipsets.
2400 */
2401 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 2402 if (tmp & RING_WAIT) {
2403 DRM_ERROR("Kicking stuck wait on %s\n",
2404 ring->name);
2405 I915_WRITE_CTL(ring, tmp);
6274f212
CW		 2406 return kick;
2407 }
2408
2409 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2410 switch (semaphore_passed(ring)) {
2411 default:
2412 return hung;
2413 case 1:
2414 DRM_ERROR("Kicking stuck semaphore on %s\n",
2415 ring->name);
2416 I915_WRITE_CTL(ring, tmp);
2417 return kick;
2418 case 0:
2419 return wait;
2420 }
9107e9d2 2421 }
ed5cbb03 2422
6274f212 2423 return hung;
ed5cbb03
MK		 2424}
2425
f65d9421
BG		 2426/**
2427 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2428 * batchbuffers in a long time. We keep track per ring seqno progress and
2429 * if there are no progress, hangcheck score for that ring is increased.
2430 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2431 * we kick the ring. If we see no progress on three subsequent calls
2432 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421
BG		 2433 */
2434void i915_hangcheck_elapsed(unsigned long data)
2435{
2436 struct drm_device *dev = (struct drm_device *)data;
2437 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 2438 struct intel_ring_buffer *ring;
b4519513 2439 int i;
05407ff8 2440 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2441 bool stuck[I915_NUM_RINGS] = { 0 };
2442#define BUSY 1
2443#define KICK 5
2444#define HUNG 20
2445#define FIRE 30
893eead0 2446
3e0dc6b0
BW		 2447 if (!i915_enable_hangcheck)
2448 return;
2449
b4519513 2450 for_each_ring(ring, dev_priv, i) {
05407ff8 2451 u32 seqno, acthd;
9107e9d2 2452 bool busy = true;
05407ff8 2453
6274f212
CW		 2454 semaphore_clear_deadlocks(dev_priv);
2455
05407ff8
MK		 2456 seqno = ring->get_seqno(ring, false);
2457 acthd = intel_ring_get_active_head(ring);
b4519513 2458
9107e9d2
CW		 2459 if (ring->hangcheck.seqno == seqno) {
2460 if (ring_idle(ring, seqno)) {
2461 if (waitqueue_active(&ring->irq_queue)) {
2462 /* Issue a wake-up to catch stuck h/w. */
2463 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2464 ring->name);
2465 wake_up_all(&ring->irq_queue);
2466 ring->hangcheck.score += HUNG;
2467 } else
2468 busy = false;
05407ff8 2469 } else {
9107e9d2
CW		 2470 int score;
2471
6274f212
CW		 2472 /* We always increment the hangcheck score
2473 * if the ring is busy and still processing
2474 * the same request, so that no single request
2475 * can run indefinitely (such as a chain of
2476 * batches). The only time we do not increment
2477 * the hangcheck score on this ring, if this
2478 * ring is in a legitimate wait for another
2479 * ring. In that case the waiting ring is a
2480 * victim and we want to be sure we catch the
2481 * right culprit. Then every time we do kick
2482 * the ring, add a small increment to the
2483 * score so that we can catch a batch that is
2484 * being repeatedly kicked and so responsible
2485 * for stalling the machine.
2486 */
ad8beaea
MK		 2487 ring->hangcheck.action = ring_stuck(ring,
2488 acthd);
2489
2490 switch (ring->hangcheck.action) {
6274f212
CW		 2491 case wait:
2492 score = 0;
2493 break;
2494 case active:
9107e9d2 2495 score = BUSY;
6274f212
CW		 2496 break;
2497 case kick:
2498 score = KICK;
2499 break;
2500 case hung:
2501 score = HUNG;
2502 stuck[i] = true;
2503 break;
2504 }
9107e9d2 2505 ring->hangcheck.score += score;
05407ff8 2506 }
9107e9d2
CW		 2507 } else {
2508 /* Gradually reduce the count so that we catch DoS
2509 * attempts across multiple batches.
2510 */
2511 if (ring->hangcheck.score > 0)
2512 ring->hangcheck.score--;
d1e61e7f
CW		 2513 }
2514
05407ff8
MK		 2515 ring->hangcheck.seqno = seqno;
2516 ring->hangcheck.acthd = acthd;
9107e9d2 2517 busy_count += busy;
893eead0 2518 }
b9201c14 2519
92cab734 2520 for_each_ring(ring, dev_priv, i) {
9107e9d2 2521 if (ring->hangcheck.score > FIRE) {
acd78c11 2522 DRM_ERROR("%s on %s\n",
05407ff8 2523 stuck[i] ? "stuck" : "no progress",
a43adf07
CW		 2524 ring->name);
2525 rings_hung++;
92cab734
MK		 2526 }
2527 }
2528
05407ff8
MK		 2529 if (rings_hung)
2530 return i915_handle_error(dev, true);
f65d9421 2531
05407ff8
MK		 2532 if (busy_count)
2533 /* Reset timer case chip hangs without another request
2534 * being added */
2535 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2536 round_jiffies_up(jiffies +
2537 DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2538}
2539
91738a95
PZ		 2540static void ibx_irq_preinstall(struct drm_device *dev)
2541{
2542 struct drm_i915_private *dev_priv = dev->dev_private;
2543
2544 if (HAS_PCH_NOP(dev))
2545 return;
2546
2547 /* south display irq */
2548 I915_WRITE(SDEIMR, 0xffffffff);
2549 /*
2550 * SDEIER is also touched by the interrupt handler to work around missed
2551 * PCH interrupts. Hence we can't update it after the interrupt handler
2552 * is enabled - instead we unconditionally enable all PCH interrupt
2553 * sources here, but then only unmask them as needed with SDEIMR.
2554 */
2555 I915_WRITE(SDEIER, 0xffffffff);
2556 POSTING_READ(SDEIER);
2557}
2558
1da177e4
LT		 2559/* drm_dma.h hooks
2560*/
f71d4af4 2561static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2562{
2563 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2564
4697995b
JB		 2565 atomic_set(&dev_priv->irq_received, 0);
2566
036a4a7d 2567 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2568
036a4a7d
ZW		 2569 /* XXX hotplug from PCH */
2570
2571 I915_WRITE(DEIMR, 0xffffffff);
2572 I915_WRITE(DEIER, 0x0);
3143a2bf 2573 POSTING_READ(DEIER);
036a4a7d
ZW		 2574
2575 /* and GT */
2576 I915_WRITE(GTIMR, 0xffffffff);
2577 I915_WRITE(GTIER, 0x0);
3143a2bf 2578 POSTING_READ(GTIER);
c650156a 2579
91738a95 2580 ibx_irq_preinstall(dev);
7d99163d
BW		 2581}
2582
2583static void ivybridge_irq_preinstall(struct drm_device *dev)
2584{
2585 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2586
2587 atomic_set(&dev_priv->irq_received, 0);
2588
2589 I915_WRITE(HWSTAM, 0xeffe);
2590
2591 /* XXX hotplug from PCH */
2592
2593 I915_WRITE(DEIMR, 0xffffffff);
2594 I915_WRITE(DEIER, 0x0);
2595 POSTING_READ(DEIER);
2596
2597 /* and GT */
2598 I915_WRITE(GTIMR, 0xffffffff);
2599 I915_WRITE(GTIER, 0x0);
2600 POSTING_READ(GTIER);
2601
eda63ffb
BW		 2602 /* Power management */
2603 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2604 I915_WRITE(GEN6_PMIER, 0x0);
2605 POSTING_READ(GEN6_PMIER);
2606
91738a95 2607 ibx_irq_preinstall(dev);
036a4a7d
ZW		 2608}
2609
7e231dbe
JB		 2610static void valleyview_irq_preinstall(struct drm_device *dev)
2611{
2612 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2613 int pipe;
2614
2615 atomic_set(&dev_priv->irq_received, 0);
2616
7e231dbe
JB		 2617 /* VLV magic */
2618 I915_WRITE(VLV_IMR, 0);
2619 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2620 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2621 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2622
7e231dbe
JB		 2623 /* and GT */
2624 I915_WRITE(GTIIR, I915_READ(GTIIR));
2625 I915_WRITE(GTIIR, I915_READ(GTIIR));
2626 I915_WRITE(GTIMR, 0xffffffff);
2627 I915_WRITE(GTIER, 0x0);
2628 POSTING_READ(GTIER);
2629
2630 I915_WRITE(DPINVGTT, 0xff);
2631
2632 I915_WRITE(PORT_HOTPLUG_EN, 0);
2633 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2634 for_each_pipe(pipe)
2635 I915_WRITE(PIPESTAT(pipe), 0xffff);
2636 I915_WRITE(VLV_IIR, 0xffffffff);
2637 I915_WRITE(VLV_IMR, 0xffffffff);
2638 I915_WRITE(VLV_IER, 0x0);
2639 POSTING_READ(VLV_IER);
2640}
2641
82a28bcf 2642static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2643{
2644 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2645 struct drm_mode_config *mode_config = &dev->mode_config;
2646 struct intel_encoder *intel_encoder;
2647 u32 mask = ~I915_READ(SDEIMR);
2648 u32 hotplug;
2649
2650 if (HAS_PCH_IBX(dev)) {
995e6b3d 2651 mask &= ~SDE_HOTPLUG_MASK;
82a28bcf 2652 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed
EE		 2653 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2654 mask |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2655 } else {
995e6b3d 2656 mask &= ~SDE_HOTPLUG_MASK_CPT;
82a28bcf 2657 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed
EE		 2658 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2659 mask |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2660 }
7fe0b973 2661
82a28bcf
DV		 2662 I915_WRITE(SDEIMR, ~mask);
2663
2664 /*
2665 * Enable digital hotplug on the PCH, and configure the DP short pulse
2666 * duration to 2ms (which is the minimum in the Display Port spec)
2667 *
2668 * This register is the same on all known PCH chips.
2669 */
7fe0b973
KP		 2670 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2671 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2672 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2673 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2674 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2675 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2676}
2677
d46da437
PZ		 2678static void ibx_irq_postinstall(struct drm_device *dev)
2679{
2680 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2681 u32 mask;
e5868a31 2682
692a04cf
DV		 2683 if (HAS_PCH_NOP(dev))
2684 return;
2685
8664281b
PZ		 2686 if (HAS_PCH_IBX(dev)) {
2687 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2688 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2689 } else {
2690 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2691
2692 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2693 }
ab5c608b 2694
d46da437
PZ		 2695 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2696 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2697}
2698
f71d4af4 2699static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 2700{
2701 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2702 /* enable kind of interrupts always enabled */
013d5aa2 2703 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
ce99c256 2704 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
8664281b 2705 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
de032bf4 2706 DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
cc609d5d 2707 u32 gt_irqs;
036a4a7d 2708
1ec14ad3 2709 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2710
2711 /* should always can generate irq */
2712 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 2713 I915_WRITE(DEIMR, dev_priv->irq_mask);
2714 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 2715 POSTING_READ(DEIER);
036a4a7d 2716
1ec14ad3 2717 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 2718
2719 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 2720 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 2721
cc609d5d
BW		 2722 gt_irqs = GT_RENDER_USER_INTERRUPT;
2723
1ec14ad3 2724 if (IS_GEN6(dev))
cc609d5d 2725 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
1ec14ad3 2726 else
cc609d5d
BW		 2727 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2728 ILK_BSD_USER_INTERRUPT;
2729
2730 I915_WRITE(GTIER, gt_irqs);
3143a2bf 2731 POSTING_READ(GTIER);
036a4a7d 2732
d46da437 2733 ibx_irq_postinstall(dev);
7fe0b973 2734
f97108d1
JB		 2735 if (IS_IRONLAKE_M(dev)) {
2736 /* Clear & enable PCU event interrupts */
2737 I915_WRITE(DEIIR, DE_PCU_EVENT);
2738 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2739 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2740 }
2741
036a4a7d
ZW		 2742 return 0;
2743}
2744
f71d4af4 2745static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2746{
2747 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2748 /* enable kind of interrupts always enabled */
b615b57a
CW		 2749 u32 display_mask =
2750 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2751 DE_PLANEC_FLIP_DONE_IVB |
2752 DE_PLANEB_FLIP_DONE_IVB |
ce99c256 2753 DE_PLANEA_FLIP_DONE_IVB |
8664281b
PZ		 2754 DE_AUX_CHANNEL_A_IVB |
2755 DE_ERR_INT_IVB;
12638c57 2756 u32 pm_irqs = GEN6_PM_RPS_EVENTS;
cc609d5d 2757 u32 gt_irqs;
b1f14ad0 2758
b1f14ad0
JB		 2759 dev_priv->irq_mask = ~display_mask;
2760
2761 /* should always can generate irq */
8664281b 2762 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
b1f14ad0
JB		 2763 I915_WRITE(DEIIR, I915_READ(DEIIR));
2764 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 2765 I915_WRITE(DEIER,
2766 display_mask |
2767 DE_PIPEC_VBLANK_IVB |
2768 DE_PIPEB_VBLANK_IVB |
2769 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 2770 POSTING_READ(DEIER);
2771
cc609d5d 2772 dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2773
2774 I915_WRITE(GTIIR, I915_READ(GTIIR));
2775 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2776
cc609d5d
BW		 2777 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2778 GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2779 I915_WRITE(GTIER, gt_irqs);
b1f14ad0
JB		 2780 POSTING_READ(GTIER);
2781
12638c57
BW		 2782 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2783 if (HAS_VEBOX(dev))
2784 pm_irqs |= PM_VEBOX_USER_INTERRUPT |
2785 PM_VEBOX_CS_ERROR_INTERRUPT;
2786
2787 /* Our enable/disable rps functions may touch these registers so
2788 * make sure to set a known state for only the non-RPS bits.
2789 * The RMW is extra paranoia since this should be called after being set
2790 * to a known state in preinstall.
2791 * */
2792 I915_WRITE(GEN6_PMIMR,
2793 (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs);
2794 I915_WRITE(GEN6_PMIER,
2795 (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs);
2796 POSTING_READ(GEN6_PMIER);
eda63ffb 2797
d46da437 2798 ibx_irq_postinstall(dev);
7fe0b973 2799
b1f14ad0
JB		 2800 return 0;
2801}
2802
7e231dbe
JB		 2803static int valleyview_irq_postinstall(struct drm_device *dev)
2804{
2805 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
cc609d5d 2806 u32 gt_irqs;
7e231dbe 2807 u32 enable_mask;
31acc7f5 2808 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
7e231dbe
JB		 2809
2810 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2811 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2812 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2813 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2814 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2815
31acc7f5
JB		 2816 /*
2817 *Leave vblank interrupts masked initially. enable/disable will
2818 * toggle them based on usage.
2819 */
2820 dev_priv->irq_mask = (~enable_mask) |
2821 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2822 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2823
20afbda2
DV		 2824 I915_WRITE(PORT_HOTPLUG_EN, 0);
2825 POSTING_READ(PORT_HOTPLUG_EN);
2826
7e231dbe
JB		 2827 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2828 I915_WRITE(VLV_IER, enable_mask);
2829 I915_WRITE(VLV_IIR, 0xffffffff);
2830 I915_WRITE(PIPESTAT(0), 0xffff);
2831 I915_WRITE(PIPESTAT(1), 0xffff);
2832 POSTING_READ(VLV_IER);
2833
31acc7f5 2834 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2835 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5
JB		 2836 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2837
7e231dbe
JB		 2838 I915_WRITE(VLV_IIR, 0xffffffff);
2839 I915_WRITE(VLV_IIR, 0xffffffff);
2840
7e231dbe 2841 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2842 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5 2843
cc609d5d
BW		 2844 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2845 GT_BLT_USER_INTERRUPT;
2846 I915_WRITE(GTIER, gt_irqs);
7e231dbe
JB		 2847 POSTING_READ(GTIER);
2848
2849 /* ack & enable invalid PTE error interrupts */
2850#if 0 /* FIXME: add support to irq handler for checking these bits */
2851 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2852 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2853#endif
2854
2855 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2856
2857 return 0;
2858}
2859
7e231dbe
JB		 2860static void valleyview_irq_uninstall(struct drm_device *dev)
2861{
2862 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2863 int pipe;
2864
2865 if (!dev_priv)
2866 return;
2867
ac4c16c5
EE		 2868 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2869
7e231dbe
JB		 2870 for_each_pipe(pipe)
2871 I915_WRITE(PIPESTAT(pipe), 0xffff);
2872
2873 I915_WRITE(HWSTAM, 0xffffffff);
2874 I915_WRITE(PORT_HOTPLUG_EN, 0);
2875 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2876 for_each_pipe(pipe)
2877 I915_WRITE(PIPESTAT(pipe), 0xffff);
2878 I915_WRITE(VLV_IIR, 0xffffffff);
2879 I915_WRITE(VLV_IMR, 0xffffffff);
2880 I915_WRITE(VLV_IER, 0x0);
2881 POSTING_READ(VLV_IER);
2882}
2883
f71d4af4 2884static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2885{
2886 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2887
2888 if (!dev_priv)
2889 return;
2890
ac4c16c5
EE		 2891 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2892
036a4a7d
ZW		 2893 I915_WRITE(HWSTAM, 0xffffffff);
2894
2895 I915_WRITE(DEIMR, 0xffffffff);
2896 I915_WRITE(DEIER, 0x0);
2897 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2898 if (IS_GEN7(dev))
2899 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2900
2901 I915_WRITE(GTIMR, 0xffffffff);
2902 I915_WRITE(GTIER, 0x0);
2903 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2904
ab5c608b
BW		 2905 if (HAS_PCH_NOP(dev))
2906 return;
2907
192aac1f
KP		 2908 I915_WRITE(SDEIMR, 0xffffffff);
2909 I915_WRITE(SDEIER, 0x0);
2910 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2911 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2912 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2913}
2914
a266c7d5 2915static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2916{
2917 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2918 int pipe;
91e3738e 2919
a266c7d5 2920 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2921
9db4a9c7
JB		 2922 for_each_pipe(pipe)
2923 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2924 I915_WRITE16(IMR, 0xffff);
2925 I915_WRITE16(IER, 0x0);
2926 POSTING_READ16(IER);
c2798b19
CW		 2927}
2928
2929static int i8xx_irq_postinstall(struct drm_device *dev)
2930{
2931 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2932
c2798b19
CW		 2933 I915_WRITE16(EMR,
2934 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2935
2936 /* Unmask the interrupts that we always want on. */
2937 dev_priv->irq_mask =
2938 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2939 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2940 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2941 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2942 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2943 I915_WRITE16(IMR, dev_priv->irq_mask);
2944
2945 I915_WRITE16(IER,
2946 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2947 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2948 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2949 I915_USER_INTERRUPT);
2950 POSTING_READ16(IER);
2951
2952 return 0;
2953}
2954
90a72f87
VS		 2955/*
2956 * Returns true when a page flip has completed.
2957 */
2958static bool i8xx_handle_vblank(struct drm_device *dev,
2959 int pipe, u16 iir)
2960{
2961 drm_i915_private_t *dev_priv = dev->dev_private;
2962 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2963
2964 if (!drm_handle_vblank(dev, pipe))
2965 return false;
2966
2967 if ((iir & flip_pending) == 0)
2968 return false;
2969
2970 intel_prepare_page_flip(dev, pipe);
2971
2972 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2973 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2974 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2975 * the flip is completed (no longer pending). Since this doesn't raise
2976 * an interrupt per se, we watch for the change at vblank.
2977 */
2978 if (I915_READ16(ISR) & flip_pending)
2979 return false;
2980
2981 intel_finish_page_flip(dev, pipe);
2982
2983 return true;
2984}
2985
ff1f525e 2986static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2987{
2988 struct drm_device *dev = (struct drm_device *) arg;
2989 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2990 u16 iir, new_iir;
2991 u32 pipe_stats[2];
2992 unsigned long irqflags;
2993 int irq_received;
2994 int pipe;
2995 u16 flip_mask =
2996 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2997 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2998
2999 atomic_inc(&dev_priv->irq_received);
3000
3001 iir = I915_READ16(IIR);
3002 if (iir == 0)
3003 return IRQ_NONE;
3004
3005 while (iir & ~flip_mask) {
3006 /* Can't rely on pipestat interrupt bit in iir as it might
3007 * have been cleared after the pipestat interrupt was received.
3008 * It doesn't set the bit in iir again, but it still produces
3009 * interrupts (for non-MSI).
3010 */
3011 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3012 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3013 i915_handle_error(dev, false);
3014
3015 for_each_pipe(pipe) {
3016 int reg = PIPESTAT(pipe);
3017 pipe_stats[pipe] = I915_READ(reg);
3018
3019 /*
3020 * Clear the PIPE*STAT regs before the IIR
3021 */
3022 if (pipe_stats[pipe] & 0x8000ffff) {
3023 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3024 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3025 pipe_name(pipe));
3026 I915_WRITE(reg, pipe_stats[pipe]);
3027 irq_received = 1;
3028 }
3029 }
3030 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3031
3032 I915_WRITE16(IIR, iir & ~flip_mask);
3033 new_iir = I915_READ16(IIR); /* Flush posted writes */
3034
d05c617e 3035 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 3036
3037 if (iir & I915_USER_INTERRUPT)
3038 notify_ring(dev, &dev_priv->ring[RCS]);
3039
3040 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3041 i8xx_handle_vblank(dev, 0, iir))
3042 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 3043
3044 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3045 i8xx_handle_vblank(dev, 1, iir))
3046 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 3047
3048 iir = new_iir;
3049 }
3050
3051 return IRQ_HANDLED;
3052}
3053
3054static void i8xx_irq_uninstall(struct drm_device * dev)
3055{
3056 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3057 int pipe;
3058
c2798b19
CW		 3059 for_each_pipe(pipe) {
3060 /* Clear enable bits; then clear status bits */
3061 I915_WRITE(PIPESTAT(pipe), 0);
3062 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3063 }
3064 I915_WRITE16(IMR, 0xffff);
3065 I915_WRITE16(IER, 0x0);
3066 I915_WRITE16(IIR, I915_READ16(IIR));
3067}
3068
a266c7d5
CW		 3069static void i915_irq_preinstall(struct drm_device * dev)
3070{
3071 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3072 int pipe;
3073
3074 atomic_set(&dev_priv->irq_received, 0);
3075
3076 if (I915_HAS_HOTPLUG(dev)) {
3077 I915_WRITE(PORT_HOTPLUG_EN, 0);
3078 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3079 }
3080
00d98ebd 3081 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 3082 for_each_pipe(pipe)
3083 I915_WRITE(PIPESTAT(pipe), 0);
3084 I915_WRITE(IMR, 0xffffffff);
3085 I915_WRITE(IER, 0x0);
3086 POSTING_READ(IER);
3087}
3088
3089static int i915_irq_postinstall(struct drm_device *dev)
3090{
3091 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 3092 u32 enable_mask;
a266c7d5 3093
38bde180
CW		 3094 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3095
3096 /* Unmask the interrupts that we always want on. */
3097 dev_priv->irq_mask =
3098 ~(I915_ASLE_INTERRUPT |
3099 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3100 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3101 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3102 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3103 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3104
3105 enable_mask =
3106 I915_ASLE_INTERRUPT |
3107 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3108 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3109 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3110 I915_USER_INTERRUPT;
3111
a266c7d5 3112 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3113 I915_WRITE(PORT_HOTPLUG_EN, 0);
3114 POSTING_READ(PORT_HOTPLUG_EN);
3115
a266c7d5
CW		 3116 /* Enable in IER... */
3117 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3118 /* and unmask in IMR */
3119 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3120 }
3121
a266c7d5
CW		 3122 I915_WRITE(IMR, dev_priv->irq_mask);
3123 I915_WRITE(IER, enable_mask);
3124 POSTING_READ(IER);
3125
f49e38dd 3126 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3127
3128 return 0;
3129}
3130
90a72f87
VS		 3131/*
3132 * Returns true when a page flip has completed.
3133 */
3134static bool i915_handle_vblank(struct drm_device *dev,
3135 int plane, int pipe, u32 iir)
3136{
3137 drm_i915_private_t *dev_priv = dev->dev_private;
3138 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3139
3140 if (!drm_handle_vblank(dev, pipe))
3141 return false;
3142
3143 if ((iir & flip_pending) == 0)
3144 return false;
3145
3146 intel_prepare_page_flip(dev, plane);
3147
3148 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3149 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3150 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3151 * the flip is completed (no longer pending). Since this doesn't raise
3152 * an interrupt per se, we watch for the change at vblank.
3153 */
3154 if (I915_READ(ISR) & flip_pending)
3155 return false;
3156
3157 intel_finish_page_flip(dev, pipe);
3158
3159 return true;
3160}
3161
ff1f525e 3162static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 3163{
3164 struct drm_device *dev = (struct drm_device *) arg;
3165 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 3166 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 3167 unsigned long irqflags;
38bde180
CW		 3168 u32 flip_mask =
3169 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3170 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3171 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 3172
3173 atomic_inc(&dev_priv->irq_received);
3174
3175 iir = I915_READ(IIR);
38bde180
CW		 3176 do {
3177 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3178 bool blc_event = false;
a266c7d5
CW		 3179
3180 /* Can't rely on pipestat interrupt bit in iir as it might
3181 * have been cleared after the pipestat interrupt was received.
3182 * It doesn't set the bit in iir again, but it still produces
3183 * interrupts (for non-MSI).
3184 */
3185 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3186 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3187 i915_handle_error(dev, false);
3188
3189 for_each_pipe(pipe) {
3190 int reg = PIPESTAT(pipe);
3191 pipe_stats[pipe] = I915_READ(reg);
3192
38bde180 3193 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 3194 if (pipe_stats[pipe] & 0x8000ffff) {
3195 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3196 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3197 pipe_name(pipe));
3198 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3199 irq_received = true;
a266c7d5
CW		 3200 }
3201 }
3202 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3203
3204 if (!irq_received)
3205 break;
3206
a266c7d5
CW		 3207 /* Consume port. Then clear IIR or we'll miss events */
3208 if ((I915_HAS_HOTPLUG(dev)) &&
3209 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3210 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 3211 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 3212
3213 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3214 hotplug_status);
b543fb04 3215 if (hotplug_trigger) {
cd569aed
EE		 3216 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
3217 i915_hpd_irq_setup(dev);
a266c7d5
CW		 3218 queue_work(dev_priv->wq,
3219 &dev_priv->hotplug_work);
b543fb04 3220 }
a266c7d5 3221 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 3222 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 3223 }
3224
38bde180 3225 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3226 new_iir = I915_READ(IIR); /* Flush posted writes */
3227
a266c7d5
CW		 3228 if (iir & I915_USER_INTERRUPT)
3229 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3230
a266c7d5 3231 for_each_pipe(pipe) {
38bde180
CW		 3232 int plane = pipe;
3233 if (IS_MOBILE(dev))
3234 plane = !plane;
90a72f87 3235
8291ee90 3236 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3237 i915_handle_vblank(dev, plane, pipe, iir))
3238 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3239
3240 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3241 blc_event = true;
3242 }
3243
a266c7d5
CW		 3244 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3245 intel_opregion_asle_intr(dev);
3246
3247 /* With MSI, interrupts are only generated when iir
3248 * transitions from zero to nonzero. If another bit got
3249 * set while we were handling the existing iir bits, then
3250 * we would never get another interrupt.
3251 *
3252 * This is fine on non-MSI as well, as if we hit this path
3253 * we avoid exiting the interrupt handler only to generate
3254 * another one.
3255 *
3256 * Note that for MSI this could cause a stray interrupt report
3257 * if an interrupt landed in the time between writing IIR and
3258 * the posting read. This should be rare enough to never
3259 * trigger the 99% of 100,000 interrupts test for disabling
3260 * stray interrupts.
3261 */
38bde180 3262 ret = IRQ_HANDLED;
a266c7d5 3263 iir = new_iir;
38bde180 3264 } while (iir & ~flip_mask);
a266c7d5 3265
d05c617e 3266 i915_update_dri1_breadcrumb(dev);
8291ee90 3267
a266c7d5
CW		 3268 return ret;
3269}
3270
3271static void i915_irq_uninstall(struct drm_device * dev)
3272{
3273 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3274 int pipe;
3275
ac4c16c5
EE		 3276 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3277
a266c7d5
CW		 3278 if (I915_HAS_HOTPLUG(dev)) {
3279 I915_WRITE(PORT_HOTPLUG_EN, 0);
3280 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3281 }
3282
00d98ebd 3283 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3284 for_each_pipe(pipe) {
3285 /* Clear enable bits; then clear status bits */
a266c7d5 3286 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3287 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3288 }
a266c7d5
CW		 3289 I915_WRITE(IMR, 0xffffffff);
3290 I915_WRITE(IER, 0x0);
3291
a266c7d5
CW		 3292 I915_WRITE(IIR, I915_READ(IIR));
3293}
3294
3295static void i965_irq_preinstall(struct drm_device * dev)
3296{
3297 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3298 int pipe;
3299
3300 atomic_set(&dev_priv->irq_received, 0);
3301
adca4730
CW		 3302 I915_WRITE(PORT_HOTPLUG_EN, 0);
3303 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3304
3305 I915_WRITE(HWSTAM, 0xeffe);
3306 for_each_pipe(pipe)
3307 I915_WRITE(PIPESTAT(pipe), 0);
3308 I915_WRITE(IMR, 0xffffffff);
3309 I915_WRITE(IER, 0x0);
3310 POSTING_READ(IER);
3311}
3312
3313static int i965_irq_postinstall(struct drm_device *dev)
3314{
3315 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 3316 u32 enable_mask;
a266c7d5
CW		 3317 u32 error_mask;
3318
a266c7d5 3319 /* Unmask the interrupts that we always want on. */
bbba0a97 3320 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3321 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3322 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3323 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3324 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3325 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3326 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3327
3328 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3329 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3330 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3331 enable_mask |= I915_USER_INTERRUPT;
3332
3333 if (IS_G4X(dev))
3334 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3335
515ac2bb 3336 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
a266c7d5 3337
a266c7d5
CW		 3338 /*
3339 * Enable some error detection, note the instruction error mask
3340 * bit is reserved, so we leave it masked.
3341 */
3342 if (IS_G4X(dev)) {
3343 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3344 GM45_ERROR_MEM_PRIV |
3345 GM45_ERROR_CP_PRIV |
3346 I915_ERROR_MEMORY_REFRESH);
3347 } else {
3348 error_mask = ~(I915_ERROR_PAGE_TABLE |
3349 I915_ERROR_MEMORY_REFRESH);
3350 }
3351 I915_WRITE(EMR, error_mask);
3352
3353 I915_WRITE(IMR, dev_priv->irq_mask);
3354 I915_WRITE(IER, enable_mask);
3355 POSTING_READ(IER);
3356
20afbda2
DV		 3357 I915_WRITE(PORT_HOTPLUG_EN, 0);
3358 POSTING_READ(PORT_HOTPLUG_EN);
3359
f49e38dd 3360 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3361
3362 return 0;
3363}
3364
bac56d5b 3365static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 3366{
3367 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 3368 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3369 struct intel_encoder *intel_encoder;
20afbda2
DV		 3370 u32 hotplug_en;
3371
bac56d5b
EE		 3372 if (I915_HAS_HOTPLUG(dev)) {
3373 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3374 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3375 /* Note HDMI and DP share hotplug bits */
e5868a31 3376 /* enable bits are the same for all generations */
cd569aed
EE		 3377 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3378 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3379 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3380 /* Programming the CRT detection parameters tends
3381 to generate a spurious hotplug event about three
3382 seconds later. So just do it once.
3383 */
3384 if (IS_G4X(dev))
3385 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3386 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3387 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3388
bac56d5b
EE		 3389 /* Ignore TV since it's buggy */
3390 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3391 }
a266c7d5
CW		 3392}
3393
ff1f525e 3394static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3395{
3396 struct drm_device *dev = (struct drm_device *) arg;
3397 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 3398 u32 iir, new_iir;
3399 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 3400 unsigned long irqflags;
3401 int irq_received;
3402 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3403 u32 flip_mask =
3404 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3405 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 3406
3407 atomic_inc(&dev_priv->irq_received);
3408
3409 iir = I915_READ(IIR);
3410
a266c7d5 3411 for (;;) {
2c8ba29f
CW		 3412 bool blc_event = false;
3413
21ad8330 3414 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 3415
3416 /* Can't rely on pipestat interrupt bit in iir as it might
3417 * have been cleared after the pipestat interrupt was received.
3418 * It doesn't set the bit in iir again, but it still produces
3419 * interrupts (for non-MSI).
3420 */
3421 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3422 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3423 i915_handle_error(dev, false);
3424
3425 for_each_pipe(pipe) {
3426 int reg = PIPESTAT(pipe);
3427 pipe_stats[pipe] = I915_READ(reg);
3428
3429 /*
3430 * Clear the PIPE*STAT regs before the IIR
3431 */
3432 if (pipe_stats[pipe] & 0x8000ffff) {
3433 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3434 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3435 pipe_name(pipe));
3436 I915_WRITE(reg, pipe_stats[pipe]);
3437 irq_received = 1;
3438 }
3439 }
3440 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3441
3442 if (!irq_received)
3443 break;
3444
3445 ret = IRQ_HANDLED;
3446
3447 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3448 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3449 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3450 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3451 HOTPLUG_INT_STATUS_G4X :
3452 HOTPLUG_INT_STATUS_I965);
a266c7d5
CW		 3453
3454 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3455 hotplug_status);
b543fb04 3456 if (hotplug_trigger) {
cd569aed
EE		 3457 if (hotplug_irq_storm_detect(dev, hotplug_trigger,
3458 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965))
3459 i915_hpd_irq_setup(dev);
a266c7d5
CW		 3460 queue_work(dev_priv->wq,
3461 &dev_priv->hotplug_work);
b543fb04 3462 }
a266c7d5
CW		 3463 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3464 I915_READ(PORT_HOTPLUG_STAT);
3465 }
3466
21ad8330 3467 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3468 new_iir = I915_READ(IIR); /* Flush posted writes */
3469
a266c7d5
CW		 3470 if (iir & I915_USER_INTERRUPT)
3471 notify_ring(dev, &dev_priv->ring[RCS]);
3472 if (iir & I915_BSD_USER_INTERRUPT)
3473 notify_ring(dev, &dev_priv->ring[VCS]);
3474
a266c7d5 3475 for_each_pipe(pipe) {
2c8ba29f 3476 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3477 i915_handle_vblank(dev, pipe, pipe, iir))
3478 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3479
3480 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3481 blc_event = true;
3482 }
3483
3484
3485 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3486 intel_opregion_asle_intr(dev);
3487
515ac2bb
DV		 3488 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3489 gmbus_irq_handler(dev);
3490
a266c7d5
CW		 3491 /* With MSI, interrupts are only generated when iir
3492 * transitions from zero to nonzero. If another bit got
3493 * set while we were handling the existing iir bits, then
3494 * we would never get another interrupt.
3495 *
3496 * This is fine on non-MSI as well, as if we hit this path
3497 * we avoid exiting the interrupt handler only to generate
3498 * another one.
3499 *
3500 * Note that for MSI this could cause a stray interrupt report
3501 * if an interrupt landed in the time between writing IIR and
3502 * the posting read. This should be rare enough to never
3503 * trigger the 99% of 100,000 interrupts test for disabling
3504 * stray interrupts.
3505 */
3506 iir = new_iir;
3507 }
3508
d05c617e 3509 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3510
a266c7d5
CW		 3511 return ret;
3512}
3513
3514static void i965_irq_uninstall(struct drm_device * dev)
3515{
3516 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3517 int pipe;
3518
3519 if (!dev_priv)
3520 return;
3521
ac4c16c5
EE		 3522 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3523
adca4730
CW		 3524 I915_WRITE(PORT_HOTPLUG_EN, 0);
3525 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3526
3527 I915_WRITE(HWSTAM, 0xffffffff);
3528 for_each_pipe(pipe)
3529 I915_WRITE(PIPESTAT(pipe), 0);
3530 I915_WRITE(IMR, 0xffffffff);
3531 I915_WRITE(IER, 0x0);
3532
3533 for_each_pipe(pipe)
3534 I915_WRITE(PIPESTAT(pipe),
3535 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3536 I915_WRITE(IIR, I915_READ(IIR));
3537}
3538
ac4c16c5
EE		 3539static void i915_reenable_hotplug_timer_func(unsigned long data)
3540{
3541 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3542 struct drm_device *dev = dev_priv->dev;
3543 struct drm_mode_config *mode_config = &dev->mode_config;
3544 unsigned long irqflags;
3545 int i;
3546
3547 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3548 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3549 struct drm_connector *connector;
3550
3551 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3552 continue;
3553
3554 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3555
3556 list_for_each_entry(connector, &mode_config->connector_list, head) {
3557 struct intel_connector *intel_connector = to_intel_connector(connector);
3558
3559 if (intel_connector->encoder->hpd_pin == i) {
3560 if (connector->polled != intel_connector->polled)
3561 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3562 drm_get_connector_name(connector));
3563 connector->polled = intel_connector->polled;
3564 if (!connector->polled)
3565 connector->polled = DRM_CONNECTOR_POLL_HPD;
3566 }
3567 }
3568 }
3569 if (dev_priv->display.hpd_irq_setup)
3570 dev_priv->display.hpd_irq_setup(dev);
3571 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3572}
3573
f71d4af4
JB		 3574void intel_irq_init(struct drm_device *dev)
3575{
8b2e326d
CW		 3576 struct drm_i915_private *dev_priv = dev->dev_private;
3577
3578 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3579 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3580 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3581 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3582
99584db3
DV		 3583 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3584 i915_hangcheck_elapsed,
61bac78e 3585 (unsigned long) dev);
ac4c16c5
EE		 3586 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3587 (unsigned long) dev_priv);
61bac78e 3588
97a19a24 3589 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3590
f71d4af4
JB		 3591 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3592 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 3593 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3594 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3595 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3596 }
3597
c3613de9
KP		 3598 if (drm_core_check_feature(dev, DRIVER_MODESET))
3599 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3600 else
3601 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 3602 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3603
7e231dbe
JB		 3604 if (IS_VALLEYVIEW(dev)) {
3605 dev->driver->irq_handler = valleyview_irq_handler;
3606 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3607 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3608 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3609 dev->driver->enable_vblank = valleyview_enable_vblank;
3610 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3611 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4a06e201 3612 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7d99163d 3613 /* Share uninstall handlers with ILK/SNB */
f71d4af4 3614 dev->driver->irq_handler = ivybridge_irq_handler;
7d99163d 3615 dev->driver->irq_preinstall = ivybridge_irq_preinstall;
f71d4af4
JB		 3616 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3617 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3618 dev->driver->enable_vblank = ivybridge_enable_vblank;
3619 dev->driver->disable_vblank = ivybridge_disable_vblank;
82a28bcf 3620 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 3621 } else if (HAS_PCH_SPLIT(dev)) {
3622 dev->driver->irq_handler = ironlake_irq_handler;
3623 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3624 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3625 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3626 dev->driver->enable_vblank = ironlake_enable_vblank;
3627 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3628 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3629 } else {
c2798b19
CW		 3630 if (INTEL_INFO(dev)->gen == 2) {
3631 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3632 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3633 dev->driver->irq_handler = i8xx_irq_handler;
3634 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3635 } else if (INTEL_INFO(dev)->gen == 3) {
3636 dev->driver->irq_preinstall = i915_irq_preinstall;
3637 dev->driver->irq_postinstall = i915_irq_postinstall;
3638 dev->driver->irq_uninstall = i915_irq_uninstall;
3639 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3640 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3641 } else {
a266c7d5
CW		 3642 dev->driver->irq_preinstall = i965_irq_preinstall;
3643 dev->driver->irq_postinstall = i965_irq_postinstall;
3644 dev->driver->irq_uninstall = i965_irq_uninstall;
3645 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3646 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3647 }
f71d4af4
JB		 3648 dev->driver->enable_vblank = i915_enable_vblank;
3649 dev->driver->disable_vblank = i915_disable_vblank;
3650 }
3651}
20afbda2
DV		 3652
3653void intel_hpd_init(struct drm_device *dev)
3654{
3655 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3656 struct drm_mode_config *mode_config = &dev->mode_config;
3657 struct drm_connector *connector;
3658 int i;
20afbda2 3659
821450c6
EE		 3660 for (i = 1; i < HPD_NUM_PINS; i++) {
3661 dev_priv->hpd_stats[i].hpd_cnt = 0;
3662 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3663 }
3664 list_for_each_entry(connector, &mode_config->connector_list, head) {
3665 struct intel_connector *intel_connector = to_intel_connector(connector);
3666 connector->polled = intel_connector->polled;
3667 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3668 connector->polled = DRM_CONNECTOR_POLL_HPD;
3669 }
20afbda2
DV		 3670 if (dev_priv->display.hpd_irq_setup)
3671 dev_priv->display.hpd_irq_setup(dev);
3672}
Linux kernel - Deliverables
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