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drm/i915: static inline for dummy crc functions
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
b2c88f5b 33#include <linux/circ_buf.h>
760285e7
DH		 34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
1da177e4 36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
e5868a31
EE		 40static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46};
47
48static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54};
55
56static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63};
64
65static const u32 hpd_status_gen4[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72};
73
e5868a31
EE		 74static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81};
82
036a4a7d 83/* For display hotplug interrupt */
995b6762 84static void
f2b115e6 85ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 86{
4bc9d430
DV		 87 assert_spin_locked(&dev_priv->irq_lock);
88
c67a470b
PZ		 89 if (dev_priv->pc8.irqs_disabled) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv->pc8.regsave.deimr &= ~mask;
92 return;
93 }
94
1ec14ad3
CW		 95 if ((dev_priv->irq_mask & mask) != 0) {
96 dev_priv->irq_mask &= ~mask;
97 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 98 POSTING_READ(DEIMR);
036a4a7d
ZW		 99 }
100}
101
0ff9800a 102static void
f2b115e6 103ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 104{
4bc9d430
DV		 105 assert_spin_locked(&dev_priv->irq_lock);
106
c67a470b
PZ		 107 if (dev_priv->pc8.irqs_disabled) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv->pc8.regsave.deimr |= mask;
110 return;
111 }
112
1ec14ad3
CW		 113 if ((dev_priv->irq_mask & mask) != mask) {
114 dev_priv->irq_mask |= mask;
115 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 116 POSTING_READ(DEIMR);
036a4a7d
ZW		 117 }
118}
119
43eaea13
PZ		 120/**
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
125 */
126static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
127 uint32_t interrupt_mask,
128 uint32_t enabled_irq_mask)
129{
130 assert_spin_locked(&dev_priv->irq_lock);
131
c67a470b
PZ		 132 if (dev_priv->pc8.irqs_disabled) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
135 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
136 interrupt_mask);
137 return;
138 }
139
43eaea13
PZ		 140 dev_priv->gt_irq_mask &= ~interrupt_mask;
141 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
142 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
143 POSTING_READ(GTIMR);
144}
145
146void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
147{
148 ilk_update_gt_irq(dev_priv, mask, mask);
149}
150
151void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
152{
153 ilk_update_gt_irq(dev_priv, mask, 0);
154}
155
edbfdb45
PZ		 156/**
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
161 */
162static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
163 uint32_t interrupt_mask,
164 uint32_t enabled_irq_mask)
165{
605cd25b 166 uint32_t new_val;
edbfdb45
PZ		 167
168 assert_spin_locked(&dev_priv->irq_lock);
169
c67a470b
PZ		 170 if (dev_priv->pc8.irqs_disabled) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
173 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
174 interrupt_mask);
175 return;
176 }
177
605cd25b 178 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 179 new_val &= ~interrupt_mask;
180 new_val |= (~enabled_irq_mask & interrupt_mask);
181
605cd25b
PZ		 182 if (new_val != dev_priv->pm_irq_mask) {
183 dev_priv->pm_irq_mask = new_val;
184 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
f52ecbcf
PZ		 185 POSTING_READ(GEN6_PMIMR);
186 }
edbfdb45
PZ		 187}
188
189void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
190{
191 snb_update_pm_irq(dev_priv, mask, mask);
192}
193
194void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
195{
196 snb_update_pm_irq(dev_priv, mask, 0);
197}
198
8664281b
PZ		 199static bool ivb_can_enable_err_int(struct drm_device *dev)
200{
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_crtc *crtc;
203 enum pipe pipe;
204
4bc9d430
DV		 205 assert_spin_locked(&dev_priv->irq_lock);
206
8664281b
PZ		 207 for_each_pipe(pipe) {
208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
209
210 if (crtc->cpu_fifo_underrun_disabled)
211 return false;
212 }
213
214 return true;
215}
216
217static bool cpt_can_enable_serr_int(struct drm_device *dev)
218{
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 enum pipe pipe;
221 struct intel_crtc *crtc;
222
fee884ed
DV		 223 assert_spin_locked(&dev_priv->irq_lock);
224
8664281b
PZ		 225 for_each_pipe(pipe) {
226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
227
228 if (crtc->pch_fifo_underrun_disabled)
229 return false;
230 }
231
232 return true;
233}
234
235static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
236 enum pipe pipe, bool enable)
237{
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
240 DE_PIPEB_FIFO_UNDERRUN;
241
242 if (enable)
243 ironlake_enable_display_irq(dev_priv, bit);
244 else
245 ironlake_disable_display_irq(dev_priv, bit);
246}
247
248static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
7336df65 249 enum pipe pipe, bool enable)
8664281b
PZ		 250{
251 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 252 if (enable) {
7336df65
DV		 253 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
254
8664281b
PZ		 255 if (!ivb_can_enable_err_int(dev))
256 return;
257
8664281b
PZ		 258 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
259 } else {
7336df65
DV		 260 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
261
262 /* Change the state _after_ we've read out the current one. */
8664281b 263 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65
DV		 264
265 if (!was_enabled &&
266 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
267 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
268 pipe_name(pipe));
269 }
8664281b
PZ		 270 }
271}
272
fee884ed
DV		 273/**
274 * ibx_display_interrupt_update - update SDEIMR
275 * @dev_priv: driver private
276 * @interrupt_mask: mask of interrupt bits to update
277 * @enabled_irq_mask: mask of interrupt bits to enable
278 */
279static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
280 uint32_t interrupt_mask,
281 uint32_t enabled_irq_mask)
282{
283 uint32_t sdeimr = I915_READ(SDEIMR);
284 sdeimr &= ~interrupt_mask;
285 sdeimr |= (~enabled_irq_mask & interrupt_mask);
286
287 assert_spin_locked(&dev_priv->irq_lock);
288
c67a470b
PZ		 289 if (dev_priv->pc8.irqs_disabled &&
290 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
291 WARN(1, "IRQs disabled\n");
292 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
293 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
294 interrupt_mask);
295 return;
296 }
297
fee884ed
DV		 298 I915_WRITE(SDEIMR, sdeimr);
299 POSTING_READ(SDEIMR);
300}
301#define ibx_enable_display_interrupt(dev_priv, bits) \
302 ibx_display_interrupt_update((dev_priv), (bits), (bits))
303#define ibx_disable_display_interrupt(dev_priv, bits) \
304 ibx_display_interrupt_update((dev_priv), (bits), 0)
305
de28075d
DV		 306static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
307 enum transcoder pch_transcoder,
8664281b
PZ		 308 bool enable)
309{
8664281b 310 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 311 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
312 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 313
314 if (enable)
fee884ed 315 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 316 else
fee884ed 317 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 318}
319
320static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
321 enum transcoder pch_transcoder,
322 bool enable)
323{
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 if (enable) {
1dd246fb
DV		 327 I915_WRITE(SERR_INT,
328 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
329
8664281b
PZ		 330 if (!cpt_can_enable_serr_int(dev))
331 return;
332
fee884ed 333 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 334 } else {
1dd246fb
DV		 335 uint32_t tmp = I915_READ(SERR_INT);
336 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
337
338 /* Change the state _after_ we've read out the current one. */
fee884ed 339 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb
DV		 340
341 if (!was_enabled &&
342 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
343 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
344 transcoder_name(pch_transcoder));
345 }
8664281b 346 }
8664281b
PZ		 347}
348
349/**
350 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
351 * @dev: drm device
352 * @pipe: pipe
353 * @enable: true if we want to report FIFO underrun errors, false otherwise
354 *
355 * This function makes us disable or enable CPU fifo underruns for a specific
356 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
357 * reporting for one pipe may also disable all the other CPU error interruts for
358 * the other pipes, due to the fact that there's just one interrupt mask/enable
359 * bit for all the pipes.
360 *
361 * Returns the previous state of underrun reporting.
362 */
363bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
364 enum pipe pipe, bool enable)
365{
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
369 unsigned long flags;
370 bool ret;
371
372 spin_lock_irqsave(&dev_priv->irq_lock, flags);
373
374 ret = !intel_crtc->cpu_fifo_underrun_disabled;
375
376 if (enable == ret)
377 goto done;
378
379 intel_crtc->cpu_fifo_underrun_disabled = !enable;
380
381 if (IS_GEN5(dev) || IS_GEN6(dev))
382 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
383 else if (IS_GEN7(dev))
7336df65 384 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b
PZ		 385
386done:
387 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
388 return ret;
389}
390
391/**
392 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
393 * @dev: drm device
394 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
395 * @enable: true if we want to report FIFO underrun errors, false otherwise
396 *
397 * This function makes us disable or enable PCH fifo underruns for a specific
398 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
399 * underrun reporting for one transcoder may also disable all the other PCH
400 * error interruts for the other transcoders, due to the fact that there's just
401 * one interrupt mask/enable bit for all the transcoders.
402 *
403 * Returns the previous state of underrun reporting.
404 */
405bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
406 enum transcoder pch_transcoder,
407 bool enable)
408{
409 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 410 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 412 unsigned long flags;
413 bool ret;
414
de28075d
DV		 415 /*
416 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
417 * has only one pch transcoder A that all pipes can use. To avoid racy
418 * pch transcoder -> pipe lookups from interrupt code simply store the
419 * underrun statistics in crtc A. Since we never expose this anywhere
420 * nor use it outside of the fifo underrun code here using the "wrong"
421 * crtc on LPT won't cause issues.
422 */
8664281b
PZ		 423
424 spin_lock_irqsave(&dev_priv->irq_lock, flags);
425
426 ret = !intel_crtc->pch_fifo_underrun_disabled;
427
428 if (enable == ret)
429 goto done;
430
431 intel_crtc->pch_fifo_underrun_disabled = !enable;
432
433 if (HAS_PCH_IBX(dev))
de28075d 434 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b
PZ		 435 else
436 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
437
438done:
439 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
440 return ret;
441}
442
443
7c463586
KP		 444void
445i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
446{
46c06a30
VS		 447 u32 reg = PIPESTAT(pipe);
448 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 449
b79480ba
DV		 450 assert_spin_locked(&dev_priv->irq_lock);
451
46c06a30
VS		 452 if ((pipestat & mask) == mask)
453 return;
454
455 /* Enable the interrupt, clear any pending status */
456 pipestat |= mask | (mask >> 16);
457 I915_WRITE(reg, pipestat);
458 POSTING_READ(reg);
7c463586
KP		 459}
460
461void
462i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
463{
46c06a30
VS		 464 u32 reg = PIPESTAT(pipe);
465 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 466
b79480ba
DV		 467 assert_spin_locked(&dev_priv->irq_lock);
468
46c06a30
VS		 469 if ((pipestat & mask) == 0)
470 return;
471
472 pipestat &= ~mask;
473 I915_WRITE(reg, pipestat);
474 POSTING_READ(reg);
7c463586
KP		 475}
476
01c66889 477/**
f49e38dd 478 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 479 */
f49e38dd 480static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 481{
1ec14ad3
CW		 482 drm_i915_private_t *dev_priv = dev->dev_private;
483 unsigned long irqflags;
484
f49e38dd
JN		 485 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
486 return;
487
1ec14ad3 488 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 489
f898780b
JN		 490 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
491 if (INTEL_INFO(dev)->gen >= 4)
492 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 493
494 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 495}
496
0a3e67a4
JB		 497/**
498 * i915_pipe_enabled - check if a pipe is enabled
499 * @dev: DRM device
500 * @pipe: pipe to check
501 *
502 * Reading certain registers when the pipe is disabled can hang the chip.
503 * Use this routine to make sure the PLL is running and the pipe is active
504 * before reading such registers if unsure.
505 */
506static int
507i915_pipe_enabled(struct drm_device *dev, int pipe)
508{
509 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 510
a01025af
DV		 511 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
512 /* Locking is horribly broken here, but whatever. */
513 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 515
a01025af
DV		 516 return intel_crtc->active;
517 } else {
518 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
519 }
0a3e67a4
JB		 520}
521
4cdb83ec
VS		 522static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
523{
524 /* Gen2 doesn't have a hardware frame counter */
525 return 0;
526}
527
42f52ef8
KP		 528/* Called from drm generic code, passed a 'crtc', which
529 * we use as a pipe index
530 */
f71d4af4 531static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 532{
533 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
534 unsigned long high_frame;
535 unsigned long low_frame;
391f75e2 536 u32 high1, high2, low, pixel, vbl_start;
0a3e67a4
JB		 537
538 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 539 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 540 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 541 return 0;
542 }
543
391f75e2
VS		 544 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
545 struct intel_crtc *intel_crtc =
546 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
547 const struct drm_display_mode *mode =
548 &intel_crtc->config.adjusted_mode;
549
550 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
551 } else {
552 enum transcoder cpu_transcoder =
553 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
554 u32 htotal;
555
556 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
557 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
558
559 vbl_start *= htotal;
560 }
561
9db4a9c7
JB		 562 high_frame = PIPEFRAME(pipe);
563 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 564
0a3e67a4
JB		 565 /*
566 * High & low register fields aren't synchronized, so make sure
567 * we get a low value that's stable across two reads of the high
568 * register.
569 */
570 do {
5eddb70b 571 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 572 low = I915_READ(low_frame);
5eddb70b 573 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 574 } while (high1 != high2);
575
5eddb70b 576 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 577 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 578 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 579
580 /*
581 * The frame counter increments at beginning of active.
582 * Cook up a vblank counter by also checking the pixel
583 * counter against vblank start.
584 */
585 return ((high1 << 8) | low) + (pixel >= vbl_start);
0a3e67a4
JB		 586}
587
f71d4af4 588static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 589{
590 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 591 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 592
593 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 594 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 595 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 596 return 0;
597 }
598
599 return I915_READ(reg);
600}
601
7c06b08a 602static bool intel_pipe_in_vblank(struct drm_device *dev, enum pipe pipe)
54ddcbd2
VS		 603{
604 struct drm_i915_private *dev_priv = dev->dev_private;
605 uint32_t status;
606
607 if (IS_VALLEYVIEW(dev)) {
608 status = pipe == PIPE_A ?
609 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
610 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
611
612 return I915_READ(VLV_ISR) & status;
7c06b08a
VS		 613 } else if (IS_GEN2(dev)) {
614 status = pipe == PIPE_A ?
615 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
616 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
617
618 return I915_READ16(ISR) & status;
619 } else if (INTEL_INFO(dev)->gen < 5) {
54ddcbd2
VS		 620 status = pipe == PIPE_A ?
621 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
622 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
623
624 return I915_READ(ISR) & status;
625 } else if (INTEL_INFO(dev)->gen < 7) {
626 status = pipe == PIPE_A ?
627 DE_PIPEA_VBLANK :
628 DE_PIPEB_VBLANK;
629
630 return I915_READ(DEISR) & status;
631 } else {
632 switch (pipe) {
633 default:
634 case PIPE_A:
635 status = DE_PIPEA_VBLANK_IVB;
636 break;
637 case PIPE_B:
638 status = DE_PIPEB_VBLANK_IVB;
639 break;
640 case PIPE_C:
641 status = DE_PIPEC_VBLANK_IVB;
642 break;
643 }
644
645 return I915_READ(DEISR) & status;
646 }
647}
648
f71d4af4 649static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 650 int *vpos, int *hpos)
651{
c2baf4b7
VS		 652 struct drm_i915_private *dev_priv = dev->dev_private;
653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
655 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
3aa18df8 656 int position;
0af7e4df
MK		 657 int vbl_start, vbl_end, htotal, vtotal;
658 bool in_vbl = true;
659 int ret = 0;
660
c2baf4b7 661 if (!intel_crtc->active) {
0af7e4df 662 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 663 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 664 return 0;
665 }
666
c2baf4b7
VS		 667 htotal = mode->crtc_htotal;
668 vtotal = mode->crtc_vtotal;
669 vbl_start = mode->crtc_vblank_start;
670 vbl_end = mode->crtc_vblank_end;
0af7e4df 671
c2baf4b7
VS		 672 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
673
7c06b08a 674 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 675 /* No obvious pixelcount register. Only query vertical
676 * scanout position from Display scan line register.
677 */
7c06b08a
VS		 678 if (IS_GEN2(dev))
679 position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
680 else
681 position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
54ddcbd2
VS		 682
683 /*
684 * The scanline counter increments at the leading edge
685 * of hsync, ie. it completely misses the active portion
686 * of the line. Fix up the counter at both edges of vblank
687 * to get a more accurate picture whether we're in vblank
688 * or not.
689 */
7c06b08a 690 in_vbl = intel_pipe_in_vblank(dev, pipe);
54ddcbd2
VS		 691 if ((in_vbl && position == vbl_start - 1) ||
692 (!in_vbl && position == vbl_end - 1))
693 position = (position + 1) % vtotal;
0af7e4df
MK		 694 } else {
695 /* Have access to pixelcount since start of frame.
696 * We can split this into vertical and horizontal
697 * scanout position.
698 */
699 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
700
3aa18df8
VS		 701 /* convert to pixel counts */
702 vbl_start *= htotal;
703 vbl_end *= htotal;
704 vtotal *= htotal;
0af7e4df
MK		 705 }
706
3aa18df8
VS		 707 in_vbl = position >= vbl_start && position < vbl_end;
708
709 /*
710 * While in vblank, position will be negative
711 * counting up towards 0 at vbl_end. And outside
712 * vblank, position will be positive counting
713 * up since vbl_end.
714 */
715 if (position >= vbl_start)
716 position -= vbl_end;
717 else
718 position += vtotal - vbl_end;
0af7e4df 719
7c06b08a 720 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3aa18df8
VS		 721 *vpos = position;
722 *hpos = 0;
723 } else {
724 *vpos = position / htotal;
725 *hpos = position - (*vpos * htotal);
726 }
0af7e4df 727
0af7e4df
MK		 728 /* In vblank? */
729 if (in_vbl)
730 ret |= DRM_SCANOUTPOS_INVBL;
731
732 return ret;
733}
734
f71d4af4 735static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 736 int *max_error,
737 struct timeval *vblank_time,
738 unsigned flags)
739{
4041b853 740 struct drm_crtc *crtc;
0af7e4df 741
7eb552ae 742 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 743 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 744 return -EINVAL;
745 }
746
747 /* Get drm_crtc to timestamp: */
4041b853
CW		 748 crtc = intel_get_crtc_for_pipe(dev, pipe);
749 if (crtc == NULL) {
750 DRM_ERROR("Invalid crtc %d\n", pipe);
751 return -EINVAL;
752 }
753
754 if (!crtc->enabled) {
755 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
756 return -EBUSY;
757 }
0af7e4df
MK		 758
759 /* Helper routine in DRM core does all the work: */
4041b853
CW		 760 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
761 vblank_time, flags,
762 crtc);
0af7e4df
MK		 763}
764
67c347ff
JN		 765static bool intel_hpd_irq_event(struct drm_device *dev,
766 struct drm_connector *connector)
321a1b30
EE		 767{
768 enum drm_connector_status old_status;
769
770 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
771 old_status = connector->status;
772
773 connector->status = connector->funcs->detect(connector, false);
67c347ff
JN		 774 if (old_status == connector->status)
775 return false;
776
777 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
321a1b30
EE		 778 connector->base.id,
779 drm_get_connector_name(connector),
67c347ff
JN		 780 drm_get_connector_status_name(old_status),
781 drm_get_connector_status_name(connector->status));
782
783 return true;
321a1b30
EE		 784}
785
5ca58282
JB		 786/*
787 * Handle hotplug events outside the interrupt handler proper.
788 */
ac4c16c5
EE		 789#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
790
5ca58282
JB		 791static void i915_hotplug_work_func(struct work_struct *work)
792{
793 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
794 hotplug_work);
795 struct drm_device *dev = dev_priv->dev;
c31c4ba3 796 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 797 struct intel_connector *intel_connector;
798 struct intel_encoder *intel_encoder;
799 struct drm_connector *connector;
800 unsigned long irqflags;
801 bool hpd_disabled = false;
321a1b30 802 bool changed = false;
142e2398 803 u32 hpd_event_bits;
4ef69c7a 804
52d7eced
DV		 805 /* HPD irq before everything is fully set up. */
806 if (!dev_priv->enable_hotplug_processing)
807 return;
808
a65e34c7 809 mutex_lock(&mode_config->mutex);
e67189ab
JB		 810 DRM_DEBUG_KMS("running encoder hotplug functions\n");
811
cd569aed 812 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 813
814 hpd_event_bits = dev_priv->hpd_event_bits;
815 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 816 list_for_each_entry(connector, &mode_config->connector_list, head) {
817 intel_connector = to_intel_connector(connector);
818 intel_encoder = intel_connector->encoder;
819 if (intel_encoder->hpd_pin > HPD_NONE &&
820 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
821 connector->polled == DRM_CONNECTOR_POLL_HPD) {
822 DRM_INFO("HPD interrupt storm detected on connector %s: "
823 "switching from hotplug detection to polling\n",
824 drm_get_connector_name(connector));
825 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
826 connector->polled = DRM_CONNECTOR_POLL_CONNECT
827 | DRM_CONNECTOR_POLL_DISCONNECT;
828 hpd_disabled = true;
829 }
142e2398
EE		 830 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
831 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
832 drm_get_connector_name(connector), intel_encoder->hpd_pin);
833 }
cd569aed
EE		 834 }
835 /* if there were no outputs to poll, poll was disabled,
836 * therefore make sure it's enabled when disabling HPD on
837 * some connectors */
ac4c16c5 838 if (hpd_disabled) {
cd569aed 839 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 840 mod_timer(&dev_priv->hotplug_reenable_timer,
841 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
842 }
cd569aed
EE		 843
844 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
845
321a1b30
EE		 846 list_for_each_entry(connector, &mode_config->connector_list, head) {
847 intel_connector = to_intel_connector(connector);
848 intel_encoder = intel_connector->encoder;
849 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
850 if (intel_encoder->hot_plug)
851 intel_encoder->hot_plug(intel_encoder);
852 if (intel_hpd_irq_event(dev, connector))
853 changed = true;
854 }
855 }
40ee3381
KP		 856 mutex_unlock(&mode_config->mutex);
857
321a1b30
EE		 858 if (changed)
859 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 860}
861
d0ecd7e2 862static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1
JB		 863{
864 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 865 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 866 u8 new_delay;
9270388e 867
d0ecd7e2 868 spin_lock(&mchdev_lock);
f97108d1 869
73edd18f
DV		 870 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
871
20e4d407 872 new_delay = dev_priv->ips.cur_delay;
9270388e 873
7648fa99 874 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 875 busy_up = I915_READ(RCPREVBSYTUPAVG);
876 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 877 max_avg = I915_READ(RCBMAXAVG);
878 min_avg = I915_READ(RCBMINAVG);
879
880 /* Handle RCS change request from hw */
b5b72e89 881 if (busy_up > max_avg) {
20e4d407
DV		 882 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
883 new_delay = dev_priv->ips.cur_delay - 1;
884 if (new_delay < dev_priv->ips.max_delay)
885 new_delay = dev_priv->ips.max_delay;
b5b72e89 886 } else if (busy_down < min_avg) {
20e4d407
DV		 887 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
888 new_delay = dev_priv->ips.cur_delay + 1;
889 if (new_delay > dev_priv->ips.min_delay)
890 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 891 }
892
7648fa99 893 if (ironlake_set_drps(dev, new_delay))
20e4d407 894 dev_priv->ips.cur_delay = new_delay;
f97108d1 895
d0ecd7e2 896 spin_unlock(&mchdev_lock);
9270388e 897
f97108d1
JB		 898 return;
899}
900
549f7365
CW		 901static void notify_ring(struct drm_device *dev,
902 struct intel_ring_buffer *ring)
903{
475553de
CW		 904 if (ring->obj == NULL)
905 return;
906
814e9b57 907 trace_i915_gem_request_complete(ring);
9862e600 908
549f7365 909 wake_up_all(&ring->irq_queue);
10cd45b6 910 i915_queue_hangcheck(dev);
549f7365
CW		 911}
912
4912d041 913static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 914{
4912d041 915 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 916 rps.work);
edbfdb45 917 u32 pm_iir;
dd75fdc8 918 int new_delay, adj;
4912d041 919
59cdb63d 920 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3
DV		 921 pm_iir = dev_priv->rps.pm_iir;
922 dev_priv->rps.pm_iir = 0;
4848405c 923 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
edbfdb45 924 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
59cdb63d 925 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 926
60611c13
PZ		 927 /* Make sure we didn't queue anything we're not going to process. */
928 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
929
4848405c 930 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 931 return;
932
4fc688ce 933 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 934
dd75fdc8 935 adj = dev_priv->rps.last_adj;
7425034a 936 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 937 if (adj > 0)
938 adj *= 2;
939 else
940 adj = 1;
941 new_delay = dev_priv->rps.cur_delay + adj;
7425034a
VS		 942
943 /*
944 * For better performance, jump directly
945 * to RPe if we're below it.
946 */
dd75fdc8
CW		 947 if (new_delay < dev_priv->rps.rpe_delay)
948 new_delay = dev_priv->rps.rpe_delay;
949 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
950 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
7425034a 951 new_delay = dev_priv->rps.rpe_delay;
dd75fdc8
CW		 952 else
953 new_delay = dev_priv->rps.min_delay;
954 adj = 0;
955 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
956 if (adj < 0)
957 adj *= 2;
958 else
959 adj = -1;
960 new_delay = dev_priv->rps.cur_delay + adj;
961 } else { /* unknown event */
962 new_delay = dev_priv->rps.cur_delay;
963 }
3b8d8d91 964
79249636
BW		 965 /* sysfs frequency interfaces may have snuck in while servicing the
966 * interrupt
967 */
dd75fdc8
CW		 968 if (new_delay < (int)dev_priv->rps.min_delay)
969 new_delay = dev_priv->rps.min_delay;
970 if (new_delay > (int)dev_priv->rps.max_delay)
971 new_delay = dev_priv->rps.max_delay;
972 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
973
974 if (IS_VALLEYVIEW(dev_priv->dev))
975 valleyview_set_rps(dev_priv->dev, new_delay);
976 else
977 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 978
4fc688ce 979 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 980}
981
e3689190
BW		 982
983/**
984 * ivybridge_parity_work - Workqueue called when a parity error interrupt
985 * occurred.
986 * @work: workqueue struct
987 *
988 * Doesn't actually do anything except notify userspace. As a consequence of
989 * this event, userspace should try to remap the bad rows since statistically
990 * it is likely the same row is more likely to go bad again.
991 */
992static void ivybridge_parity_work(struct work_struct *work)
993{
994 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 995 l3_parity.error_work);
e3689190 996 u32 error_status, row, bank, subbank;
35a85ac6 997 char *parity_event[6];
e3689190
BW		 998 uint32_t misccpctl;
999 unsigned long flags;
35a85ac6 1000 uint8_t slice = 0;
e3689190
BW		 1001
1002 /* We must turn off DOP level clock gating to access the L3 registers.
1003 * In order to prevent a get/put style interface, acquire struct mutex
1004 * any time we access those registers.
1005 */
1006 mutex_lock(&dev_priv->dev->struct_mutex);
1007
35a85ac6
BW		 1008 /* If we've screwed up tracking, just let the interrupt fire again */
1009 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1010 goto out;
1011
e3689190
BW		 1012 misccpctl = I915_READ(GEN7_MISCCPCTL);
1013 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1014 POSTING_READ(GEN7_MISCCPCTL);
1015
35a85ac6
BW		 1016 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1017 u32 reg;
e3689190 1018
35a85ac6
BW		 1019 slice--;
1020 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1021 break;
e3689190 1022
35a85ac6 1023 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 1024
35a85ac6 1025 reg = GEN7_L3CDERRST1 + (slice * 0x200);
e3689190 1026
35a85ac6
BW		 1027 error_status = I915_READ(reg);
1028 row = GEN7_PARITY_ERROR_ROW(error_status);
1029 bank = GEN7_PARITY_ERROR_BANK(error_status);
1030 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1031
1032 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1033 POSTING_READ(reg);
1034
1035 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1036 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1037 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1038 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1039 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1040 parity_event[5] = NULL;
1041
1042 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
1043 KOBJ_CHANGE, parity_event);
e3689190 1044
35a85ac6
BW		 1045 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1046 slice, row, bank, subbank);
e3689190 1047
35a85ac6
BW		 1048 kfree(parity_event[4]);
1049 kfree(parity_event[3]);
1050 kfree(parity_event[2]);
1051 kfree(parity_event[1]);
1052 }
e3689190 1053
35a85ac6 1054 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 1055
35a85ac6
BW		 1056out:
1057 WARN_ON(dev_priv->l3_parity.which_slice);
1058 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1059 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1060 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1061
1062 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 1063}
1064
35a85ac6 1065static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190
BW		 1066{
1067 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e3689190 1068
040d2baa 1069 if (!HAS_L3_DPF(dev))
e3689190
BW		 1070 return;
1071
d0ecd7e2 1072 spin_lock(&dev_priv->irq_lock);
35a85ac6 1073 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 1074 spin_unlock(&dev_priv->irq_lock);
e3689190 1075
35a85ac6
BW		 1076 iir &= GT_PARITY_ERROR(dev);
1077 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1078 dev_priv->l3_parity.which_slice |= 1 << 1;
1079
1080 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1081 dev_priv->l3_parity.which_slice |= 1 << 0;
1082
a4da4fa4 1083 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1084}
1085
f1af8fc1
PZ		 1086static void ilk_gt_irq_handler(struct drm_device *dev,
1087 struct drm_i915_private *dev_priv,
1088 u32 gt_iir)
1089{
1090 if (gt_iir &
1091 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1092 notify_ring(dev, &dev_priv->ring[RCS]);
1093 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1094 notify_ring(dev, &dev_priv->ring[VCS]);
1095}
1096
e7b4c6b1
DV		 1097static void snb_gt_irq_handler(struct drm_device *dev,
1098 struct drm_i915_private *dev_priv,
1099 u32 gt_iir)
1100{
1101
cc609d5d
BW		 1102 if (gt_iir &
1103 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1104 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1105 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 1106 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 1107 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 1108 notify_ring(dev, &dev_priv->ring[BCS]);
1109
cc609d5d
BW		 1110 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1111 GT_BSD_CS_ERROR_INTERRUPT |
1112 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 1113 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1114 i915_handle_error(dev, false);
1115 }
e3689190 1116
35a85ac6
BW		 1117 if (gt_iir & GT_PARITY_ERROR(dev))
1118 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1119}
1120
b543fb04
EE		 1121#define HPD_STORM_DETECT_PERIOD 1000
1122#define HPD_STORM_THRESHOLD 5
1123
10a504de 1124static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 1125 u32 hotplug_trigger,
1126 const u32 *hpd)
b543fb04
EE		 1127{
1128 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 1129 int i;
10a504de 1130 bool storm_detected = false;
b543fb04 1131
91d131d2
DV		 1132 if (!hotplug_trigger)
1133 return;
1134
b5ea2d56 1135 spin_lock(&dev_priv->irq_lock);
b543fb04 1136 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 1137
b8f102e8
EE		 1138 WARN(((hpd[i] & hotplug_trigger) &&
1139 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
1140 "Received HPD interrupt although disabled\n");
1141
b543fb04
EE		 1142 if (!(hpd[i] & hotplug_trigger) ||
1143 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1144 continue;
1145
bc5ead8c 1146 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 1147 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1148 dev_priv->hpd_stats[i].hpd_last_jiffies
1149 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1150 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1151 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1152 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1153 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1154 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1155 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1156 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1157 storm_detected = true;
b543fb04
EE		 1158 } else {
1159 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1160 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1161 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1162 }
1163 }
1164
10a504de
DV		 1165 if (storm_detected)
1166 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1167 spin_unlock(&dev_priv->irq_lock);
5876fa0d 1168
645416f5
DV		 1169 /*
1170 * Our hotplug handler can grab modeset locks (by calling down into the
1171 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1172 * queue for otherwise the flush_work in the pageflip code will
1173 * deadlock.
1174 */
1175 schedule_work(&dev_priv->hotplug_work);
b543fb04
EE		 1176}
1177
515ac2bb
DV		 1178static void gmbus_irq_handler(struct drm_device *dev)
1179{
28c70f16
DV		 1180 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1181
28c70f16 1182 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1183}
1184
ce99c256
DV		 1185static void dp_aux_irq_handler(struct drm_device *dev)
1186{
9ee32fea
DV		 1187 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1188
9ee32fea 1189 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1190}
1191
8bf1e9f1
SH		 1192#if defined(CONFIG_DEBUG_FS)
1193static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
1194{
1195 struct drm_i915_private *dev_priv = dev->dev_private;
1196 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1197 struct intel_pipe_crc_entry *entry;
ac2300d4 1198 int head, tail;
b2c88f5b 1199
0c912c79
DL		 1200 if (!pipe_crc->entries) {
1201 DRM_ERROR("spurious interrupt\n");
1202 return;
1203 }
1204
b2c88f5b
DL		 1205 head = atomic_read(&pipe_crc->head);
1206 tail = atomic_read(&pipe_crc->tail);
1207
1208 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1209 DRM_ERROR("CRC buffer overflowing\n");
1210 return;
1211 }
1212
1213 entry = &pipe_crc->entries[head];
8bf1e9f1 1214
ac2300d4 1215 entry->frame = I915_READ(PIPEFRAME(pipe));
8bf1e9f1
SH		 1216 entry->crc[0] = I915_READ(PIPE_CRC_RES_1_IVB(pipe));
1217 entry->crc[1] = I915_READ(PIPE_CRC_RES_2_IVB(pipe));
1218 entry->crc[2] = I915_READ(PIPE_CRC_RES_3_IVB(pipe));
1219 entry->crc[3] = I915_READ(PIPE_CRC_RES_4_IVB(pipe));
1220 entry->crc[4] = I915_READ(PIPE_CRC_RES_5_IVB(pipe));
b2c88f5b
DL		 1221
1222 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1223 atomic_set(&pipe_crc->head, head);
07144428
DL		 1224
1225 wake_up_interruptible(&pipe_crc->wq);
8bf1e9f1
SH		 1226}
1227#else
f8c168fa 1228static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
8bf1e9f1
SH		 1229#endif
1230
1403c0d4
PZ		 1231/* The RPS events need forcewake, so we add them to a work queue and mask their
1232 * IMR bits until the work is done. Other interrupts can be processed without
1233 * the work queue. */
1234static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1235{
41a05a3a 1236 if (pm_iir & GEN6_PM_RPS_EVENTS) {
59cdb63d 1237 spin_lock(&dev_priv->irq_lock);
41a05a3a 1238 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
4d3b3d5f 1239 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
59cdb63d 1240 spin_unlock(&dev_priv->irq_lock);
2adbee62
DV		 1241
1242 queue_work(dev_priv->wq, &dev_priv->rps.work);
baf02a1f 1243 }
baf02a1f 1244
1403c0d4
PZ		 1245 if (HAS_VEBOX(dev_priv->dev)) {
1246 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1247 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 1248
1403c0d4
PZ		 1249 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1250 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1251 i915_handle_error(dev_priv->dev, false);
1252 }
12638c57 1253 }
baf02a1f
BW		 1254}
1255
ff1f525e 1256static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 1257{
1258 struct drm_device *dev = (struct drm_device *) arg;
1259 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1260 u32 iir, gt_iir, pm_iir;
1261 irqreturn_t ret = IRQ_NONE;
1262 unsigned long irqflags;
1263 int pipe;
1264 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 1265
1266 atomic_inc(&dev_priv->irq_received);
1267
7e231dbe
JB		 1268 while (true) {
1269 iir = I915_READ(VLV_IIR);
1270 gt_iir = I915_READ(GTIIR);
1271 pm_iir = I915_READ(GEN6_PMIIR);
1272
1273 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1274 goto out;
1275
1276 ret = IRQ_HANDLED;
1277
e7b4c6b1 1278 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 1279
1280 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1281 for_each_pipe(pipe) {
1282 int reg = PIPESTAT(pipe);
1283 pipe_stats[pipe] = I915_READ(reg);
1284
1285 /*
1286 * Clear the PIPE*STAT regs before the IIR
1287 */
1288 if (pipe_stats[pipe] & 0x8000ffff) {
1289 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1290 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1291 pipe_name(pipe));
1292 I915_WRITE(reg, pipe_stats[pipe]);
1293 }
1294 }
1295 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1296
31acc7f5
JB		 1297 for_each_pipe(pipe) {
1298 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1299 drm_handle_vblank(dev, pipe);
1300
1301 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1302 intel_prepare_page_flip(dev, pipe);
1303 intel_finish_page_flip(dev, pipe);
1304 }
1305 }
1306
7e231dbe
JB		 1307 /* Consume port. Then clear IIR or we'll miss events */
1308 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1309 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1310 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 1311
1312 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1313 hotplug_status);
91d131d2
DV		 1314
1315 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1316
7e231dbe
JB		 1317 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1318 I915_READ(PORT_HOTPLUG_STAT);
1319 }
1320
515ac2bb
DV		 1321 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1322 gmbus_irq_handler(dev);
7e231dbe 1323
60611c13 1324 if (pm_iir)
d0ecd7e2 1325 gen6_rps_irq_handler(dev_priv, pm_iir);
7e231dbe
JB		 1326
1327 I915_WRITE(GTIIR, gt_iir);
1328 I915_WRITE(GEN6_PMIIR, pm_iir);
1329 I915_WRITE(VLV_IIR, iir);
1330 }
1331
1332out:
1333 return ret;
1334}
1335
23e81d69 1336static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1337{
1338 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1339 int pipe;
b543fb04 1340 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1341
91d131d2
DV		 1342 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1343
cfc33bf7
VS		 1344 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1345 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1346 SDE_AUDIO_POWER_SHIFT);
776ad806 1347 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1348 port_name(port));
1349 }
776ad806 1350
ce99c256
DV		 1351 if (pch_iir & SDE_AUX_MASK)
1352 dp_aux_irq_handler(dev);
1353
776ad806 1354 if (pch_iir & SDE_GMBUS)
515ac2bb 1355 gmbus_irq_handler(dev);
776ad806
JB		 1356
1357 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1358 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1359
1360 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1361 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1362
1363 if (pch_iir & SDE_POISON)
1364 DRM_ERROR("PCH poison interrupt\n");
1365
9db4a9c7
JB		 1366 if (pch_iir & SDE_FDI_MASK)
1367 for_each_pipe(pipe)
1368 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1369 pipe_name(pipe),
1370 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1371
1372 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1373 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1374
1375 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1376 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1377
776ad806 1378 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1379 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1380 false))
1381 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1382
1383 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1384 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1385 false))
1386 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1387}
1388
1389static void ivb_err_int_handler(struct drm_device *dev)
1390{
1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392 u32 err_int = I915_READ(GEN7_ERR_INT);
1393
de032bf4
PZ		 1394 if (err_int & ERR_INT_POISON)
1395 DRM_ERROR("Poison interrupt\n");
1396
8664281b
PZ		 1397 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1398 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1399 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1400
1401 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1402 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1403 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1404
1405 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1406 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1407 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1408
8bf1e9f1
SH		 1409 if (err_int & ERR_INT_PIPE_CRC_DONE_A)
1410 ivb_pipe_crc_update(dev, PIPE_A);
1411
1412 if (err_int & ERR_INT_PIPE_CRC_DONE_B)
1413 ivb_pipe_crc_update(dev, PIPE_B);
1414
1415 if (err_int & ERR_INT_PIPE_CRC_DONE_C)
1416 ivb_pipe_crc_update(dev, PIPE_C);
1417
8664281b
PZ		 1418 I915_WRITE(GEN7_ERR_INT, err_int);
1419}
1420
1421static void cpt_serr_int_handler(struct drm_device *dev)
1422{
1423 struct drm_i915_private *dev_priv = dev->dev_private;
1424 u32 serr_int = I915_READ(SERR_INT);
1425
de032bf4
PZ		 1426 if (serr_int & SERR_INT_POISON)
1427 DRM_ERROR("PCH poison interrupt\n");
1428
8664281b
PZ		 1429 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1430 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1431 false))
1432 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1433
1434 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1435 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1436 false))
1437 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1438
1439 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1440 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1441 false))
1442 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1443
1444 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1445}
1446
23e81d69
AJ		 1447static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1448{
1449 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1450 int pipe;
b543fb04 1451 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1452
91d131d2
DV		 1453 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1454
cfc33bf7
VS		 1455 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1456 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1457 SDE_AUDIO_POWER_SHIFT_CPT);
1458 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1459 port_name(port));
1460 }
23e81d69
AJ		 1461
1462 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1463 dp_aux_irq_handler(dev);
23e81d69
AJ		 1464
1465 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1466 gmbus_irq_handler(dev);
23e81d69
AJ		 1467
1468 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1469 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1470
1471 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1472 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1473
1474 if (pch_iir & SDE_FDI_MASK_CPT)
1475 for_each_pipe(pipe)
1476 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1477 pipe_name(pipe),
1478 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1479
1480 if (pch_iir & SDE_ERROR_CPT)
1481 cpt_serr_int_handler(dev);
23e81d69
AJ		 1482}
1483
c008bc6e
PZ		 1484static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1485{
1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487
1488 if (de_iir & DE_AUX_CHANNEL_A)
1489 dp_aux_irq_handler(dev);
1490
1491 if (de_iir & DE_GSE)
1492 intel_opregion_asle_intr(dev);
1493
1494 if (de_iir & DE_PIPEA_VBLANK)
1495 drm_handle_vblank(dev, 0);
1496
1497 if (de_iir & DE_PIPEB_VBLANK)
1498 drm_handle_vblank(dev, 1);
1499
1500 if (de_iir & DE_POISON)
1501 DRM_ERROR("Poison interrupt\n");
1502
1503 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1504 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1505 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1506
1507 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1508 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1509 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1510
1511 if (de_iir & DE_PLANEA_FLIP_DONE) {
1512 intel_prepare_page_flip(dev, 0);
1513 intel_finish_page_flip_plane(dev, 0);
1514 }
1515
1516 if (de_iir & DE_PLANEB_FLIP_DONE) {
1517 intel_prepare_page_flip(dev, 1);
1518 intel_finish_page_flip_plane(dev, 1);
1519 }
1520
1521 /* check event from PCH */
1522 if (de_iir & DE_PCH_EVENT) {
1523 u32 pch_iir = I915_READ(SDEIIR);
1524
1525 if (HAS_PCH_CPT(dev))
1526 cpt_irq_handler(dev, pch_iir);
1527 else
1528 ibx_irq_handler(dev, pch_iir);
1529
1530 /* should clear PCH hotplug event before clear CPU irq */
1531 I915_WRITE(SDEIIR, pch_iir);
1532 }
1533
1534 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1535 ironlake_rps_change_irq_handler(dev);
1536}
1537
9719fb98
PZ		 1538static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1539{
1540 struct drm_i915_private *dev_priv = dev->dev_private;
1541 int i;
1542
1543 if (de_iir & DE_ERR_INT_IVB)
1544 ivb_err_int_handler(dev);
1545
1546 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1547 dp_aux_irq_handler(dev);
1548
1549 if (de_iir & DE_GSE_IVB)
1550 intel_opregion_asle_intr(dev);
1551
1552 for (i = 0; i < 3; i++) {
1553 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1554 drm_handle_vblank(dev, i);
1555 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1556 intel_prepare_page_flip(dev, i);
1557 intel_finish_page_flip_plane(dev, i);
1558 }
1559 }
1560
1561 /* check event from PCH */
1562 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1563 u32 pch_iir = I915_READ(SDEIIR);
1564
1565 cpt_irq_handler(dev, pch_iir);
1566
1567 /* clear PCH hotplug event before clear CPU irq */
1568 I915_WRITE(SDEIIR, pch_iir);
1569 }
1570}
1571
f1af8fc1 1572static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1573{
1574 struct drm_device *dev = (struct drm_device *) arg;
1575 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
f1af8fc1 1576 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 1577 irqreturn_t ret = IRQ_NONE;
b1f14ad0
JB		 1578
1579 atomic_inc(&dev_priv->irq_received);
1580
8664281b
PZ		 1581 /* We get interrupts on unclaimed registers, so check for this before we
1582 * do any I915_{READ,WRITE}. */
907b28c5 1583 intel_uncore_check_errors(dev);
8664281b 1584
b1f14ad0
JB		 1585 /* disable master interrupt before clearing iir */
1586 de_ier = I915_READ(DEIER);
1587 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 1588 POSTING_READ(DEIER);
b1f14ad0 1589
44498aea
PZ		 1590 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1591 * interrupts will will be stored on its back queue, and then we'll be
1592 * able to process them after we restore SDEIER (as soon as we restore
1593 * it, we'll get an interrupt if SDEIIR still has something to process
1594 * due to its back queue). */
ab5c608b
BW		 1595 if (!HAS_PCH_NOP(dev)) {
1596 sde_ier = I915_READ(SDEIER);
1597 I915_WRITE(SDEIER, 0);
1598 POSTING_READ(SDEIER);
1599 }
44498aea 1600
b1f14ad0 1601 gt_iir = I915_READ(GTIIR);
0e43406b 1602 if (gt_iir) {
d8fc8a47 1603 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 1604 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 1605 else
1606 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
0e43406b
CW		 1607 I915_WRITE(GTIIR, gt_iir);
1608 ret = IRQ_HANDLED;
b1f14ad0
JB		 1609 }
1610
0e43406b
CW		 1611 de_iir = I915_READ(DEIIR);
1612 if (de_iir) {
f1af8fc1
PZ		 1613 if (INTEL_INFO(dev)->gen >= 7)
1614 ivb_display_irq_handler(dev, de_iir);
1615 else
1616 ilk_display_irq_handler(dev, de_iir);
0e43406b
CW		 1617 I915_WRITE(DEIIR, de_iir);
1618 ret = IRQ_HANDLED;
b1f14ad0
JB		 1619 }
1620
f1af8fc1
PZ		 1621 if (INTEL_INFO(dev)->gen >= 6) {
1622 u32 pm_iir = I915_READ(GEN6_PMIIR);
1623 if (pm_iir) {
1403c0d4 1624 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1
PZ		 1625 I915_WRITE(GEN6_PMIIR, pm_iir);
1626 ret = IRQ_HANDLED;
1627 }
0e43406b 1628 }
b1f14ad0 1629
b1f14ad0
JB		 1630 I915_WRITE(DEIER, de_ier);
1631 POSTING_READ(DEIER);
ab5c608b
BW		 1632 if (!HAS_PCH_NOP(dev)) {
1633 I915_WRITE(SDEIER, sde_ier);
1634 POSTING_READ(SDEIER);
1635 }
b1f14ad0
JB		 1636
1637 return ret;
1638}
1639
17e1df07
DV		 1640static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1641 bool reset_completed)
1642{
1643 struct intel_ring_buffer *ring;
1644 int i;
1645
1646 /*
1647 * Notify all waiters for GPU completion events that reset state has
1648 * been changed, and that they need to restart their wait after
1649 * checking for potential errors (and bail out to drop locks if there is
1650 * a gpu reset pending so that i915_error_work_func can acquire them).
1651 */
1652
1653 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1654 for_each_ring(ring, dev_priv, i)
1655 wake_up_all(&ring->irq_queue);
1656
1657 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1658 wake_up_all(&dev_priv->pending_flip_queue);
1659
1660 /*
1661 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1662 * reset state is cleared.
1663 */
1664 if (reset_completed)
1665 wake_up_all(&dev_priv->gpu_error.reset_queue);
1666}
1667
8a905236
JB		 1668/**
1669 * i915_error_work_func - do process context error handling work
1670 * @work: work struct
1671 *
1672 * Fire an error uevent so userspace can see that a hang or error
1673 * was detected.
1674 */
1675static void i915_error_work_func(struct work_struct *work)
1676{
1f83fee0
DV		 1677 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1678 work);
1679 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1680 gpu_error);
8a905236 1681 struct drm_device *dev = dev_priv->dev;
cce723ed
BW		 1682 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1683 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1684 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 1685 int ret;
8a905236 1686
f316a42c
BG		 1687 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1688
7db0ba24
DV		 1689 /*
1690 * Note that there's only one work item which does gpu resets, so we
1691 * need not worry about concurrent gpu resets potentially incrementing
1692 * error->reset_counter twice. We only need to take care of another
1693 * racing irq/hangcheck declaring the gpu dead for a second time. A
1694 * quick check for that is good enough: schedule_work ensures the
1695 * correct ordering between hang detection and this work item, and since
1696 * the reset in-progress bit is only ever set by code outside of this
1697 * work we don't need to worry about any other races.
1698 */
1699 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1700 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1701 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1702 reset_event);
1f83fee0 1703
17e1df07
DV		 1704 /*
1705 * All state reset _must_ be completed before we update the
1706 * reset counter, for otherwise waiters might miss the reset
1707 * pending state and not properly drop locks, resulting in
1708 * deadlocks with the reset work.
1709 */
f69061be
DV		 1710 ret = i915_reset(dev);
1711
17e1df07
DV		 1712 intel_display_handle_reset(dev);
1713
f69061be
DV		 1714 if (ret == 0) {
1715 /*
1716 * After all the gem state is reset, increment the reset
1717 * counter and wake up everyone waiting for the reset to
1718 * complete.
1719 *
1720 * Since unlock operations are a one-sided barrier only,
1721 * we need to insert a barrier here to order any seqno
1722 * updates before
1723 * the counter increment.
1724 */
1725 smp_mb__before_atomic_inc();
1726 atomic_inc(&dev_priv->gpu_error.reset_counter);
1727
1728 kobject_uevent_env(&dev->primary->kdev.kobj,
1729 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1730 } else {
1731 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1732 }
1f83fee0 1733
17e1df07
DV		 1734 /*
1735 * Note: The wake_up also serves as a memory barrier so that
1736 * waiters see the update value of the reset counter atomic_t.
1737 */
1738 i915_error_wake_up(dev_priv, true);
f316a42c 1739 }
8a905236
JB		 1740}
1741
35aed2e6 1742static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1743{
1744 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1745 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1746 u32 eir = I915_READ(EIR);
050ee91f 1747 int pipe, i;
8a905236 1748
35aed2e6
CW		 1749 if (!eir)
1750 return;
8a905236 1751
a70491cc 1752 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1753
bd9854f9
BW		 1754 i915_get_extra_instdone(dev, instdone);
1755
8a905236
JB		 1756 if (IS_G4X(dev)) {
1757 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1758 u32 ipeir = I915_READ(IPEIR_I965);
1759
a70491cc
JP		 1760 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1761 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1762 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1763 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1764 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1765 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1766 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1767 POSTING_READ(IPEIR_I965);
8a905236
JB		 1768 }
1769 if (eir & GM45_ERROR_PAGE_TABLE) {
1770 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1771 pr_err("page table error\n");
1772 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1773 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1774 POSTING_READ(PGTBL_ER);
8a905236
JB		 1775 }
1776 }
1777
a6c45cf0 1778 if (!IS_GEN2(dev)) {
8a905236
JB		 1779 if (eir & I915_ERROR_PAGE_TABLE) {
1780 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1781 pr_err("page table error\n");
1782 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1783 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1784 POSTING_READ(PGTBL_ER);
8a905236
JB		 1785 }
1786 }
1787
1788 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1789 pr_err("memory refresh error:\n");
9db4a9c7 1790 for_each_pipe(pipe)
a70491cc 1791 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1792 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1793 /* pipestat has already been acked */
1794 }
1795 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1796 pr_err("instruction error\n");
1797 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1798 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1799 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1800 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1801 u32 ipeir = I915_READ(IPEIR);
1802
a70491cc
JP		 1803 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1804 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1805 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1806 I915_WRITE(IPEIR, ipeir);
3143a2bf 1807 POSTING_READ(IPEIR);
8a905236
JB		 1808 } else {
1809 u32 ipeir = I915_READ(IPEIR_I965);
1810
a70491cc
JP		 1811 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1812 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1813 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1814 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1815 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1816 POSTING_READ(IPEIR_I965);
8a905236
JB		 1817 }
1818 }
1819
1820 I915_WRITE(EIR, eir);
3143a2bf 1821 POSTING_READ(EIR);
8a905236
JB		 1822 eir = I915_READ(EIR);
1823 if (eir) {
1824 /*
1825 * some errors might have become stuck,
1826 * mask them.
1827 */
1828 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1829 I915_WRITE(EMR, I915_READ(EMR) | eir);
1830 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1831 }
35aed2e6
CW		 1832}
1833
1834/**
1835 * i915_handle_error - handle an error interrupt
1836 * @dev: drm device
1837 *
1838 * Do some basic checking of regsiter state at error interrupt time and
1839 * dump it to the syslog. Also call i915_capture_error_state() to make
1840 * sure we get a record and make it available in debugfs. Fire a uevent
1841 * so userspace knows something bad happened (should trigger collection
1842 * of a ring dump etc.).
1843 */
527f9e90 1844void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1845{
1846 struct drm_i915_private *dev_priv = dev->dev_private;
1847
1848 i915_capture_error_state(dev);
1849 i915_report_and_clear_eir(dev);
8a905236 1850
ba1234d1 1851 if (wedged) {
f69061be
DV		 1852 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1853 &dev_priv->gpu_error.reset_counter);
ba1234d1 1854
11ed50ec 1855 /*
17e1df07
DV		 1856 * Wakeup waiting processes so that the reset work function
1857 * i915_error_work_func doesn't deadlock trying to grab various
1858 * locks. By bumping the reset counter first, the woken
1859 * processes will see a reset in progress and back off,
1860 * releasing their locks and then wait for the reset completion.
1861 * We must do this for _all_ gpu waiters that might hold locks
1862 * that the reset work needs to acquire.
1863 *
1864 * Note: The wake_up serves as the required memory barrier to
1865 * ensure that the waiters see the updated value of the reset
1866 * counter atomic_t.
11ed50ec 1867 */
17e1df07 1868 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 1869 }
1870
122f46ba
DV		 1871 /*
1872 * Our reset work can grab modeset locks (since it needs to reset the
1873 * state of outstanding pagelips). Hence it must not be run on our own
1874 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1875 * code will deadlock.
1876 */
1877 schedule_work(&dev_priv->gpu_error.work);
8a905236
JB		 1878}
1879
21ad8330 1880static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 1881{
1882 drm_i915_private_t *dev_priv = dev->dev_private;
1883 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1885 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1886 struct intel_unpin_work *work;
1887 unsigned long flags;
1888 bool stall_detected;
1889
1890 /* Ignore early vblank irqs */
1891 if (intel_crtc == NULL)
1892 return;
1893
1894 spin_lock_irqsave(&dev->event_lock, flags);
1895 work = intel_crtc->unpin_work;
1896
e7d841ca
CW		 1897 if (work == NULL ||
1898 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1899 !work->enable_stall_check) {
4e5359cd
SF		 1900 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1901 spin_unlock_irqrestore(&dev->event_lock, flags);
1902 return;
1903 }
1904
1905 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1906 obj = work->pending_flip_obj;
a6c45cf0 1907 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1908 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 1909 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 1910 i915_gem_obj_ggtt_offset(obj);
4e5359cd 1911 } else {
9db4a9c7 1912 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 1913 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
01f2c773 1914 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1915 crtc->x * crtc->fb->bits_per_pixel/8);
1916 }
1917
1918 spin_unlock_irqrestore(&dev->event_lock, flags);
1919
1920 if (stall_detected) {
1921 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1922 intel_prepare_page_flip(dev, intel_crtc->plane);
1923 }
1924}
1925
42f52ef8
KP		 1926/* Called from drm generic code, passed 'crtc' which
1927 * we use as a pipe index
1928 */
f71d4af4 1929static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1930{
1931 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1932 unsigned long irqflags;
71e0ffa5 1933
5eddb70b 1934 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1935 return -EINVAL;
0a3e67a4 1936
1ec14ad3 1937 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1938 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1939 i915_enable_pipestat(dev_priv, pipe,
1940 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1941 else
7c463586
KP		 1942 i915_enable_pipestat(dev_priv, pipe,
1943 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1944
1945 /* maintain vblank delivery even in deep C-states */
1946 if (dev_priv->info->gen == 3)
6b26c86d 1947 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1948 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1949
0a3e67a4
JB		 1950 return 0;
1951}
1952
f71d4af4 1953static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1954{
1955 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1956 unsigned long irqflags;
b518421f
PZ		 1957 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1958 DE_PIPE_VBLANK_ILK(pipe);
f796cf8f
JB		 1959
1960 if (!i915_pipe_enabled(dev, pipe))
1961 return -EINVAL;
1962
1963 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 1964 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 1965 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1966
1967 return 0;
1968}
1969
7e231dbe
JB		 1970static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1971{
1972 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1973 unsigned long irqflags;
31acc7f5 1974 u32 imr;
7e231dbe
JB		 1975
1976 if (!i915_pipe_enabled(dev, pipe))
1977 return -EINVAL;
1978
1979 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1980 imr = I915_READ(VLV_IMR);
31acc7f5 1981 if (pipe == 0)
7e231dbe 1982 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1983 else
7e231dbe 1984 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1985 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1986 i915_enable_pipestat(dev_priv, pipe,
1987 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1988 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1989
1990 return 0;
1991}
1992
42f52ef8
KP		 1993/* Called from drm generic code, passed 'crtc' which
1994 * we use as a pipe index
1995 */
f71d4af4 1996static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1997{
1998 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1999 unsigned long irqflags;
0a3e67a4 2000
1ec14ad3 2001 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 2002 if (dev_priv->info->gen == 3)
6b26c86d 2003 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2004
f796cf8f
JB		 2005 i915_disable_pipestat(dev_priv, pipe,
2006 PIPE_VBLANK_INTERRUPT_ENABLE |
2007 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2008 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2009}
2010
f71d4af4 2011static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2012{
2013 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2014 unsigned long irqflags;
b518421f
PZ		 2015 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2016 DE_PIPE_VBLANK_ILK(pipe);
f796cf8f
JB		 2017
2018 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2019 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2020 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2021}
2022
7e231dbe
JB		 2023static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2024{
2025 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2026 unsigned long irqflags;
31acc7f5 2027 u32 imr;
7e231dbe
JB		 2028
2029 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2030 i915_disable_pipestat(dev_priv, pipe,
2031 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 2032 imr = I915_READ(VLV_IMR);
31acc7f5 2033 if (pipe == 0)
7e231dbe 2034 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2035 else
7e231dbe 2036 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2037 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 2038 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2039}
2040
893eead0
CW		 2041static u32
2042ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2043{
893eead0
CW		 2044 return list_entry(ring->request_list.prev,
2045 struct drm_i915_gem_request, list)->seqno;
2046}
2047
9107e9d2
CW		 2048static bool
2049ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2050{
2051 return (list_empty(&ring->request_list) ||
2052 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 2053}
2054
6274f212
CW		 2055static struct intel_ring_buffer *
2056semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 2057{
2058 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 2059 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 2060
2061 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2062 if ((ipehr & ~(0x3 << 16)) !=
2063 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 2064 return NULL;
a24a11e6
CW		 2065
2066 /* ACTHD is likely pointing to the dword after the actual command,
2067 * so scan backwards until we find the MBOX.
2068 */
6274f212 2069 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 2070 acthd_min = max((int)acthd - 3 * 4, 0);
2071 do {
2072 cmd = ioread32(ring->virtual_start + acthd);
2073 if (cmd == ipehr)
2074 break;
2075
2076 acthd -= 4;
2077 if (acthd < acthd_min)
6274f212 2078 return NULL;
a24a11e6
CW		 2079 } while (1);
2080
6274f212
CW		 2081 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2082 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 2083}
2084
6274f212
CW		 2085static int semaphore_passed(struct intel_ring_buffer *ring)
2086{
2087 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2088 struct intel_ring_buffer *signaller;
2089 u32 seqno, ctl;
2090
2091 ring->hangcheck.deadlock = true;
2092
2093 signaller = semaphore_waits_for(ring, &seqno);
2094 if (signaller == NULL || signaller->hangcheck.deadlock)
2095 return -1;
2096
2097 /* cursory check for an unkickable deadlock */
2098 ctl = I915_READ_CTL(signaller);
2099 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2100 return -1;
2101
2102 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2103}
2104
2105static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2106{
2107 struct intel_ring_buffer *ring;
2108 int i;
2109
2110 for_each_ring(ring, dev_priv, i)
2111 ring->hangcheck.deadlock = false;
2112}
2113
ad8beaea
MK		 2114static enum intel_ring_hangcheck_action
2115ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 2116{
2117 struct drm_device *dev = ring->dev;
2118 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2119 u32 tmp;
2120
6274f212 2121 if (ring->hangcheck.acthd != acthd)
f2f4d82f 2122 return HANGCHECK_ACTIVE;
6274f212 2123
9107e9d2 2124 if (IS_GEN2(dev))
f2f4d82f 2125 return HANGCHECK_HUNG;
9107e9d2
CW		 2126
2127 /* Is the chip hanging on a WAIT_FOR_EVENT?
2128 * If so we can simply poke the RB_WAIT bit
2129 * and break the hang. This should work on
2130 * all but the second generation chipsets.
2131 */
2132 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 2133 if (tmp & RING_WAIT) {
2134 DRM_ERROR("Kicking stuck wait on %s\n",
2135 ring->name);
09e14bf3 2136 i915_handle_error(dev, false);
1ec14ad3 2137 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2138 return HANGCHECK_KICK;
6274f212
CW		 2139 }
2140
2141 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2142 switch (semaphore_passed(ring)) {
2143 default:
f2f4d82f 2144 return HANGCHECK_HUNG;
6274f212
CW		 2145 case 1:
2146 DRM_ERROR("Kicking stuck semaphore on %s\n",
2147 ring->name);
09e14bf3 2148 i915_handle_error(dev, false);
6274f212 2149 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2150 return HANGCHECK_KICK;
6274f212 2151 case 0:
f2f4d82f 2152 return HANGCHECK_WAIT;
6274f212 2153 }
9107e9d2 2154 }
ed5cbb03 2155
f2f4d82f 2156 return HANGCHECK_HUNG;
ed5cbb03
MK		 2157}
2158
f65d9421
BG		 2159/**
2160 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2161 * batchbuffers in a long time. We keep track per ring seqno progress and
2162 * if there are no progress, hangcheck score for that ring is increased.
2163 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2164 * we kick the ring. If we see no progress on three subsequent calls
2165 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 2166 */
a658b5d2 2167static void i915_hangcheck_elapsed(unsigned long data)
f65d9421
BG		 2168{
2169 struct drm_device *dev = (struct drm_device *)data;
2170 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 2171 struct intel_ring_buffer *ring;
b4519513 2172 int i;
05407ff8 2173 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2174 bool stuck[I915_NUM_RINGS] = { 0 };
2175#define BUSY 1
2176#define KICK 5
2177#define HUNG 20
2178#define FIRE 30
893eead0 2179
3e0dc6b0
BW		 2180 if (!i915_enable_hangcheck)
2181 return;
2182
b4519513 2183 for_each_ring(ring, dev_priv, i) {
05407ff8 2184 u32 seqno, acthd;
9107e9d2 2185 bool busy = true;
05407ff8 2186
6274f212
CW		 2187 semaphore_clear_deadlocks(dev_priv);
2188
05407ff8
MK		 2189 seqno = ring->get_seqno(ring, false);
2190 acthd = intel_ring_get_active_head(ring);
b4519513 2191
9107e9d2
CW		 2192 if (ring->hangcheck.seqno == seqno) {
2193 if (ring_idle(ring, seqno)) {
da661464
MK		 2194 ring->hangcheck.action = HANGCHECK_IDLE;
2195
9107e9d2
CW		 2196 if (waitqueue_active(&ring->irq_queue)) {
2197 /* Issue a wake-up to catch stuck h/w. */
094f9a54
CW		 2198 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2199 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2200 ring->name);
2201 wake_up_all(&ring->irq_queue);
2202 }
2203 /* Safeguard against driver failure */
2204 ring->hangcheck.score += BUSY;
9107e9d2
CW		 2205 } else
2206 busy = false;
05407ff8 2207 } else {
6274f212
CW		 2208 /* We always increment the hangcheck score
2209 * if the ring is busy and still processing
2210 * the same request, so that no single request
2211 * can run indefinitely (such as a chain of
2212 * batches). The only time we do not increment
2213 * the hangcheck score on this ring, if this
2214 * ring is in a legitimate wait for another
2215 * ring. In that case the waiting ring is a
2216 * victim and we want to be sure we catch the
2217 * right culprit. Then every time we do kick
2218 * the ring, add a small increment to the
2219 * score so that we can catch a batch that is
2220 * being repeatedly kicked and so responsible
2221 * for stalling the machine.
2222 */
ad8beaea
MK		 2223 ring->hangcheck.action = ring_stuck(ring,
2224 acthd);
2225
2226 switch (ring->hangcheck.action) {
da661464 2227 case HANGCHECK_IDLE:
f2f4d82f 2228 case HANGCHECK_WAIT:
6274f212 2229 break;
f2f4d82f 2230 case HANGCHECK_ACTIVE:
ea04cb31 2231 ring->hangcheck.score += BUSY;
6274f212 2232 break;
f2f4d82f 2233 case HANGCHECK_KICK:
ea04cb31 2234 ring->hangcheck.score += KICK;
6274f212 2235 break;
f2f4d82f 2236 case HANGCHECK_HUNG:
ea04cb31 2237 ring->hangcheck.score += HUNG;
6274f212
CW		 2238 stuck[i] = true;
2239 break;
2240 }
05407ff8 2241 }
9107e9d2 2242 } else {
da661464
MK		 2243 ring->hangcheck.action = HANGCHECK_ACTIVE;
2244
9107e9d2
CW		 2245 /* Gradually reduce the count so that we catch DoS
2246 * attempts across multiple batches.
2247 */
2248 if (ring->hangcheck.score > 0)
2249 ring->hangcheck.score--;
d1e61e7f
CW		 2250 }
2251
05407ff8
MK		 2252 ring->hangcheck.seqno = seqno;
2253 ring->hangcheck.acthd = acthd;
9107e9d2 2254 busy_count += busy;
893eead0 2255 }
b9201c14 2256
92cab734 2257 for_each_ring(ring, dev_priv, i) {
9107e9d2 2258 if (ring->hangcheck.score > FIRE) {
b8d88d1d
DV		 2259 DRM_INFO("%s on %s\n",
2260 stuck[i] ? "stuck" : "no progress",
2261 ring->name);
a43adf07 2262 rings_hung++;
92cab734
MK		 2263 }
2264 }
2265
05407ff8
MK		 2266 if (rings_hung)
2267 return i915_handle_error(dev, true);
f65d9421 2268
05407ff8
MK		 2269 if (busy_count)
2270 /* Reset timer case chip hangs without another request
2271 * being added */
10cd45b6
MK		 2272 i915_queue_hangcheck(dev);
2273}
2274
2275void i915_queue_hangcheck(struct drm_device *dev)
2276{
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278 if (!i915_enable_hangcheck)
2279 return;
2280
2281 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2282 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2283}
2284
91738a95
PZ		 2285static void ibx_irq_preinstall(struct drm_device *dev)
2286{
2287 struct drm_i915_private *dev_priv = dev->dev_private;
2288
2289 if (HAS_PCH_NOP(dev))
2290 return;
2291
2292 /* south display irq */
2293 I915_WRITE(SDEIMR, 0xffffffff);
2294 /*
2295 * SDEIER is also touched by the interrupt handler to work around missed
2296 * PCH interrupts. Hence we can't update it after the interrupt handler
2297 * is enabled - instead we unconditionally enable all PCH interrupt
2298 * sources here, but then only unmask them as needed with SDEIMR.
2299 */
2300 I915_WRITE(SDEIER, 0xffffffff);
2301 POSTING_READ(SDEIER);
2302}
2303
d18ea1b5
DV		 2304static void gen5_gt_irq_preinstall(struct drm_device *dev)
2305{
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307
2308 /* and GT */
2309 I915_WRITE(GTIMR, 0xffffffff);
2310 I915_WRITE(GTIER, 0x0);
2311 POSTING_READ(GTIER);
2312
2313 if (INTEL_INFO(dev)->gen >= 6) {
2314 /* and PM */
2315 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2316 I915_WRITE(GEN6_PMIER, 0x0);
2317 POSTING_READ(GEN6_PMIER);
2318 }
2319}
2320
1da177e4
LT		 2321/* drm_dma.h hooks
2322*/
f71d4af4 2323static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2324{
2325 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2326
4697995b
JB		 2327 atomic_set(&dev_priv->irq_received, 0);
2328
036a4a7d 2329 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2330
036a4a7d
ZW		 2331 I915_WRITE(DEIMR, 0xffffffff);
2332 I915_WRITE(DEIER, 0x0);
3143a2bf 2333 POSTING_READ(DEIER);
036a4a7d 2334
d18ea1b5 2335 gen5_gt_irq_preinstall(dev);
c650156a 2336
91738a95 2337 ibx_irq_preinstall(dev);
7d99163d
BW		 2338}
2339
7e231dbe
JB		 2340static void valleyview_irq_preinstall(struct drm_device *dev)
2341{
2342 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2343 int pipe;
2344
2345 atomic_set(&dev_priv->irq_received, 0);
2346
7e231dbe
JB		 2347 /* VLV magic */
2348 I915_WRITE(VLV_IMR, 0);
2349 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2350 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2351 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2352
7e231dbe
JB		 2353 /* and GT */
2354 I915_WRITE(GTIIR, I915_READ(GTIIR));
2355 I915_WRITE(GTIIR, I915_READ(GTIIR));
d18ea1b5
DV		 2356
2357 gen5_gt_irq_preinstall(dev);
7e231dbe
JB		 2358
2359 I915_WRITE(DPINVGTT, 0xff);
2360
2361 I915_WRITE(PORT_HOTPLUG_EN, 0);
2362 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2363 for_each_pipe(pipe)
2364 I915_WRITE(PIPESTAT(pipe), 0xffff);
2365 I915_WRITE(VLV_IIR, 0xffffffff);
2366 I915_WRITE(VLV_IMR, 0xffffffff);
2367 I915_WRITE(VLV_IER, 0x0);
2368 POSTING_READ(VLV_IER);
2369}
2370
82a28bcf 2371static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2372{
2373 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2374 struct drm_mode_config *mode_config = &dev->mode_config;
2375 struct intel_encoder *intel_encoder;
fee884ed 2376 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2377
2378 if (HAS_PCH_IBX(dev)) {
fee884ed 2379 hotplug_irqs = SDE_HOTPLUG_MASK;
82a28bcf 2380 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2381 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2382 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2383 } else {
fee884ed 2384 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
82a28bcf 2385 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2386 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2387 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2388 }
7fe0b973 2389
fee884ed 2390 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 2391
2392 /*
2393 * Enable digital hotplug on the PCH, and configure the DP short pulse
2394 * duration to 2ms (which is the minimum in the Display Port spec)
2395 *
2396 * This register is the same on all known PCH chips.
2397 */
7fe0b973
KP		 2398 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2399 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2400 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2401 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2402 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2403 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2404}
2405
d46da437
PZ		 2406static void ibx_irq_postinstall(struct drm_device *dev)
2407{
2408 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2409 u32 mask;
e5868a31 2410
692a04cf
DV		 2411 if (HAS_PCH_NOP(dev))
2412 return;
2413
8664281b
PZ		 2414 if (HAS_PCH_IBX(dev)) {
2415 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2416 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2417 } else {
2418 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2419
2420 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2421 }
ab5c608b 2422
d46da437
PZ		 2423 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2424 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2425}
2426
0a9a8c91
DV		 2427static void gen5_gt_irq_postinstall(struct drm_device *dev)
2428{
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 u32 pm_irqs, gt_irqs;
2431
2432 pm_irqs = gt_irqs = 0;
2433
2434 dev_priv->gt_irq_mask = ~0;
040d2baa 2435 if (HAS_L3_DPF(dev)) {
0a9a8c91 2436 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 2437 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2438 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 2439 }
2440
2441 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2442 if (IS_GEN5(dev)) {
2443 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2444 ILK_BSD_USER_INTERRUPT;
2445 } else {
2446 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2447 }
2448
2449 I915_WRITE(GTIIR, I915_READ(GTIIR));
2450 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2451 I915_WRITE(GTIER, gt_irqs);
2452 POSTING_READ(GTIER);
2453
2454 if (INTEL_INFO(dev)->gen >= 6) {
2455 pm_irqs |= GEN6_PM_RPS_EVENTS;
2456
2457 if (HAS_VEBOX(dev))
2458 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2459
605cd25b 2460 dev_priv->pm_irq_mask = 0xffffffff;
0a9a8c91 2461 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
605cd25b 2462 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
0a9a8c91
DV		 2463 I915_WRITE(GEN6_PMIER, pm_irqs);
2464 POSTING_READ(GEN6_PMIER);
2465 }
2466}
2467
f71d4af4 2468static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2469{
4bc9d430 2470 unsigned long irqflags;
036a4a7d 2471 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8e76f8dc
PZ		 2472 u32 display_mask, extra_mask;
2473
2474 if (INTEL_INFO(dev)->gen >= 7) {
2475 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2476 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2477 DE_PLANEB_FLIP_DONE_IVB |
2478 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2479 DE_ERR_INT_IVB);
2480 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2481 DE_PIPEA_VBLANK_IVB);
2482
2483 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2484 } else {
2485 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2486 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2487 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2488 DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
2489 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2490 }
036a4a7d 2491
1ec14ad3 2492 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2493
2494 /* should always can generate irq */
2495 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2496 I915_WRITE(DEIMR, dev_priv->irq_mask);
8e76f8dc 2497 I915_WRITE(DEIER, display_mask | extra_mask);
3143a2bf 2498 POSTING_READ(DEIER);
036a4a7d 2499
0a9a8c91 2500 gen5_gt_irq_postinstall(dev);
036a4a7d 2501
d46da437 2502 ibx_irq_postinstall(dev);
7fe0b973 2503
f97108d1 2504 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2505 /* Enable PCU event interrupts
2506 *
2507 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2508 * setup is guaranteed to run in single-threaded context. But we
2509 * need it to make the assert_spin_locked happy. */
2510 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2511 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2512 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2513 }
2514
036a4a7d
ZW		 2515 return 0;
2516}
2517
7e231dbe
JB		 2518static int valleyview_irq_postinstall(struct drm_device *dev)
2519{
2520 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2521 u32 enable_mask;
31acc7f5 2522 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
b79480ba 2523 unsigned long irqflags;
7e231dbe
JB		 2524
2525 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2526 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2527 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2528 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2529 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2530
31acc7f5
JB		 2531 /*
2532 *Leave vblank interrupts masked initially. enable/disable will
2533 * toggle them based on usage.
2534 */
2535 dev_priv->irq_mask = (~enable_mask) |
2536 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2537 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2538
20afbda2
DV		 2539 I915_WRITE(PORT_HOTPLUG_EN, 0);
2540 POSTING_READ(PORT_HOTPLUG_EN);
2541
7e231dbe
JB		 2542 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2543 I915_WRITE(VLV_IER, enable_mask);
2544 I915_WRITE(VLV_IIR, 0xffffffff);
2545 I915_WRITE(PIPESTAT(0), 0xffff);
2546 I915_WRITE(PIPESTAT(1), 0xffff);
2547 POSTING_READ(VLV_IER);
2548
b79480ba
DV		 2549 /* Interrupt setup is already guaranteed to be single-threaded, this is
2550 * just to make the assert_spin_locked check happy. */
2551 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2552 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2553 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5 2554 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
b79480ba 2555 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 2556
7e231dbe
JB		 2557 I915_WRITE(VLV_IIR, 0xffffffff);
2558 I915_WRITE(VLV_IIR, 0xffffffff);
2559
0a9a8c91 2560 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 2561
2562 /* ack & enable invalid PTE error interrupts */
2563#if 0 /* FIXME: add support to irq handler for checking these bits */
2564 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2565 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2566#endif
2567
2568 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2569
2570 return 0;
2571}
2572
7e231dbe
JB		 2573static void valleyview_irq_uninstall(struct drm_device *dev)
2574{
2575 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2576 int pipe;
2577
2578 if (!dev_priv)
2579 return;
2580
ac4c16c5
EE		 2581 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2582
7e231dbe
JB		 2583 for_each_pipe(pipe)
2584 I915_WRITE(PIPESTAT(pipe), 0xffff);
2585
2586 I915_WRITE(HWSTAM, 0xffffffff);
2587 I915_WRITE(PORT_HOTPLUG_EN, 0);
2588 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2589 for_each_pipe(pipe)
2590 I915_WRITE(PIPESTAT(pipe), 0xffff);
2591 I915_WRITE(VLV_IIR, 0xffffffff);
2592 I915_WRITE(VLV_IMR, 0xffffffff);
2593 I915_WRITE(VLV_IER, 0x0);
2594 POSTING_READ(VLV_IER);
2595}
2596
f71d4af4 2597static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2598{
2599 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2600
2601 if (!dev_priv)
2602 return;
2603
ac4c16c5
EE		 2604 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2605
036a4a7d
ZW		 2606 I915_WRITE(HWSTAM, 0xffffffff);
2607
2608 I915_WRITE(DEIMR, 0xffffffff);
2609 I915_WRITE(DEIER, 0x0);
2610 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2611 if (IS_GEN7(dev))
2612 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2613
2614 I915_WRITE(GTIMR, 0xffffffff);
2615 I915_WRITE(GTIER, 0x0);
2616 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2617
ab5c608b
BW		 2618 if (HAS_PCH_NOP(dev))
2619 return;
2620
192aac1f
KP		 2621 I915_WRITE(SDEIMR, 0xffffffff);
2622 I915_WRITE(SDEIER, 0x0);
2623 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2624 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2625 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2626}
2627
a266c7d5 2628static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2629{
2630 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2631 int pipe;
91e3738e 2632
a266c7d5 2633 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2634
9db4a9c7
JB		 2635 for_each_pipe(pipe)
2636 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2637 I915_WRITE16(IMR, 0xffff);
2638 I915_WRITE16(IER, 0x0);
2639 POSTING_READ16(IER);
c2798b19
CW		 2640}
2641
2642static int i8xx_irq_postinstall(struct drm_device *dev)
2643{
2644 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2645
c2798b19
CW		 2646 I915_WRITE16(EMR,
2647 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2648
2649 /* Unmask the interrupts that we always want on. */
2650 dev_priv->irq_mask =
2651 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2652 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2653 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2654 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2655 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2656 I915_WRITE16(IMR, dev_priv->irq_mask);
2657
2658 I915_WRITE16(IER,
2659 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2660 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2661 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2662 I915_USER_INTERRUPT);
2663 POSTING_READ16(IER);
2664
2665 return 0;
2666}
2667
90a72f87
VS		 2668/*
2669 * Returns true when a page flip has completed.
2670 */
2671static bool i8xx_handle_vblank(struct drm_device *dev,
2672 int pipe, u16 iir)
2673{
2674 drm_i915_private_t *dev_priv = dev->dev_private;
2675 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2676
2677 if (!drm_handle_vblank(dev, pipe))
2678 return false;
2679
2680 if ((iir & flip_pending) == 0)
2681 return false;
2682
2683 intel_prepare_page_flip(dev, pipe);
2684
2685 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2686 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2687 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2688 * the flip is completed (no longer pending). Since this doesn't raise
2689 * an interrupt per se, we watch for the change at vblank.
2690 */
2691 if (I915_READ16(ISR) & flip_pending)
2692 return false;
2693
2694 intel_finish_page_flip(dev, pipe);
2695
2696 return true;
2697}
2698
ff1f525e 2699static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2700{
2701 struct drm_device *dev = (struct drm_device *) arg;
2702 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2703 u16 iir, new_iir;
2704 u32 pipe_stats[2];
2705 unsigned long irqflags;
c2798b19
CW		 2706 int pipe;
2707 u16 flip_mask =
2708 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2709 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2710
2711 atomic_inc(&dev_priv->irq_received);
2712
2713 iir = I915_READ16(IIR);
2714 if (iir == 0)
2715 return IRQ_NONE;
2716
2717 while (iir & ~flip_mask) {
2718 /* Can't rely on pipestat interrupt bit in iir as it might
2719 * have been cleared after the pipestat interrupt was received.
2720 * It doesn't set the bit in iir again, but it still produces
2721 * interrupts (for non-MSI).
2722 */
2723 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2724 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2725 i915_handle_error(dev, false);
2726
2727 for_each_pipe(pipe) {
2728 int reg = PIPESTAT(pipe);
2729 pipe_stats[pipe] = I915_READ(reg);
2730
2731 /*
2732 * Clear the PIPE*STAT regs before the IIR
2733 */
2734 if (pipe_stats[pipe] & 0x8000ffff) {
2735 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2736 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2737 pipe_name(pipe));
2738 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19
CW		 2739 }
2740 }
2741 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2742
2743 I915_WRITE16(IIR, iir & ~flip_mask);
2744 new_iir = I915_READ16(IIR); /* Flush posted writes */
2745
d05c617e 2746 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2747
2748 if (iir & I915_USER_INTERRUPT)
2749 notify_ring(dev, &dev_priv->ring[RCS]);
2750
2751 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2752 i8xx_handle_vblank(dev, 0, iir))
2753 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 2754
2755 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2756 i8xx_handle_vblank(dev, 1, iir))
2757 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 2758
2759 iir = new_iir;
2760 }
2761
2762 return IRQ_HANDLED;
2763}
2764
2765static void i8xx_irq_uninstall(struct drm_device * dev)
2766{
2767 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2768 int pipe;
2769
c2798b19
CW		 2770 for_each_pipe(pipe) {
2771 /* Clear enable bits; then clear status bits */
2772 I915_WRITE(PIPESTAT(pipe), 0);
2773 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2774 }
2775 I915_WRITE16(IMR, 0xffff);
2776 I915_WRITE16(IER, 0x0);
2777 I915_WRITE16(IIR, I915_READ16(IIR));
2778}
2779
a266c7d5
CW		 2780static void i915_irq_preinstall(struct drm_device * dev)
2781{
2782 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2783 int pipe;
2784
2785 atomic_set(&dev_priv->irq_received, 0);
2786
2787 if (I915_HAS_HOTPLUG(dev)) {
2788 I915_WRITE(PORT_HOTPLUG_EN, 0);
2789 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2790 }
2791
00d98ebd 2792 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2793 for_each_pipe(pipe)
2794 I915_WRITE(PIPESTAT(pipe), 0);
2795 I915_WRITE(IMR, 0xffffffff);
2796 I915_WRITE(IER, 0x0);
2797 POSTING_READ(IER);
2798}
2799
2800static int i915_irq_postinstall(struct drm_device *dev)
2801{
2802 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2803 u32 enable_mask;
a266c7d5 2804
38bde180
CW		 2805 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2806
2807 /* Unmask the interrupts that we always want on. */
2808 dev_priv->irq_mask =
2809 ~(I915_ASLE_INTERRUPT |
2810 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2811 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2812 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2813 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2814 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2815
2816 enable_mask =
2817 I915_ASLE_INTERRUPT |
2818 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2819 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2820 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2821 I915_USER_INTERRUPT;
2822
a266c7d5 2823 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 2824 I915_WRITE(PORT_HOTPLUG_EN, 0);
2825 POSTING_READ(PORT_HOTPLUG_EN);
2826
a266c7d5
CW		 2827 /* Enable in IER... */
2828 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2829 /* and unmask in IMR */
2830 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2831 }
2832
a266c7d5
CW		 2833 I915_WRITE(IMR, dev_priv->irq_mask);
2834 I915_WRITE(IER, enable_mask);
2835 POSTING_READ(IER);
2836
f49e38dd 2837 i915_enable_asle_pipestat(dev);
20afbda2
DV		 2838
2839 return 0;
2840}
2841
90a72f87
VS		 2842/*
2843 * Returns true when a page flip has completed.
2844 */
2845static bool i915_handle_vblank(struct drm_device *dev,
2846 int plane, int pipe, u32 iir)
2847{
2848 drm_i915_private_t *dev_priv = dev->dev_private;
2849 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2850
2851 if (!drm_handle_vblank(dev, pipe))
2852 return false;
2853
2854 if ((iir & flip_pending) == 0)
2855 return false;
2856
2857 intel_prepare_page_flip(dev, plane);
2858
2859 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2860 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2861 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2862 * the flip is completed (no longer pending). Since this doesn't raise
2863 * an interrupt per se, we watch for the change at vblank.
2864 */
2865 if (I915_READ(ISR) & flip_pending)
2866 return false;
2867
2868 intel_finish_page_flip(dev, pipe);
2869
2870 return true;
2871}
2872
ff1f525e 2873static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2874{
2875 struct drm_device *dev = (struct drm_device *) arg;
2876 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2877 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2878 unsigned long irqflags;
38bde180
CW		 2879 u32 flip_mask =
2880 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2881 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 2882 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2883
2884 atomic_inc(&dev_priv->irq_received);
2885
2886 iir = I915_READ(IIR);
38bde180
CW		 2887 do {
2888 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2889 bool blc_event = false;
a266c7d5
CW		 2890
2891 /* Can't rely on pipestat interrupt bit in iir as it might
2892 * have been cleared after the pipestat interrupt was received.
2893 * It doesn't set the bit in iir again, but it still produces
2894 * interrupts (for non-MSI).
2895 */
2896 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2897 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2898 i915_handle_error(dev, false);
2899
2900 for_each_pipe(pipe) {
2901 int reg = PIPESTAT(pipe);
2902 pipe_stats[pipe] = I915_READ(reg);
2903
38bde180 2904 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2905 if (pipe_stats[pipe] & 0x8000ffff) {
2906 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2907 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2908 pipe_name(pipe));
2909 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2910 irq_received = true;
a266c7d5
CW		 2911 }
2912 }
2913 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2914
2915 if (!irq_received)
2916 break;
2917
a266c7d5
CW		 2918 /* Consume port. Then clear IIR or we'll miss events */
2919 if ((I915_HAS_HOTPLUG(dev)) &&
2920 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2921 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 2922 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 2923
2924 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2925 hotplug_status);
91d131d2
DV		 2926
2927 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
2928
a266c7d5 2929 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2930 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2931 }
2932
38bde180 2933 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2934 new_iir = I915_READ(IIR); /* Flush posted writes */
2935
a266c7d5
CW		 2936 if (iir & I915_USER_INTERRUPT)
2937 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2938
a266c7d5 2939 for_each_pipe(pipe) {
38bde180
CW		 2940 int plane = pipe;
2941 if (IS_MOBILE(dev))
2942 plane = !plane;
90a72f87 2943
8291ee90 2944 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2945 i915_handle_vblank(dev, plane, pipe, iir))
2946 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 2947
2948 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2949 blc_event = true;
2950 }
2951
a266c7d5
CW		 2952 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2953 intel_opregion_asle_intr(dev);
2954
2955 /* With MSI, interrupts are only generated when iir
2956 * transitions from zero to nonzero. If another bit got
2957 * set while we were handling the existing iir bits, then
2958 * we would never get another interrupt.
2959 *
2960 * This is fine on non-MSI as well, as if we hit this path
2961 * we avoid exiting the interrupt handler only to generate
2962 * another one.
2963 *
2964 * Note that for MSI this could cause a stray interrupt report
2965 * if an interrupt landed in the time between writing IIR and
2966 * the posting read. This should be rare enough to never
2967 * trigger the 99% of 100,000 interrupts test for disabling
2968 * stray interrupts.
2969 */
38bde180 2970 ret = IRQ_HANDLED;
a266c7d5 2971 iir = new_iir;
38bde180 2972 } while (iir & ~flip_mask);
a266c7d5 2973
d05c617e 2974 i915_update_dri1_breadcrumb(dev);
8291ee90 2975
a266c7d5
CW		 2976 return ret;
2977}
2978
2979static void i915_irq_uninstall(struct drm_device * dev)
2980{
2981 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2982 int pipe;
2983
ac4c16c5
EE		 2984 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2985
a266c7d5
CW		 2986 if (I915_HAS_HOTPLUG(dev)) {
2987 I915_WRITE(PORT_HOTPLUG_EN, 0);
2988 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2989 }
2990
00d98ebd 2991 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2992 for_each_pipe(pipe) {
2993 /* Clear enable bits; then clear status bits */
a266c7d5 2994 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2995 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2996 }
a266c7d5
CW		 2997 I915_WRITE(IMR, 0xffffffff);
2998 I915_WRITE(IER, 0x0);
2999
a266c7d5
CW		 3000 I915_WRITE(IIR, I915_READ(IIR));
3001}
3002
3003static void i965_irq_preinstall(struct drm_device * dev)
3004{
3005 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3006 int pipe;
3007
3008 atomic_set(&dev_priv->irq_received, 0);
3009
adca4730
CW		 3010 I915_WRITE(PORT_HOTPLUG_EN, 0);
3011 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3012
3013 I915_WRITE(HWSTAM, 0xeffe);
3014 for_each_pipe(pipe)
3015 I915_WRITE(PIPESTAT(pipe), 0);
3016 I915_WRITE(IMR, 0xffffffff);
3017 I915_WRITE(IER, 0x0);
3018 POSTING_READ(IER);
3019}
3020
3021static int i965_irq_postinstall(struct drm_device *dev)
3022{
3023 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 3024 u32 enable_mask;
a266c7d5 3025 u32 error_mask;
b79480ba 3026 unsigned long irqflags;
a266c7d5 3027
a266c7d5 3028 /* Unmask the interrupts that we always want on. */
bbba0a97 3029 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3030 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3031 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3032 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3033 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3034 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3035 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3036
3037 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3038 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3039 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3040 enable_mask |= I915_USER_INTERRUPT;
3041
3042 if (IS_G4X(dev))
3043 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3044
b79480ba
DV		 3045 /* Interrupt setup is already guaranteed to be single-threaded, this is
3046 * just to make the assert_spin_locked check happy. */
3047 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
515ac2bb 3048 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
b79480ba 3049 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 3050
a266c7d5
CW		 3051 /*
3052 * Enable some error detection, note the instruction error mask
3053 * bit is reserved, so we leave it masked.
3054 */
3055 if (IS_G4X(dev)) {
3056 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3057 GM45_ERROR_MEM_PRIV |
3058 GM45_ERROR_CP_PRIV |
3059 I915_ERROR_MEMORY_REFRESH);
3060 } else {
3061 error_mask = ~(I915_ERROR_PAGE_TABLE |
3062 I915_ERROR_MEMORY_REFRESH);
3063 }
3064 I915_WRITE(EMR, error_mask);
3065
3066 I915_WRITE(IMR, dev_priv->irq_mask);
3067 I915_WRITE(IER, enable_mask);
3068 POSTING_READ(IER);
3069
20afbda2
DV		 3070 I915_WRITE(PORT_HOTPLUG_EN, 0);
3071 POSTING_READ(PORT_HOTPLUG_EN);
3072
f49e38dd 3073 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3074
3075 return 0;
3076}
3077
bac56d5b 3078static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 3079{
3080 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 3081 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3082 struct intel_encoder *intel_encoder;
20afbda2
DV		 3083 u32 hotplug_en;
3084
b5ea2d56
DV		 3085 assert_spin_locked(&dev_priv->irq_lock);
3086
bac56d5b
EE		 3087 if (I915_HAS_HOTPLUG(dev)) {
3088 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3089 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3090 /* Note HDMI and DP share hotplug bits */
e5868a31 3091 /* enable bits are the same for all generations */
cd569aed
EE		 3092 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3093 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3094 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3095 /* Programming the CRT detection parameters tends
3096 to generate a spurious hotplug event about three
3097 seconds later. So just do it once.
3098 */
3099 if (IS_G4X(dev))
3100 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3101 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3102 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3103
bac56d5b
EE		 3104 /* Ignore TV since it's buggy */
3105 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3106 }
a266c7d5
CW		 3107}
3108
ff1f525e 3109static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3110{
3111 struct drm_device *dev = (struct drm_device *) arg;
3112 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 3113 u32 iir, new_iir;
3114 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 3115 unsigned long irqflags;
3116 int irq_received;
3117 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3118 u32 flip_mask =
3119 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3120 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 3121
3122 atomic_inc(&dev_priv->irq_received);
3123
3124 iir = I915_READ(IIR);
3125
a266c7d5 3126 for (;;) {
2c8ba29f
CW		 3127 bool blc_event = false;
3128
21ad8330 3129 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 3130
3131 /* Can't rely on pipestat interrupt bit in iir as it might
3132 * have been cleared after the pipestat interrupt was received.
3133 * It doesn't set the bit in iir again, but it still produces
3134 * interrupts (for non-MSI).
3135 */
3136 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3137 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3138 i915_handle_error(dev, false);
3139
3140 for_each_pipe(pipe) {
3141 int reg = PIPESTAT(pipe);
3142 pipe_stats[pipe] = I915_READ(reg);
3143
3144 /*
3145 * Clear the PIPE*STAT regs before the IIR
3146 */
3147 if (pipe_stats[pipe] & 0x8000ffff) {
3148 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3149 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3150 pipe_name(pipe));
3151 I915_WRITE(reg, pipe_stats[pipe]);
3152 irq_received = 1;
3153 }
3154 }
3155 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3156
3157 if (!irq_received)
3158 break;
3159
3160 ret = IRQ_HANDLED;
3161
3162 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3163 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3164 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3165 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3166 HOTPLUG_INT_STATUS_G4X :
4f7fd709 3167 HOTPLUG_INT_STATUS_I915);
a266c7d5
CW		 3168
3169 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3170 hotplug_status);
91d131d2
DV		 3171
3172 intel_hpd_irq_handler(dev, hotplug_trigger,
3173 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3174
a266c7d5
CW		 3175 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3176 I915_READ(PORT_HOTPLUG_STAT);
3177 }
3178
21ad8330 3179 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3180 new_iir = I915_READ(IIR); /* Flush posted writes */
3181
a266c7d5
CW		 3182 if (iir & I915_USER_INTERRUPT)
3183 notify_ring(dev, &dev_priv->ring[RCS]);
3184 if (iir & I915_BSD_USER_INTERRUPT)
3185 notify_ring(dev, &dev_priv->ring[VCS]);
3186
a266c7d5 3187 for_each_pipe(pipe) {
2c8ba29f 3188 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3189 i915_handle_vblank(dev, pipe, pipe, iir))
3190 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3191
3192 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3193 blc_event = true;
3194 }
3195
3196
3197 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3198 intel_opregion_asle_intr(dev);
3199
515ac2bb
DV		 3200 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3201 gmbus_irq_handler(dev);
3202
a266c7d5
CW		 3203 /* With MSI, interrupts are only generated when iir
3204 * transitions from zero to nonzero. If another bit got
3205 * set while we were handling the existing iir bits, then
3206 * we would never get another interrupt.
3207 *
3208 * This is fine on non-MSI as well, as if we hit this path
3209 * we avoid exiting the interrupt handler only to generate
3210 * another one.
3211 *
3212 * Note that for MSI this could cause a stray interrupt report
3213 * if an interrupt landed in the time between writing IIR and
3214 * the posting read. This should be rare enough to never
3215 * trigger the 99% of 100,000 interrupts test for disabling
3216 * stray interrupts.
3217 */
3218 iir = new_iir;
3219 }
3220
d05c617e 3221 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3222
a266c7d5
CW		 3223 return ret;
3224}
3225
3226static void i965_irq_uninstall(struct drm_device * dev)
3227{
3228 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3229 int pipe;
3230
3231 if (!dev_priv)
3232 return;
3233
ac4c16c5
EE		 3234 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3235
adca4730
CW		 3236 I915_WRITE(PORT_HOTPLUG_EN, 0);
3237 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3238
3239 I915_WRITE(HWSTAM, 0xffffffff);
3240 for_each_pipe(pipe)
3241 I915_WRITE(PIPESTAT(pipe), 0);
3242 I915_WRITE(IMR, 0xffffffff);
3243 I915_WRITE(IER, 0x0);
3244
3245 for_each_pipe(pipe)
3246 I915_WRITE(PIPESTAT(pipe),
3247 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3248 I915_WRITE(IIR, I915_READ(IIR));
3249}
3250
ac4c16c5
EE		 3251static void i915_reenable_hotplug_timer_func(unsigned long data)
3252{
3253 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3254 struct drm_device *dev = dev_priv->dev;
3255 struct drm_mode_config *mode_config = &dev->mode_config;
3256 unsigned long irqflags;
3257 int i;
3258
3259 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3260 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3261 struct drm_connector *connector;
3262
3263 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3264 continue;
3265
3266 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3267
3268 list_for_each_entry(connector, &mode_config->connector_list, head) {
3269 struct intel_connector *intel_connector = to_intel_connector(connector);
3270
3271 if (intel_connector->encoder->hpd_pin == i) {
3272 if (connector->polled != intel_connector->polled)
3273 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3274 drm_get_connector_name(connector));
3275 connector->polled = intel_connector->polled;
3276 if (!connector->polled)
3277 connector->polled = DRM_CONNECTOR_POLL_HPD;
3278 }
3279 }
3280 }
3281 if (dev_priv->display.hpd_irq_setup)
3282 dev_priv->display.hpd_irq_setup(dev);
3283 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3284}
3285
f71d4af4
JB		 3286void intel_irq_init(struct drm_device *dev)
3287{
8b2e326d
CW		 3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289
3290 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3291 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3292 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3293 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3294
99584db3
DV		 3295 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3296 i915_hangcheck_elapsed,
61bac78e 3297 (unsigned long) dev);
ac4c16c5
EE		 3298 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3299 (unsigned long) dev_priv);
61bac78e 3300
97a19a24 3301 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3302
4cdb83ec
VS		 3303 if (IS_GEN2(dev)) {
3304 dev->max_vblank_count = 0;
3305 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3306 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3307 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3308 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
391f75e2
VS		 3309 } else {
3310 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3311 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 3312 }
3313
c2baf4b7 3314 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
c3613de9 3315 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
c2baf4b7
VS		 3316 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3317 }
f71d4af4 3318
7e231dbe
JB		 3319 if (IS_VALLEYVIEW(dev)) {
3320 dev->driver->irq_handler = valleyview_irq_handler;
3321 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3322 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3323 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3324 dev->driver->enable_vblank = valleyview_enable_vblank;
3325 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3326 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
f71d4af4
JB		 3327 } else if (HAS_PCH_SPLIT(dev)) {
3328 dev->driver->irq_handler = ironlake_irq_handler;
3329 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3330 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3331 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3332 dev->driver->enable_vblank = ironlake_enable_vblank;
3333 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3334 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3335 } else {
c2798b19
CW		 3336 if (INTEL_INFO(dev)->gen == 2) {
3337 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3338 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3339 dev->driver->irq_handler = i8xx_irq_handler;
3340 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3341 } else if (INTEL_INFO(dev)->gen == 3) {
3342 dev->driver->irq_preinstall = i915_irq_preinstall;
3343 dev->driver->irq_postinstall = i915_irq_postinstall;
3344 dev->driver->irq_uninstall = i915_irq_uninstall;
3345 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3346 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3347 } else {
a266c7d5
CW		 3348 dev->driver->irq_preinstall = i965_irq_preinstall;
3349 dev->driver->irq_postinstall = i965_irq_postinstall;
3350 dev->driver->irq_uninstall = i965_irq_uninstall;
3351 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3352 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3353 }
f71d4af4
JB		 3354 dev->driver->enable_vblank = i915_enable_vblank;
3355 dev->driver->disable_vblank = i915_disable_vblank;
3356 }
3357}
20afbda2
DV		 3358
3359void intel_hpd_init(struct drm_device *dev)
3360{
3361 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3362 struct drm_mode_config *mode_config = &dev->mode_config;
3363 struct drm_connector *connector;
b5ea2d56 3364 unsigned long irqflags;
821450c6 3365 int i;
20afbda2 3366
821450c6
EE		 3367 for (i = 1; i < HPD_NUM_PINS; i++) {
3368 dev_priv->hpd_stats[i].hpd_cnt = 0;
3369 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3370 }
3371 list_for_each_entry(connector, &mode_config->connector_list, head) {
3372 struct intel_connector *intel_connector = to_intel_connector(connector);
3373 connector->polled = intel_connector->polled;
3374 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3375 connector->polled = DRM_CONNECTOR_POLL_HPD;
3376 }
b5ea2d56
DV		 3377
3378 /* Interrupt setup is already guaranteed to be single-threaded, this is
3379 * just to make the assert_spin_locked checks happy. */
3380 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3381 if (dev_priv->display.hpd_irq_setup)
3382 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3383 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3384}
c67a470b
PZ		 3385
3386/* Disable interrupts so we can allow Package C8+. */
3387void hsw_pc8_disable_interrupts(struct drm_device *dev)
3388{
3389 struct drm_i915_private *dev_priv = dev->dev_private;
3390 unsigned long irqflags;
3391
3392 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3393
3394 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3395 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3396 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3397 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3398 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3399
3400 ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB);
3401 ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT);
3402 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3403 snb_disable_pm_irq(dev_priv, 0xffffffff);
3404
3405 dev_priv->pc8.irqs_disabled = true;
3406
3407 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3408}
3409
3410/* Restore interrupts so we can recover from Package C8+. */
3411void hsw_pc8_restore_interrupts(struct drm_device *dev)
3412{
3413 struct drm_i915_private *dev_priv = dev->dev_private;
3414 unsigned long irqflags;
3415 uint32_t val, expected;
3416
3417 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3418
3419 val = I915_READ(DEIMR);
3420 expected = ~DE_PCH_EVENT_IVB;
3421 WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);
3422
3423 val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT;
3424 expected = ~SDE_HOTPLUG_MASK_CPT;
3425 WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3426 val, expected);
3427
3428 val = I915_READ(GTIMR);
3429 expected = 0xffffffff;
3430 WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);
3431
3432 val = I915_READ(GEN6_PMIMR);
3433 expected = 0xffffffff;
3434 WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
3435 expected);
3436
3437 dev_priv->pc8.irqs_disabled = false;
3438
3439 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3440 ibx_enable_display_interrupt(dev_priv,
3441 ~dev_priv->pc8.regsave.sdeimr &
3442 ~SDE_HOTPLUG_MASK_CPT);
3443 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3444 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3445 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3446
3447 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3448}
Linux kernel - Deliverables
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