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42f5551d CW |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
a09d0ba1 | 25 | #include <linux/console.h> |
42f5551d CW |
26 | #include <linux/vgaarb.h> |
27 | #include <linux/vga_switcheroo.h> | |
28 | ||
29 | #include "i915_drv.h" | |
30 | ||
31 | #define GEN_DEFAULT_PIPEOFFSETS \ | |
32 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
33 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
34 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
35 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
36 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } | |
37 | ||
38 | #define GEN_CHV_PIPEOFFSETS \ | |
39 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
40 | CHV_PIPE_C_OFFSET }, \ | |
41 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
42 | CHV_TRANSCODER_C_OFFSET, }, \ | |
43 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ | |
44 | CHV_PALETTE_C_OFFSET } | |
45 | ||
46 | #define CURSOR_OFFSETS \ | |
47 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
48 | ||
49 | #define IVB_CURSOR_OFFSETS \ | |
50 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
51 | ||
52 | #define BDW_COLORS \ | |
53 | .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } | |
54 | #define CHV_COLORS \ | |
55 | .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } | |
56 | ||
0eec8dc7 CS |
57 | #define GEN2_FEATURES \ |
58 | .gen = 2, .num_pipes = 1, \ | |
59 | .has_overlay = 1, .overlay_needs_physical = 1, \ | |
804b8712 | 60 | .has_gmch_display = 1, \ |
3177659a | 61 | .hws_needs_physical = 1, \ |
0eec8dc7 CS |
62 | .ring_mask = RENDER_RING, \ |
63 | GEN_DEFAULT_PIPEOFFSETS, \ | |
64 | CURSOR_OFFSETS | |
65 | ||
42f5551d | 66 | static const struct intel_device_info intel_i830_info = { |
0eec8dc7 CS |
67 | GEN2_FEATURES, |
68 | .is_mobile = 1, .cursor_needs_physical = 1, | |
69 | .num_pipes = 2, /* legal, last one wins */ | |
42f5551d CW |
70 | }; |
71 | ||
72 | static const struct intel_device_info intel_845g_info = { | |
0eec8dc7 | 73 | GEN2_FEATURES, |
42f5551d CW |
74 | }; |
75 | ||
76 | static const struct intel_device_info intel_i85x_info = { | |
0eec8dc7 CS |
77 | GEN2_FEATURES, |
78 | .is_i85x = 1, .is_mobile = 1, | |
79 | .num_pipes = 2, /* legal, last one wins */ | |
42f5551d | 80 | .cursor_needs_physical = 1, |
42f5551d | 81 | .has_fbc = 1, |
42f5551d CW |
82 | }; |
83 | ||
84 | static const struct intel_device_info intel_i865g_info = { | |
0eec8dc7 | 85 | GEN2_FEATURES, |
42f5551d CW |
86 | }; |
87 | ||
54d2a6a1 CS |
88 | #define GEN3_FEATURES \ |
89 | .gen = 3, .num_pipes = 2, \ | |
804b8712 | 90 | .has_gmch_display = 1, \ |
54d2a6a1 CS |
91 | .ring_mask = RENDER_RING, \ |
92 | GEN_DEFAULT_PIPEOFFSETS, \ | |
93 | CURSOR_OFFSETS | |
94 | ||
42f5551d | 95 | static const struct intel_device_info intel_i915g_info = { |
54d2a6a1 CS |
96 | GEN3_FEATURES, |
97 | .is_i915g = 1, .cursor_needs_physical = 1, | |
42f5551d | 98 | .has_overlay = 1, .overlay_needs_physical = 1, |
3177659a | 99 | .hws_needs_physical = 1, |
42f5551d CW |
100 | }; |
101 | static const struct intel_device_info intel_i915gm_info = { | |
54d2a6a1 CS |
102 | GEN3_FEATURES, |
103 | .is_mobile = 1, | |
42f5551d CW |
104 | .cursor_needs_physical = 1, |
105 | .has_overlay = 1, .overlay_needs_physical = 1, | |
106 | .supports_tv = 1, | |
107 | .has_fbc = 1, | |
3177659a | 108 | .hws_needs_physical = 1, |
42f5551d CW |
109 | }; |
110 | static const struct intel_device_info intel_i945g_info = { | |
54d2a6a1 CS |
111 | GEN3_FEATURES, |
112 | .has_hotplug = 1, .cursor_needs_physical = 1, | |
42f5551d | 113 | .has_overlay = 1, .overlay_needs_physical = 1, |
3177659a | 114 | .hws_needs_physical = 1, |
42f5551d CW |
115 | }; |
116 | static const struct intel_device_info intel_i945gm_info = { | |
54d2a6a1 CS |
117 | GEN3_FEATURES, |
118 | .is_i945gm = 1, .is_mobile = 1, | |
42f5551d CW |
119 | .has_hotplug = 1, .cursor_needs_physical = 1, |
120 | .has_overlay = 1, .overlay_needs_physical = 1, | |
121 | .supports_tv = 1, | |
122 | .has_fbc = 1, | |
3177659a | 123 | .hws_needs_physical = 1, |
42f5551d CW |
124 | }; |
125 | ||
4d495bea CS |
126 | #define GEN4_FEATURES \ |
127 | .gen = 4, .num_pipes = 2, \ | |
128 | .has_hotplug = 1, \ | |
804b8712 | 129 | .has_gmch_display = 1, \ |
4d495bea CS |
130 | .ring_mask = RENDER_RING, \ |
131 | GEN_DEFAULT_PIPEOFFSETS, \ | |
132 | CURSOR_OFFSETS | |
133 | ||
42f5551d | 134 | static const struct intel_device_info intel_i965g_info = { |
4d495bea CS |
135 | GEN4_FEATURES, |
136 | .is_broadwater = 1, | |
42f5551d | 137 | .has_overlay = 1, |
3177659a | 138 | .hws_needs_physical = 1, |
42f5551d CW |
139 | }; |
140 | ||
141 | static const struct intel_device_info intel_i965gm_info = { | |
4d495bea CS |
142 | GEN4_FEATURES, |
143 | .is_crestline = 1, | |
144 | .is_mobile = 1, .has_fbc = 1, | |
42f5551d CW |
145 | .has_overlay = 1, |
146 | .supports_tv = 1, | |
3177659a | 147 | .hws_needs_physical = 1, |
42f5551d CW |
148 | }; |
149 | ||
150 | static const struct intel_device_info intel_g33_info = { | |
54d2a6a1 CS |
151 | GEN3_FEATURES, |
152 | .is_g33 = 1, | |
3177659a | 153 | .has_hotplug = 1, |
42f5551d | 154 | .has_overlay = 1, |
42f5551d CW |
155 | }; |
156 | ||
157 | static const struct intel_device_info intel_g45_info = { | |
4d495bea | 158 | GEN4_FEATURES, |
3177659a | 159 | .is_g4x = 1, |
4d495bea | 160 | .has_pipe_cxsr = 1, |
42f5551d | 161 | .ring_mask = RENDER_RING | BSD_RING, |
42f5551d CW |
162 | }; |
163 | ||
164 | static const struct intel_device_info intel_gm45_info = { | |
4d495bea CS |
165 | GEN4_FEATURES, |
166 | .is_g4x = 1, | |
3177659a | 167 | .is_mobile = 1, .has_fbc = 1, |
4d495bea | 168 | .has_pipe_cxsr = 1, |
42f5551d CW |
169 | .supports_tv = 1, |
170 | .ring_mask = RENDER_RING | BSD_RING, | |
42f5551d CW |
171 | }; |
172 | ||
173 | static const struct intel_device_info intel_pineview_info = { | |
54d2a6a1 CS |
174 | GEN3_FEATURES, |
175 | .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, | |
3177659a | 176 | .has_hotplug = 1, |
42f5551d | 177 | .has_overlay = 1, |
42f5551d CW |
178 | }; |
179 | ||
a1323380 CS |
180 | #define GEN5_FEATURES \ |
181 | .gen = 5, .num_pipes = 2, \ | |
3177659a | 182 | .has_hotplug = 1, \ |
b355f109 | 183 | .has_gmbus_irq = 1, \ |
a1323380 CS |
184 | .ring_mask = RENDER_RING | BSD_RING, \ |
185 | GEN_DEFAULT_PIPEOFFSETS, \ | |
186 | CURSOR_OFFSETS | |
187 | ||
42f5551d | 188 | static const struct intel_device_info intel_ironlake_d_info = { |
a1323380 | 189 | GEN5_FEATURES, |
42f5551d CW |
190 | }; |
191 | ||
192 | static const struct intel_device_info intel_ironlake_m_info = { | |
a1323380 CS |
193 | GEN5_FEATURES, |
194 | .is_mobile = 1, | |
42f5551d CW |
195 | }; |
196 | ||
07db6be7 CS |
197 | #define GEN6_FEATURES \ |
198 | .gen = 6, .num_pipes = 2, \ | |
3177659a | 199 | .has_hotplug = 1, \ |
07db6be7 CS |
200 | .has_fbc = 1, \ |
201 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
202 | .has_llc = 1, \ | |
86f3624b | 203 | .has_rc6 = 1, \ |
33b5bf82 | 204 | .has_rc6p = 1, \ |
b355f109 | 205 | .has_gmbus_irq = 1, \ |
e1a52536 | 206 | .has_hw_contexts = 1, \ |
07db6be7 CS |
207 | GEN_DEFAULT_PIPEOFFSETS, \ |
208 | CURSOR_OFFSETS | |
209 | ||
42f5551d | 210 | static const struct intel_device_info intel_sandybridge_d_info = { |
07db6be7 | 211 | GEN6_FEATURES, |
42f5551d CW |
212 | }; |
213 | ||
214 | static const struct intel_device_info intel_sandybridge_m_info = { | |
07db6be7 CS |
215 | GEN6_FEATURES, |
216 | .is_mobile = 1, | |
42f5551d CW |
217 | }; |
218 | ||
219 | #define GEN7_FEATURES \ | |
220 | .gen = 7, .num_pipes = 3, \ | |
3177659a | 221 | .has_hotplug = 1, \ |
42f5551d CW |
222 | .has_fbc = 1, \ |
223 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
224 | .has_llc = 1, \ | |
86f3624b | 225 | .has_rc6 = 1, \ |
33b5bf82 | 226 | .has_rc6p = 1, \ |
b355f109 | 227 | .has_gmbus_irq = 1, \ |
e1a52536 | 228 | .has_hw_contexts = 1, \ |
42f5551d CW |
229 | GEN_DEFAULT_PIPEOFFSETS, \ |
230 | IVB_CURSOR_OFFSETS | |
231 | ||
232 | static const struct intel_device_info intel_ivybridge_d_info = { | |
233 | GEN7_FEATURES, | |
234 | .is_ivybridge = 1, | |
ca9c4523 | 235 | .has_l3_dpf = 1, |
42f5551d CW |
236 | }; |
237 | ||
238 | static const struct intel_device_info intel_ivybridge_m_info = { | |
239 | GEN7_FEATURES, | |
240 | .is_ivybridge = 1, | |
241 | .is_mobile = 1, | |
ca9c4523 | 242 | .has_l3_dpf = 1, |
42f5551d CW |
243 | }; |
244 | ||
245 | static const struct intel_device_info intel_ivybridge_q_info = { | |
246 | GEN7_FEATURES, | |
247 | .is_ivybridge = 1, | |
248 | .num_pipes = 0, /* legal, last one wins */ | |
ca9c4523 | 249 | .has_l3_dpf = 1, |
42f5551d CW |
250 | }; |
251 | ||
252 | #define VLV_FEATURES \ | |
253 | .gen = 7, .num_pipes = 2, \ | |
6e3b84d8 | 254 | .has_psr = 1, \ |
4aa4c23f | 255 | .has_runtime_pm = 1, \ |
86f3624b | 256 | .has_rc6 = 1, \ |
b355f109 | 257 | .has_gmbus_irq = 1, \ |
e1a52536 | 258 | .has_hw_contexts = 1, \ |
804b8712 | 259 | .has_gmch_display = 1, \ |
3177659a | 260 | .has_hotplug = 1, \ |
42f5551d CW |
261 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
262 | .display_mmio_offset = VLV_DISPLAY_BASE, \ | |
263 | GEN_DEFAULT_PIPEOFFSETS, \ | |
264 | CURSOR_OFFSETS | |
265 | ||
8d9c20e1 | 266 | static const struct intel_device_info intel_valleyview_info = { |
42f5551d CW |
267 | VLV_FEATURES, |
268 | .is_valleyview = 1, | |
269 | }; | |
270 | ||
271 | #define HSW_FEATURES \ | |
272 | GEN7_FEATURES, \ | |
273 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
274 | .has_ddi = 1, \ | |
6e3b84d8 | 275 | .has_fpga_dbg = 1, \ |
4aa4c23f | 276 | .has_psr = 1, \ |
53233f08 | 277 | .has_resource_streamer = 1, \ |
1d3fe53b | 278 | .has_dp_mst = 1, \ |
33b5bf82 | 279 | .has_rc6p = 0 /* RC6p removed-by HSW */, \ |
4aa4c23f | 280 | .has_runtime_pm = 1 |
42f5551d | 281 | |
8d9c20e1 | 282 | static const struct intel_device_info intel_haswell_info = { |
42f5551d CW |
283 | HSW_FEATURES, |
284 | .is_haswell = 1, | |
ca9c4523 | 285 | .has_l3_dpf = 1, |
42f5551d CW |
286 | }; |
287 | ||
42f5551d CW |
288 | #define BDW_FEATURES \ |
289 | HSW_FEATURES, \ | |
4586f1d0 CS |
290 | BDW_COLORS, \ |
291 | .has_logical_ring_contexts = 1 | |
42f5551d | 292 | |
8d9c20e1 | 293 | static const struct intel_device_info intel_broadwell_info = { |
42f5551d CW |
294 | BDW_FEATURES, |
295 | .gen = 8, | |
296 | .is_broadwell = 1, | |
297 | }; | |
298 | ||
8d9c20e1 | 299 | static const struct intel_device_info intel_broadwell_gt3_info = { |
42f5551d CW |
300 | BDW_FEATURES, |
301 | .gen = 8, | |
302 | .is_broadwell = 1, | |
303 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, | |
304 | }; | |
305 | ||
42f5551d CW |
306 | static const struct intel_device_info intel_cherryview_info = { |
307 | .gen = 8, .num_pipes = 3, | |
3177659a | 308 | .has_hotplug = 1, |
42f5551d CW |
309 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
310 | .is_cherryview = 1, | |
6e3b84d8 | 311 | .has_psr = 1, |
4aa4c23f | 312 | .has_runtime_pm = 1, |
53233f08 | 313 | .has_resource_streamer = 1, |
86f3624b | 314 | .has_rc6 = 1, |
b355f109 | 315 | .has_gmbus_irq = 1, |
e1a52536 | 316 | .has_hw_contexts = 1, |
4586f1d0 | 317 | .has_logical_ring_contexts = 1, |
804b8712 | 318 | .has_gmch_display = 1, |
42f5551d CW |
319 | .display_mmio_offset = VLV_DISPLAY_BASE, |
320 | GEN_CHV_PIPEOFFSETS, | |
321 | CURSOR_OFFSETS, | |
322 | CHV_COLORS, | |
323 | }; | |
324 | ||
325 | static const struct intel_device_info intel_skylake_info = { | |
326 | BDW_FEATURES, | |
327 | .is_skylake = 1, | |
328 | .gen = 9, | |
3bacde19 | 329 | .has_csr = 1, |
3d810fbe | 330 | .has_guc = 1, |
42f5551d CW |
331 | }; |
332 | ||
333 | static const struct intel_device_info intel_skylake_gt3_info = { | |
334 | BDW_FEATURES, | |
335 | .is_skylake = 1, | |
336 | .gen = 9, | |
3bacde19 | 337 | .has_csr = 1, |
3d810fbe | 338 | .has_guc = 1, |
42f5551d CW |
339 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
340 | }; | |
341 | ||
342 | static const struct intel_device_info intel_broxton_info = { | |
42f5551d CW |
343 | .is_broxton = 1, |
344 | .gen = 9, | |
3177659a | 345 | .has_hotplug = 1, |
42f5551d CW |
346 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
347 | .num_pipes = 3, | |
348 | .has_ddi = 1, | |
349 | .has_fpga_dbg = 1, | |
350 | .has_fbc = 1, | |
4aa4c23f | 351 | .has_runtime_pm = 1, |
42f5551d | 352 | .has_pooled_eu = 0, |
3bacde19 | 353 | .has_csr = 1, |
53233f08 | 354 | .has_resource_streamer = 1, |
86f3624b | 355 | .has_rc6 = 1, |
1d3fe53b | 356 | .has_dp_mst = 1, |
b355f109 | 357 | .has_gmbus_irq = 1, |
e1a52536 | 358 | .has_hw_contexts = 1, |
4586f1d0 | 359 | .has_logical_ring_contexts = 1, |
3d810fbe | 360 | .has_guc = 1, |
42f5551d CW |
361 | GEN_DEFAULT_PIPEOFFSETS, |
362 | IVB_CURSOR_OFFSETS, | |
363 | BDW_COLORS, | |
364 | }; | |
365 | ||
366 | static const struct intel_device_info intel_kabylake_info = { | |
367 | BDW_FEATURES, | |
368 | .is_kabylake = 1, | |
369 | .gen = 9, | |
3bacde19 | 370 | .has_csr = 1, |
3d810fbe | 371 | .has_guc = 1, |
42f5551d CW |
372 | }; |
373 | ||
374 | static const struct intel_device_info intel_kabylake_gt3_info = { | |
375 | BDW_FEATURES, | |
376 | .is_kabylake = 1, | |
377 | .gen = 9, | |
3bacde19 | 378 | .has_csr = 1, |
3d810fbe | 379 | .has_guc = 1, |
42f5551d CW |
380 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
381 | }; | |
382 | ||
383 | /* | |
384 | * Make sure any device matches here are from most specific to most | |
385 | * general. For example, since the Quanta match is based on the subsystem | |
386 | * and subvendor IDs, we need it to come before the more general IVB | |
387 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
388 | */ | |
389 | static const struct pci_device_id pciidlist[] = { | |
390 | INTEL_I830_IDS(&intel_i830_info), | |
391 | INTEL_I845G_IDS(&intel_845g_info), | |
392 | INTEL_I85X_IDS(&intel_i85x_info), | |
393 | INTEL_I865G_IDS(&intel_i865g_info), | |
394 | INTEL_I915G_IDS(&intel_i915g_info), | |
395 | INTEL_I915GM_IDS(&intel_i915gm_info), | |
396 | INTEL_I945G_IDS(&intel_i945g_info), | |
397 | INTEL_I945GM_IDS(&intel_i945gm_info), | |
398 | INTEL_I965G_IDS(&intel_i965g_info), | |
399 | INTEL_G33_IDS(&intel_g33_info), | |
400 | INTEL_I965GM_IDS(&intel_i965gm_info), | |
401 | INTEL_GM45_IDS(&intel_gm45_info), | |
402 | INTEL_G45_IDS(&intel_g45_info), | |
403 | INTEL_PINEVIEW_IDS(&intel_pineview_info), | |
404 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), | |
405 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), | |
406 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), | |
407 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), | |
408 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ | |
409 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), | |
410 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), | |
8d9c20e1 CS |
411 | INTEL_HSW_IDS(&intel_haswell_info), |
412 | INTEL_VLV_IDS(&intel_valleyview_info), | |
413 | INTEL_BDW_GT12_IDS(&intel_broadwell_info), | |
414 | INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), | |
42f5551d CW |
415 | INTEL_CHV_IDS(&intel_cherryview_info), |
416 | INTEL_SKL_GT1_IDS(&intel_skylake_info), | |
417 | INTEL_SKL_GT2_IDS(&intel_skylake_info), | |
418 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), | |
419 | INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), | |
420 | INTEL_BXT_IDS(&intel_broxton_info), | |
421 | INTEL_KBL_GT1_IDS(&intel_kabylake_info), | |
422 | INTEL_KBL_GT2_IDS(&intel_kabylake_info), | |
423 | INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), | |
424 | INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), | |
425 | {0, 0, 0} | |
426 | }; | |
427 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
428 | ||
429 | extern int i915_driver_load(struct pci_dev *pdev, | |
430 | const struct pci_device_id *ent); | |
431 | ||
432 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
433 | { | |
434 | struct intel_device_info *intel_info = | |
435 | (struct intel_device_info *) ent->driver_data; | |
436 | ||
437 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { | |
438 | DRM_INFO("This hardware requires preliminary hardware support.\n" | |
439 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
440 | return -ENODEV; | |
441 | } | |
442 | ||
443 | /* Only bind to function 0 of the device. Early generations | |
444 | * used function 1 as a placeholder for multi-head. This causes | |
445 | * us confusion instead, especially on the systems where both | |
446 | * functions have the same PCI-ID! | |
447 | */ | |
448 | if (PCI_FUNC(pdev->devfn)) | |
449 | return -ENODEV; | |
450 | ||
451 | /* | |
452 | * apple-gmux is needed on dual GPU MacBook Pro | |
453 | * to probe the panel if we're the inactive GPU. | |
454 | */ | |
455 | if (vga_switcheroo_client_probe_defer(pdev)) | |
456 | return -EPROBE_DEFER; | |
457 | ||
458 | return i915_driver_load(pdev, ent); | |
459 | } | |
460 | ||
461 | extern void i915_driver_unload(struct drm_device *dev); | |
462 | ||
463 | static void i915_pci_remove(struct pci_dev *pdev) | |
464 | { | |
465 | struct drm_device *dev = pci_get_drvdata(pdev); | |
466 | ||
467 | i915_driver_unload(dev); | |
468 | drm_dev_unref(dev); | |
469 | } | |
470 | ||
471 | extern const struct dev_pm_ops i915_pm_ops; | |
472 | ||
a09d0ba1 | 473 | static struct pci_driver i915_pci_driver = { |
42f5551d CW |
474 | .name = DRIVER_NAME, |
475 | .id_table = pciidlist, | |
476 | .probe = i915_pci_probe, | |
477 | .remove = i915_pci_remove, | |
478 | .driver.pm = &i915_pm_ops, | |
479 | }; | |
a09d0ba1 CW |
480 | |
481 | static int __init i915_init(void) | |
482 | { | |
483 | bool use_kms = true; | |
484 | ||
485 | /* | |
486 | * Enable KMS by default, unless explicitly overriden by | |
487 | * either the i915.modeset prarameter or by the | |
488 | * vga_text_mode_force boot option. | |
489 | */ | |
490 | ||
491 | if (i915.modeset == 0) | |
492 | use_kms = false; | |
493 | ||
494 | if (vgacon_text_force() && i915.modeset == -1) | |
495 | use_kms = false; | |
496 | ||
497 | if (!use_kms) { | |
498 | /* Silently fail loading to not upset userspace. */ | |
499 | DRM_DEBUG_DRIVER("KMS disabled.\n"); | |
500 | return 0; | |
501 | } | |
502 | ||
503 | return pci_register_driver(&i915_pci_driver); | |
504 | } | |
505 | ||
506 | static void __exit i915_exit(void) | |
507 | { | |
508 | if (!i915_pci_driver.driver.owner) | |
509 | return; | |
510 | ||
511 | pci_unregister_driver(&i915_pci_driver); | |
512 | } | |
513 | ||
514 | module_init(i915_init); | |
515 | module_exit(i915_exit); | |
516 | ||
517 | MODULE_AUTHOR("Tungsten Graphics, Inc."); | |
518 | MODULE_AUTHOR("Intel Corporation"); | |
519 | ||
520 | MODULE_DESCRIPTION(DRIVER_DESC); | |
521 | MODULE_LICENSE("GPL and additional rights"); |