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42f5551d CW |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
a09d0ba1 | 25 | #include <linux/console.h> |
42f5551d CW |
26 | #include <linux/vgaarb.h> |
27 | #include <linux/vga_switcheroo.h> | |
28 | ||
29 | #include "i915_drv.h" | |
30 | ||
31 | #define GEN_DEFAULT_PIPEOFFSETS \ | |
32 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
33 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
34 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
35 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
36 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } | |
37 | ||
38 | #define GEN_CHV_PIPEOFFSETS \ | |
39 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
40 | CHV_PIPE_C_OFFSET }, \ | |
41 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
42 | CHV_TRANSCODER_C_OFFSET, }, \ | |
43 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ | |
44 | CHV_PALETTE_C_OFFSET } | |
45 | ||
46 | #define CURSOR_OFFSETS \ | |
47 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
48 | ||
49 | #define IVB_CURSOR_OFFSETS \ | |
50 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
51 | ||
52 | #define BDW_COLORS \ | |
53 | .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } | |
54 | #define CHV_COLORS \ | |
55 | .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } | |
56 | ||
57 | static const struct intel_device_info intel_i830_info = { | |
58 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, | |
59 | .has_overlay = 1, .overlay_needs_physical = 1, | |
60 | .ring_mask = RENDER_RING, | |
61 | GEN_DEFAULT_PIPEOFFSETS, | |
62 | CURSOR_OFFSETS, | |
63 | }; | |
64 | ||
65 | static const struct intel_device_info intel_845g_info = { | |
66 | .gen = 2, .num_pipes = 1, | |
67 | .has_overlay = 1, .overlay_needs_physical = 1, | |
68 | .ring_mask = RENDER_RING, | |
69 | GEN_DEFAULT_PIPEOFFSETS, | |
70 | CURSOR_OFFSETS, | |
71 | }; | |
72 | ||
73 | static const struct intel_device_info intel_i85x_info = { | |
74 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, | |
75 | .cursor_needs_physical = 1, | |
76 | .has_overlay = 1, .overlay_needs_physical = 1, | |
77 | .has_fbc = 1, | |
78 | .ring_mask = RENDER_RING, | |
79 | GEN_DEFAULT_PIPEOFFSETS, | |
80 | CURSOR_OFFSETS, | |
81 | }; | |
82 | ||
83 | static const struct intel_device_info intel_i865g_info = { | |
84 | .gen = 2, .num_pipes = 1, | |
85 | .has_overlay = 1, .overlay_needs_physical = 1, | |
86 | .ring_mask = RENDER_RING, | |
87 | GEN_DEFAULT_PIPEOFFSETS, | |
88 | CURSOR_OFFSETS, | |
89 | }; | |
90 | ||
91 | static const struct intel_device_info intel_i915g_info = { | |
92 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, | |
93 | .has_overlay = 1, .overlay_needs_physical = 1, | |
94 | .ring_mask = RENDER_RING, | |
95 | GEN_DEFAULT_PIPEOFFSETS, | |
96 | CURSOR_OFFSETS, | |
97 | }; | |
98 | static const struct intel_device_info intel_i915gm_info = { | |
99 | .gen = 3, .is_mobile = 1, .num_pipes = 2, | |
100 | .cursor_needs_physical = 1, | |
101 | .has_overlay = 1, .overlay_needs_physical = 1, | |
102 | .supports_tv = 1, | |
103 | .has_fbc = 1, | |
104 | .ring_mask = RENDER_RING, | |
105 | GEN_DEFAULT_PIPEOFFSETS, | |
106 | CURSOR_OFFSETS, | |
107 | }; | |
108 | static const struct intel_device_info intel_i945g_info = { | |
109 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, | |
110 | .has_overlay = 1, .overlay_needs_physical = 1, | |
111 | .ring_mask = RENDER_RING, | |
112 | GEN_DEFAULT_PIPEOFFSETS, | |
113 | CURSOR_OFFSETS, | |
114 | }; | |
115 | static const struct intel_device_info intel_i945gm_info = { | |
116 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, | |
117 | .has_hotplug = 1, .cursor_needs_physical = 1, | |
118 | .has_overlay = 1, .overlay_needs_physical = 1, | |
119 | .supports_tv = 1, | |
120 | .has_fbc = 1, | |
121 | .ring_mask = RENDER_RING, | |
122 | GEN_DEFAULT_PIPEOFFSETS, | |
123 | CURSOR_OFFSETS, | |
124 | }; | |
125 | ||
126 | static const struct intel_device_info intel_i965g_info = { | |
127 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, | |
128 | .has_hotplug = 1, | |
129 | .has_overlay = 1, | |
130 | .ring_mask = RENDER_RING, | |
131 | GEN_DEFAULT_PIPEOFFSETS, | |
132 | CURSOR_OFFSETS, | |
133 | }; | |
134 | ||
135 | static const struct intel_device_info intel_i965gm_info = { | |
136 | .gen = 4, .is_crestline = 1, .num_pipes = 2, | |
137 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, | |
138 | .has_overlay = 1, | |
139 | .supports_tv = 1, | |
140 | .ring_mask = RENDER_RING, | |
141 | GEN_DEFAULT_PIPEOFFSETS, | |
142 | CURSOR_OFFSETS, | |
143 | }; | |
144 | ||
145 | static const struct intel_device_info intel_g33_info = { | |
146 | .gen = 3, .is_g33 = 1, .num_pipes = 2, | |
147 | .need_gfx_hws = 1, .has_hotplug = 1, | |
148 | .has_overlay = 1, | |
149 | .ring_mask = RENDER_RING, | |
150 | GEN_DEFAULT_PIPEOFFSETS, | |
151 | CURSOR_OFFSETS, | |
152 | }; | |
153 | ||
154 | static const struct intel_device_info intel_g45_info = { | |
155 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, | |
156 | .has_pipe_cxsr = 1, .has_hotplug = 1, | |
157 | .ring_mask = RENDER_RING | BSD_RING, | |
158 | GEN_DEFAULT_PIPEOFFSETS, | |
159 | CURSOR_OFFSETS, | |
160 | }; | |
161 | ||
162 | static const struct intel_device_info intel_gm45_info = { | |
163 | .gen = 4, .is_g4x = 1, .num_pipes = 2, | |
164 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, | |
165 | .has_pipe_cxsr = 1, .has_hotplug = 1, | |
166 | .supports_tv = 1, | |
167 | .ring_mask = RENDER_RING | BSD_RING, | |
168 | GEN_DEFAULT_PIPEOFFSETS, | |
169 | CURSOR_OFFSETS, | |
170 | }; | |
171 | ||
172 | static const struct intel_device_info intel_pineview_info = { | |
173 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, | |
174 | .need_gfx_hws = 1, .has_hotplug = 1, | |
175 | .has_overlay = 1, | |
6ce21357 | 176 | .ring_mask = RENDER_RING, |
42f5551d CW |
177 | GEN_DEFAULT_PIPEOFFSETS, |
178 | CURSOR_OFFSETS, | |
179 | }; | |
180 | ||
181 | static const struct intel_device_info intel_ironlake_d_info = { | |
182 | .gen = 5, .num_pipes = 2, | |
183 | .need_gfx_hws = 1, .has_hotplug = 1, | |
184 | .ring_mask = RENDER_RING | BSD_RING, | |
185 | GEN_DEFAULT_PIPEOFFSETS, | |
186 | CURSOR_OFFSETS, | |
187 | }; | |
188 | ||
189 | static const struct intel_device_info intel_ironlake_m_info = { | |
190 | .gen = 5, .is_mobile = 1, .num_pipes = 2, | |
191 | .need_gfx_hws = 1, .has_hotplug = 1, | |
192 | .has_fbc = 1, | |
193 | .ring_mask = RENDER_RING | BSD_RING, | |
194 | GEN_DEFAULT_PIPEOFFSETS, | |
195 | CURSOR_OFFSETS, | |
196 | }; | |
197 | ||
198 | static const struct intel_device_info intel_sandybridge_d_info = { | |
199 | .gen = 6, .num_pipes = 2, | |
200 | .need_gfx_hws = 1, .has_hotplug = 1, | |
201 | .has_fbc = 1, | |
202 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, | |
203 | .has_llc = 1, | |
204 | GEN_DEFAULT_PIPEOFFSETS, | |
205 | CURSOR_OFFSETS, | |
206 | }; | |
207 | ||
208 | static const struct intel_device_info intel_sandybridge_m_info = { | |
209 | .gen = 6, .is_mobile = 1, .num_pipes = 2, | |
210 | .need_gfx_hws = 1, .has_hotplug = 1, | |
211 | .has_fbc = 1, | |
212 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, | |
213 | .has_llc = 1, | |
214 | GEN_DEFAULT_PIPEOFFSETS, | |
215 | CURSOR_OFFSETS, | |
216 | }; | |
217 | ||
218 | #define GEN7_FEATURES \ | |
219 | .gen = 7, .num_pipes = 3, \ | |
220 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
221 | .has_fbc = 1, \ | |
222 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
223 | .has_llc = 1, \ | |
224 | GEN_DEFAULT_PIPEOFFSETS, \ | |
225 | IVB_CURSOR_OFFSETS | |
226 | ||
227 | static const struct intel_device_info intel_ivybridge_d_info = { | |
228 | GEN7_FEATURES, | |
229 | .is_ivybridge = 1, | |
230 | }; | |
231 | ||
232 | static const struct intel_device_info intel_ivybridge_m_info = { | |
233 | GEN7_FEATURES, | |
234 | .is_ivybridge = 1, | |
235 | .is_mobile = 1, | |
236 | }; | |
237 | ||
238 | static const struct intel_device_info intel_ivybridge_q_info = { | |
239 | GEN7_FEATURES, | |
240 | .is_ivybridge = 1, | |
241 | .num_pipes = 0, /* legal, last one wins */ | |
242 | }; | |
243 | ||
244 | #define VLV_FEATURES \ | |
245 | .gen = 7, .num_pipes = 2, \ | |
6e3b84d8 | 246 | .has_psr = 1, \ |
42f5551d CW |
247 | .need_gfx_hws = 1, .has_hotplug = 1, \ |
248 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
249 | .display_mmio_offset = VLV_DISPLAY_BASE, \ | |
250 | GEN_DEFAULT_PIPEOFFSETS, \ | |
251 | CURSOR_OFFSETS | |
252 | ||
8d9c20e1 | 253 | static const struct intel_device_info intel_valleyview_info = { |
42f5551d CW |
254 | VLV_FEATURES, |
255 | .is_valleyview = 1, | |
256 | }; | |
257 | ||
258 | #define HSW_FEATURES \ | |
259 | GEN7_FEATURES, \ | |
260 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
261 | .has_ddi = 1, \ | |
6e3b84d8 CS |
262 | .has_fpga_dbg = 1, \ |
263 | .has_psr = 1 | |
42f5551d | 264 | |
8d9c20e1 | 265 | static const struct intel_device_info intel_haswell_info = { |
42f5551d CW |
266 | HSW_FEATURES, |
267 | .is_haswell = 1, | |
268 | }; | |
269 | ||
42f5551d CW |
270 | #define BDW_FEATURES \ |
271 | HSW_FEATURES, \ | |
272 | BDW_COLORS | |
273 | ||
8d9c20e1 | 274 | static const struct intel_device_info intel_broadwell_info = { |
42f5551d CW |
275 | BDW_FEATURES, |
276 | .gen = 8, | |
277 | .is_broadwell = 1, | |
278 | }; | |
279 | ||
8d9c20e1 | 280 | static const struct intel_device_info intel_broadwell_gt3_info = { |
42f5551d CW |
281 | BDW_FEATURES, |
282 | .gen = 8, | |
283 | .is_broadwell = 1, | |
284 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, | |
285 | }; | |
286 | ||
42f5551d CW |
287 | static const struct intel_device_info intel_cherryview_info = { |
288 | .gen = 8, .num_pipes = 3, | |
289 | .need_gfx_hws = 1, .has_hotplug = 1, | |
290 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
291 | .is_cherryview = 1, | |
6e3b84d8 | 292 | .has_psr = 1, |
42f5551d CW |
293 | .display_mmio_offset = VLV_DISPLAY_BASE, |
294 | GEN_CHV_PIPEOFFSETS, | |
295 | CURSOR_OFFSETS, | |
296 | CHV_COLORS, | |
297 | }; | |
298 | ||
299 | static const struct intel_device_info intel_skylake_info = { | |
300 | BDW_FEATURES, | |
301 | .is_skylake = 1, | |
302 | .gen = 9, | |
303 | }; | |
304 | ||
305 | static const struct intel_device_info intel_skylake_gt3_info = { | |
306 | BDW_FEATURES, | |
307 | .is_skylake = 1, | |
308 | .gen = 9, | |
309 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, | |
310 | }; | |
311 | ||
312 | static const struct intel_device_info intel_broxton_info = { | |
42f5551d CW |
313 | .is_broxton = 1, |
314 | .gen = 9, | |
315 | .need_gfx_hws = 1, .has_hotplug = 1, | |
316 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
317 | .num_pipes = 3, | |
318 | .has_ddi = 1, | |
319 | .has_fpga_dbg = 1, | |
320 | .has_fbc = 1, | |
321 | .has_pooled_eu = 0, | |
322 | GEN_DEFAULT_PIPEOFFSETS, | |
323 | IVB_CURSOR_OFFSETS, | |
324 | BDW_COLORS, | |
325 | }; | |
326 | ||
327 | static const struct intel_device_info intel_kabylake_info = { | |
328 | BDW_FEATURES, | |
329 | .is_kabylake = 1, | |
330 | .gen = 9, | |
331 | }; | |
332 | ||
333 | static const struct intel_device_info intel_kabylake_gt3_info = { | |
334 | BDW_FEATURES, | |
335 | .is_kabylake = 1, | |
336 | .gen = 9, | |
337 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, | |
338 | }; | |
339 | ||
340 | /* | |
341 | * Make sure any device matches here are from most specific to most | |
342 | * general. For example, since the Quanta match is based on the subsystem | |
343 | * and subvendor IDs, we need it to come before the more general IVB | |
344 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
345 | */ | |
346 | static const struct pci_device_id pciidlist[] = { | |
347 | INTEL_I830_IDS(&intel_i830_info), | |
348 | INTEL_I845G_IDS(&intel_845g_info), | |
349 | INTEL_I85X_IDS(&intel_i85x_info), | |
350 | INTEL_I865G_IDS(&intel_i865g_info), | |
351 | INTEL_I915G_IDS(&intel_i915g_info), | |
352 | INTEL_I915GM_IDS(&intel_i915gm_info), | |
353 | INTEL_I945G_IDS(&intel_i945g_info), | |
354 | INTEL_I945GM_IDS(&intel_i945gm_info), | |
355 | INTEL_I965G_IDS(&intel_i965g_info), | |
356 | INTEL_G33_IDS(&intel_g33_info), | |
357 | INTEL_I965GM_IDS(&intel_i965gm_info), | |
358 | INTEL_GM45_IDS(&intel_gm45_info), | |
359 | INTEL_G45_IDS(&intel_g45_info), | |
360 | INTEL_PINEVIEW_IDS(&intel_pineview_info), | |
361 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), | |
362 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), | |
363 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), | |
364 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), | |
365 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ | |
366 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), | |
367 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), | |
8d9c20e1 CS |
368 | INTEL_HSW_IDS(&intel_haswell_info), |
369 | INTEL_VLV_IDS(&intel_valleyview_info), | |
370 | INTEL_BDW_GT12_IDS(&intel_broadwell_info), | |
371 | INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), | |
42f5551d CW |
372 | INTEL_CHV_IDS(&intel_cherryview_info), |
373 | INTEL_SKL_GT1_IDS(&intel_skylake_info), | |
374 | INTEL_SKL_GT2_IDS(&intel_skylake_info), | |
375 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), | |
376 | INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), | |
377 | INTEL_BXT_IDS(&intel_broxton_info), | |
378 | INTEL_KBL_GT1_IDS(&intel_kabylake_info), | |
379 | INTEL_KBL_GT2_IDS(&intel_kabylake_info), | |
380 | INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), | |
381 | INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), | |
382 | {0, 0, 0} | |
383 | }; | |
384 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
385 | ||
386 | extern int i915_driver_load(struct pci_dev *pdev, | |
387 | const struct pci_device_id *ent); | |
388 | ||
389 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
390 | { | |
391 | struct intel_device_info *intel_info = | |
392 | (struct intel_device_info *) ent->driver_data; | |
393 | ||
394 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { | |
395 | DRM_INFO("This hardware requires preliminary hardware support.\n" | |
396 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
397 | return -ENODEV; | |
398 | } | |
399 | ||
400 | /* Only bind to function 0 of the device. Early generations | |
401 | * used function 1 as a placeholder for multi-head. This causes | |
402 | * us confusion instead, especially on the systems where both | |
403 | * functions have the same PCI-ID! | |
404 | */ | |
405 | if (PCI_FUNC(pdev->devfn)) | |
406 | return -ENODEV; | |
407 | ||
408 | /* | |
409 | * apple-gmux is needed on dual GPU MacBook Pro | |
410 | * to probe the panel if we're the inactive GPU. | |
411 | */ | |
412 | if (vga_switcheroo_client_probe_defer(pdev)) | |
413 | return -EPROBE_DEFER; | |
414 | ||
415 | return i915_driver_load(pdev, ent); | |
416 | } | |
417 | ||
418 | extern void i915_driver_unload(struct drm_device *dev); | |
419 | ||
420 | static void i915_pci_remove(struct pci_dev *pdev) | |
421 | { | |
422 | struct drm_device *dev = pci_get_drvdata(pdev); | |
423 | ||
424 | i915_driver_unload(dev); | |
425 | drm_dev_unref(dev); | |
426 | } | |
427 | ||
428 | extern const struct dev_pm_ops i915_pm_ops; | |
429 | ||
a09d0ba1 | 430 | static struct pci_driver i915_pci_driver = { |
42f5551d CW |
431 | .name = DRIVER_NAME, |
432 | .id_table = pciidlist, | |
433 | .probe = i915_pci_probe, | |
434 | .remove = i915_pci_remove, | |
435 | .driver.pm = &i915_pm_ops, | |
436 | }; | |
a09d0ba1 CW |
437 | |
438 | static int __init i915_init(void) | |
439 | { | |
440 | bool use_kms = true; | |
441 | ||
442 | /* | |
443 | * Enable KMS by default, unless explicitly overriden by | |
444 | * either the i915.modeset prarameter or by the | |
445 | * vga_text_mode_force boot option. | |
446 | */ | |
447 | ||
448 | if (i915.modeset == 0) | |
449 | use_kms = false; | |
450 | ||
451 | if (vgacon_text_force() && i915.modeset == -1) | |
452 | use_kms = false; | |
453 | ||
454 | if (!use_kms) { | |
455 | /* Silently fail loading to not upset userspace. */ | |
456 | DRM_DEBUG_DRIVER("KMS disabled.\n"); | |
457 | return 0; | |
458 | } | |
459 | ||
460 | return pci_register_driver(&i915_pci_driver); | |
461 | } | |
462 | ||
463 | static void __exit i915_exit(void) | |
464 | { | |
465 | if (!i915_pci_driver.driver.owner) | |
466 | return; | |
467 | ||
468 | pci_unregister_driver(&i915_pci_driver); | |
469 | } | |
470 | ||
471 | module_init(i915_init); | |
472 | module_exit(i915_exit); | |
473 | ||
474 | MODULE_AUTHOR("Tungsten Graphics, Inc."); | |
475 | MODULE_AUTHOR("Intel Corporation"); | |
476 | ||
477 | MODULE_DESCRIPTION(DRIVER_DESC); | |
478 | MODULE_LICENSE("GPL and additional rights"); |