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585fb111 JB |
1 | /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
2 | * All Rights Reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the | |
6 | * "Software"), to deal in the Software without restriction, including | |
7 | * without limitation the rights to use, copy, modify, merge, publish, | |
8 | * distribute, sub license, and/or sell copies of the Software, and to | |
9 | * permit persons to whom the Software is furnished to do so, subject to | |
10 | * the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the | |
13 | * next paragraph) shall be included in all copies or substantial portions | |
14 | * of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
19 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef _I915_REG_H_ | |
26 | #define _I915_REG_H_ | |
27 | ||
585fb111 JB |
28 | /* |
29 | * The Bridge device's PCI config space has information about the | |
30 | * fb aperture size and the amount of pre-reserved memory. | |
31 | */ | |
32 | #define INTEL_GMCH_CTRL 0x52 | |
33 | #define INTEL_GMCH_ENABLED 0x4 | |
34 | #define INTEL_GMCH_MEM_MASK 0x1 | |
35 | #define INTEL_GMCH_MEM_64M 0x1 | |
36 | #define INTEL_GMCH_MEM_128M 0 | |
37 | ||
241fa85b | 38 | #define INTEL_GMCH_GMS_MASK (0xf << 4) |
585fb111 JB |
39 | #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) |
40 | #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) | |
41 | #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) | |
42 | #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) | |
43 | #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) | |
44 | #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) | |
45 | ||
46 | #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) | |
47 | #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) | |
241fa85b EA |
48 | #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4) |
49 | #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4) | |
50 | #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) | |
51 | #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) | |
52 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) | |
53 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) | |
585fb111 JB |
54 | |
55 | /* PCI config space */ | |
56 | ||
57 | #define HPLLCC 0xc0 /* 855 only */ | |
58 | #define GC_CLOCK_CONTROL_MASK (3 << 0) | |
59 | #define GC_CLOCK_133_200 (0 << 0) | |
60 | #define GC_CLOCK_100_200 (1 << 0) | |
61 | #define GC_CLOCK_100_133 (2 << 0) | |
62 | #define GC_CLOCK_166_250 (3 << 0) | |
63 | #define GCFGC 0xf0 /* 915+ only */ | |
64 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) | |
65 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) | |
66 | #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) | |
67 | #define GC_DISPLAY_CLOCK_MASK (7 << 4) | |
68 | #define LBB 0xf4 | |
69 | ||
70 | /* VGA stuff */ | |
71 | ||
72 | #define VGA_ST01_MDA 0x3ba | |
73 | #define VGA_ST01_CGA 0x3da | |
74 | ||
75 | #define VGA_MSR_WRITE 0x3c2 | |
76 | #define VGA_MSR_READ 0x3cc | |
77 | #define VGA_MSR_MEM_EN (1<<1) | |
78 | #define VGA_MSR_CGA_MODE (1<<0) | |
79 | ||
80 | #define VGA_SR_INDEX 0x3c4 | |
81 | #define VGA_SR_DATA 0x3c5 | |
82 | ||
83 | #define VGA_AR_INDEX 0x3c0 | |
84 | #define VGA_AR_VID_EN (1<<5) | |
85 | #define VGA_AR_DATA_WRITE 0x3c0 | |
86 | #define VGA_AR_DATA_READ 0x3c1 | |
87 | ||
88 | #define VGA_GR_INDEX 0x3ce | |
89 | #define VGA_GR_DATA 0x3cf | |
90 | /* GR05 */ | |
91 | #define VGA_GR_MEM_READ_MODE_SHIFT 3 | |
92 | #define VGA_GR_MEM_READ_MODE_PLANE 1 | |
93 | /* GR06 */ | |
94 | #define VGA_GR_MEM_MODE_MASK 0xc | |
95 | #define VGA_GR_MEM_MODE_SHIFT 2 | |
96 | #define VGA_GR_MEM_A0000_AFFFF 0 | |
97 | #define VGA_GR_MEM_A0000_BFFFF 1 | |
98 | #define VGA_GR_MEM_B0000_B7FFF 2 | |
99 | #define VGA_GR_MEM_B0000_BFFFF 3 | |
100 | ||
101 | #define VGA_DACMASK 0x3c6 | |
102 | #define VGA_DACRX 0x3c7 | |
103 | #define VGA_DACWX 0x3c8 | |
104 | #define VGA_DACDATA 0x3c9 | |
105 | ||
106 | #define VGA_CR_INDEX_MDA 0x3b4 | |
107 | #define VGA_CR_DATA_MDA 0x3b5 | |
108 | #define VGA_CR_INDEX_CGA 0x3d4 | |
109 | #define VGA_CR_DATA_CGA 0x3d5 | |
110 | ||
111 | /* | |
112 | * Memory interface instructions used by the kernel | |
113 | */ | |
114 | #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) | |
115 | ||
116 | #define MI_NOOP MI_INSTR(0, 0) | |
117 | #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) | |
118 | #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) | |
119 | #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) | |
120 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) | |
121 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) | |
122 | #define MI_FLUSH MI_INSTR(0x04, 0) | |
123 | #define MI_READ_FLUSH (1 << 0) | |
124 | #define MI_EXE_FLUSH (1 << 1) | |
125 | #define MI_NO_WRITE_FLUSH (1 << 2) | |
126 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ | |
127 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ | |
128 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) | |
129 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) | |
130 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) | |
131 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) | |
132 | #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ | |
133 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) | |
134 | #define MI_STORE_DWORD_INDEX_SHIFT 2 | |
135 | #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) | |
136 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) | |
137 | #define MI_BATCH_NON_SECURE (1) | |
138 | #define MI_BATCH_NON_SECURE_I965 (1<<8) | |
139 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) | |
140 | ||
141 | /* | |
142 | * 3D instructions used by the kernel | |
143 | */ | |
144 | #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) | |
145 | ||
146 | #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) | |
147 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
148 | #define SC_UPDATE_SCISSOR (0x1<<1) | |
149 | #define SC_ENABLE_MASK (0x1<<0) | |
150 | #define SC_ENABLE (0x1<<0) | |
151 | #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) | |
152 | #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) | |
153 | #define SCI_YMIN_MASK (0xffff<<16) | |
154 | #define SCI_XMIN_MASK (0xffff<<0) | |
155 | #define SCI_YMAX_MASK (0xffff<<16) | |
156 | #define SCI_XMAX_MASK (0xffff<<0) | |
157 | #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
158 | #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) | |
159 | #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) | |
160 | #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) | |
161 | #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) | |
162 | #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) | |
163 | #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) | |
164 | #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) | |
165 | #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) | |
166 | #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) | |
167 | #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) | |
168 | #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) | |
169 | #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) | |
170 | #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) | |
171 | #define BLT_DEPTH_8 (0<<24) | |
172 | #define BLT_DEPTH_16_565 (1<<24) | |
173 | #define BLT_DEPTH_16_1555 (2<<24) | |
174 | #define BLT_DEPTH_32 (3<<24) | |
175 | #define BLT_ROP_GXCOPY (0xcc<<16) | |
176 | #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ | |
177 | #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ | |
178 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) | |
179 | #define ASYNC_FLIP (1<<22) | |
180 | #define DISPLAY_PLANE_A (0<<20) | |
181 | #define DISPLAY_PLANE_B (1<<20) | |
182 | ||
183 | /* | |
de151cf6 | 184 | * Fence registers |
585fb111 | 185 | */ |
de151cf6 | 186 | #define FENCE_REG_830_0 0x2000 |
dc529a4f | 187 | #define FENCE_REG_945_8 0x3000 |
de151cf6 JB |
188 | #define I830_FENCE_START_MASK 0x07f80000 |
189 | #define I830_FENCE_TILING_Y_SHIFT 12 | |
0f973f27 | 190 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
de151cf6 JB |
191 | #define I830_FENCE_PITCH_SHIFT 4 |
192 | #define I830_FENCE_REG_VALID (1<<0) | |
e76a16de EA |
193 | #define I915_FENCE_MAX_PITCH_VAL 0x10 |
194 | #define I830_FENCE_MAX_PITCH_VAL 6 | |
8d7773a3 | 195 | #define I830_FENCE_MAX_SIZE_VAL (1<<8) |
de151cf6 JB |
196 | |
197 | #define I915_FENCE_START_MASK 0x0ff00000 | |
0f973f27 | 198 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
585fb111 | 199 | |
de151cf6 JB |
200 | #define FENCE_REG_965_0 0x03000 |
201 | #define I965_FENCE_PITCH_SHIFT 2 | |
202 | #define I965_FENCE_TILING_Y_SHIFT 1 | |
203 | #define I965_FENCE_REG_VALID (1<<0) | |
8d7773a3 | 204 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
de151cf6 JB |
205 | |
206 | /* | |
207 | * Instruction and interrupt control regs | |
208 | */ | |
585fb111 JB |
209 | #define PRB0_TAIL 0x02030 |
210 | #define PRB0_HEAD 0x02034 | |
211 | #define PRB0_START 0x02038 | |
212 | #define PRB0_CTL 0x0203c | |
213 | #define TAIL_ADDR 0x001FFFF8 | |
214 | #define HEAD_WRAP_COUNT 0xFFE00000 | |
215 | #define HEAD_WRAP_ONE 0x00200000 | |
216 | #define HEAD_ADDR 0x001FFFFC | |
217 | #define RING_NR_PAGES 0x001FF000 | |
218 | #define RING_REPORT_MASK 0x00000006 | |
219 | #define RING_REPORT_64K 0x00000002 | |
220 | #define RING_REPORT_128K 0x00000004 | |
221 | #define RING_NO_REPORT 0x00000000 | |
222 | #define RING_VALID_MASK 0x00000001 | |
223 | #define RING_VALID 0x00000001 | |
224 | #define RING_INVALID 0x00000000 | |
225 | #define PRB1_TAIL 0x02040 /* 915+ only */ | |
226 | #define PRB1_HEAD 0x02044 /* 915+ only */ | |
227 | #define PRB1_START 0x02048 /* 915+ only */ | |
228 | #define PRB1_CTL 0x0204c /* 915+ only */ | |
229 | #define ACTHD_I965 0x02074 | |
230 | #define HWS_PGA 0x02080 | |
231 | #define HWS_ADDRESS_MASK 0xfffff000 | |
232 | #define HWS_START_ADDRESS_SHIFT 4 | |
233 | #define IPEIR 0x02088 | |
234 | #define NOPID 0x02094 | |
235 | #define HWSTAM 0x02098 | |
236 | #define SCPD0 0x0209c /* 915+ only */ | |
237 | #define IER 0x020a0 | |
238 | #define IIR 0x020a4 | |
239 | #define IMR 0x020a8 | |
240 | #define ISR 0x020ac | |
241 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) | |
242 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) | |
243 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) | |
244 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) | |
245 | #define I915_HWB_OOM_INTERRUPT (1<<13) | |
246 | #define I915_SYNC_STATUS_INTERRUPT (1<<12) | |
247 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) | |
248 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) | |
249 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) | |
250 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) | |
251 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) | |
252 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) | |
253 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) | |
254 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) | |
255 | #define I915_DEBUG_INTERRUPT (1<<2) | |
256 | #define I915_USER_INTERRUPT (1<<1) | |
257 | #define I915_ASLE_INTERRUPT (1<<0) | |
258 | #define EIR 0x020b0 | |
259 | #define EMR 0x020b4 | |
260 | #define ESR 0x020b8 | |
261 | #define INSTPM 0x020c0 | |
262 | #define ACTHD 0x020c8 | |
263 | #define FW_BLC 0x020d8 | |
264 | #define FW_BLC_SELF 0x020e0 /* 915+ only */ | |
265 | #define MI_ARB_STATE 0x020e4 /* 915+ only */ | |
266 | #define CACHE_MODE_0 0x02120 /* 915+ only */ | |
267 | #define CM0_MASK_SHIFT 16 | |
268 | #define CM0_IZ_OPT_DISABLE (1<<6) | |
269 | #define CM0_ZR_OPT_DISABLE (1<<5) | |
270 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) | |
271 | #define CM0_COLOR_EVICT_DISABLE (1<<3) | |
272 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) | |
273 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) | |
274 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ | |
275 | ||
de151cf6 | 276 | |
585fb111 JB |
277 | /* |
278 | * Framebuffer compression (915+ only) | |
279 | */ | |
280 | ||
281 | #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ | |
282 | #define FBC_LL_BASE 0x03204 /* 4k page aligned */ | |
283 | #define FBC_CONTROL 0x03208 | |
284 | #define FBC_CTL_EN (1<<31) | |
285 | #define FBC_CTL_PERIODIC (1<<30) | |
286 | #define FBC_CTL_INTERVAL_SHIFT (16) | |
287 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) | |
288 | #define FBC_CTL_STRIDE_SHIFT (5) | |
289 | #define FBC_CTL_FENCENO (1<<0) | |
290 | #define FBC_COMMAND 0x0320c | |
291 | #define FBC_CMD_COMPRESS (1<<0) | |
292 | #define FBC_STATUS 0x03210 | |
293 | #define FBC_STAT_COMPRESSING (1<<31) | |
294 | #define FBC_STAT_COMPRESSED (1<<30) | |
295 | #define FBC_STAT_MODIFIED (1<<29) | |
296 | #define FBC_STAT_CURRENT_LINE (1<<0) | |
297 | #define FBC_CONTROL2 0x03214 | |
298 | #define FBC_CTL_FENCE_DBL (0<<4) | |
299 | #define FBC_CTL_IDLE_IMM (0<<2) | |
300 | #define FBC_CTL_IDLE_FULL (1<<2) | |
301 | #define FBC_CTL_IDLE_LINE (2<<2) | |
302 | #define FBC_CTL_IDLE_DEBUG (3<<2) | |
303 | #define FBC_CTL_CPU_FENCE (1<<1) | |
304 | #define FBC_CTL_PLANEA (0<<0) | |
305 | #define FBC_CTL_PLANEB (1<<0) | |
306 | #define FBC_FENCE_OFF 0x0321b | |
307 | ||
308 | #define FBC_LL_SIZE (1536) | |
309 | ||
310 | /* | |
311 | * GPIO regs | |
312 | */ | |
313 | #define GPIOA 0x5010 | |
314 | #define GPIOB 0x5014 | |
315 | #define GPIOC 0x5018 | |
316 | #define GPIOD 0x501c | |
317 | #define GPIOE 0x5020 | |
318 | #define GPIOF 0x5024 | |
319 | #define GPIOG 0x5028 | |
320 | #define GPIOH 0x502c | |
321 | # define GPIO_CLOCK_DIR_MASK (1 << 0) | |
322 | # define GPIO_CLOCK_DIR_IN (0 << 1) | |
323 | # define GPIO_CLOCK_DIR_OUT (1 << 1) | |
324 | # define GPIO_CLOCK_VAL_MASK (1 << 2) | |
325 | # define GPIO_CLOCK_VAL_OUT (1 << 3) | |
326 | # define GPIO_CLOCK_VAL_IN (1 << 4) | |
327 | # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) | |
328 | # define GPIO_DATA_DIR_MASK (1 << 8) | |
329 | # define GPIO_DATA_DIR_IN (0 << 9) | |
330 | # define GPIO_DATA_DIR_OUT (1 << 9) | |
331 | # define GPIO_DATA_VAL_MASK (1 << 10) | |
332 | # define GPIO_DATA_VAL_OUT (1 << 11) | |
333 | # define GPIO_DATA_VAL_IN (1 << 12) | |
334 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) | |
335 | ||
336 | /* | |
337 | * Clock control & power management | |
338 | */ | |
339 | ||
340 | #define VGA0 0x6000 | |
341 | #define VGA1 0x6004 | |
342 | #define VGA_PD 0x6010 | |
343 | #define VGA0_PD_P2_DIV_4 (1 << 7) | |
344 | #define VGA0_PD_P1_DIV_2 (1 << 5) | |
345 | #define VGA0_PD_P1_SHIFT 0 | |
346 | #define VGA0_PD_P1_MASK (0x1f << 0) | |
347 | #define VGA1_PD_P2_DIV_4 (1 << 15) | |
348 | #define VGA1_PD_P1_DIV_2 (1 << 13) | |
349 | #define VGA1_PD_P1_SHIFT 8 | |
350 | #define VGA1_PD_P1_MASK (0x1f << 8) | |
351 | #define DPLL_A 0x06014 | |
352 | #define DPLL_B 0x06018 | |
353 | #define DPLL_VCO_ENABLE (1 << 31) | |
354 | #define DPLL_DVO_HIGH_SPEED (1 << 30) | |
355 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) | |
356 | #define DPLL_VGA_MODE_DIS (1 << 28) | |
357 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ | |
358 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ | |
359 | #define DPLL_MODE_MASK (3 << 26) | |
360 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ | |
361 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ | |
362 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ | |
363 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ | |
364 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ | |
365 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ | |
2177832f | 366 | #define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */ |
585fb111 JB |
367 | |
368 | #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) | |
369 | #define I915_CRC_ERROR_ENABLE (1UL<<29) | |
370 | #define I915_CRC_DONE_ENABLE (1UL<<28) | |
371 | #define I915_GMBUS_EVENT_ENABLE (1UL<<27) | |
372 | #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) | |
373 | #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) | |
374 | #define I915_DPST_EVENT_ENABLE (1UL<<23) | |
375 | #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) | |
376 | #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) | |
377 | #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) | |
378 | #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ | |
379 | #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) | |
380 | #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) | |
381 | #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) | |
382 | #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) | |
383 | #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) | |
384 | #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) | |
385 | #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) | |
386 | #define I915_DPST_EVENT_STATUS (1UL<<7) | |
387 | #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) | |
388 | #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) | |
389 | #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) | |
390 | #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ | |
391 | #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1) | |
392 | #define I915_OVERLAY_UPDATED_STATUS (1UL<<0) | |
393 | ||
394 | #define SRX_INDEX 0x3c4 | |
395 | #define SRX_DATA 0x3c5 | |
396 | #define SR01 1 | |
397 | #define SR01_SCREEN_OFF (1<<5) | |
398 | ||
399 | #define PPCR 0x61204 | |
400 | #define PPCR_ON (1<<0) | |
401 | ||
402 | #define DVOB 0x61140 | |
403 | #define DVOB_ON (1<<31) | |
404 | #define DVOC 0x61160 | |
405 | #define DVOC_ON (1<<31) | |
406 | #define LVDS 0x61180 | |
407 | #define LVDS_ON (1<<31) | |
408 | ||
409 | #define ADPA 0x61100 | |
410 | #define ADPA_DPMS_MASK (~(3<<10)) | |
411 | #define ADPA_DPMS_ON (0<<10) | |
412 | #define ADPA_DPMS_SUSPEND (1<<10) | |
413 | #define ADPA_DPMS_STANDBY (2<<10) | |
414 | #define ADPA_DPMS_OFF (3<<10) | |
415 | ||
416 | #define RING_TAIL 0x00 | |
417 | #define TAIL_ADDR 0x001FFFF8 | |
418 | #define RING_HEAD 0x04 | |
419 | #define HEAD_WRAP_COUNT 0xFFE00000 | |
420 | #define HEAD_WRAP_ONE 0x00200000 | |
421 | #define HEAD_ADDR 0x001FFFFC | |
422 | #define RING_START 0x08 | |
423 | #define START_ADDR 0xFFFFF000 | |
424 | #define RING_LEN 0x0C | |
425 | #define RING_NR_PAGES 0x001FF000 | |
426 | #define RING_REPORT_MASK 0x00000006 | |
427 | #define RING_REPORT_64K 0x00000002 | |
428 | #define RING_REPORT_128K 0x00000004 | |
429 | #define RING_NO_REPORT 0x00000000 | |
430 | #define RING_VALID_MASK 0x00000001 | |
431 | #define RING_VALID 0x00000001 | |
432 | #define RING_INVALID 0x00000000 | |
433 | ||
434 | /* Scratch pad debug 0 reg: | |
435 | */ | |
436 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 | |
437 | /* | |
438 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within | |
439 | * this field (only one bit may be set). | |
440 | */ | |
441 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 | |
442 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 | |
2177832f | 443 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15 |
585fb111 JB |
444 | /* i830, required in DVO non-gang */ |
445 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) | |
446 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ | |
447 | #define PLL_REF_INPUT_DREFCLK (0 << 13) | |
448 | #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ | |
449 | #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ | |
450 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) | |
451 | #define PLL_REF_INPUT_MASK (3 << 13) | |
452 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 | |
453 | /* | |
454 | * Parallel to Serial Load Pulse phase selection. | |
455 | * Selects the phase for the 10X DPLL clock for the PCIe | |
456 | * digital display port. The range is 4 to 13; 10 or more | |
457 | * is just a flip delay. The default is 6 | |
458 | */ | |
459 | #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) | |
460 | #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) | |
461 | /* | |
462 | * SDVO multiplier for 945G/GM. Not used on 965. | |
463 | */ | |
464 | #define SDVO_MULTIPLIER_MASK 0x000000ff | |
465 | #define SDVO_MULTIPLIER_SHIFT_HIRES 4 | |
466 | #define SDVO_MULTIPLIER_SHIFT_VGA 0 | |
467 | #define DPLL_A_MD 0x0601c /* 965+ only */ | |
468 | /* | |
469 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. | |
470 | * | |
471 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. | |
472 | */ | |
473 | #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 | |
474 | #define DPLL_MD_UDI_DIVIDER_SHIFT 24 | |
475 | /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ | |
476 | #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 | |
477 | #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 | |
478 | /* | |
479 | * SDVO/UDI pixel multiplier. | |
480 | * | |
481 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus | |
482 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate | |
483 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing | |
484 | * dummy bytes in the datastream at an increased clock rate, with both sides of | |
485 | * the link knowing how many bytes are fill. | |
486 | * | |
487 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock | |
488 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be | |
489 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and | |
490 | * through an SDVO command. | |
491 | * | |
492 | * This register field has values of multiplication factor minus 1, with | |
493 | * a maximum multiplier of 5 for SDVO. | |
494 | */ | |
495 | #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 | |
496 | #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 | |
497 | /* | |
498 | * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. | |
499 | * This best be set to the default value (3) or the CRT won't work. No, | |
500 | * I don't entirely understand what this does... | |
501 | */ | |
502 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f | |
503 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 | |
504 | #define DPLL_B_MD 0x06020 /* 965+ only */ | |
505 | #define FPA0 0x06040 | |
506 | #define FPA1 0x06044 | |
507 | #define FPB0 0x06048 | |
508 | #define FPB1 0x0604c | |
509 | #define FP_N_DIV_MASK 0x003f0000 | |
2177832f | 510 | #define FP_N_IGD_DIV_MASK 0x00ff0000 |
585fb111 JB |
511 | #define FP_N_DIV_SHIFT 16 |
512 | #define FP_M1_DIV_MASK 0x00003f00 | |
513 | #define FP_M1_DIV_SHIFT 8 | |
514 | #define FP_M2_DIV_MASK 0x0000003f | |
2177832f | 515 | #define FP_M2_IGD_DIV_MASK 0x000000ff |
585fb111 JB |
516 | #define FP_M2_DIV_SHIFT 0 |
517 | #define DPLL_TEST 0x606c | |
518 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) | |
519 | #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) | |
520 | #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) | |
521 | #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) | |
522 | #define DPLLB_TEST_N_BYPASS (1 << 19) | |
523 | #define DPLLB_TEST_M_BYPASS (1 << 18) | |
524 | #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) | |
525 | #define DPLLA_TEST_N_BYPASS (1 << 3) | |
526 | #define DPLLA_TEST_M_BYPASS (1 << 2) | |
527 | #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) | |
528 | #define D_STATE 0x6104 | |
529 | #define CG_2D_DIS 0x6200 | |
0ba0e9e1 | 530 | #define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) |
585fb111 JB |
531 | #define CG_3D_DIS 0x6204 |
532 | ||
533 | /* | |
534 | * Palette regs | |
535 | */ | |
536 | ||
537 | #define PALETTE_A 0x0a000 | |
538 | #define PALETTE_B 0x0a800 | |
539 | ||
673a394b EA |
540 | /* MCH MMIO space */ |
541 | ||
542 | /* | |
543 | * MCHBAR mirror. | |
544 | * | |
545 | * This mirrors the MCHBAR MMIO space whose location is determined by | |
546 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in | |
547 | * every way. It is not accessible from the CP register read instructions. | |
548 | * | |
549 | */ | |
550 | #define MCHBAR_MIRROR_BASE 0x10000 | |
551 | ||
552 | /** 915-945 and GM965 MCH register controlling DRAM channel access */ | |
553 | #define DCC 0x10200 | |
554 | #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) | |
555 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) | |
556 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) | |
557 | #define DCC_ADDRESSING_MODE_MASK (3 << 0) | |
558 | #define DCC_CHANNEL_XOR_DISABLE (1 << 10) | |
a7f014f2 | 559 | #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) |
673a394b EA |
560 | |
561 | /** 965 MCH register controlling DRAM channel configuration */ | |
562 | #define C0DRB3 0x10206 | |
563 | #define C1DRB3 0x10606 | |
564 | ||
881ee988 KP |
565 | /** GM965 GM45 render standby register */ |
566 | #define MCHBAR_RENDER_STANDBY 0x111B8 | |
567 | ||
7d57382e EA |
568 | #define PEG_BAND_GAP_DATA 0x14d68 |
569 | ||
585fb111 JB |
570 | /* |
571 | * Overlay regs | |
572 | */ | |
573 | ||
574 | #define OVADD 0x30000 | |
575 | #define DOVSTA 0x30008 | |
576 | #define OC_BUF (0x3<<20) | |
577 | #define OGAMC5 0x30010 | |
578 | #define OGAMC4 0x30014 | |
579 | #define OGAMC3 0x30018 | |
580 | #define OGAMC2 0x3001c | |
581 | #define OGAMC1 0x30020 | |
582 | #define OGAMC0 0x30024 | |
583 | ||
584 | /* | |
585 | * Display engine regs | |
586 | */ | |
587 | ||
588 | /* Pipe A timing regs */ | |
589 | #define HTOTAL_A 0x60000 | |
590 | #define HBLANK_A 0x60004 | |
591 | #define HSYNC_A 0x60008 | |
592 | #define VTOTAL_A 0x6000c | |
593 | #define VBLANK_A 0x60010 | |
594 | #define VSYNC_A 0x60014 | |
595 | #define PIPEASRC 0x6001c | |
596 | #define BCLRPAT_A 0x60020 | |
597 | ||
598 | /* Pipe B timing regs */ | |
599 | #define HTOTAL_B 0x61000 | |
600 | #define HBLANK_B 0x61004 | |
601 | #define HSYNC_B 0x61008 | |
602 | #define VTOTAL_B 0x6100c | |
603 | #define VBLANK_B 0x61010 | |
604 | #define VSYNC_B 0x61014 | |
605 | #define PIPEBSRC 0x6101c | |
606 | #define BCLRPAT_B 0x61020 | |
607 | ||
608 | /* VGA port control */ | |
609 | #define ADPA 0x61100 | |
610 | #define ADPA_DAC_ENABLE (1<<31) | |
611 | #define ADPA_DAC_DISABLE 0 | |
612 | #define ADPA_PIPE_SELECT_MASK (1<<30) | |
613 | #define ADPA_PIPE_A_SELECT 0 | |
614 | #define ADPA_PIPE_B_SELECT (1<<30) | |
615 | #define ADPA_USE_VGA_HVPOLARITY (1<<15) | |
616 | #define ADPA_SETS_HVPOLARITY 0 | |
617 | #define ADPA_VSYNC_CNTL_DISABLE (1<<11) | |
618 | #define ADPA_VSYNC_CNTL_ENABLE 0 | |
619 | #define ADPA_HSYNC_CNTL_DISABLE (1<<10) | |
620 | #define ADPA_HSYNC_CNTL_ENABLE 0 | |
621 | #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) | |
622 | #define ADPA_VSYNC_ACTIVE_LOW 0 | |
623 | #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) | |
624 | #define ADPA_HSYNC_ACTIVE_LOW 0 | |
625 | #define ADPA_DPMS_MASK (~(3<<10)) | |
626 | #define ADPA_DPMS_ON (0<<10) | |
627 | #define ADPA_DPMS_SUSPEND (1<<10) | |
628 | #define ADPA_DPMS_STANDBY (2<<10) | |
629 | #define ADPA_DPMS_OFF (3<<10) | |
630 | ||
631 | /* Hotplug control (945+ only) */ | |
632 | #define PORT_HOTPLUG_EN 0x61110 | |
7d57382e EA |
633 | #define HDMIB_HOTPLUG_INT_EN (1 << 29) |
634 | #define HDMIC_HOTPLUG_INT_EN (1 << 28) | |
635 | #define HDMID_HOTPLUG_INT_EN (1 << 27) | |
585fb111 JB |
636 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
637 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) | |
638 | #define TV_HOTPLUG_INT_EN (1 << 18) | |
639 | #define CRT_HOTPLUG_INT_EN (1 << 9) | |
640 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) | |
771cb081 ZY |
641 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
642 | /* must use period 64 on GM45 according to docs */ | |
643 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) | |
644 | #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) | |
645 | #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) | |
646 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) | |
647 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) | |
648 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) | |
649 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) | |
650 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) | |
651 | #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) | |
652 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) | |
653 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) | |
654 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) | |
655 | #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */ | |
5ca58282 JB |
656 | #define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f |
657 | #define HOTPLUG_EN_MASK (HDMIB_HOTPLUG_INT_EN | \ | |
658 | HDMIC_HOTPLUG_INT_EN | \ | |
659 | HDMID_HOTPLUG_INT_EN | \ | |
660 | SDVOB_HOTPLUG_INT_EN | \ | |
661 | SDVOC_HOTPLUG_INT_EN | \ | |
662 | TV_HOTPLUG_INT_EN | \ | |
663 | CRT_HOTPLUG_INT_EN) | |
771cb081 | 664 | |
585fb111 JB |
665 | |
666 | #define PORT_HOTPLUG_STAT 0x61114 | |
7d57382e EA |
667 | #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) |
668 | #define HDMIC_HOTPLUG_INT_STATUS (1 << 28) | |
669 | #define HDMID_HOTPLUG_INT_STATUS (1 << 27) | |
585fb111 JB |
670 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
671 | #define TV_HOTPLUG_INT_STATUS (1 << 10) | |
672 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) | |
673 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) | |
674 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) | |
675 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) | |
676 | #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) | |
677 | #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) | |
678 | ||
679 | /* SDVO port control */ | |
680 | #define SDVOB 0x61140 | |
681 | #define SDVOC 0x61160 | |
682 | #define SDVO_ENABLE (1 << 31) | |
683 | #define SDVO_PIPE_B_SELECT (1 << 30) | |
684 | #define SDVO_STALL_SELECT (1 << 29) | |
685 | #define SDVO_INTERRUPT_ENABLE (1 << 26) | |
686 | /** | |
687 | * 915G/GM SDVO pixel multiplier. | |
688 | * | |
689 | * Programmed value is multiplier - 1, up to 5x. | |
690 | * | |
691 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK | |
692 | */ | |
693 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) | |
694 | #define SDVO_PORT_MULTIPLY_SHIFT 23 | |
695 | #define SDVO_PHASE_SELECT_MASK (15 << 19) | |
696 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) | |
697 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) | |
698 | #define SDVOC_GANG_MODE (1 << 16) | |
7d57382e EA |
699 | #define SDVO_ENCODING_SDVO (0x0 << 10) |
700 | #define SDVO_ENCODING_HDMI (0x2 << 10) | |
701 | /** Requird for HDMI operation */ | |
702 | #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) | |
585fb111 | 703 | #define SDVO_BORDER_ENABLE (1 << 7) |
7d57382e EA |
704 | #define SDVO_AUDIO_ENABLE (1 << 6) |
705 | /** New with 965, default is to be set */ | |
706 | #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) | |
707 | /** New with 965, default is to be set */ | |
708 | #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) | |
585fb111 JB |
709 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) |
710 | #define SDVO_DETECTED (1 << 2) | |
711 | /* Bits to be preserved when writing */ | |
712 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) | |
713 | #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) | |
714 | ||
715 | /* DVO port control */ | |
716 | #define DVOA 0x61120 | |
717 | #define DVOB 0x61140 | |
718 | #define DVOC 0x61160 | |
719 | #define DVO_ENABLE (1 << 31) | |
720 | #define DVO_PIPE_B_SELECT (1 << 30) | |
721 | #define DVO_PIPE_STALL_UNUSED (0 << 28) | |
722 | #define DVO_PIPE_STALL (1 << 28) | |
723 | #define DVO_PIPE_STALL_TV (2 << 28) | |
724 | #define DVO_PIPE_STALL_MASK (3 << 28) | |
725 | #define DVO_USE_VGA_SYNC (1 << 15) | |
726 | #define DVO_DATA_ORDER_I740 (0 << 14) | |
727 | #define DVO_DATA_ORDER_FP (1 << 14) | |
728 | #define DVO_VSYNC_DISABLE (1 << 11) | |
729 | #define DVO_HSYNC_DISABLE (1 << 10) | |
730 | #define DVO_VSYNC_TRISTATE (1 << 9) | |
731 | #define DVO_HSYNC_TRISTATE (1 << 8) | |
732 | #define DVO_BORDER_ENABLE (1 << 7) | |
733 | #define DVO_DATA_ORDER_GBRG (1 << 6) | |
734 | #define DVO_DATA_ORDER_RGGB (0 << 6) | |
735 | #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) | |
736 | #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) | |
737 | #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) | |
738 | #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) | |
739 | #define DVO_BLANK_ACTIVE_HIGH (1 << 2) | |
740 | #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ | |
741 | #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ | |
742 | #define DVO_PRESERVE_MASK (0x7<<24) | |
743 | #define DVOA_SRCDIM 0x61124 | |
744 | #define DVOB_SRCDIM 0x61144 | |
745 | #define DVOC_SRCDIM 0x61164 | |
746 | #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 | |
747 | #define DVO_SRCDIM_VERTICAL_SHIFT 0 | |
748 | ||
749 | /* LVDS port control */ | |
750 | #define LVDS 0x61180 | |
751 | /* | |
752 | * Enables the LVDS port. This bit must be set before DPLLs are enabled, as | |
753 | * the DPLL semantics change when the LVDS is assigned to that pipe. | |
754 | */ | |
755 | #define LVDS_PORT_EN (1 << 31) | |
756 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ | |
757 | #define LVDS_PIPEB_SELECT (1 << 30) | |
758 | /* | |
759 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per | |
760 | * pixel. | |
761 | */ | |
762 | #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) | |
763 | #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) | |
764 | #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) | |
765 | /* | |
766 | * Controls the A3 data pair, which contains the additional LSBs for 24 bit | |
767 | * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be | |
768 | * on. | |
769 | */ | |
770 | #define LVDS_A3_POWER_MASK (3 << 6) | |
771 | #define LVDS_A3_POWER_DOWN (0 << 6) | |
772 | #define LVDS_A3_POWER_UP (3 << 6) | |
773 | /* | |
774 | * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP | |
775 | * is set. | |
776 | */ | |
777 | #define LVDS_CLKB_POWER_MASK (3 << 4) | |
778 | #define LVDS_CLKB_POWER_DOWN (0 << 4) | |
779 | #define LVDS_CLKB_POWER_UP (3 << 4) | |
780 | /* | |
781 | * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 | |
782 | * setting for whether we are in dual-channel mode. The B3 pair will | |
783 | * additionally only be powered up when LVDS_A3_POWER_UP is set. | |
784 | */ | |
785 | #define LVDS_B0B3_POWER_MASK (3 << 2) | |
786 | #define LVDS_B0B3_POWER_DOWN (0 << 2) | |
787 | #define LVDS_B0B3_POWER_UP (3 << 2) | |
788 | ||
789 | /* Panel power sequencing */ | |
790 | #define PP_STATUS 0x61200 | |
791 | #define PP_ON (1 << 31) | |
792 | /* | |
793 | * Indicates that all dependencies of the panel are on: | |
794 | * | |
795 | * - PLL enabled | |
796 | * - pipe enabled | |
797 | * - LVDS/DVOB/DVOC on | |
798 | */ | |
799 | #define PP_READY (1 << 30) | |
800 | #define PP_SEQUENCE_NONE (0 << 28) | |
801 | #define PP_SEQUENCE_ON (1 << 28) | |
802 | #define PP_SEQUENCE_OFF (2 << 28) | |
803 | #define PP_SEQUENCE_MASK 0x30000000 | |
804 | #define PP_CONTROL 0x61204 | |
805 | #define POWER_TARGET_ON (1 << 0) | |
806 | #define PP_ON_DELAYS 0x61208 | |
807 | #define PP_OFF_DELAYS 0x6120c | |
808 | #define PP_DIVISOR 0x61210 | |
809 | ||
810 | /* Panel fitting */ | |
811 | #define PFIT_CONTROL 0x61230 | |
812 | #define PFIT_ENABLE (1 << 31) | |
813 | #define PFIT_PIPE_MASK (3 << 29) | |
814 | #define PFIT_PIPE_SHIFT 29 | |
815 | #define VERT_INTERP_DISABLE (0 << 10) | |
816 | #define VERT_INTERP_BILINEAR (1 << 10) | |
817 | #define VERT_INTERP_MASK (3 << 10) | |
818 | #define VERT_AUTO_SCALE (1 << 9) | |
819 | #define HORIZ_INTERP_DISABLE (0 << 6) | |
820 | #define HORIZ_INTERP_BILINEAR (1 << 6) | |
821 | #define HORIZ_INTERP_MASK (3 << 6) | |
822 | #define HORIZ_AUTO_SCALE (1 << 5) | |
823 | #define PANEL_8TO6_DITHER_ENABLE (1 << 3) | |
824 | #define PFIT_PGM_RATIOS 0x61234 | |
825 | #define PFIT_VERT_SCALE_MASK 0xfff00000 | |
826 | #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 | |
827 | #define PFIT_AUTO_RATIOS 0x61238 | |
828 | ||
829 | /* Backlight control */ | |
830 | #define BLC_PWM_CTL 0x61254 | |
831 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) | |
832 | #define BLC_PWM_CTL2 0x61250 /* 965+ only */ | |
8ee1c3db | 833 | #define BLM_COMBINATION_MODE (1 << 30) |
585fb111 JB |
834 | /* |
835 | * This is the most significant 15 bits of the number of backlight cycles in a | |
836 | * complete cycle of the modulated backlight control. | |
837 | * | |
838 | * The actual value is this field multiplied by two. | |
839 | */ | |
840 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) | |
841 | #define BLM_LEGACY_MODE (1 << 16) | |
842 | /* | |
843 | * This is the number of cycles out of the backlight modulation cycle for which | |
844 | * the backlight is on. | |
845 | * | |
846 | * This field must be no greater than the number of cycles in the complete | |
847 | * backlight modulation cycle. | |
848 | */ | |
849 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) | |
850 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) | |
851 | ||
852 | /* TV port control */ | |
853 | #define TV_CTL 0x68000 | |
854 | /** Enables the TV encoder */ | |
855 | # define TV_ENC_ENABLE (1 << 31) | |
856 | /** Sources the TV encoder input from pipe B instead of A. */ | |
857 | # define TV_ENC_PIPEB_SELECT (1 << 30) | |
858 | /** Outputs composite video (DAC A only) */ | |
859 | # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) | |
860 | /** Outputs SVideo video (DAC B/C) */ | |
861 | # define TV_ENC_OUTPUT_SVIDEO (1 << 28) | |
862 | /** Outputs Component video (DAC A/B/C) */ | |
863 | # define TV_ENC_OUTPUT_COMPONENT (2 << 28) | |
864 | /** Outputs Composite and SVideo (DAC A/B/C) */ | |
865 | # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) | |
866 | # define TV_TRILEVEL_SYNC (1 << 21) | |
867 | /** Enables slow sync generation (945GM only) */ | |
868 | # define TV_SLOW_SYNC (1 << 20) | |
869 | /** Selects 4x oversampling for 480i and 576p */ | |
870 | # define TV_OVERSAMPLE_4X (0 << 18) | |
871 | /** Selects 2x oversampling for 720p and 1080i */ | |
872 | # define TV_OVERSAMPLE_2X (1 << 18) | |
873 | /** Selects no oversampling for 1080p */ | |
874 | # define TV_OVERSAMPLE_NONE (2 << 18) | |
875 | /** Selects 8x oversampling */ | |
876 | # define TV_OVERSAMPLE_8X (3 << 18) | |
877 | /** Selects progressive mode rather than interlaced */ | |
878 | # define TV_PROGRESSIVE (1 << 17) | |
879 | /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ | |
880 | # define TV_PAL_BURST (1 << 16) | |
881 | /** Field for setting delay of Y compared to C */ | |
882 | # define TV_YC_SKEW_MASK (7 << 12) | |
883 | /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ | |
884 | # define TV_ENC_SDP_FIX (1 << 11) | |
885 | /** | |
886 | * Enables a fix for the 915GM only. | |
887 | * | |
888 | * Not sure what it does. | |
889 | */ | |
890 | # define TV_ENC_C0_FIX (1 << 10) | |
891 | /** Bits that must be preserved by software */ | |
d2d9f232 | 892 | # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) |
585fb111 JB |
893 | # define TV_FUSE_STATE_MASK (3 << 4) |
894 | /** Read-only state that reports all features enabled */ | |
895 | # define TV_FUSE_STATE_ENABLED (0 << 4) | |
896 | /** Read-only state that reports that Macrovision is disabled in hardware*/ | |
897 | # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) | |
898 | /** Read-only state that reports that TV-out is disabled in hardware. */ | |
899 | # define TV_FUSE_STATE_DISABLED (2 << 4) | |
900 | /** Normal operation */ | |
901 | # define TV_TEST_MODE_NORMAL (0 << 0) | |
902 | /** Encoder test pattern 1 - combo pattern */ | |
903 | # define TV_TEST_MODE_PATTERN_1 (1 << 0) | |
904 | /** Encoder test pattern 2 - full screen vertical 75% color bars */ | |
905 | # define TV_TEST_MODE_PATTERN_2 (2 << 0) | |
906 | /** Encoder test pattern 3 - full screen horizontal 75% color bars */ | |
907 | # define TV_TEST_MODE_PATTERN_3 (3 << 0) | |
908 | /** Encoder test pattern 4 - random noise */ | |
909 | # define TV_TEST_MODE_PATTERN_4 (4 << 0) | |
910 | /** Encoder test pattern 5 - linear color ramps */ | |
911 | # define TV_TEST_MODE_PATTERN_5 (5 << 0) | |
912 | /** | |
913 | * This test mode forces the DACs to 50% of full output. | |
914 | * | |
915 | * This is used for load detection in combination with TVDAC_SENSE_MASK | |
916 | */ | |
917 | # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) | |
918 | # define TV_TEST_MODE_MASK (7 << 0) | |
919 | ||
920 | #define TV_DAC 0x68004 | |
921 | /** | |
922 | * Reports that DAC state change logic has reported change (RO). | |
923 | * | |
924 | * This gets cleared when TV_DAC_STATE_EN is cleared | |
925 | */ | |
926 | # define TVDAC_STATE_CHG (1 << 31) | |
927 | # define TVDAC_SENSE_MASK (7 << 28) | |
928 | /** Reports that DAC A voltage is above the detect threshold */ | |
929 | # define TVDAC_A_SENSE (1 << 30) | |
930 | /** Reports that DAC B voltage is above the detect threshold */ | |
931 | # define TVDAC_B_SENSE (1 << 29) | |
932 | /** Reports that DAC C voltage is above the detect threshold */ | |
933 | # define TVDAC_C_SENSE (1 << 28) | |
934 | /** | |
935 | * Enables DAC state detection logic, for load-based TV detection. | |
936 | * | |
937 | * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set | |
938 | * to off, for load detection to work. | |
939 | */ | |
940 | # define TVDAC_STATE_CHG_EN (1 << 27) | |
941 | /** Sets the DAC A sense value to high */ | |
942 | # define TVDAC_A_SENSE_CTL (1 << 26) | |
943 | /** Sets the DAC B sense value to high */ | |
944 | # define TVDAC_B_SENSE_CTL (1 << 25) | |
945 | /** Sets the DAC C sense value to high */ | |
946 | # define TVDAC_C_SENSE_CTL (1 << 24) | |
947 | /** Overrides the ENC_ENABLE and DAC voltage levels */ | |
948 | # define DAC_CTL_OVERRIDE (1 << 7) | |
949 | /** Sets the slew rate. Must be preserved in software */ | |
950 | # define ENC_TVDAC_SLEW_FAST (1 << 6) | |
951 | # define DAC_A_1_3_V (0 << 4) | |
952 | # define DAC_A_1_1_V (1 << 4) | |
953 | # define DAC_A_0_7_V (2 << 4) | |
954 | # define DAC_A_OFF (3 << 4) | |
955 | # define DAC_B_1_3_V (0 << 2) | |
956 | # define DAC_B_1_1_V (1 << 2) | |
957 | # define DAC_B_0_7_V (2 << 2) | |
958 | # define DAC_B_OFF (3 << 2) | |
959 | # define DAC_C_1_3_V (0 << 0) | |
960 | # define DAC_C_1_1_V (1 << 0) | |
961 | # define DAC_C_0_7_V (2 << 0) | |
962 | # define DAC_C_OFF (3 << 0) | |
963 | ||
964 | /** | |
965 | * CSC coefficients are stored in a floating point format with 9 bits of | |
966 | * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, | |
967 | * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with | |
968 | * -1 (0x3) being the only legal negative value. | |
969 | */ | |
970 | #define TV_CSC_Y 0x68010 | |
971 | # define TV_RY_MASK 0x07ff0000 | |
972 | # define TV_RY_SHIFT 16 | |
973 | # define TV_GY_MASK 0x00000fff | |
974 | # define TV_GY_SHIFT 0 | |
975 | ||
976 | #define TV_CSC_Y2 0x68014 | |
977 | # define TV_BY_MASK 0x07ff0000 | |
978 | # define TV_BY_SHIFT 16 | |
979 | /** | |
980 | * Y attenuation for component video. | |
981 | * | |
982 | * Stored in 1.9 fixed point. | |
983 | */ | |
984 | # define TV_AY_MASK 0x000003ff | |
985 | # define TV_AY_SHIFT 0 | |
986 | ||
987 | #define TV_CSC_U 0x68018 | |
988 | # define TV_RU_MASK 0x07ff0000 | |
989 | # define TV_RU_SHIFT 16 | |
990 | # define TV_GU_MASK 0x000007ff | |
991 | # define TV_GU_SHIFT 0 | |
992 | ||
993 | #define TV_CSC_U2 0x6801c | |
994 | # define TV_BU_MASK 0x07ff0000 | |
995 | # define TV_BU_SHIFT 16 | |
996 | /** | |
997 | * U attenuation for component video. | |
998 | * | |
999 | * Stored in 1.9 fixed point. | |
1000 | */ | |
1001 | # define TV_AU_MASK 0x000003ff | |
1002 | # define TV_AU_SHIFT 0 | |
1003 | ||
1004 | #define TV_CSC_V 0x68020 | |
1005 | # define TV_RV_MASK 0x0fff0000 | |
1006 | # define TV_RV_SHIFT 16 | |
1007 | # define TV_GV_MASK 0x000007ff | |
1008 | # define TV_GV_SHIFT 0 | |
1009 | ||
1010 | #define TV_CSC_V2 0x68024 | |
1011 | # define TV_BV_MASK 0x07ff0000 | |
1012 | # define TV_BV_SHIFT 16 | |
1013 | /** | |
1014 | * V attenuation for component video. | |
1015 | * | |
1016 | * Stored in 1.9 fixed point. | |
1017 | */ | |
1018 | # define TV_AV_MASK 0x000007ff | |
1019 | # define TV_AV_SHIFT 0 | |
1020 | ||
1021 | #define TV_CLR_KNOBS 0x68028 | |
1022 | /** 2s-complement brightness adjustment */ | |
1023 | # define TV_BRIGHTNESS_MASK 0xff000000 | |
1024 | # define TV_BRIGHTNESS_SHIFT 24 | |
1025 | /** Contrast adjustment, as a 2.6 unsigned floating point number */ | |
1026 | # define TV_CONTRAST_MASK 0x00ff0000 | |
1027 | # define TV_CONTRAST_SHIFT 16 | |
1028 | /** Saturation adjustment, as a 2.6 unsigned floating point number */ | |
1029 | # define TV_SATURATION_MASK 0x0000ff00 | |
1030 | # define TV_SATURATION_SHIFT 8 | |
1031 | /** Hue adjustment, as an integer phase angle in degrees */ | |
1032 | # define TV_HUE_MASK 0x000000ff | |
1033 | # define TV_HUE_SHIFT 0 | |
1034 | ||
1035 | #define TV_CLR_LEVEL 0x6802c | |
1036 | /** Controls the DAC level for black */ | |
1037 | # define TV_BLACK_LEVEL_MASK 0x01ff0000 | |
1038 | # define TV_BLACK_LEVEL_SHIFT 16 | |
1039 | /** Controls the DAC level for blanking */ | |
1040 | # define TV_BLANK_LEVEL_MASK 0x000001ff | |
1041 | # define TV_BLANK_LEVEL_SHIFT 0 | |
1042 | ||
1043 | #define TV_H_CTL_1 0x68030 | |
1044 | /** Number of pixels in the hsync. */ | |
1045 | # define TV_HSYNC_END_MASK 0x1fff0000 | |
1046 | # define TV_HSYNC_END_SHIFT 16 | |
1047 | /** Total number of pixels minus one in the line (display and blanking). */ | |
1048 | # define TV_HTOTAL_MASK 0x00001fff | |
1049 | # define TV_HTOTAL_SHIFT 0 | |
1050 | ||
1051 | #define TV_H_CTL_2 0x68034 | |
1052 | /** Enables the colorburst (needed for non-component color) */ | |
1053 | # define TV_BURST_ENA (1 << 31) | |
1054 | /** Offset of the colorburst from the start of hsync, in pixels minus one. */ | |
1055 | # define TV_HBURST_START_SHIFT 16 | |
1056 | # define TV_HBURST_START_MASK 0x1fff0000 | |
1057 | /** Length of the colorburst */ | |
1058 | # define TV_HBURST_LEN_SHIFT 0 | |
1059 | # define TV_HBURST_LEN_MASK 0x0001fff | |
1060 | ||
1061 | #define TV_H_CTL_3 0x68038 | |
1062 | /** End of hblank, measured in pixels minus one from start of hsync */ | |
1063 | # define TV_HBLANK_END_SHIFT 16 | |
1064 | # define TV_HBLANK_END_MASK 0x1fff0000 | |
1065 | /** Start of hblank, measured in pixels minus one from start of hsync */ | |
1066 | # define TV_HBLANK_START_SHIFT 0 | |
1067 | # define TV_HBLANK_START_MASK 0x0001fff | |
1068 | ||
1069 | #define TV_V_CTL_1 0x6803c | |
1070 | /** XXX */ | |
1071 | # define TV_NBR_END_SHIFT 16 | |
1072 | # define TV_NBR_END_MASK 0x07ff0000 | |
1073 | /** XXX */ | |
1074 | # define TV_VI_END_F1_SHIFT 8 | |
1075 | # define TV_VI_END_F1_MASK 0x00003f00 | |
1076 | /** XXX */ | |
1077 | # define TV_VI_END_F2_SHIFT 0 | |
1078 | # define TV_VI_END_F2_MASK 0x0000003f | |
1079 | ||
1080 | #define TV_V_CTL_2 0x68040 | |
1081 | /** Length of vsync, in half lines */ | |
1082 | # define TV_VSYNC_LEN_MASK 0x07ff0000 | |
1083 | # define TV_VSYNC_LEN_SHIFT 16 | |
1084 | /** Offset of the start of vsync in field 1, measured in one less than the | |
1085 | * number of half lines. | |
1086 | */ | |
1087 | # define TV_VSYNC_START_F1_MASK 0x00007f00 | |
1088 | # define TV_VSYNC_START_F1_SHIFT 8 | |
1089 | /** | |
1090 | * Offset of the start of vsync in field 2, measured in one less than the | |
1091 | * number of half lines. | |
1092 | */ | |
1093 | # define TV_VSYNC_START_F2_MASK 0x0000007f | |
1094 | # define TV_VSYNC_START_F2_SHIFT 0 | |
1095 | ||
1096 | #define TV_V_CTL_3 0x68044 | |
1097 | /** Enables generation of the equalization signal */ | |
1098 | # define TV_EQUAL_ENA (1 << 31) | |
1099 | /** Length of vsync, in half lines */ | |
1100 | # define TV_VEQ_LEN_MASK 0x007f0000 | |
1101 | # define TV_VEQ_LEN_SHIFT 16 | |
1102 | /** Offset of the start of equalization in field 1, measured in one less than | |
1103 | * the number of half lines. | |
1104 | */ | |
1105 | # define TV_VEQ_START_F1_MASK 0x0007f00 | |
1106 | # define TV_VEQ_START_F1_SHIFT 8 | |
1107 | /** | |
1108 | * Offset of the start of equalization in field 2, measured in one less than | |
1109 | * the number of half lines. | |
1110 | */ | |
1111 | # define TV_VEQ_START_F2_MASK 0x000007f | |
1112 | # define TV_VEQ_START_F2_SHIFT 0 | |
1113 | ||
1114 | #define TV_V_CTL_4 0x68048 | |
1115 | /** | |
1116 | * Offset to start of vertical colorburst, measured in one less than the | |
1117 | * number of lines from vertical start. | |
1118 | */ | |
1119 | # define TV_VBURST_START_F1_MASK 0x003f0000 | |
1120 | # define TV_VBURST_START_F1_SHIFT 16 | |
1121 | /** | |
1122 | * Offset to the end of vertical colorburst, measured in one less than the | |
1123 | * number of lines from the start of NBR. | |
1124 | */ | |
1125 | # define TV_VBURST_END_F1_MASK 0x000000ff | |
1126 | # define TV_VBURST_END_F1_SHIFT 0 | |
1127 | ||
1128 | #define TV_V_CTL_5 0x6804c | |
1129 | /** | |
1130 | * Offset to start of vertical colorburst, measured in one less than the | |
1131 | * number of lines from vertical start. | |
1132 | */ | |
1133 | # define TV_VBURST_START_F2_MASK 0x003f0000 | |
1134 | # define TV_VBURST_START_F2_SHIFT 16 | |
1135 | /** | |
1136 | * Offset to the end of vertical colorburst, measured in one less than the | |
1137 | * number of lines from the start of NBR. | |
1138 | */ | |
1139 | # define TV_VBURST_END_F2_MASK 0x000000ff | |
1140 | # define TV_VBURST_END_F2_SHIFT 0 | |
1141 | ||
1142 | #define TV_V_CTL_6 0x68050 | |
1143 | /** | |
1144 | * Offset to start of vertical colorburst, measured in one less than the | |
1145 | * number of lines from vertical start. | |
1146 | */ | |
1147 | # define TV_VBURST_START_F3_MASK 0x003f0000 | |
1148 | # define TV_VBURST_START_F3_SHIFT 16 | |
1149 | /** | |
1150 | * Offset to the end of vertical colorburst, measured in one less than the | |
1151 | * number of lines from the start of NBR. | |
1152 | */ | |
1153 | # define TV_VBURST_END_F3_MASK 0x000000ff | |
1154 | # define TV_VBURST_END_F3_SHIFT 0 | |
1155 | ||
1156 | #define TV_V_CTL_7 0x68054 | |
1157 | /** | |
1158 | * Offset to start of vertical colorburst, measured in one less than the | |
1159 | * number of lines from vertical start. | |
1160 | */ | |
1161 | # define TV_VBURST_START_F4_MASK 0x003f0000 | |
1162 | # define TV_VBURST_START_F4_SHIFT 16 | |
1163 | /** | |
1164 | * Offset to the end of vertical colorburst, measured in one less than the | |
1165 | * number of lines from the start of NBR. | |
1166 | */ | |
1167 | # define TV_VBURST_END_F4_MASK 0x000000ff | |
1168 | # define TV_VBURST_END_F4_SHIFT 0 | |
1169 | ||
1170 | #define TV_SC_CTL_1 0x68060 | |
1171 | /** Turns on the first subcarrier phase generation DDA */ | |
1172 | # define TV_SC_DDA1_EN (1 << 31) | |
1173 | /** Turns on the first subcarrier phase generation DDA */ | |
1174 | # define TV_SC_DDA2_EN (1 << 30) | |
1175 | /** Turns on the first subcarrier phase generation DDA */ | |
1176 | # define TV_SC_DDA3_EN (1 << 29) | |
1177 | /** Sets the subcarrier DDA to reset frequency every other field */ | |
1178 | # define TV_SC_RESET_EVERY_2 (0 << 24) | |
1179 | /** Sets the subcarrier DDA to reset frequency every fourth field */ | |
1180 | # define TV_SC_RESET_EVERY_4 (1 << 24) | |
1181 | /** Sets the subcarrier DDA to reset frequency every eighth field */ | |
1182 | # define TV_SC_RESET_EVERY_8 (2 << 24) | |
1183 | /** Sets the subcarrier DDA to never reset the frequency */ | |
1184 | # define TV_SC_RESET_NEVER (3 << 24) | |
1185 | /** Sets the peak amplitude of the colorburst.*/ | |
1186 | # define TV_BURST_LEVEL_MASK 0x00ff0000 | |
1187 | # define TV_BURST_LEVEL_SHIFT 16 | |
1188 | /** Sets the increment of the first subcarrier phase generation DDA */ | |
1189 | # define TV_SCDDA1_INC_MASK 0x00000fff | |
1190 | # define TV_SCDDA1_INC_SHIFT 0 | |
1191 | ||
1192 | #define TV_SC_CTL_2 0x68064 | |
1193 | /** Sets the rollover for the second subcarrier phase generation DDA */ | |
1194 | # define TV_SCDDA2_SIZE_MASK 0x7fff0000 | |
1195 | # define TV_SCDDA2_SIZE_SHIFT 16 | |
1196 | /** Sets the increent of the second subcarrier phase generation DDA */ | |
1197 | # define TV_SCDDA2_INC_MASK 0x00007fff | |
1198 | # define TV_SCDDA2_INC_SHIFT 0 | |
1199 | ||
1200 | #define TV_SC_CTL_3 0x68068 | |
1201 | /** Sets the rollover for the third subcarrier phase generation DDA */ | |
1202 | # define TV_SCDDA3_SIZE_MASK 0x7fff0000 | |
1203 | # define TV_SCDDA3_SIZE_SHIFT 16 | |
1204 | /** Sets the increent of the third subcarrier phase generation DDA */ | |
1205 | # define TV_SCDDA3_INC_MASK 0x00007fff | |
1206 | # define TV_SCDDA3_INC_SHIFT 0 | |
1207 | ||
1208 | #define TV_WIN_POS 0x68070 | |
1209 | /** X coordinate of the display from the start of horizontal active */ | |
1210 | # define TV_XPOS_MASK 0x1fff0000 | |
1211 | # define TV_XPOS_SHIFT 16 | |
1212 | /** Y coordinate of the display from the start of vertical active (NBR) */ | |
1213 | # define TV_YPOS_MASK 0x00000fff | |
1214 | # define TV_YPOS_SHIFT 0 | |
1215 | ||
1216 | #define TV_WIN_SIZE 0x68074 | |
1217 | /** Horizontal size of the display window, measured in pixels*/ | |
1218 | # define TV_XSIZE_MASK 0x1fff0000 | |
1219 | # define TV_XSIZE_SHIFT 16 | |
1220 | /** | |
1221 | * Vertical size of the display window, measured in pixels. | |
1222 | * | |
1223 | * Must be even for interlaced modes. | |
1224 | */ | |
1225 | # define TV_YSIZE_MASK 0x00000fff | |
1226 | # define TV_YSIZE_SHIFT 0 | |
1227 | ||
1228 | #define TV_FILTER_CTL_1 0x68080 | |
1229 | /** | |
1230 | * Enables automatic scaling calculation. | |
1231 | * | |
1232 | * If set, the rest of the registers are ignored, and the calculated values can | |
1233 | * be read back from the register. | |
1234 | */ | |
1235 | # define TV_AUTO_SCALE (1 << 31) | |
1236 | /** | |
1237 | * Disables the vertical filter. | |
1238 | * | |
1239 | * This is required on modes more than 1024 pixels wide */ | |
1240 | # define TV_V_FILTER_BYPASS (1 << 29) | |
1241 | /** Enables adaptive vertical filtering */ | |
1242 | # define TV_VADAPT (1 << 28) | |
1243 | # define TV_VADAPT_MODE_MASK (3 << 26) | |
1244 | /** Selects the least adaptive vertical filtering mode */ | |
1245 | # define TV_VADAPT_MODE_LEAST (0 << 26) | |
1246 | /** Selects the moderately adaptive vertical filtering mode */ | |
1247 | # define TV_VADAPT_MODE_MODERATE (1 << 26) | |
1248 | /** Selects the most adaptive vertical filtering mode */ | |
1249 | # define TV_VADAPT_MODE_MOST (3 << 26) | |
1250 | /** | |
1251 | * Sets the horizontal scaling factor. | |
1252 | * | |
1253 | * This should be the fractional part of the horizontal scaling factor divided | |
1254 | * by the oversampling rate. TV_HSCALE should be less than 1, and set to: | |
1255 | * | |
1256 | * (src width - 1) / ((oversample * dest width) - 1) | |
1257 | */ | |
1258 | # define TV_HSCALE_FRAC_MASK 0x00003fff | |
1259 | # define TV_HSCALE_FRAC_SHIFT 0 | |
1260 | ||
1261 | #define TV_FILTER_CTL_2 0x68084 | |
1262 | /** | |
1263 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. | |
1264 | * | |
1265 | * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) | |
1266 | */ | |
1267 | # define TV_VSCALE_INT_MASK 0x00038000 | |
1268 | # define TV_VSCALE_INT_SHIFT 15 | |
1269 | /** | |
1270 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. | |
1271 | * | |
1272 | * \sa TV_VSCALE_INT_MASK | |
1273 | */ | |
1274 | # define TV_VSCALE_FRAC_MASK 0x00007fff | |
1275 | # define TV_VSCALE_FRAC_SHIFT 0 | |
1276 | ||
1277 | #define TV_FILTER_CTL_3 0x68088 | |
1278 | /** | |
1279 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. | |
1280 | * | |
1281 | * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) | |
1282 | * | |
1283 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. | |
1284 | */ | |
1285 | # define TV_VSCALE_IP_INT_MASK 0x00038000 | |
1286 | # define TV_VSCALE_IP_INT_SHIFT 15 | |
1287 | /** | |
1288 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. | |
1289 | * | |
1290 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. | |
1291 | * | |
1292 | * \sa TV_VSCALE_IP_INT_MASK | |
1293 | */ | |
1294 | # define TV_VSCALE_IP_FRAC_MASK 0x00007fff | |
1295 | # define TV_VSCALE_IP_FRAC_SHIFT 0 | |
1296 | ||
1297 | #define TV_CC_CONTROL 0x68090 | |
1298 | # define TV_CC_ENABLE (1 << 31) | |
1299 | /** | |
1300 | * Specifies which field to send the CC data in. | |
1301 | * | |
1302 | * CC data is usually sent in field 0. | |
1303 | */ | |
1304 | # define TV_CC_FID_MASK (1 << 27) | |
1305 | # define TV_CC_FID_SHIFT 27 | |
1306 | /** Sets the horizontal position of the CC data. Usually 135. */ | |
1307 | # define TV_CC_HOFF_MASK 0x03ff0000 | |
1308 | # define TV_CC_HOFF_SHIFT 16 | |
1309 | /** Sets the vertical position of the CC data. Usually 21 */ | |
1310 | # define TV_CC_LINE_MASK 0x0000003f | |
1311 | # define TV_CC_LINE_SHIFT 0 | |
1312 | ||
1313 | #define TV_CC_DATA 0x68094 | |
1314 | # define TV_CC_RDY (1 << 31) | |
1315 | /** Second word of CC data to be transmitted. */ | |
1316 | # define TV_CC_DATA_2_MASK 0x007f0000 | |
1317 | # define TV_CC_DATA_2_SHIFT 16 | |
1318 | /** First word of CC data to be transmitted. */ | |
1319 | # define TV_CC_DATA_1_MASK 0x0000007f | |
1320 | # define TV_CC_DATA_1_SHIFT 0 | |
1321 | ||
1322 | #define TV_H_LUMA_0 0x68100 | |
1323 | #define TV_H_LUMA_59 0x681ec | |
1324 | #define TV_H_CHROMA_0 0x68200 | |
1325 | #define TV_H_CHROMA_59 0x682ec | |
1326 | #define TV_V_LUMA_0 0x68300 | |
1327 | #define TV_V_LUMA_42 0x683a8 | |
1328 | #define TV_V_CHROMA_0 0x68400 | |
1329 | #define TV_V_CHROMA_42 0x684a8 | |
1330 | ||
1331 | /* Display & cursor control */ | |
1332 | ||
1333 | /* Pipe A */ | |
1334 | #define PIPEADSL 0x70000 | |
1335 | #define PIPEACONF 0x70008 | |
1336 | #define PIPEACONF_ENABLE (1<<31) | |
1337 | #define PIPEACONF_DISABLE 0 | |
1338 | #define PIPEACONF_DOUBLE_WIDE (1<<30) | |
1339 | #define I965_PIPECONF_ACTIVE (1<<30) | |
1340 | #define PIPEACONF_SINGLE_WIDE 0 | |
1341 | #define PIPEACONF_PIPE_UNLOCKED 0 | |
1342 | #define PIPEACONF_PIPE_LOCKED (1<<25) | |
1343 | #define PIPEACONF_PALETTE 0 | |
1344 | #define PIPEACONF_GAMMA (1<<24) | |
1345 | #define PIPECONF_FORCE_BORDER (1<<25) | |
1346 | #define PIPECONF_PROGRESSIVE (0 << 21) | |
1347 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) | |
1348 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) | |
1349 | #define PIPEASTAT 0x70024 | |
1350 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) | |
1351 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) | |
1352 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) | |
1353 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) | |
1354 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) | |
1355 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) | |
1356 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) | |
1357 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) | |
1358 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) | |
1359 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) | |
1360 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) | |
1361 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ | |
1362 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ | |
1363 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) | |
1364 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) | |
1365 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) | |
1366 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) | |
1367 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) | |
1368 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) | |
1369 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) | |
1370 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) | |
1371 | #define PIPE_DPST_EVENT_STATUS (1UL<<7) | |
1372 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) | |
1373 | #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) | |
1374 | #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) | |
1375 | #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ | |
1376 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ | |
1377 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) | |
1378 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) | |
1379 | ||
1380 | #define DSPARB 0x70030 | |
1381 | #define DSPARB_CSTART_MASK (0x7f << 7) | |
1382 | #define DSPARB_CSTART_SHIFT 7 | |
1383 | #define DSPARB_BSTART_MASK (0x7f) | |
1384 | #define DSPARB_BSTART_SHIFT 0 | |
1385 | /* | |
1386 | * The two pipe frame counter registers are not synchronized, so | |
1387 | * reading a stable value is somewhat tricky. The following code | |
1388 | * should work: | |
1389 | * | |
1390 | * do { | |
1391 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
1392 | * PIPE_FRAME_HIGH_SHIFT; | |
1393 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> | |
1394 | * PIPE_FRAME_LOW_SHIFT); | |
1395 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
1396 | * PIPE_FRAME_HIGH_SHIFT); | |
1397 | * } while (high1 != high2); | |
1398 | * frame = (high1 << 8) | low1; | |
1399 | */ | |
1400 | #define PIPEAFRAMEHIGH 0x70040 | |
1401 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff | |
1402 | #define PIPE_FRAME_HIGH_SHIFT 0 | |
1403 | #define PIPEAFRAMEPIXEL 0x70044 | |
1404 | #define PIPE_FRAME_LOW_MASK 0xff000000 | |
1405 | #define PIPE_FRAME_LOW_SHIFT 24 | |
1406 | #define PIPE_PIXEL_MASK 0x00ffffff | |
1407 | #define PIPE_PIXEL_SHIFT 0 | |
9880b7a5 JB |
1408 | /* GM45+ just has to be different */ |
1409 | #define PIPEA_FRMCOUNT_GM45 0x70040 | |
1410 | #define PIPEA_FLIPCOUNT_GM45 0x70044 | |
585fb111 JB |
1411 | |
1412 | /* Cursor A & B regs */ | |
1413 | #define CURACNTR 0x70080 | |
14b60391 JB |
1414 | /* Old style CUR*CNTR flags (desktop 8xx) */ |
1415 | #define CURSOR_ENABLE 0x80000000 | |
1416 | #define CURSOR_GAMMA_ENABLE 0x40000000 | |
1417 | #define CURSOR_STRIDE_MASK 0x30000000 | |
1418 | #define CURSOR_FORMAT_SHIFT 24 | |
1419 | #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) | |
1420 | #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) | |
1421 | #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) | |
1422 | #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) | |
1423 | #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) | |
1424 | #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) | |
1425 | /* New style CUR*CNTR flags */ | |
1426 | #define CURSOR_MODE 0x27 | |
585fb111 JB |
1427 | #define CURSOR_MODE_DISABLE 0x00 |
1428 | #define CURSOR_MODE_64_32B_AX 0x07 | |
1429 | #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) | |
14b60391 JB |
1430 | #define MCURSOR_PIPE_SELECT (1 << 28) |
1431 | #define MCURSOR_PIPE_A 0x00 | |
1432 | #define MCURSOR_PIPE_B (1 << 28) | |
585fb111 JB |
1433 | #define MCURSOR_GAMMA_ENABLE (1 << 26) |
1434 | #define CURABASE 0x70084 | |
1435 | #define CURAPOS 0x70088 | |
1436 | #define CURSOR_POS_MASK 0x007FF | |
1437 | #define CURSOR_POS_SIGN 0x8000 | |
1438 | #define CURSOR_X_SHIFT 0 | |
1439 | #define CURSOR_Y_SHIFT 16 | |
14b60391 | 1440 | #define CURSIZE 0x700a0 |
585fb111 JB |
1441 | #define CURBCNTR 0x700c0 |
1442 | #define CURBBASE 0x700c4 | |
1443 | #define CURBPOS 0x700c8 | |
1444 | ||
1445 | /* Display A control */ | |
1446 | #define DSPACNTR 0x70180 | |
1447 | #define DISPLAY_PLANE_ENABLE (1<<31) | |
1448 | #define DISPLAY_PLANE_DISABLE 0 | |
1449 | #define DISPPLANE_GAMMA_ENABLE (1<<30) | |
1450 | #define DISPPLANE_GAMMA_DISABLE 0 | |
1451 | #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) | |
1452 | #define DISPPLANE_8BPP (0x2<<26) | |
1453 | #define DISPPLANE_15_16BPP (0x4<<26) | |
1454 | #define DISPPLANE_16BPP (0x5<<26) | |
1455 | #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) | |
1456 | #define DISPPLANE_32BPP (0x7<<26) | |
1457 | #define DISPPLANE_STEREO_ENABLE (1<<25) | |
1458 | #define DISPPLANE_STEREO_DISABLE 0 | |
1459 | #define DISPPLANE_SEL_PIPE_MASK (1<<24) | |
1460 | #define DISPPLANE_SEL_PIPE_A 0 | |
1461 | #define DISPPLANE_SEL_PIPE_B (1<<24) | |
1462 | #define DISPPLANE_SRC_KEY_ENABLE (1<<22) | |
1463 | #define DISPPLANE_SRC_KEY_DISABLE 0 | |
1464 | #define DISPPLANE_LINE_DOUBLE (1<<20) | |
1465 | #define DISPPLANE_NO_LINE_DOUBLE 0 | |
1466 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 | |
1467 | #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) | |
f544847f | 1468 | #define DISPPLANE_TILED (1<<10) |
585fb111 JB |
1469 | #define DSPAADDR 0x70184 |
1470 | #define DSPASTRIDE 0x70188 | |
1471 | #define DSPAPOS 0x7018C /* reserved */ | |
1472 | #define DSPASIZE 0x70190 | |
1473 | #define DSPASURF 0x7019C /* 965+ only */ | |
1474 | #define DSPATILEOFF 0x701A4 /* 965+ only */ | |
1475 | ||
1476 | /* VBIOS flags */ | |
1477 | #define SWF00 0x71410 | |
1478 | #define SWF01 0x71414 | |
1479 | #define SWF02 0x71418 | |
1480 | #define SWF03 0x7141c | |
1481 | #define SWF04 0x71420 | |
1482 | #define SWF05 0x71424 | |
1483 | #define SWF06 0x71428 | |
1484 | #define SWF10 0x70410 | |
1485 | #define SWF11 0x70414 | |
1486 | #define SWF14 0x71420 | |
1487 | #define SWF30 0x72414 | |
1488 | #define SWF31 0x72418 | |
1489 | #define SWF32 0x7241c | |
1490 | ||
1491 | /* Pipe B */ | |
1492 | #define PIPEBDSL 0x71000 | |
1493 | #define PIPEBCONF 0x71008 | |
1494 | #define PIPEBSTAT 0x71024 | |
1495 | #define PIPEBFRAMEHIGH 0x71040 | |
1496 | #define PIPEBFRAMEPIXEL 0x71044 | |
9880b7a5 JB |
1497 | #define PIPEB_FRMCOUNT_GM45 0x71040 |
1498 | #define PIPEB_FLIPCOUNT_GM45 0x71044 | |
1499 | ||
585fb111 JB |
1500 | |
1501 | /* Display B control */ | |
1502 | #define DSPBCNTR 0x71180 | |
1503 | #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) | |
1504 | #define DISPPLANE_ALPHA_TRANS_DISABLE 0 | |
1505 | #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 | |
1506 | #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) | |
1507 | #define DSPBADDR 0x71184 | |
1508 | #define DSPBSTRIDE 0x71188 | |
1509 | #define DSPBPOS 0x7118C | |
1510 | #define DSPBSIZE 0x71190 | |
1511 | #define DSPBSURF 0x7119C | |
1512 | #define DSPBTILEOFF 0x711A4 | |
1513 | ||
1514 | /* VBIOS regs */ | |
1515 | #define VGACNTRL 0x71400 | |
1516 | # define VGA_DISP_DISABLE (1 << 31) | |
1517 | # define VGA_2X_MODE (1 << 30) | |
1518 | # define VGA_PIPE_B_SELECT (1 << 29) | |
1519 | ||
1520 | #endif /* _I915_REG_H_ */ |