Commit | Line | Data |
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585fb111 JB |
1 | /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
2 | * All Rights Reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the | |
6 | * "Software"), to deal in the Software without restriction, including | |
7 | * without limitation the rights to use, copy, modify, merge, publish, | |
8 | * distribute, sub license, and/or sell copies of the Software, and to | |
9 | * permit persons to whom the Software is furnished to do so, subject to | |
10 | * the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the | |
13 | * next paragraph) shall be included in all copies or substantial portions | |
14 | * of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
19 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef _I915_REG_H_ | |
26 | #define _I915_REG_H_ | |
27 | ||
f0f59a00 VS |
28 | typedef struct { |
29 | uint32_t reg; | |
30 | } i915_reg_t; | |
31 | ||
32 | #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) | |
33 | ||
34 | #define INVALID_MMIO_REG _MMIO(0) | |
35 | ||
36 | static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg) | |
37 | { | |
38 | return reg.reg; | |
39 | } | |
40 | ||
41 | static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) | |
42 | { | |
43 | return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); | |
44 | } | |
45 | ||
46 | static inline bool i915_mmio_reg_valid(i915_reg_t reg) | |
47 | { | |
48 | return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); | |
49 | } | |
50 | ||
5eddb70b | 51 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
f0f59a00 | 52 | #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) |
70d21f0e | 53 | #define _PLANE(plane, a, b) _PIPE(plane, a, b) |
f0f59a00 VS |
54 | #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b) |
55 | #define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a))) | |
56 | #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) | |
2b139522 | 57 | #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) |
f0f59a00 | 58 | #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) |
2d401b17 VS |
59 | #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ |
60 | (pipe) == PIPE_B ? (b) : (c)) | |
f0f59a00 | 61 | #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c)) |
e7d7cad0 JN |
62 | #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \ |
63 | (port) == PORT_B ? (b) : (c)) | |
f0f59a00 | 64 | #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c)) |
2b139522 | 65 | |
98533251 DL |
66 | #define _MASKED_FIELD(mask, value) ({ \ |
67 | if (__builtin_constant_p(mask)) \ | |
68 | BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ | |
69 | if (__builtin_constant_p(value)) \ | |
70 | BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ | |
71 | if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ | |
72 | BUILD_BUG_ON_MSG((value) & ~(mask), \ | |
73 | "Incorrect value for mask"); \ | |
74 | (mask) << 16 | (value); }) | |
75 | #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) | |
76 | #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) | |
77 | ||
78 | ||
6b26c86d | 79 | |
585fb111 JB |
80 | /* PCI config space */ |
81 | ||
1b1d2716 VS |
82 | #define HPLLCC 0xc0 /* 85x only */ |
83 | #define GC_CLOCK_CONTROL_MASK (0x7 << 0) | |
585fb111 JB |
84 | #define GC_CLOCK_133_200 (0 << 0) |
85 | #define GC_CLOCK_100_200 (1 << 0) | |
86 | #define GC_CLOCK_100_133 (2 << 0) | |
1b1d2716 VS |
87 | #define GC_CLOCK_133_266 (3 << 0) |
88 | #define GC_CLOCK_133_200_2 (4 << 0) | |
89 | #define GC_CLOCK_133_266_2 (5 << 0) | |
90 | #define GC_CLOCK_166_266 (6 << 0) | |
91 | #define GC_CLOCK_166_250 (7 << 0) | |
92 | ||
f97108d1 | 93 | #define GCFGC2 0xda |
585fb111 JB |
94 | #define GCFGC 0xf0 /* 915+ only */ |
95 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) | |
96 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) | |
97 | #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) | |
257a7ffc DV |
98 | #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) |
99 | #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) | |
100 | #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) | |
101 | #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) | |
102 | #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) | |
103 | #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) | |
585fb111 | 104 | #define GC_DISPLAY_CLOCK_MASK (7 << 4) |
652c393a JB |
105 | #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) |
106 | #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) | |
107 | #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) | |
108 | #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) | |
109 | #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) | |
110 | #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) | |
111 | #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) | |
112 | #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) | |
113 | #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) | |
114 | #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) | |
115 | #define I945_GC_RENDER_CLOCK_MASK (7 << 0) | |
116 | #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) | |
117 | #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) | |
118 | #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) | |
119 | #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) | |
120 | #define I915_GC_RENDER_CLOCK_MASK (7 << 0) | |
121 | #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) | |
122 | #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) | |
123 | #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) | |
9f49c376 | 124 | #define GCDGMBUS 0xcc |
7f1bdbcb DV |
125 | #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ |
126 | ||
eeccdcac KG |
127 | |
128 | /* Graphics reset regs */ | |
59ea9054 | 129 | #define I915_GDRST 0xc0 /* PCI config register */ |
eeccdcac KG |
130 | #define GRDOM_FULL (0<<2) |
131 | #define GRDOM_RENDER (1<<2) | |
132 | #define GRDOM_MEDIA (3<<2) | |
8a5c2ae7 | 133 | #define GRDOM_MASK (3<<2) |
73bbf6bd | 134 | #define GRDOM_RESET_STATUS (1<<1) |
5ccce180 | 135 | #define GRDOM_RESET_ENABLE (1<<0) |
585fb111 | 136 | |
f0f59a00 | 137 | #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) |
b3a3f03d VS |
138 | #define ILK_GRDOM_FULL (0<<1) |
139 | #define ILK_GRDOM_RENDER (1<<1) | |
140 | #define ILK_GRDOM_MEDIA (3<<1) | |
141 | #define ILK_GRDOM_MASK (3<<1) | |
142 | #define ILK_GRDOM_RESET_ENABLE (1<<0) | |
143 | ||
f0f59a00 | 144 | #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ |
07b7ddd9 JB |
145 | #define GEN6_MBC_SNPCR_SHIFT 21 |
146 | #define GEN6_MBC_SNPCR_MASK (3<<21) | |
147 | #define GEN6_MBC_SNPCR_MAX (0<<21) | |
148 | #define GEN6_MBC_SNPCR_MED (1<<21) | |
149 | #define GEN6_MBC_SNPCR_LOW (2<<21) | |
150 | #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ | |
151 | ||
f0f59a00 VS |
152 | #define VLV_G3DCTL _MMIO(0x9024) |
153 | #define VLV_GSCKGCTL _MMIO(0x9028) | |
9e72b46c | 154 | |
f0f59a00 | 155 | #define GEN6_MBCTL _MMIO(0x0907c) |
5eb719cd DV |
156 | #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) |
157 | #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) | |
158 | #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) | |
159 | #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) | |
160 | #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) | |
161 | ||
f0f59a00 | 162 | #define GEN6_GDRST _MMIO(0x941c) |
cff458c2 EA |
163 | #define GEN6_GRDOM_FULL (1 << 0) |
164 | #define GEN6_GRDOM_RENDER (1 << 1) | |
165 | #define GEN6_GRDOM_MEDIA (1 << 2) | |
166 | #define GEN6_GRDOM_BLT (1 << 3) | |
167 | ||
f0f59a00 VS |
168 | #define RING_PP_DIR_BASE(ring) _MMIO((ring)->mmio_base+0x228) |
169 | #define RING_PP_DIR_BASE_READ(ring) _MMIO((ring)->mmio_base+0x518) | |
170 | #define RING_PP_DIR_DCLV(ring) _MMIO((ring)->mmio_base+0x220) | |
5eb719cd DV |
171 | #define PP_DIR_DCLV_2G 0xffffffff |
172 | ||
f0f59a00 VS |
173 | #define GEN8_RING_PDP_UDW(ring, n) _MMIO((ring)->mmio_base+0x270 + (n) * 8 + 4) |
174 | #define GEN8_RING_PDP_LDW(ring, n) _MMIO((ring)->mmio_base+0x270 + (n) * 8) | |
94e409c1 | 175 | |
f0f59a00 | 176 | #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) |
0cea6502 JM |
177 | #define GEN8_RPCS_ENABLE (1 << 31) |
178 | #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) | |
179 | #define GEN8_RPCS_S_CNT_SHIFT 15 | |
180 | #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) | |
181 | #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) | |
182 | #define GEN8_RPCS_SS_CNT_SHIFT 8 | |
183 | #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) | |
184 | #define GEN8_RPCS_EU_MAX_SHIFT 4 | |
185 | #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) | |
186 | #define GEN8_RPCS_EU_MIN_SHIFT 0 | |
187 | #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) | |
188 | ||
f0f59a00 | 189 | #define GAM_ECOCHK _MMIO(0x4090) |
81e231af | 190 | #define BDW_DISABLE_HDC_INVALIDATION (1<<25) |
5eb719cd | 191 | #define ECOCHK_SNB_BIT (1<<10) |
6381b550 | 192 | #define ECOCHK_DIS_TLB (1<<8) |
e3dff585 | 193 | #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) |
5eb719cd DV |
194 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) |
195 | #define ECOCHK_PPGTT_CACHE4B (0x0<<3) | |
a6f429a5 VS |
196 | #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) |
197 | #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) | |
198 | #define ECOCHK_PPGTT_UC_HSW (0x1<<3) | |
199 | #define ECOCHK_PPGTT_WT_HSW (0x2<<3) | |
200 | #define ECOCHK_PPGTT_WB_HSW (0x3<<3) | |
5eb719cd | 201 | |
f0f59a00 | 202 | #define GAC_ECO_BITS _MMIO(0x14090) |
3b9d7888 | 203 | #define ECOBITS_SNB_BIT (1<<13) |
48ecfa10 DV |
204 | #define ECOBITS_PPGTT_CACHE64B (3<<8) |
205 | #define ECOBITS_PPGTT_CACHE4B (0<<8) | |
206 | ||
f0f59a00 | 207 | #define GAB_CTL _MMIO(0x24000) |
be901a5a DV |
208 | #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) |
209 | ||
f0f59a00 | 210 | #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) |
3774eb50 PZ |
211 | #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) |
212 | #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) | |
213 | #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) | |
214 | #define GEN6_STOLEN_RESERVED_1M (0 << 4) | |
215 | #define GEN6_STOLEN_RESERVED_512K (1 << 4) | |
216 | #define GEN6_STOLEN_RESERVED_256K (2 << 4) | |
217 | #define GEN6_STOLEN_RESERVED_128K (3 << 4) | |
218 | #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) | |
219 | #define GEN7_STOLEN_RESERVED_1M (0 << 5) | |
220 | #define GEN7_STOLEN_RESERVED_256K (1 << 5) | |
221 | #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) | |
222 | #define GEN8_STOLEN_RESERVED_1M (0 << 7) | |
223 | #define GEN8_STOLEN_RESERVED_2M (1 << 7) | |
224 | #define GEN8_STOLEN_RESERVED_4M (2 << 7) | |
225 | #define GEN8_STOLEN_RESERVED_8M (3 << 7) | |
40bae736 | 226 | |
585fb111 JB |
227 | /* VGA stuff */ |
228 | ||
229 | #define VGA_ST01_MDA 0x3ba | |
230 | #define VGA_ST01_CGA 0x3da | |
231 | ||
f0f59a00 | 232 | #define _VGA_MSR_WRITE _MMIO(0x3c2) |
585fb111 JB |
233 | #define VGA_MSR_WRITE 0x3c2 |
234 | #define VGA_MSR_READ 0x3cc | |
235 | #define VGA_MSR_MEM_EN (1<<1) | |
236 | #define VGA_MSR_CGA_MODE (1<<0) | |
237 | ||
5434fd92 | 238 | #define VGA_SR_INDEX 0x3c4 |
f930ddd0 | 239 | #define SR01 1 |
5434fd92 | 240 | #define VGA_SR_DATA 0x3c5 |
585fb111 JB |
241 | |
242 | #define VGA_AR_INDEX 0x3c0 | |
243 | #define VGA_AR_VID_EN (1<<5) | |
244 | #define VGA_AR_DATA_WRITE 0x3c0 | |
245 | #define VGA_AR_DATA_READ 0x3c1 | |
246 | ||
247 | #define VGA_GR_INDEX 0x3ce | |
248 | #define VGA_GR_DATA 0x3cf | |
249 | /* GR05 */ | |
250 | #define VGA_GR_MEM_READ_MODE_SHIFT 3 | |
251 | #define VGA_GR_MEM_READ_MODE_PLANE 1 | |
252 | /* GR06 */ | |
253 | #define VGA_GR_MEM_MODE_MASK 0xc | |
254 | #define VGA_GR_MEM_MODE_SHIFT 2 | |
255 | #define VGA_GR_MEM_A0000_AFFFF 0 | |
256 | #define VGA_GR_MEM_A0000_BFFFF 1 | |
257 | #define VGA_GR_MEM_B0000_B7FFF 2 | |
258 | #define VGA_GR_MEM_B0000_BFFFF 3 | |
259 | ||
260 | #define VGA_DACMASK 0x3c6 | |
261 | #define VGA_DACRX 0x3c7 | |
262 | #define VGA_DACWX 0x3c8 | |
263 | #define VGA_DACDATA 0x3c9 | |
264 | ||
265 | #define VGA_CR_INDEX_MDA 0x3b4 | |
266 | #define VGA_CR_DATA_MDA 0x3b5 | |
267 | #define VGA_CR_INDEX_CGA 0x3d4 | |
268 | #define VGA_CR_DATA_CGA 0x3d5 | |
269 | ||
351e3db2 BV |
270 | /* |
271 | * Instruction field definitions used by the command parser | |
272 | */ | |
273 | #define INSTR_CLIENT_SHIFT 29 | |
274 | #define INSTR_CLIENT_MASK 0xE0000000 | |
275 | #define INSTR_MI_CLIENT 0x0 | |
276 | #define INSTR_BC_CLIENT 0x2 | |
277 | #define INSTR_RC_CLIENT 0x3 | |
278 | #define INSTR_SUBCLIENT_SHIFT 27 | |
279 | #define INSTR_SUBCLIENT_MASK 0x18000000 | |
280 | #define INSTR_MEDIA_SUBCLIENT 0x2 | |
86ef630d MN |
281 | #define INSTR_26_TO_24_MASK 0x7000000 |
282 | #define INSTR_26_TO_24_SHIFT 24 | |
351e3db2 | 283 | |
585fb111 JB |
284 | /* |
285 | * Memory interface instructions used by the kernel | |
286 | */ | |
287 | #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) | |
d4d48035 BV |
288 | /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ |
289 | #define MI_GLOBAL_GTT (1<<22) | |
585fb111 JB |
290 | |
291 | #define MI_NOOP MI_INSTR(0, 0) | |
292 | #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) | |
293 | #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) | |
02e792fb | 294 | #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) |
585fb111 JB |
295 | #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) |
296 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) | |
297 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) | |
298 | #define MI_FLUSH MI_INSTR(0x04, 0) | |
299 | #define MI_READ_FLUSH (1 << 0) | |
300 | #define MI_EXE_FLUSH (1 << 1) | |
301 | #define MI_NO_WRITE_FLUSH (1 << 2) | |
302 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ | |
303 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ | |
1cafd347 | 304 | #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ |
0e79284d BW |
305 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) |
306 | #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) | |
307 | #define MI_ARB_ENABLE (1<<0) | |
308 | #define MI_ARB_DISABLE (0<<0) | |
585fb111 | 309 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
88271da3 JB |
310 | #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) |
311 | #define MI_SUSPEND_FLUSH_EN (1<<0) | |
86ef630d | 312 | #define MI_SET_APPID MI_INSTR(0x0e, 0) |
0206e353 | 313 | #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) |
02e792fb DV |
314 | #define MI_OVERLAY_CONTINUE (0x0<<21) |
315 | #define MI_OVERLAY_ON (0x1<<21) | |
316 | #define MI_OVERLAY_OFF (0x2<<21) | |
585fb111 | 317 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
6b95a207 | 318 | #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) |
1afe3e9d | 319 | #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) |
6b95a207 | 320 | #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) |
cb05d8de DV |
321 | /* IVB has funny definitions for which plane to flip. */ |
322 | #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) | |
323 | #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) | |
324 | #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) | |
325 | #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) | |
326 | #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) | |
327 | #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) | |
830c81db DL |
328 | /* SKL ones */ |
329 | #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8) | |
330 | #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8) | |
331 | #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8) | |
332 | #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8) | |
333 | #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8) | |
334 | #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8) | |
335 | #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8) | |
336 | #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8) | |
337 | #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8) | |
3e78998a | 338 | #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ |
0e79284d BW |
339 | #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
340 | #define MI_SEMAPHORE_UPDATE (1<<21) | |
341 | #define MI_SEMAPHORE_COMPARE (1<<20) | |
342 | #define MI_SEMAPHORE_REGISTER (1<<18) | |
343 | #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ | |
344 | #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ | |
345 | #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ | |
346 | #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ | |
347 | #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ | |
348 | #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ | |
349 | #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ | |
350 | #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ | |
351 | #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ | |
352 | #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ | |
353 | #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ | |
354 | #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ | |
a028c4b0 DV |
355 | #define MI_SEMAPHORE_SYNC_INVALID (3<<16) |
356 | #define MI_SEMAPHORE_SYNC_MASK (3<<16) | |
aa40d6bb ZN |
357 | #define MI_SET_CONTEXT MI_INSTR(0x18, 0) |
358 | #define MI_MM_SPACE_GTT (1<<8) | |
359 | #define MI_MM_SPACE_PHYSICAL (0<<8) | |
360 | #define MI_SAVE_EXT_STATE_EN (1<<3) | |
361 | #define MI_RESTORE_EXT_STATE_EN (1<<2) | |
88271da3 | 362 | #define MI_FORCE_RESTORE (1<<1) |
aa40d6bb | 363 | #define MI_RESTORE_INHIBIT (1<<0) |
4c436d55 AJ |
364 | #define HSW_MI_RS_SAVE_STATE_EN (1<<3) |
365 | #define HSW_MI_RS_RESTORE_STATE_EN (1<<2) | |
3e78998a BW |
366 | #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ |
367 | #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) | |
5ee426ca BW |
368 | #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ |
369 | #define MI_SEMAPHORE_POLL (1<<15) | |
370 | #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) | |
585fb111 | 371 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
8edfbb8b VS |
372 | #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2) |
373 | #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */ | |
374 | #define MI_USE_GGTT (1 << 22) /* g4x+ */ | |
585fb111 JB |
375 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
376 | #define MI_STORE_DWORD_INDEX_SHIFT 2 | |
c6642782 DV |
377 | /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: |
378 | * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw | |
379 | * simply ignores the register load under certain conditions. | |
380 | * - One can actually load arbitrary many arbitrary registers: Simply issue x | |
381 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! | |
382 | */ | |
7ec55f46 | 383 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) |
8670d6f9 | 384 | #define MI_LRI_FORCE_POSTED (1<<12) |
f1afe24f AS |
385 | #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1) |
386 | #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2) | |
0e79284d | 387 | #define MI_SRM_LRM_GLOBAL_GTT (1<<22) |
71a77e07 | 388 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
9a289771 JB |
389 | #define MI_FLUSH_DW_STORE_INDEX (1<<21) |
390 | #define MI_INVALIDATE_TLB (1<<18) | |
391 | #define MI_FLUSH_DW_OP_STOREDW (1<<14) | |
d4d48035 | 392 | #define MI_FLUSH_DW_OP_MASK (3<<14) |
b18b396b | 393 | #define MI_FLUSH_DW_NOTIFY (1<<8) |
9a289771 JB |
394 | #define MI_INVALIDATE_BSD (1<<7) |
395 | #define MI_FLUSH_DW_USE_GTT (1<<2) | |
396 | #define MI_FLUSH_DW_USE_PPGTT (0<<2) | |
f1afe24f AS |
397 | #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1) |
398 | #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) | |
585fb111 | 399 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
d7d4eedd CW |
400 | #define MI_BATCH_NON_SECURE (1) |
401 | /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ | |
0e79284d | 402 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
d7d4eedd | 403 | #define MI_BATCH_PPGTT_HSW (1<<8) |
0e79284d | 404 | #define MI_BATCH_NON_SECURE_HSW (1<<13) |
585fb111 | 405 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
65f56876 | 406 | #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
1c7a0623 | 407 | #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) |
919032ec | 408 | #define MI_BATCH_RESOURCE_STREAMER (1<<10) |
0e79284d | 409 | |
f0f59a00 VS |
410 | #define MI_PREDICATE_SRC0 _MMIO(0x2400) |
411 | #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) | |
412 | #define MI_PREDICATE_SRC1 _MMIO(0x2408) | |
413 | #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) | |
9435373e | 414 | |
f0f59a00 | 415 | #define MI_PREDICATE_RESULT_2 _MMIO(0x2214) |
9435373e RV |
416 | #define LOWER_SLICE_ENABLED (1<<0) |
417 | #define LOWER_SLICE_DISABLED (0<<0) | |
418 | ||
585fb111 JB |
419 | /* |
420 | * 3D instructions used by the kernel | |
421 | */ | |
422 | #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) | |
423 | ||
424 | #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) | |
425 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
426 | #define SC_UPDATE_SCISSOR (0x1<<1) | |
427 | #define SC_ENABLE_MASK (0x1<<0) | |
428 | #define SC_ENABLE (0x1<<0) | |
429 | #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) | |
430 | #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) | |
431 | #define SCI_YMIN_MASK (0xffff<<16) | |
432 | #define SCI_XMIN_MASK (0xffff<<0) | |
433 | #define SCI_YMAX_MASK (0xffff<<16) | |
434 | #define SCI_XMAX_MASK (0xffff<<0) | |
435 | #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
436 | #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) | |
437 | #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) | |
438 | #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) | |
439 | #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) | |
440 | #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) | |
441 | #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) | |
442 | #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) | |
443 | #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) | |
c4d69da1 CW |
444 | |
445 | #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) | |
446 | #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) | |
585fb111 JB |
447 | #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
448 | #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) | |
c4d69da1 CW |
449 | #define BLT_WRITE_A (2<<20) |
450 | #define BLT_WRITE_RGB (1<<20) | |
451 | #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) | |
585fb111 JB |
452 | #define BLT_DEPTH_8 (0<<24) |
453 | #define BLT_DEPTH_16_565 (1<<24) | |
454 | #define BLT_DEPTH_16_1555 (2<<24) | |
455 | #define BLT_DEPTH_32 (3<<24) | |
c4d69da1 CW |
456 | #define BLT_ROP_SRC_COPY (0xcc<<16) |
457 | #define BLT_ROP_COLOR_COPY (0xf0<<16) | |
585fb111 JB |
458 | #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ |
459 | #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ | |
460 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) | |
461 | #define ASYNC_FLIP (1<<22) | |
462 | #define DISPLAY_PLANE_A (0<<20) | |
463 | #define DISPLAY_PLANE_B (1<<20) | |
68d97538 | 464 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) |
0160f055 | 465 | #define PIPE_CONTROL_FLUSH_L3 (1<<27) |
b9e1faa7 | 466 | #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ |
f0a346bd | 467 | #define PIPE_CONTROL_MMIO_WRITE (1<<23) |
114d4f70 | 468 | #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) |
8d315287 | 469 | #define PIPE_CONTROL_CS_STALL (1<<20) |
cc0f6398 | 470 | #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
148b83d0 | 471 | #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) |
9d971b37 | 472 | #define PIPE_CONTROL_QW_WRITE (1<<14) |
d4d48035 | 473 | #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) |
9d971b37 KG |
474 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) |
475 | #define PIPE_CONTROL_WRITE_FLUSH (1<<12) | |
8d315287 | 476 | #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ |
9d971b37 KG |
477 | #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ |
478 | #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ | |
479 | #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) | |
480 | #define PIPE_CONTROL_NOTIFY (1<<8) | |
3e78998a | 481 | #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ |
c82435bb | 482 | #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) |
8d315287 JB |
483 | #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) |
484 | #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) | |
485 | #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) | |
9d971b37 | 486 | #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) |
8d315287 | 487 | #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) |
e552eb70 | 488 | #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ |
585fb111 | 489 | |
3a6fa984 BV |
490 | /* |
491 | * Commands used only by the command parser | |
492 | */ | |
493 | #define MI_SET_PREDICATE MI_INSTR(0x01, 0) | |
494 | #define MI_ARB_CHECK MI_INSTR(0x05, 0) | |
495 | #define MI_RS_CONTROL MI_INSTR(0x06, 0) | |
496 | #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) | |
497 | #define MI_PREDICATE MI_INSTR(0x0C, 0) | |
498 | #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) | |
499 | #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) | |
9c640d1d | 500 | #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) |
3a6fa984 BV |
501 | #define MI_URB_CLEAR MI_INSTR(0x19, 0) |
502 | #define MI_UPDATE_GTT MI_INSTR(0x23, 0) | |
503 | #define MI_CLFLUSH MI_INSTR(0x27, 0) | |
d4d48035 BV |
504 | #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) |
505 | #define MI_REPORT_PERF_COUNT_GGTT (1<<0) | |
3a6fa984 BV |
506 | #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) |
507 | #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) | |
508 | #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) | |
509 | #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) | |
510 | #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) | |
511 | ||
512 | #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) | |
513 | #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) | |
f0a346bd BV |
514 | #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) |
515 | #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) | |
3a6fa984 BV |
516 | #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) |
517 | #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) | |
518 | #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ | |
519 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) | |
520 | #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ | |
521 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) | |
522 | #define GFX_OP_3DSTATE_SO_DECL_LIST \ | |
523 | ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) | |
524 | ||
525 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ | |
526 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) | |
527 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ | |
528 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) | |
529 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ | |
530 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) | |
531 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ | |
532 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) | |
533 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ | |
534 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) | |
535 | ||
536 | #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) | |
537 | ||
538 | #define COLOR_BLT ((0x2<<29)|(0x40<<22)) | |
539 | #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) | |
dc96e9b8 | 540 | |
5947de9b BV |
541 | /* |
542 | * Registers used only by the command parser | |
543 | */ | |
f0f59a00 VS |
544 | #define BCS_SWCTRL _MMIO(0x22200) |
545 | ||
546 | #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) | |
547 | #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) | |
548 | #define HS_INVOCATION_COUNT _MMIO(0x2300) | |
549 | #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) | |
550 | #define DS_INVOCATION_COUNT _MMIO(0x2308) | |
551 | #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) | |
552 | #define IA_VERTICES_COUNT _MMIO(0x2310) | |
553 | #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) | |
554 | #define IA_PRIMITIVES_COUNT _MMIO(0x2318) | |
555 | #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) | |
556 | #define VS_INVOCATION_COUNT _MMIO(0x2320) | |
557 | #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) | |
558 | #define GS_INVOCATION_COUNT _MMIO(0x2328) | |
559 | #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) | |
560 | #define GS_PRIMITIVES_COUNT _MMIO(0x2330) | |
561 | #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) | |
562 | #define CL_INVOCATION_COUNT _MMIO(0x2338) | |
563 | #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) | |
564 | #define CL_PRIMITIVES_COUNT _MMIO(0x2340) | |
565 | #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) | |
566 | #define PS_INVOCATION_COUNT _MMIO(0x2348) | |
567 | #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) | |
568 | #define PS_DEPTH_COUNT _MMIO(0x2350) | |
569 | #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) | |
5947de9b BV |
570 | |
571 | /* There are the 4 64-bit counter registers, one for each stream output */ | |
f0f59a00 VS |
572 | #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) |
573 | #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) | |
5947de9b | 574 | |
f0f59a00 VS |
575 | #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) |
576 | #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) | |
113a0476 | 577 | |
f0f59a00 VS |
578 | #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) |
579 | #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) | |
580 | #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) | |
581 | #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) | |
582 | #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C) | |
583 | #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) | |
113a0476 | 584 | |
f0f59a00 VS |
585 | #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) |
586 | #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) | |
587 | #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) | |
7b9748cb | 588 | |
f0f59a00 | 589 | #define OACONTROL _MMIO(0x2360) |
180b813c | 590 | |
220375aa BV |
591 | #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 |
592 | #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 | |
f0f59a00 | 593 | #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) |
220375aa | 594 | |
dc96e9b8 CW |
595 | /* |
596 | * Reset registers | |
597 | */ | |
f0f59a00 | 598 | #define DEBUG_RESET_I830 _MMIO(0x6070) |
dc96e9b8 CW |
599 | #define DEBUG_RESET_FULL (1<<7) |
600 | #define DEBUG_RESET_RENDER (1<<8) | |
601 | #define DEBUG_RESET_DISPLAY (1<<9) | |
602 | ||
57f350b6 | 603 | /* |
5a09ae9f JN |
604 | * IOSF sideband |
605 | */ | |
f0f59a00 | 606 | #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) |
5a09ae9f JN |
607 | #define IOSF_DEVFN_SHIFT 24 |
608 | #define IOSF_OPCODE_SHIFT 16 | |
609 | #define IOSF_PORT_SHIFT 8 | |
610 | #define IOSF_BYTE_ENABLES_SHIFT 4 | |
611 | #define IOSF_BAR_SHIFT 1 | |
612 | #define IOSF_SB_BUSY (1<<0) | |
4688d45f JN |
613 | #define IOSF_PORT_BUNIT 0x03 |
614 | #define IOSF_PORT_PUNIT 0x04 | |
5a09ae9f JN |
615 | #define IOSF_PORT_NC 0x11 |
616 | #define IOSF_PORT_DPIO 0x12 | |
e9f882a3 JN |
617 | #define IOSF_PORT_GPIO_NC 0x13 |
618 | #define IOSF_PORT_CCK 0x14 | |
4688d45f JN |
619 | #define IOSF_PORT_DPIO_2 0x1a |
620 | #define IOSF_PORT_FLISDSI 0x1b | |
dfb19ed2 D |
621 | #define IOSF_PORT_GPIO_SC 0x48 |
622 | #define IOSF_PORT_GPIO_SUS 0xa8 | |
4688d45f | 623 | #define IOSF_PORT_CCU 0xa9 |
f0f59a00 VS |
624 | #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) |
625 | #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) | |
5a09ae9f | 626 | |
30a970c6 JB |
627 | /* See configdb bunit SB addr map */ |
628 | #define BUNIT_REG_BISOC 0x11 | |
629 | ||
30a970c6 | 630 | #define PUNIT_REG_DSPFREQ 0x36 |
383c5a6a VS |
631 | #define DSPFREQSTAT_SHIFT_CHV 24 |
632 | #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) | |
633 | #define DSPFREQGUAR_SHIFT_CHV 8 | |
634 | #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) | |
30a970c6 JB |
635 | #define DSPFREQSTAT_SHIFT 30 |
636 | #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) | |
637 | #define DSPFREQGUAR_SHIFT 14 | |
638 | #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) | |
cfb41411 VS |
639 | #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ |
640 | #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ | |
641 | #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ | |
26972b0a VS |
642 | #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) |
643 | #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) | |
644 | #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) | |
645 | #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) | |
646 | #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) | |
647 | #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) | |
648 | #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) | |
649 | #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) | |
650 | #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) | |
651 | #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) | |
652 | #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) | |
653 | #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) | |
a30180a5 ID |
654 | |
655 | /* See the PUNIT HAS v0.8 for the below bits */ | |
656 | enum punit_power_well { | |
cd02ac52 | 657 | /* These numbers are fixed and must match the position of the pw bits */ |
a30180a5 ID |
658 | PUNIT_POWER_WELL_RENDER = 0, |
659 | PUNIT_POWER_WELL_MEDIA = 1, | |
660 | PUNIT_POWER_WELL_DISP2D = 3, | |
661 | PUNIT_POWER_WELL_DPIO_CMN_BC = 5, | |
662 | PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, | |
663 | PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, | |
664 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, | |
665 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, | |
666 | PUNIT_POWER_WELL_DPIO_RX0 = 10, | |
667 | PUNIT_POWER_WELL_DPIO_RX1 = 11, | |
5d6f7ea7 | 668 | PUNIT_POWER_WELL_DPIO_CMN_D = 12, |
a30180a5 | 669 | |
cd02ac52 | 670 | /* Not actual bit groups. Used as IDs for lookup_power_well() */ |
56fcfd63 | 671 | PUNIT_POWER_WELL_ALWAYS_ON, |
a30180a5 ID |
672 | }; |
673 | ||
94dd5138 | 674 | enum skl_disp_power_wells { |
cd02ac52 | 675 | /* These numbers are fixed and must match the position of the pw bits */ |
94dd5138 S |
676 | SKL_DISP_PW_MISC_IO, |
677 | SKL_DISP_PW_DDI_A_E, | |
678 | SKL_DISP_PW_DDI_B, | |
679 | SKL_DISP_PW_DDI_C, | |
680 | SKL_DISP_PW_DDI_D, | |
681 | SKL_DISP_PW_1 = 14, | |
682 | SKL_DISP_PW_2, | |
56fcfd63 | 683 | |
cd02ac52 | 684 | /* Not actual bit groups. Used as IDs for lookup_power_well() */ |
56fcfd63 | 685 | SKL_DISP_PW_ALWAYS_ON, |
9f836f90 | 686 | SKL_DISP_PW_DC_OFF, |
94dd5138 S |
687 | }; |
688 | ||
689 | #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2)) | |
690 | #define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1)) | |
691 | ||
02f4c9e0 CML |
692 | #define PUNIT_REG_PWRGT_CTRL 0x60 |
693 | #define PUNIT_REG_PWRGT_STATUS 0x61 | |
a30180a5 ID |
694 | #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) |
695 | #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) | |
696 | #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) | |
697 | #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) | |
698 | #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) | |
02f4c9e0 | 699 | |
5a09ae9f JN |
700 | #define PUNIT_REG_GPU_LFM 0xd3 |
701 | #define PUNIT_REG_GPU_FREQ_REQ 0xd4 | |
702 | #define PUNIT_REG_GPU_FREQ_STS 0xd8 | |
c8e9627d | 703 | #define GPLLENABLE (1<<4) |
e8474409 | 704 | #define GENFREQSTATUS (1<<0) |
5a09ae9f | 705 | #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc |
31685c25 | 706 | #define PUNIT_REG_CZ_TIMESTAMP 0xce |
5a09ae9f JN |
707 | |
708 | #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ | |
709 | #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ | |
710 | ||
095acd5f D |
711 | #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 |
712 | #define FB_GFX_FREQ_FUSE_MASK 0xff | |
713 | #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 | |
714 | #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 | |
715 | #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 | |
716 | ||
717 | #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 | |
718 | #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 | |
719 | ||
fc1ac8de VS |
720 | #define PUNIT_REG_DDR_SETUP2 0x139 |
721 | #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) | |
722 | #define FORCE_DDR_LOW_FREQ (1 << 1) | |
723 | #define FORCE_DDR_HIGH_FREQ (1 << 0) | |
724 | ||
2b6b3a09 D |
725 | #define PUNIT_GPU_STATUS_REG 0xdb |
726 | #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 | |
727 | #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff | |
728 | #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 | |
729 | #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff | |
730 | ||
731 | #define PUNIT_GPU_DUTYCYCLE_REG 0xdf | |
732 | #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 | |
733 | #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff | |
734 | ||
5a09ae9f JN |
735 | #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c |
736 | #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 | |
737 | #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 | |
738 | #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 | |
739 | #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 | |
740 | #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 | |
741 | #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 | |
742 | #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 | |
743 | #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 | |
744 | #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 | |
745 | ||
3ef62342 D |
746 | #define VLV_TURBO_SOC_OVERRIDE 0x04 |
747 | #define VLV_OVERRIDE_EN 1 | |
748 | #define VLV_SOC_TDP_EN (1 << 1) | |
749 | #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) | |
750 | #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) | |
751 | ||
31685c25 | 752 | #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 |
31685c25 | 753 | |
be4fc046 | 754 | /* vlv2 north clock has */ |
24eb2d59 CML |
755 | #define CCK_FUSE_REG 0x8 |
756 | #define CCK_FUSE_HPLL_FREQ_MASK 0x3 | |
be4fc046 | 757 | #define CCK_REG_DSI_PLL_FUSE 0x44 |
758 | #define CCK_REG_DSI_PLL_CONTROL 0x48 | |
759 | #define DSI_PLL_VCO_EN (1 << 31) | |
760 | #define DSI_PLL_LDO_GATE (1 << 30) | |
761 | #define DSI_PLL_P1_POST_DIV_SHIFT 17 | |
762 | #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) | |
763 | #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) | |
764 | #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) | |
765 | #define DSI_PLL_MUX_MASK (3 << 9) | |
766 | #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) | |
767 | #define DSI_PLL_MUX_DSI0_CCK (1 << 10) | |
768 | #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) | |
769 | #define DSI_PLL_MUX_DSI1_CCK (1 << 9) | |
770 | #define DSI_PLL_CLK_GATE_MASK (0xf << 5) | |
771 | #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) | |
772 | #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) | |
773 | #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) | |
774 | #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) | |
775 | #define DSI_PLL_LOCK (1 << 0) | |
776 | #define CCK_REG_DSI_PLL_DIVIDER 0x4c | |
777 | #define DSI_PLL_LFSR (1 << 31) | |
778 | #define DSI_PLL_FRACTION_EN (1 << 30) | |
779 | #define DSI_PLL_FRAC_COUNTER_SHIFT 27 | |
780 | #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) | |
781 | #define DSI_PLL_USYNC_CNT_SHIFT 18 | |
782 | #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) | |
783 | #define DSI_PLL_N1_DIV_SHIFT 16 | |
784 | #define DSI_PLL_N1_DIV_MASK (3 << 16) | |
785 | #define DSI_PLL_M1_DIV_SHIFT 0 | |
786 | #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) | |
bfa7df01 | 787 | #define CCK_CZ_CLOCK_CONTROL 0x62 |
30a970c6 | 788 | #define CCK_DISPLAY_CLOCK_CONTROL 0x6b |
87d5d259 VK |
789 | #define CCK_TRUNK_FORCE_ON (1 << 17) |
790 | #define CCK_TRUNK_FORCE_OFF (1 << 16) | |
791 | #define CCK_FREQUENCY_STATUS (0x1f << 8) | |
792 | #define CCK_FREQUENCY_STATUS_SHIFT 8 | |
793 | #define CCK_FREQUENCY_VALUES (0x1f << 0) | |
be4fc046 | 794 | |
0e767189 VS |
795 | /** |
796 | * DOC: DPIO | |
797 | * | |
eee21566 | 798 | * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI |
0e767189 VS |
799 | * ports. DPIO is the name given to such a display PHY. These PHYs |
800 | * don't follow the standard programming model using direct MMIO | |
801 | * registers, and instead their registers must be accessed trough IOSF | |
802 | * sideband. VLV has one such PHY for driving ports B and C, and CHV | |
803 | * adds another PHY for driving port D. Each PHY responds to specific | |
804 | * IOSF-SB port. | |
805 | * | |
806 | * Each display PHY is made up of one or two channels. Each channel | |
807 | * houses a common lane part which contains the PLL and other common | |
808 | * logic. CH0 common lane also contains the IOSF-SB logic for the | |
809 | * Common Register Interface (CRI) ie. the DPIO registers. CRI clock | |
810 | * must be running when any DPIO registers are accessed. | |
811 | * | |
812 | * In addition to having their own registers, the PHYs are also | |
813 | * controlled through some dedicated signals from the display | |
814 | * controller. These include PLL reference clock enable, PLL enable, | |
815 | * and CRI clock selection, for example. | |
816 | * | |
817 | * Eeach channel also has two splines (also called data lanes), and | |
818 | * each spline is made up of one Physical Access Coding Sub-Layer | |
819 | * (PCS) block and two TX lanes. So each channel has two PCS blocks | |
820 | * and four TX lanes. The TX lanes are used as DP lanes or TMDS | |
821 | * data/clock pairs depending on the output type. | |
822 | * | |
823 | * Additionally the PHY also contains an AUX lane with AUX blocks | |
824 | * for each channel. This is used for DP AUX communication, but | |
825 | * this fact isn't really relevant for the driver since AUX is | |
826 | * controlled from the display controller side. No DPIO registers | |
827 | * need to be accessed during AUX communication, | |
828 | * | |
eee21566 | 829 | * Generally on VLV/CHV the common lane corresponds to the pipe and |
32197aab | 830 | * the spline (PCS/TX) corresponds to the port. |
0e767189 VS |
831 | * |
832 | * For dual channel PHY (VLV/CHV): | |
833 | * | |
834 | * pipe A == CMN/PLL/REF CH0 | |
54d9d493 | 835 | * |
0e767189 VS |
836 | * pipe B == CMN/PLL/REF CH1 |
837 | * | |
838 | * port B == PCS/TX CH0 | |
839 | * | |
840 | * port C == PCS/TX CH1 | |
841 | * | |
842 | * This is especially important when we cross the streams | |
843 | * ie. drive port B with pipe B, or port C with pipe A. | |
844 | * | |
845 | * For single channel PHY (CHV): | |
846 | * | |
847 | * pipe C == CMN/PLL/REF CH0 | |
848 | * | |
849 | * port D == PCS/TX CH0 | |
850 | * | |
eee21566 ID |
851 | * On BXT the entire PHY channel corresponds to the port. That means |
852 | * the PLL is also now associated with the port rather than the pipe, | |
853 | * and so the clock needs to be routed to the appropriate transcoder. | |
854 | * Port A PLL is directly connected to transcoder EDP and port B/C | |
855 | * PLLs can be routed to any transcoder A/B/C. | |
856 | * | |
857 | * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is | |
858 | * digital port D (CHV) or port A (BXT). | |
598fac6b | 859 | * |
f03d8ede DCLP |
860 | * |
861 | * Dual channel PHY (VLV/CHV/BXT) | |
862 | * --------------------------------- | |
863 | * | CH0 | CH1 | | |
864 | * | CMN/PLL/REF | CMN/PLL/REF | | |
865 | * |---------------|---------------| Display PHY | |
866 | * | PCS01 | PCS23 | PCS01 | PCS23 | | |
867 | * |-------|-------|-------|-------| | |
868 | * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| | |
869 | * --------------------------------- | |
870 | * | DDI0 | DDI1 | DP/HDMI ports | |
871 | * --------------------------------- | |
872 | * | |
873 | * Single channel PHY (CHV/BXT) | |
874 | * ----------------- | |
875 | * | CH0 | | |
876 | * | CMN/PLL/REF | | |
877 | * |---------------| Display PHY | |
878 | * | PCS01 | PCS23 | | |
879 | * |-------|-------| | |
880 | * |TX0|TX1|TX2|TX3| | |
881 | * ----------------- | |
882 | * | DDI2 | DP/HDMI port | |
883 | * ----------------- | |
57f350b6 | 884 | */ |
5a09ae9f | 885 | #define DPIO_DEVFN 0 |
5a09ae9f | 886 | |
f0f59a00 | 887 | #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) |
57f350b6 JB |
888 | #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ |
889 | #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ | |
890 | #define DPIO_SFR_BYPASS (1<<1) | |
40e9cf64 | 891 | #define DPIO_CMNRST (1<<0) |
57f350b6 | 892 | |
e4607fcf CML |
893 | #define DPIO_PHY(pipe) ((pipe) >> 1) |
894 | #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) | |
895 | ||
598fac6b DV |
896 | /* |
897 | * Per pipe/PLL DPIO regs | |
898 | */ | |
ab3c759a | 899 | #define _VLV_PLL_DW3_CH0 0x800c |
57f350b6 | 900 | #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ |
598fac6b DV |
901 | #define DPIO_POST_DIV_DAC 0 |
902 | #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ | |
903 | #define DPIO_POST_DIV_LVDS1 2 | |
904 | #define DPIO_POST_DIV_LVDS2 3 | |
57f350b6 JB |
905 | #define DPIO_K_SHIFT (24) /* 4 bits */ |
906 | #define DPIO_P1_SHIFT (21) /* 3 bits */ | |
907 | #define DPIO_P2_SHIFT (16) /* 5 bits */ | |
908 | #define DPIO_N_SHIFT (12) /* 4 bits */ | |
909 | #define DPIO_ENABLE_CALIBRATION (1<<11) | |
910 | #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ | |
911 | #define DPIO_M2DIV_MASK 0xff | |
ab3c759a CML |
912 | #define _VLV_PLL_DW3_CH1 0x802c |
913 | #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) | |
57f350b6 | 914 | |
ab3c759a | 915 | #define _VLV_PLL_DW5_CH0 0x8014 |
57f350b6 JB |
916 | #define DPIO_REFSEL_OVERRIDE 27 |
917 | #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ | |
918 | #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ | |
919 | #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ | |
b56747aa | 920 | #define DPIO_PLL_REFCLK_SEL_MASK 3 |
57f350b6 JB |
921 | #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
922 | #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ | |
ab3c759a CML |
923 | #define _VLV_PLL_DW5_CH1 0x8034 |
924 | #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) | |
57f350b6 | 925 | |
ab3c759a CML |
926 | #define _VLV_PLL_DW7_CH0 0x801c |
927 | #define _VLV_PLL_DW7_CH1 0x803c | |
928 | #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) | |
57f350b6 | 929 | |
ab3c759a CML |
930 | #define _VLV_PLL_DW8_CH0 0x8040 |
931 | #define _VLV_PLL_DW8_CH1 0x8060 | |
932 | #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) | |
598fac6b | 933 | |
ab3c759a CML |
934 | #define VLV_PLL_DW9_BCAST 0xc044 |
935 | #define _VLV_PLL_DW9_CH0 0x8044 | |
936 | #define _VLV_PLL_DW9_CH1 0x8064 | |
937 | #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) | |
598fac6b | 938 | |
ab3c759a CML |
939 | #define _VLV_PLL_DW10_CH0 0x8048 |
940 | #define _VLV_PLL_DW10_CH1 0x8068 | |
941 | #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) | |
598fac6b | 942 | |
ab3c759a CML |
943 | #define _VLV_PLL_DW11_CH0 0x804c |
944 | #define _VLV_PLL_DW11_CH1 0x806c | |
945 | #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) | |
57f350b6 | 946 | |
ab3c759a CML |
947 | /* Spec for ref block start counts at DW10 */ |
948 | #define VLV_REF_DW13 0x80ac | |
598fac6b | 949 | |
ab3c759a | 950 | #define VLV_CMN_DW0 0x8100 |
dc96e9b8 | 951 | |
598fac6b DV |
952 | /* |
953 | * Per DDI channel DPIO regs | |
954 | */ | |
955 | ||
ab3c759a CML |
956 | #define _VLV_PCS_DW0_CH0 0x8200 |
957 | #define _VLV_PCS_DW0_CH1 0x8400 | |
598fac6b DV |
958 | #define DPIO_PCS_TX_LANE2_RESET (1<<16) |
959 | #define DPIO_PCS_TX_LANE1_RESET (1<<7) | |
570e2a74 VS |
960 | #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4) |
961 | #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3) | |
ab3c759a | 962 | #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) |
598fac6b | 963 | |
97fd4d5c VS |
964 | #define _VLV_PCS01_DW0_CH0 0x200 |
965 | #define _VLV_PCS23_DW0_CH0 0x400 | |
966 | #define _VLV_PCS01_DW0_CH1 0x2600 | |
967 | #define _VLV_PCS23_DW0_CH1 0x2800 | |
968 | #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) | |
969 | #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) | |
970 | ||
ab3c759a CML |
971 | #define _VLV_PCS_DW1_CH0 0x8204 |
972 | #define _VLV_PCS_DW1_CH1 0x8404 | |
d2152b25 | 973 | #define CHV_PCS_REQ_SOFTRESET_EN (1<<23) |
598fac6b DV |
974 | #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) |
975 | #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) | |
976 | #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) | |
977 | #define DPIO_PCS_CLK_SOFT_RESET (1<<5) | |
ab3c759a CML |
978 | #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) |
979 | ||
97fd4d5c VS |
980 | #define _VLV_PCS01_DW1_CH0 0x204 |
981 | #define _VLV_PCS23_DW1_CH0 0x404 | |
982 | #define _VLV_PCS01_DW1_CH1 0x2604 | |
983 | #define _VLV_PCS23_DW1_CH1 0x2804 | |
984 | #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) | |
985 | #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) | |
986 | ||
ab3c759a CML |
987 | #define _VLV_PCS_DW8_CH0 0x8220 |
988 | #define _VLV_PCS_DW8_CH1 0x8420 | |
9197c88b VS |
989 | #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) |
990 | #define CHV_PCS_USEDCLKCHANNEL (1 << 21) | |
ab3c759a CML |
991 | #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) |
992 | ||
993 | #define _VLV_PCS01_DW8_CH0 0x0220 | |
994 | #define _VLV_PCS23_DW8_CH0 0x0420 | |
995 | #define _VLV_PCS01_DW8_CH1 0x2620 | |
996 | #define _VLV_PCS23_DW8_CH1 0x2820 | |
997 | #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) | |
998 | #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) | |
999 | ||
1000 | #define _VLV_PCS_DW9_CH0 0x8224 | |
1001 | #define _VLV_PCS_DW9_CH1 0x8424 | |
a02ef3c7 VS |
1002 | #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13) |
1003 | #define DPIO_PCS_TX2MARGIN_000 (0<<13) | |
1004 | #define DPIO_PCS_TX2MARGIN_101 (1<<13) | |
1005 | #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10) | |
1006 | #define DPIO_PCS_TX1MARGIN_000 (0<<10) | |
1007 | #define DPIO_PCS_TX1MARGIN_101 (1<<10) | |
ab3c759a CML |
1008 | #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) |
1009 | ||
a02ef3c7 VS |
1010 | #define _VLV_PCS01_DW9_CH0 0x224 |
1011 | #define _VLV_PCS23_DW9_CH0 0x424 | |
1012 | #define _VLV_PCS01_DW9_CH1 0x2624 | |
1013 | #define _VLV_PCS23_DW9_CH1 0x2824 | |
1014 | #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) | |
1015 | #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) | |
1016 | ||
9d556c99 CML |
1017 | #define _CHV_PCS_DW10_CH0 0x8228 |
1018 | #define _CHV_PCS_DW10_CH1 0x8428 | |
1019 | #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) | |
1020 | #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) | |
a02ef3c7 VS |
1021 | #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24) |
1022 | #define DPIO_PCS_TX2DEEMP_9P5 (0<<24) | |
1023 | #define DPIO_PCS_TX2DEEMP_6P0 (2<<24) | |
1024 | #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16) | |
1025 | #define DPIO_PCS_TX1DEEMP_9P5 (0<<16) | |
1026 | #define DPIO_PCS_TX1DEEMP_6P0 (2<<16) | |
9d556c99 CML |
1027 | #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) |
1028 | ||
1966e59e VS |
1029 | #define _VLV_PCS01_DW10_CH0 0x0228 |
1030 | #define _VLV_PCS23_DW10_CH0 0x0428 | |
1031 | #define _VLV_PCS01_DW10_CH1 0x2628 | |
1032 | #define _VLV_PCS23_DW10_CH1 0x2828 | |
1033 | #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) | |
1034 | #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) | |
1035 | ||
ab3c759a CML |
1036 | #define _VLV_PCS_DW11_CH0 0x822c |
1037 | #define _VLV_PCS_DW11_CH1 0x842c | |
2e523e98 | 1038 | #define DPIO_TX2_STAGGER_MASK(x) ((x)<<24) |
570e2a74 VS |
1039 | #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) |
1040 | #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) | |
1041 | #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) | |
ab3c759a CML |
1042 | #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) |
1043 | ||
570e2a74 VS |
1044 | #define _VLV_PCS01_DW11_CH0 0x022c |
1045 | #define _VLV_PCS23_DW11_CH0 0x042c | |
1046 | #define _VLV_PCS01_DW11_CH1 0x262c | |
1047 | #define _VLV_PCS23_DW11_CH1 0x282c | |
142d2eca VS |
1048 | #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) |
1049 | #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) | |
570e2a74 | 1050 | |
2e523e98 VS |
1051 | #define _VLV_PCS01_DW12_CH0 0x0230 |
1052 | #define _VLV_PCS23_DW12_CH0 0x0430 | |
1053 | #define _VLV_PCS01_DW12_CH1 0x2630 | |
1054 | #define _VLV_PCS23_DW12_CH1 0x2830 | |
1055 | #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) | |
1056 | #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) | |
1057 | ||
ab3c759a CML |
1058 | #define _VLV_PCS_DW12_CH0 0x8230 |
1059 | #define _VLV_PCS_DW12_CH1 0x8430 | |
2e523e98 VS |
1060 | #define DPIO_TX2_STAGGER_MULT(x) ((x)<<20) |
1061 | #define DPIO_TX1_STAGGER_MULT(x) ((x)<<16) | |
1062 | #define DPIO_TX1_STAGGER_MASK(x) ((x)<<8) | |
1063 | #define DPIO_LANESTAGGER_STRAP_OVRD (1<<6) | |
1064 | #define DPIO_LANESTAGGER_STRAP(x) ((x)<<0) | |
ab3c759a CML |
1065 | #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) |
1066 | ||
1067 | #define _VLV_PCS_DW14_CH0 0x8238 | |
1068 | #define _VLV_PCS_DW14_CH1 0x8438 | |
1069 | #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) | |
1070 | ||
1071 | #define _VLV_PCS_DW23_CH0 0x825c | |
1072 | #define _VLV_PCS_DW23_CH1 0x845c | |
1073 | #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) | |
1074 | ||
1075 | #define _VLV_TX_DW2_CH0 0x8288 | |
1076 | #define _VLV_TX_DW2_CH1 0x8488 | |
1fb44505 VS |
1077 | #define DPIO_SWING_MARGIN000_SHIFT 16 |
1078 | #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) | |
9d556c99 | 1079 | #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 |
ab3c759a CML |
1080 | #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) |
1081 | ||
1082 | #define _VLV_TX_DW3_CH0 0x828c | |
1083 | #define _VLV_TX_DW3_CH1 0x848c | |
9d556c99 CML |
1084 | /* The following bit for CHV phy */ |
1085 | #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) | |
1fb44505 VS |
1086 | #define DPIO_SWING_MARGIN101_SHIFT 16 |
1087 | #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) | |
ab3c759a CML |
1088 | #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) |
1089 | ||
1090 | #define _VLV_TX_DW4_CH0 0x8290 | |
1091 | #define _VLV_TX_DW4_CH1 0x8490 | |
9d556c99 CML |
1092 | #define DPIO_SWING_DEEMPH9P5_SHIFT 24 |
1093 | #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) | |
1fb44505 VS |
1094 | #define DPIO_SWING_DEEMPH6P0_SHIFT 16 |
1095 | #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) | |
ab3c759a CML |
1096 | #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) |
1097 | ||
1098 | #define _VLV_TX3_DW4_CH0 0x690 | |
1099 | #define _VLV_TX3_DW4_CH1 0x2a90 | |
1100 | #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) | |
1101 | ||
1102 | #define _VLV_TX_DW5_CH0 0x8294 | |
1103 | #define _VLV_TX_DW5_CH1 0x8494 | |
598fac6b | 1104 | #define DPIO_TX_OCALINIT_EN (1<<31) |
ab3c759a CML |
1105 | #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) |
1106 | ||
1107 | #define _VLV_TX_DW11_CH0 0x82ac | |
1108 | #define _VLV_TX_DW11_CH1 0x84ac | |
1109 | #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) | |
1110 | ||
1111 | #define _VLV_TX_DW14_CH0 0x82b8 | |
1112 | #define _VLV_TX_DW14_CH1 0x84b8 | |
1113 | #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) | |
b56747aa | 1114 | |
9d556c99 CML |
1115 | /* CHV dpPhy registers */ |
1116 | #define _CHV_PLL_DW0_CH0 0x8000 | |
1117 | #define _CHV_PLL_DW0_CH1 0x8180 | |
1118 | #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) | |
1119 | ||
1120 | #define _CHV_PLL_DW1_CH0 0x8004 | |
1121 | #define _CHV_PLL_DW1_CH1 0x8184 | |
1122 | #define DPIO_CHV_N_DIV_SHIFT 8 | |
1123 | #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) | |
1124 | #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) | |
1125 | ||
1126 | #define _CHV_PLL_DW2_CH0 0x8008 | |
1127 | #define _CHV_PLL_DW2_CH1 0x8188 | |
1128 | #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) | |
1129 | ||
1130 | #define _CHV_PLL_DW3_CH0 0x800c | |
1131 | #define _CHV_PLL_DW3_CH1 0x818c | |
1132 | #define DPIO_CHV_FRAC_DIV_EN (1 << 16) | |
1133 | #define DPIO_CHV_FIRST_MOD (0 << 8) | |
1134 | #define DPIO_CHV_SECOND_MOD (1 << 8) | |
1135 | #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 | |
a945ce7e | 1136 | #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) |
9d556c99 CML |
1137 | #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) |
1138 | ||
1139 | #define _CHV_PLL_DW6_CH0 0x8018 | |
1140 | #define _CHV_PLL_DW6_CH1 0x8198 | |
1141 | #define DPIO_CHV_GAIN_CTRL_SHIFT 16 | |
1142 | #define DPIO_CHV_INT_COEFF_SHIFT 8 | |
1143 | #define DPIO_CHV_PROP_COEFF_SHIFT 0 | |
1144 | #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) | |
1145 | ||
d3eee4ba VP |
1146 | #define _CHV_PLL_DW8_CH0 0x8020 |
1147 | #define _CHV_PLL_DW8_CH1 0x81A0 | |
9cbe40c1 VP |
1148 | #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 |
1149 | #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) | |
d3eee4ba VP |
1150 | #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) |
1151 | ||
1152 | #define _CHV_PLL_DW9_CH0 0x8024 | |
1153 | #define _CHV_PLL_DW9_CH1 0x81A4 | |
1154 | #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ | |
de3a0fde | 1155 | #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) |
d3eee4ba VP |
1156 | #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ |
1157 | #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) | |
1158 | ||
6669e39f VS |
1159 | #define _CHV_CMN_DW0_CH0 0x8100 |
1160 | #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 | |
1161 | #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 | |
1162 | #define DPIO_ALLDL_POWERDOWN (1 << 1) | |
1163 | #define DPIO_ANYDL_POWERDOWN (1 << 0) | |
1164 | ||
b9e5ac3c VS |
1165 | #define _CHV_CMN_DW5_CH0 0x8114 |
1166 | #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) | |
1167 | #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) | |
1168 | #define CHV_BUFRIGHTENA1_FORCE (3 << 20) | |
1169 | #define CHV_BUFRIGHTENA1_MASK (3 << 20) | |
1170 | #define CHV_BUFLEFTENA1_DISABLE (0 << 22) | |
1171 | #define CHV_BUFLEFTENA1_NORMAL (1 << 22) | |
1172 | #define CHV_BUFLEFTENA1_FORCE (3 << 22) | |
1173 | #define CHV_BUFLEFTENA1_MASK (3 << 22) | |
1174 | ||
9d556c99 CML |
1175 | #define _CHV_CMN_DW13_CH0 0x8134 |
1176 | #define _CHV_CMN_DW0_CH1 0x8080 | |
1177 | #define DPIO_CHV_S1_DIV_SHIFT 21 | |
1178 | #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ | |
1179 | #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ | |
1180 | #define DPIO_CHV_K_DIV_SHIFT 4 | |
1181 | #define DPIO_PLL_FREQLOCK (1 << 1) | |
1182 | #define DPIO_PLL_LOCK (1 << 0) | |
1183 | #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) | |
1184 | ||
1185 | #define _CHV_CMN_DW14_CH0 0x8138 | |
1186 | #define _CHV_CMN_DW1_CH1 0x8084 | |
1187 | #define DPIO_AFC_RECAL (1 << 14) | |
1188 | #define DPIO_DCLKP_EN (1 << 13) | |
b9e5ac3c VS |
1189 | #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ |
1190 | #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ | |
1191 | #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ | |
1192 | #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ | |
1193 | #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ | |
1194 | #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ | |
1195 | #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ | |
1196 | #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ | |
9d556c99 CML |
1197 | #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) |
1198 | ||
9197c88b VS |
1199 | #define _CHV_CMN_DW19_CH0 0x814c |
1200 | #define _CHV_CMN_DW6_CH1 0x8098 | |
6669e39f VS |
1201 | #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ |
1202 | #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ | |
e0fce78f | 1203 | #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ |
9197c88b | 1204 | #define CHV_CMN_USEDCLKCHANNEL (1 << 13) |
e0fce78f | 1205 | |
9197c88b VS |
1206 | #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) |
1207 | ||
e0fce78f VS |
1208 | #define CHV_CMN_DW28 0x8170 |
1209 | #define DPIO_CL1POWERDOWNEN (1 << 23) | |
1210 | #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) | |
ee279218 VS |
1211 | #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) |
1212 | #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) | |
1213 | #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) | |
1214 | #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) | |
e0fce78f | 1215 | |
9d556c99 | 1216 | #define CHV_CMN_DW30 0x8178 |
3e288786 | 1217 | #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) |
9d556c99 CML |
1218 | #define DPIO_LRC_BYPASS (1 << 3) |
1219 | ||
1220 | #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ | |
1221 | (lane) * 0x200 + (offset)) | |
1222 | ||
f72df8db VS |
1223 | #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) |
1224 | #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) | |
1225 | #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) | |
1226 | #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) | |
1227 | #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) | |
1228 | #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) | |
1229 | #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) | |
1230 | #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) | |
1231 | #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) | |
1232 | #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) | |
1233 | #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) | |
9d556c99 CML |
1234 | #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) |
1235 | #define DPIO_FRC_LATENCY_SHFIT 8 | |
1236 | #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) | |
1237 | #define DPIO_UPAR_SHIFT 30 | |
5c6706e5 VK |
1238 | |
1239 | /* BXT PHY registers */ | |
f0f59a00 | 1240 | #define _BXT_PHY(phy, a, b) _MMIO_PIPE((phy), (a), (b)) |
5c6706e5 | 1241 | |
f0f59a00 | 1242 | #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) |
5c6706e5 VK |
1243 | #define GT_DISPLAY_POWER_ON(phy) (1 << (phy)) |
1244 | ||
1245 | #define _PHY_CTL_FAMILY_EDP 0x64C80 | |
1246 | #define _PHY_CTL_FAMILY_DDI 0x64C90 | |
1247 | #define COMMON_RESET_DIS (1 << 31) | |
1248 | #define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \ | |
1249 | _PHY_CTL_FAMILY_EDP) | |
1250 | ||
dfb82408 S |
1251 | /* BXT PHY PLL registers */ |
1252 | #define _PORT_PLL_A 0x46074 | |
1253 | #define _PORT_PLL_B 0x46078 | |
1254 | #define _PORT_PLL_C 0x4607c | |
1255 | #define PORT_PLL_ENABLE (1 << 31) | |
1256 | #define PORT_PLL_LOCK (1 << 30) | |
1257 | #define PORT_PLL_REF_SEL (1 << 27) | |
f0f59a00 | 1258 | #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) |
dfb82408 S |
1259 | |
1260 | #define _PORT_PLL_EBB_0_A 0x162034 | |
1261 | #define _PORT_PLL_EBB_0_B 0x6C034 | |
1262 | #define _PORT_PLL_EBB_0_C 0x6C340 | |
aa610dcb ID |
1263 | #define PORT_PLL_P1_SHIFT 13 |
1264 | #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) | |
1265 | #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) | |
1266 | #define PORT_PLL_P2_SHIFT 8 | |
1267 | #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) | |
1268 | #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) | |
f0f59a00 | 1269 | #define BXT_PORT_PLL_EBB_0(port) _MMIO_PORT3(port, _PORT_PLL_EBB_0_A, \ |
dfb82408 S |
1270 | _PORT_PLL_EBB_0_B, \ |
1271 | _PORT_PLL_EBB_0_C) | |
1272 | ||
1273 | #define _PORT_PLL_EBB_4_A 0x162038 | |
1274 | #define _PORT_PLL_EBB_4_B 0x6C038 | |
1275 | #define _PORT_PLL_EBB_4_C 0x6C344 | |
1276 | #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) | |
1277 | #define PORT_PLL_RECALIBRATE (1 << 14) | |
f0f59a00 | 1278 | #define BXT_PORT_PLL_EBB_4(port) _MMIO_PORT3(port, _PORT_PLL_EBB_4_A, \ |
dfb82408 S |
1279 | _PORT_PLL_EBB_4_B, \ |
1280 | _PORT_PLL_EBB_4_C) | |
1281 | ||
1282 | #define _PORT_PLL_0_A 0x162100 | |
1283 | #define _PORT_PLL_0_B 0x6C100 | |
1284 | #define _PORT_PLL_0_C 0x6C380 | |
1285 | /* PORT_PLL_0_A */ | |
1286 | #define PORT_PLL_M2_MASK 0xFF | |
1287 | /* PORT_PLL_1_A */ | |
aa610dcb ID |
1288 | #define PORT_PLL_N_SHIFT 8 |
1289 | #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) | |
1290 | #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) | |
dfb82408 S |
1291 | /* PORT_PLL_2_A */ |
1292 | #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF | |
1293 | /* PORT_PLL_3_A */ | |
1294 | #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) | |
1295 | /* PORT_PLL_6_A */ | |
1296 | #define PORT_PLL_PROP_COEFF_MASK 0xF | |
1297 | #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) | |
1298 | #define PORT_PLL_INT_COEFF(x) ((x) << 8) | |
1299 | #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) | |
1300 | #define PORT_PLL_GAIN_CTL(x) ((x) << 16) | |
1301 | /* PORT_PLL_8_A */ | |
1302 | #define PORT_PLL_TARGET_CNT_MASK 0x3FF | |
b6dc71f3 | 1303 | /* PORT_PLL_9_A */ |
05712c15 ID |
1304 | #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 |
1305 | #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) | |
b6dc71f3 VK |
1306 | /* PORT_PLL_10_A */ |
1307 | #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) | |
e6292556 | 1308 | #define PORT_PLL_DCO_AMP_DEFAULT 15 |
b6dc71f3 | 1309 | #define PORT_PLL_DCO_AMP_MASK 0x3c00 |
68d97538 | 1310 | #define PORT_PLL_DCO_AMP(x) ((x)<<10) |
dfb82408 S |
1311 | #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \ |
1312 | _PORT_PLL_0_B, \ | |
1313 | _PORT_PLL_0_C) | |
f0f59a00 | 1314 | #define BXT_PORT_PLL(port, idx) _MMIO(_PORT_PLL_BASE(port) + (idx) * 4) |
dfb82408 | 1315 | |
5c6706e5 VK |
1316 | /* BXT PHY common lane registers */ |
1317 | #define _PORT_CL1CM_DW0_A 0x162000 | |
1318 | #define _PORT_CL1CM_DW0_BC 0x6C000 | |
1319 | #define PHY_POWER_GOOD (1 << 16) | |
1320 | #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ | |
1321 | _PORT_CL1CM_DW0_A) | |
1322 | ||
1323 | #define _PORT_CL1CM_DW9_A 0x162024 | |
1324 | #define _PORT_CL1CM_DW9_BC 0x6C024 | |
1325 | #define IREF0RC_OFFSET_SHIFT 8 | |
1326 | #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) | |
1327 | #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \ | |
1328 | _PORT_CL1CM_DW9_A) | |
1329 | ||
1330 | #define _PORT_CL1CM_DW10_A 0x162028 | |
1331 | #define _PORT_CL1CM_DW10_BC 0x6C028 | |
1332 | #define IREF1RC_OFFSET_SHIFT 8 | |
1333 | #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) | |
1334 | #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \ | |
1335 | _PORT_CL1CM_DW10_A) | |
1336 | ||
1337 | #define _PORT_CL1CM_DW28_A 0x162070 | |
1338 | #define _PORT_CL1CM_DW28_BC 0x6C070 | |
1339 | #define OCL1_POWER_DOWN_EN (1 << 23) | |
1340 | #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) | |
1341 | #define SUS_CLK_CONFIG 0x3 | |
1342 | #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \ | |
1343 | _PORT_CL1CM_DW28_A) | |
1344 | ||
1345 | #define _PORT_CL1CM_DW30_A 0x162078 | |
1346 | #define _PORT_CL1CM_DW30_BC 0x6C078 | |
1347 | #define OCL2_LDOFUSE_PWR_DIS (1 << 6) | |
1348 | #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \ | |
1349 | _PORT_CL1CM_DW30_A) | |
1350 | ||
1351 | /* Defined for PHY0 only */ | |
f0f59a00 | 1352 | #define BXT_PORT_CL2CM_DW6_BC _MMIO(0x6C358) |
5c6706e5 VK |
1353 | #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) |
1354 | ||
1355 | /* BXT PHY Ref registers */ | |
1356 | #define _PORT_REF_DW3_A 0x16218C | |
1357 | #define _PORT_REF_DW3_BC 0x6C18C | |
1358 | #define GRC_DONE (1 << 22) | |
1359 | #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \ | |
1360 | _PORT_REF_DW3_A) | |
1361 | ||
1362 | #define _PORT_REF_DW6_A 0x162198 | |
1363 | #define _PORT_REF_DW6_BC 0x6C198 | |
1364 | /* | |
1365 | * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them | |
1366 | * after testing. | |
1367 | */ | |
1368 | #define GRC_CODE_SHIFT 23 | |
1369 | #define GRC_CODE_MASK (0x1FF << GRC_CODE_SHIFT) | |
1370 | #define GRC_CODE_FAST_SHIFT 16 | |
1371 | #define GRC_CODE_FAST_MASK (0x7F << GRC_CODE_FAST_SHIFT) | |
1372 | #define GRC_CODE_SLOW_SHIFT 8 | |
1373 | #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) | |
1374 | #define GRC_CODE_NOM_MASK 0xFF | |
1375 | #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \ | |
1376 | _PORT_REF_DW6_A) | |
1377 | ||
1378 | #define _PORT_REF_DW8_A 0x1621A0 | |
1379 | #define _PORT_REF_DW8_BC 0x6C1A0 | |
1380 | #define GRC_DIS (1 << 15) | |
1381 | #define GRC_RDY_OVRD (1 << 1) | |
1382 | #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \ | |
1383 | _PORT_REF_DW8_A) | |
1384 | ||
dfb82408 | 1385 | /* BXT PHY PCS registers */ |
96fb9f9b VK |
1386 | #define _PORT_PCS_DW10_LN01_A 0x162428 |
1387 | #define _PORT_PCS_DW10_LN01_B 0x6C428 | |
1388 | #define _PORT_PCS_DW10_LN01_C 0x6C828 | |
1389 | #define _PORT_PCS_DW10_GRP_A 0x162C28 | |
1390 | #define _PORT_PCS_DW10_GRP_B 0x6CC28 | |
1391 | #define _PORT_PCS_DW10_GRP_C 0x6CE28 | |
f0f59a00 | 1392 | #define BXT_PORT_PCS_DW10_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW10_LN01_A, \ |
96fb9f9b VK |
1393 | _PORT_PCS_DW10_LN01_B, \ |
1394 | _PORT_PCS_DW10_LN01_C) | |
f0f59a00 | 1395 | #define BXT_PORT_PCS_DW10_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW10_GRP_A, \ |
96fb9f9b VK |
1396 | _PORT_PCS_DW10_GRP_B, \ |
1397 | _PORT_PCS_DW10_GRP_C) | |
1398 | #define TX2_SWING_CALC_INIT (1 << 31) | |
1399 | #define TX1_SWING_CALC_INIT (1 << 30) | |
1400 | ||
dfb82408 S |
1401 | #define _PORT_PCS_DW12_LN01_A 0x162430 |
1402 | #define _PORT_PCS_DW12_LN01_B 0x6C430 | |
1403 | #define _PORT_PCS_DW12_LN01_C 0x6C830 | |
1404 | #define _PORT_PCS_DW12_LN23_A 0x162630 | |
1405 | #define _PORT_PCS_DW12_LN23_B 0x6C630 | |
1406 | #define _PORT_PCS_DW12_LN23_C 0x6CA30 | |
1407 | #define _PORT_PCS_DW12_GRP_A 0x162c30 | |
1408 | #define _PORT_PCS_DW12_GRP_B 0x6CC30 | |
1409 | #define _PORT_PCS_DW12_GRP_C 0x6CE30 | |
1410 | #define LANESTAGGER_STRAP_OVRD (1 << 6) | |
1411 | #define LANE_STAGGER_MASK 0x1F | |
f0f59a00 | 1412 | #define BXT_PORT_PCS_DW12_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN01_A, \ |
dfb82408 S |
1413 | _PORT_PCS_DW12_LN01_B, \ |
1414 | _PORT_PCS_DW12_LN01_C) | |
f0f59a00 | 1415 | #define BXT_PORT_PCS_DW12_LN23(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN23_A, \ |
dfb82408 S |
1416 | _PORT_PCS_DW12_LN23_B, \ |
1417 | _PORT_PCS_DW12_LN23_C) | |
f0f59a00 | 1418 | #define BXT_PORT_PCS_DW12_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW12_GRP_A, \ |
dfb82408 S |
1419 | _PORT_PCS_DW12_GRP_B, \ |
1420 | _PORT_PCS_DW12_GRP_C) | |
1421 | ||
5c6706e5 VK |
1422 | /* BXT PHY TX registers */ |
1423 | #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ | |
1424 | ((lane) & 1) * 0x80) | |
1425 | ||
96fb9f9b VK |
1426 | #define _PORT_TX_DW2_LN0_A 0x162508 |
1427 | #define _PORT_TX_DW2_LN0_B 0x6C508 | |
1428 | #define _PORT_TX_DW2_LN0_C 0x6C908 | |
1429 | #define _PORT_TX_DW2_GRP_A 0x162D08 | |
1430 | #define _PORT_TX_DW2_GRP_B 0x6CD08 | |
1431 | #define _PORT_TX_DW2_GRP_C 0x6CF08 | |
f0f59a00 | 1432 | #define BXT_PORT_TX_DW2_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW2_GRP_A, \ |
96fb9f9b VK |
1433 | _PORT_TX_DW2_GRP_B, \ |
1434 | _PORT_TX_DW2_GRP_C) | |
f0f59a00 | 1435 | #define BXT_PORT_TX_DW2_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW2_LN0_A, \ |
96fb9f9b VK |
1436 | _PORT_TX_DW2_LN0_B, \ |
1437 | _PORT_TX_DW2_LN0_C) | |
1438 | #define MARGIN_000_SHIFT 16 | |
1439 | #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) | |
1440 | #define UNIQ_TRANS_SCALE_SHIFT 8 | |
1441 | #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) | |
1442 | ||
1443 | #define _PORT_TX_DW3_LN0_A 0x16250C | |
1444 | #define _PORT_TX_DW3_LN0_B 0x6C50C | |
1445 | #define _PORT_TX_DW3_LN0_C 0x6C90C | |
1446 | #define _PORT_TX_DW3_GRP_A 0x162D0C | |
1447 | #define _PORT_TX_DW3_GRP_B 0x6CD0C | |
1448 | #define _PORT_TX_DW3_GRP_C 0x6CF0C | |
f0f59a00 | 1449 | #define BXT_PORT_TX_DW3_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW3_GRP_A, \ |
96fb9f9b VK |
1450 | _PORT_TX_DW3_GRP_B, \ |
1451 | _PORT_TX_DW3_GRP_C) | |
f0f59a00 | 1452 | #define BXT_PORT_TX_DW3_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW3_LN0_A, \ |
96fb9f9b VK |
1453 | _PORT_TX_DW3_LN0_B, \ |
1454 | _PORT_TX_DW3_LN0_C) | |
9c58a049 SJ |
1455 | #define SCALE_DCOMP_METHOD (1 << 26) |
1456 | #define UNIQUE_TRANGE_EN_METHOD (1 << 27) | |
96fb9f9b VK |
1457 | |
1458 | #define _PORT_TX_DW4_LN0_A 0x162510 | |
1459 | #define _PORT_TX_DW4_LN0_B 0x6C510 | |
1460 | #define _PORT_TX_DW4_LN0_C 0x6C910 | |
1461 | #define _PORT_TX_DW4_GRP_A 0x162D10 | |
1462 | #define _PORT_TX_DW4_GRP_B 0x6CD10 | |
1463 | #define _PORT_TX_DW4_GRP_C 0x6CF10 | |
f0f59a00 | 1464 | #define BXT_PORT_TX_DW4_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW4_LN0_A, \ |
96fb9f9b VK |
1465 | _PORT_TX_DW4_LN0_B, \ |
1466 | _PORT_TX_DW4_LN0_C) | |
f0f59a00 | 1467 | #define BXT_PORT_TX_DW4_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW4_GRP_A, \ |
96fb9f9b VK |
1468 | _PORT_TX_DW4_GRP_B, \ |
1469 | _PORT_TX_DW4_GRP_C) | |
1470 | #define DEEMPH_SHIFT 24 | |
1471 | #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) | |
1472 | ||
5c6706e5 VK |
1473 | #define _PORT_TX_DW14_LN0_A 0x162538 |
1474 | #define _PORT_TX_DW14_LN0_B 0x6C538 | |
1475 | #define _PORT_TX_DW14_LN0_C 0x6C938 | |
1476 | #define LATENCY_OPTIM_SHIFT 30 | |
1477 | #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) | |
f0f59a00 | 1478 | #define BXT_PORT_TX_DW14_LN(port, lane) _MMIO(_PORT3((port), _PORT_TX_DW14_LN0_A, \ |
5c6706e5 VK |
1479 | _PORT_TX_DW14_LN0_B, \ |
1480 | _PORT_TX_DW14_LN0_C) + \ | |
1481 | _BXT_LANE_OFFSET(lane)) | |
1482 | ||
f8896f5d | 1483 | /* UAIMI scratch pad register 1 */ |
f0f59a00 | 1484 | #define UAIMI_SPR1 _MMIO(0x4F074) |
f8896f5d DW |
1485 | /* SKL VccIO mask */ |
1486 | #define SKL_VCCIO_MASK 0x1 | |
1487 | /* SKL balance leg register */ | |
f0f59a00 | 1488 | #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) |
f8896f5d DW |
1489 | /* I_boost values */ |
1490 | #define BALANCE_LEG_SHIFT(port) (8+3*(port)) | |
1491 | #define BALANCE_LEG_MASK(port) (7<<(8+3*(port))) | |
1492 | /* Balance leg disable bits */ | |
1493 | #define BALANCE_LEG_DISABLE_SHIFT 23 | |
1494 | ||
585fb111 | 1495 | /* |
de151cf6 | 1496 | * Fence registers |
eecf613a VS |
1497 | * [0-7] @ 0x2000 gen2,gen3 |
1498 | * [8-15] @ 0x3000 945,g33,pnv | |
1499 | * | |
1500 | * [0-15] @ 0x3000 gen4,gen5 | |
1501 | * | |
1502 | * [0-15] @ 0x100000 gen6,vlv,chv | |
1503 | * [0-31] @ 0x100000 gen7+ | |
585fb111 | 1504 | */ |
f0f59a00 | 1505 | #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) |
de151cf6 JB |
1506 | #define I830_FENCE_START_MASK 0x07f80000 |
1507 | #define I830_FENCE_TILING_Y_SHIFT 12 | |
0f973f27 | 1508 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
de151cf6 JB |
1509 | #define I830_FENCE_PITCH_SHIFT 4 |
1510 | #define I830_FENCE_REG_VALID (1<<0) | |
c36a2a6d | 1511 | #define I915_FENCE_MAX_PITCH_VAL 4 |
e76a16de | 1512 | #define I830_FENCE_MAX_PITCH_VAL 6 |
8d7773a3 | 1513 | #define I830_FENCE_MAX_SIZE_VAL (1<<8) |
de151cf6 JB |
1514 | |
1515 | #define I915_FENCE_START_MASK 0x0ff00000 | |
0f973f27 | 1516 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
585fb111 | 1517 | |
f0f59a00 VS |
1518 | #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) |
1519 | #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) | |
de151cf6 JB |
1520 | #define I965_FENCE_PITCH_SHIFT 2 |
1521 | #define I965_FENCE_TILING_Y_SHIFT 1 | |
1522 | #define I965_FENCE_REG_VALID (1<<0) | |
8d7773a3 | 1523 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
de151cf6 | 1524 | |
f0f59a00 VS |
1525 | #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) |
1526 | #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) | |
eecf613a | 1527 | #define GEN6_FENCE_PITCH_SHIFT 32 |
3a062478 | 1528 | #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 |
4e901fdc | 1529 | |
2b6b3a09 | 1530 | |
f691e2f4 | 1531 | /* control register for cpu gtt access */ |
f0f59a00 | 1532 | #define TILECTL _MMIO(0x101000) |
f691e2f4 | 1533 | #define TILECTL_SWZCTL (1 << 0) |
e3a29055 | 1534 | #define TILECTL_TLBPF (1 << 1) |
f691e2f4 DV |
1535 | #define TILECTL_TLB_PREFETCH_DIS (1 << 2) |
1536 | #define TILECTL_BACKSNOOP_DIS (1 << 3) | |
1537 | ||
de151cf6 JB |
1538 | /* |
1539 | * Instruction and interrupt control regs | |
1540 | */ | |
f0f59a00 | 1541 | #define PGTBL_CTL _MMIO(0x02020) |
f1e1c212 VS |
1542 | #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ |
1543 | #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ | |
f0f59a00 VS |
1544 | #define PGTBL_ER _MMIO(0x02024) |
1545 | #define PRB0_BASE (0x2030-0x30) | |
1546 | #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */ | |
1547 | #define PRB2_BASE (0x2050-0x30) /* gen3 */ | |
1548 | #define SRB0_BASE (0x2100-0x30) /* gen2 */ | |
1549 | #define SRB1_BASE (0x2110-0x30) /* gen2 */ | |
1550 | #define SRB2_BASE (0x2120-0x30) /* 830 */ | |
1551 | #define SRB3_BASE (0x2130-0x30) /* 830 */ | |
333e9fe9 DV |
1552 | #define RENDER_RING_BASE 0x02000 |
1553 | #define BSD_RING_BASE 0x04000 | |
1554 | #define GEN6_BSD_RING_BASE 0x12000 | |
845f74a7 | 1555 | #define GEN8_BSD2_RING_BASE 0x1c000 |
1950de14 | 1556 | #define VEBOX_RING_BASE 0x1a000 |
549f7365 | 1557 | #define BLT_RING_BASE 0x22000 |
f0f59a00 VS |
1558 | #define RING_TAIL(base) _MMIO((base)+0x30) |
1559 | #define RING_HEAD(base) _MMIO((base)+0x34) | |
1560 | #define RING_START(base) _MMIO((base)+0x38) | |
1561 | #define RING_CTL(base) _MMIO((base)+0x3c) | |
1562 | #define RING_SYNC_0(base) _MMIO((base)+0x40) | |
1563 | #define RING_SYNC_1(base) _MMIO((base)+0x44) | |
1564 | #define RING_SYNC_2(base) _MMIO((base)+0x48) | |
1950de14 BW |
1565 | #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) |
1566 | #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) | |
1567 | #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) | |
1568 | #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) | |
1569 | #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) | |
1570 | #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) | |
1571 | #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) | |
1572 | #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) | |
1573 | #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) | |
1574 | #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) | |
1575 | #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) | |
1576 | #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) | |
f0f59a00 VS |
1577 | #define GEN6_NOSYNC INVALID_MMIO_REG |
1578 | #define RING_PSMI_CTL(base) _MMIO((base)+0x50) | |
1579 | #define RING_MAX_IDLE(base) _MMIO((base)+0x54) | |
1580 | #define RING_HWS_PGA(base) _MMIO((base)+0x80) | |
1581 | #define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080) | |
1582 | #define RING_RESET_CTL(base) _MMIO((base)+0xd0) | |
7fd2d269 MK |
1583 | #define RESET_CTL_REQUEST_RESET (1 << 0) |
1584 | #define RESET_CTL_READY_TO_RESET (1 << 1) | |
9e72b46c | 1585 | |
f0f59a00 | 1586 | #define HSW_GTT_CACHE_EN _MMIO(0x4024) |
6d50b065 | 1587 | #define GTT_CACHE_EN_ALL 0xF0007FFF |
f0f59a00 VS |
1588 | #define GEN7_WR_WATERMARK _MMIO(0x4028) |
1589 | #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) | |
1590 | #define ARB_MODE _MMIO(0x4030) | |
f691e2f4 DV |
1591 | #define ARB_MODE_SWIZZLE_SNB (1<<4) |
1592 | #define ARB_MODE_SWIZZLE_IVB (1<<5) | |
f0f59a00 VS |
1593 | #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) |
1594 | #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) | |
9e72b46c | 1595 | /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ |
f0f59a00 | 1596 | #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) |
9e72b46c | 1597 | #define GEN7_LRA_LIMITS_REG_NUM 13 |
f0f59a00 VS |
1598 | #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) |
1599 | #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) | |
9e72b46c | 1600 | |
f0f59a00 | 1601 | #define GAMTARBMODE _MMIO(0x04a08) |
4afe8d33 | 1602 | #define ARB_MODE_BWGTLB_DISABLE (1<<9) |
31a5336e | 1603 | #define ARB_MODE_SWIZZLE_BDW (1<<1) |
f0f59a00 VS |
1604 | #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) |
1605 | #define RING_FAULT_REG(ring) _MMIO(0x4094 + 0x100*(ring)->id) | |
828c7908 | 1606 | #define RING_FAULT_GTTSEL_MASK (1<<11) |
68d97538 VS |
1607 | #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) |
1608 | #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) | |
828c7908 | 1609 | #define RING_FAULT_VALID (1<<0) |
f0f59a00 VS |
1610 | #define DONE_REG _MMIO(0x40b0) |
1611 | #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) | |
1612 | #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) | |
1613 | #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) | |
1614 | #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) | |
1615 | #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) | |
1616 | #define RING_ACTHD(base) _MMIO((base)+0x74) | |
1617 | #define RING_ACTHD_UDW(base) _MMIO((base)+0x5c) | |
1618 | #define RING_NOPID(base) _MMIO((base)+0x94) | |
1619 | #define RING_IMR(base) _MMIO((base)+0xa8) | |
1620 | #define RING_HWSTAM(base) _MMIO((base)+0x98) | |
1621 | #define RING_TIMESTAMP(base) _MMIO((base)+0x358) | |
1622 | #define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4) | |
585fb111 JB |
1623 | #define TAIL_ADDR 0x001FFFF8 |
1624 | #define HEAD_WRAP_COUNT 0xFFE00000 | |
1625 | #define HEAD_WRAP_ONE 0x00200000 | |
1626 | #define HEAD_ADDR 0x001FFFFC | |
1627 | #define RING_NR_PAGES 0x001FF000 | |
1628 | #define RING_REPORT_MASK 0x00000006 | |
1629 | #define RING_REPORT_64K 0x00000002 | |
1630 | #define RING_REPORT_128K 0x00000004 | |
1631 | #define RING_NO_REPORT 0x00000000 | |
1632 | #define RING_VALID_MASK 0x00000001 | |
1633 | #define RING_VALID 0x00000001 | |
1634 | #define RING_INVALID 0x00000000 | |
4b60e5cb CW |
1635 | #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ |
1636 | #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ | |
1ec14ad3 | 1637 | #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ |
9e72b46c | 1638 | |
33136b06 AS |
1639 | #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4) |
1640 | #define RING_MAX_NONPRIV_SLOTS 12 | |
1641 | ||
f0f59a00 | 1642 | #define GEN7_TLB_RD_ADDR _MMIO(0x4700) |
9e72b46c | 1643 | |
8168bd48 | 1644 | #if 0 |
f0f59a00 VS |
1645 | #define PRB0_TAIL _MMIO(0x2030) |
1646 | #define PRB0_HEAD _MMIO(0x2034) | |
1647 | #define PRB0_START _MMIO(0x2038) | |
1648 | #define PRB0_CTL _MMIO(0x203c) | |
1649 | #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */ | |
1650 | #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */ | |
1651 | #define PRB1_START _MMIO(0x2048) /* 915+ only */ | |
1652 | #define PRB1_CTL _MMIO(0x204c) /* 915+ only */ | |
8168bd48 | 1653 | #endif |
f0f59a00 VS |
1654 | #define IPEIR_I965 _MMIO(0x2064) |
1655 | #define IPEHR_I965 _MMIO(0x2068) | |
1656 | #define GEN7_SC_INSTDONE _MMIO(0x7100) | |
1657 | #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) | |
1658 | #define GEN7_ROW_INSTDONE _MMIO(0xe164) | |
d53bd484 | 1659 | #define I915_NUM_INSTDONE_REG 4 |
f0f59a00 VS |
1660 | #define RING_IPEIR(base) _MMIO((base)+0x64) |
1661 | #define RING_IPEHR(base) _MMIO((base)+0x68) | |
f1d54348 ID |
1662 | /* |
1663 | * On GEN4, only the render ring INSTDONE exists and has a different | |
1664 | * layout than the GEN7+ version. | |
bd93a50e | 1665 | * The GEN2 counterpart of this register is GEN2_INSTDONE. |
f1d54348 | 1666 | */ |
f0f59a00 VS |
1667 | #define RING_INSTDONE(base) _MMIO((base)+0x6c) |
1668 | #define RING_INSTPS(base) _MMIO((base)+0x70) | |
1669 | #define RING_DMA_FADD(base) _MMIO((base)+0x78) | |
1670 | #define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */ | |
1671 | #define RING_INSTPM(base) _MMIO((base)+0xc0) | |
1672 | #define RING_MI_MODE(base) _MMIO((base)+0x9c) | |
1673 | #define INSTPS _MMIO(0x2070) /* 965+ only */ | |
1674 | #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ | |
1675 | #define ACTHD_I965 _MMIO(0x2074) | |
1676 | #define HWS_PGA _MMIO(0x2080) | |
585fb111 JB |
1677 | #define HWS_ADDRESS_MASK 0xfffff000 |
1678 | #define HWS_START_ADDRESS_SHIFT 4 | |
f0f59a00 | 1679 | #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ |
97f5ab66 | 1680 | #define PWRCTX_EN (1<<0) |
f0f59a00 VS |
1681 | #define IPEIR _MMIO(0x2088) |
1682 | #define IPEHR _MMIO(0x208c) | |
1683 | #define GEN2_INSTDONE _MMIO(0x2090) | |
1684 | #define NOPID _MMIO(0x2094) | |
1685 | #define HWSTAM _MMIO(0x2098) | |
1686 | #define DMA_FADD_I8XX _MMIO(0x20d0) | |
1687 | #define RING_BBSTATE(base) _MMIO((base)+0x110) | |
35dc3f97 | 1688 | #define RING_BB_PPGTT (1 << 5) |
f0f59a00 VS |
1689 | #define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */ |
1690 | #define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */ | |
1691 | #define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */ | |
1692 | #define RING_BBADDR(base) _MMIO((base)+0x140) | |
1693 | #define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */ | |
1694 | #define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */ | |
1695 | #define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */ | |
1696 | #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */ | |
1697 | #define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */ | |
1698 | ||
1699 | #define ERROR_GEN6 _MMIO(0x40a0) | |
1700 | #define GEN7_ERR_INT _MMIO(0x44040) | |
de032bf4 | 1701 | #define ERR_INT_POISON (1<<31) |
8664281b | 1702 | #define ERR_INT_MMIO_UNCLAIMED (1<<13) |
8bf1e9f1 | 1703 | #define ERR_INT_PIPE_CRC_DONE_C (1<<8) |
8664281b | 1704 | #define ERR_INT_FIFO_UNDERRUN_C (1<<6) |
8bf1e9f1 | 1705 | #define ERR_INT_PIPE_CRC_DONE_B (1<<5) |
8664281b | 1706 | #define ERR_INT_FIFO_UNDERRUN_B (1<<3) |
8bf1e9f1 | 1707 | #define ERR_INT_PIPE_CRC_DONE_A (1<<2) |
68d97538 | 1708 | #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3)) |
8664281b | 1709 | #define ERR_INT_FIFO_UNDERRUN_A (1<<0) |
68d97538 | 1710 | #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3)) |
f406839f | 1711 | |
f0f59a00 VS |
1712 | #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) |
1713 | #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) | |
6c826f34 | 1714 | |
f0f59a00 | 1715 | #define FPGA_DBG _MMIO(0x42300) |
3f1e109a PZ |
1716 | #define FPGA_DBG_RM_NOCLAIM (1<<31) |
1717 | ||
8ac3e1bb MK |
1718 | #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) |
1719 | #define CLAIM_ER_CLR (1 << 31) | |
1720 | #define CLAIM_ER_OVERFLOW (1 << 16) | |
1721 | #define CLAIM_ER_CTR_MASK 0xffff | |
1722 | ||
f0f59a00 | 1723 | #define DERRMR _MMIO(0x44050) |
4e0bbc31 | 1724 | /* Note that HBLANK events are reserved on bdw+ */ |
ffe74d75 CW |
1725 | #define DERRMR_PIPEA_SCANLINE (1<<0) |
1726 | #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) | |
1727 | #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) | |
1728 | #define DERRMR_PIPEA_VBLANK (1<<3) | |
1729 | #define DERRMR_PIPEA_HBLANK (1<<5) | |
1730 | #define DERRMR_PIPEB_SCANLINE (1<<8) | |
1731 | #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) | |
1732 | #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) | |
1733 | #define DERRMR_PIPEB_VBLANK (1<<11) | |
1734 | #define DERRMR_PIPEB_HBLANK (1<<13) | |
1735 | /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ | |
1736 | #define DERRMR_PIPEC_SCANLINE (1<<14) | |
1737 | #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) | |
1738 | #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) | |
1739 | #define DERRMR_PIPEC_VBLANK (1<<21) | |
1740 | #define DERRMR_PIPEC_HBLANK (1<<22) | |
1741 | ||
0f3b6849 | 1742 | |
de6e2eaf EA |
1743 | /* GM45+ chicken bits -- debug workaround bits that may be required |
1744 | * for various sorts of correct behavior. The top 16 bits of each are | |
1745 | * the enables for writing to the corresponding low bit. | |
1746 | */ | |
f0f59a00 | 1747 | #define _3D_CHICKEN _MMIO(0x2084) |
4283908e | 1748 | #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) |
f0f59a00 | 1749 | #define _3D_CHICKEN2 _MMIO(0x208c) |
de6e2eaf EA |
1750 | /* Disables pipelining of read flushes past the SF-WIZ interface. |
1751 | * Required on all Ironlake steppings according to the B-Spec, but the | |
1752 | * particular danger of not doing so is not specified. | |
1753 | */ | |
1754 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) | |
f0f59a00 | 1755 | #define _3D_CHICKEN3 _MMIO(0x2090) |
87f8020e | 1756 | #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) |
26b6e44a | 1757 | #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
e927ecde VS |
1758 | #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ |
1759 | #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ | |
de6e2eaf | 1760 | |
f0f59a00 | 1761 | #define MI_MODE _MMIO(0x209c) |
71cf39b1 | 1762 | # define VS_TIMER_DISPATCH (1 << 6) |
fc74d8e0 | 1763 | # define MI_FLUSH_ENABLE (1 << 12) |
1c8c38c5 | 1764 | # define ASYNC_FLIP_PERF_DISABLE (1 << 14) |
e9fea574 | 1765 | # define MODE_IDLE (1 << 9) |
9991ae78 | 1766 | # define STOP_RING (1 << 8) |
71cf39b1 | 1767 | |
f0f59a00 VS |
1768 | #define GEN6_GT_MODE _MMIO(0x20d0) |
1769 | #define GEN7_GT_MODE _MMIO(0x7008) | |
8d85d272 VS |
1770 | #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) |
1771 | #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) | |
1772 | #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) | |
1773 | #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) | |
98533251 | 1774 | #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) |
6547fbdb | 1775 | #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) |
68d97538 VS |
1776 | #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) |
1777 | #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) | |
f8f2ac9a | 1778 | |
f0f59a00 VS |
1779 | #define GFX_MODE _MMIO(0x2520) |
1780 | #define GFX_MODE_GEN7 _MMIO(0x229c) | |
1781 | #define RING_MODE_GEN7(ring) _MMIO((ring)->mmio_base+0x29c) | |
1ec14ad3 | 1782 | #define GFX_RUN_LIST_ENABLE (1<<15) |
4df001d3 | 1783 | #define GFX_INTERRUPT_STEERING (1<<14) |
aa83e30d | 1784 | #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) |
1ec14ad3 CW |
1785 | #define GFX_SURFACE_FAULT_ENABLE (1<<12) |
1786 | #define GFX_REPLAY_MODE (1<<11) | |
1787 | #define GFX_PSMI_GRANULARITY (1<<10) | |
1788 | #define GFX_PPGTT_ENABLE (1<<9) | |
2dba3239 | 1789 | #define GEN8_GFX_PPGTT_48B (1<<7) |
1ec14ad3 | 1790 | |
4df001d3 DG |
1791 | #define GFX_FORWARD_VBLANK_MASK (3<<5) |
1792 | #define GFX_FORWARD_VBLANK_NEVER (0<<5) | |
1793 | #define GFX_FORWARD_VBLANK_ALWAYS (1<<5) | |
1794 | #define GFX_FORWARD_VBLANK_COND (2<<5) | |
1795 | ||
a7e806de | 1796 | #define VLV_DISPLAY_BASE 0x180000 |
b6fdd0f2 | 1797 | #define VLV_MIPI_BASE VLV_DISPLAY_BASE |
a7e806de | 1798 | |
f0f59a00 VS |
1799 | #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) |
1800 | #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) | |
1801 | #define SCPD0 _MMIO(0x209c) /* 915+ only */ | |
1802 | #define IER _MMIO(0x20a0) | |
1803 | #define IIR _MMIO(0x20a4) | |
1804 | #define IMR _MMIO(0x20a8) | |
1805 | #define ISR _MMIO(0x20ac) | |
1806 | #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) | |
e4443e45 | 1807 | #define GINT_DIS (1<<22) |
2d809570 | 1808 | #define GCFG_DIS (1<<8) |
f0f59a00 VS |
1809 | #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) |
1810 | #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) | |
1811 | #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) | |
1812 | #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) | |
1813 | #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) | |
1814 | #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) | |
1815 | #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) | |
38807746 D |
1816 | #define VLV_PCBR_ADDR_SHIFT 12 |
1817 | ||
90a72f87 | 1818 | #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ |
f0f59a00 VS |
1819 | #define EIR _MMIO(0x20b0) |
1820 | #define EMR _MMIO(0x20b4) | |
1821 | #define ESR _MMIO(0x20b8) | |
63eeaf38 JB |
1822 | #define GM45_ERROR_PAGE_TABLE (1<<5) |
1823 | #define GM45_ERROR_MEM_PRIV (1<<4) | |
1824 | #define I915_ERROR_PAGE_TABLE (1<<4) | |
1825 | #define GM45_ERROR_CP_PRIV (1<<3) | |
1826 | #define I915_ERROR_MEMORY_REFRESH (1<<1) | |
1827 | #define I915_ERROR_INSTRUCTION (1<<0) | |
f0f59a00 | 1828 | #define INSTPM _MMIO(0x20c0) |
ee980b80 | 1829 | #define INSTPM_SELF_EN (1<<12) /* 915GM only */ |
3299254f | 1830 | #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts |
8692d00e CW |
1831 | will not assert AGPBUSY# and will only |
1832 | be delivered when out of C3. */ | |
84f9f938 | 1833 | #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ |
884020bf CW |
1834 | #define INSTPM_TLB_INVALIDATE (1<<9) |
1835 | #define INSTPM_SYNC_FLUSH (1<<5) | |
f0f59a00 VS |
1836 | #define ACTHD _MMIO(0x20c8) |
1837 | #define MEM_MODE _MMIO(0x20cc) | |
1038392b VS |
1838 | #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */ |
1839 | #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */ | |
1840 | #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ | |
f0f59a00 VS |
1841 | #define FW_BLC _MMIO(0x20d8) |
1842 | #define FW_BLC2 _MMIO(0x20dc) | |
1843 | #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ | |
ee980b80 LP |
1844 | #define FW_BLC_SELF_EN_MASK (1<<31) |
1845 | #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ | |
1846 | #define FW_BLC_SELF_EN (1<<15) /* 945 only */ | |
7662c8bd SL |
1847 | #define MM_BURST_LENGTH 0x00700000 |
1848 | #define MM_FIFO_WATERMARK 0x0001F000 | |
1849 | #define LM_BURST_LENGTH 0x00000700 | |
1850 | #define LM_FIFO_WATERMARK 0x0000001F | |
f0f59a00 | 1851 | #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ |
45503ded KP |
1852 | |
1853 | /* Make render/texture TLB fetches lower priorty than associated data | |
1854 | * fetches. This is not turned on by default | |
1855 | */ | |
1856 | #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) | |
1857 | ||
1858 | /* Isoch request wait on GTT enable (Display A/B/C streams). | |
1859 | * Make isoch requests stall on the TLB update. May cause | |
1860 | * display underruns (test mode only) | |
1861 | */ | |
1862 | #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) | |
1863 | ||
1864 | /* Block grant count for isoch requests when block count is | |
1865 | * set to a finite value. | |
1866 | */ | |
1867 | #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) | |
1868 | #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ | |
1869 | #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ | |
1870 | #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ | |
1871 | #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ | |
1872 | ||
1873 | /* Enable render writes to complete in C2/C3/C4 power states. | |
1874 | * If this isn't enabled, render writes are prevented in low | |
1875 | * power states. That seems bad to me. | |
1876 | */ | |
1877 | #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) | |
1878 | ||
1879 | /* This acknowledges an async flip immediately instead | |
1880 | * of waiting for 2TLB fetches. | |
1881 | */ | |
1882 | #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) | |
1883 | ||
1884 | /* Enables non-sequential data reads through arbiter | |
1885 | */ | |
0206e353 | 1886 | #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) |
45503ded KP |
1887 | |
1888 | /* Disable FSB snooping of cacheable write cycles from binner/render | |
1889 | * command stream | |
1890 | */ | |
1891 | #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) | |
1892 | ||
1893 | /* Arbiter time slice for non-isoch streams */ | |
1894 | #define MI_ARB_TIME_SLICE_MASK (7 << 5) | |
1895 | #define MI_ARB_TIME_SLICE_1 (0 << 5) | |
1896 | #define MI_ARB_TIME_SLICE_2 (1 << 5) | |
1897 | #define MI_ARB_TIME_SLICE_4 (2 << 5) | |
1898 | #define MI_ARB_TIME_SLICE_6 (3 << 5) | |
1899 | #define MI_ARB_TIME_SLICE_8 (4 << 5) | |
1900 | #define MI_ARB_TIME_SLICE_10 (5 << 5) | |
1901 | #define MI_ARB_TIME_SLICE_14 (6 << 5) | |
1902 | #define MI_ARB_TIME_SLICE_16 (7 << 5) | |
1903 | ||
1904 | /* Low priority grace period page size */ | |
1905 | #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ | |
1906 | #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) | |
1907 | ||
1908 | /* Disable display A/B trickle feed */ | |
1909 | #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) | |
1910 | ||
1911 | /* Set display plane priority */ | |
1912 | #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ | |
1913 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ | |
1914 | ||
f0f59a00 | 1915 | #define MI_STATE _MMIO(0x20e4) /* gen2 only */ |
54e472ae VS |
1916 | #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ |
1917 | #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ | |
1918 | ||
f0f59a00 | 1919 | #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ |
4358a374 | 1920 | #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) |
585fb111 JB |
1921 | #define CM0_IZ_OPT_DISABLE (1<<6) |
1922 | #define CM0_ZR_OPT_DISABLE (1<<5) | |
009be664 | 1923 | #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) |
585fb111 JB |
1924 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) |
1925 | #define CM0_COLOR_EVICT_DISABLE (1<<3) | |
1926 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) | |
1927 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) | |
f0f59a00 VS |
1928 | #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ |
1929 | #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) | |
0f9b91c7 | 1930 | #define GFX_FLSH_CNTL_EN (1<<0) |
f0f59a00 | 1931 | #define ECOSKPD _MMIO(0x21d0) |
1afe3e9d JB |
1932 | #define ECO_GATING_CX_ONLY (1<<3) |
1933 | #define ECO_FLIP_DONE (1<<0) | |
585fb111 | 1934 | |
f0f59a00 | 1935 | #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ |
4e04632e | 1936 | #define RC_OP_FLUSH_ENABLE (1<<0) |
fe27c606 | 1937 | #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) |
f0f59a00 | 1938 | #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ |
5d708680 DL |
1939 | #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) |
1940 | #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) | |
9370cd98 | 1941 | #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1) |
fb046853 | 1942 | |
f0f59a00 | 1943 | #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0) |
4efe0708 JB |
1944 | #define GEN6_BLITTER_LOCK_SHIFT 16 |
1945 | #define GEN6_BLITTER_FBC_NOTIFY (1<<3) | |
1946 | ||
f0f59a00 | 1947 | #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050) |
2c550183 | 1948 | #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) |
295e8bb7 | 1949 | #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) |
e4443e45 | 1950 | #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) |
295e8bb7 | 1951 | |
693d11c3 | 1952 | /* Fuse readout registers for GT */ |
f0f59a00 | 1953 | #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) |
c93043ae JM |
1954 | #define CHV_FGT_DISABLE_SS0 (1 << 10) |
1955 | #define CHV_FGT_DISABLE_SS1 (1 << 11) | |
693d11c3 D |
1956 | #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 |
1957 | #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) | |
1958 | #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 | |
1959 | #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) | |
1960 | #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 | |
1961 | #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) | |
1962 | #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 | |
1963 | #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) | |
1964 | ||
f0f59a00 | 1965 | #define GEN8_FUSE2 _MMIO(0x9120) |
91bedd34 ŁD |
1966 | #define GEN8_F2_SS_DIS_SHIFT 21 |
1967 | #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) | |
3873218f JM |
1968 | #define GEN8_F2_S_ENA_SHIFT 25 |
1969 | #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) | |
1970 | ||
1971 | #define GEN9_F2_SS_DIS_SHIFT 20 | |
1972 | #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) | |
1973 | ||
f0f59a00 | 1974 | #define GEN8_EU_DISABLE0 _MMIO(0x9134) |
91bedd34 ŁD |
1975 | #define GEN8_EU_DIS0_S0_MASK 0xffffff |
1976 | #define GEN8_EU_DIS0_S1_SHIFT 24 | |
1977 | #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) | |
1978 | ||
f0f59a00 | 1979 | #define GEN8_EU_DISABLE1 _MMIO(0x9138) |
91bedd34 ŁD |
1980 | #define GEN8_EU_DIS1_S1_MASK 0xffff |
1981 | #define GEN8_EU_DIS1_S2_SHIFT 16 | |
1982 | #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) | |
1983 | ||
f0f59a00 | 1984 | #define GEN8_EU_DISABLE2 _MMIO(0x913c) |
91bedd34 ŁD |
1985 | #define GEN8_EU_DIS2_S2_MASK 0xff |
1986 | ||
f0f59a00 | 1987 | #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4) |
3873218f | 1988 | |
f0f59a00 | 1989 | #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) |
12f55818 CW |
1990 | #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) |
1991 | #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) | |
1992 | #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) | |
1993 | #define GEN6_BSD_GO_INDICATOR (1 << 4) | |
881f47b6 | 1994 | |
cc609d5d BW |
1995 | /* On modern GEN architectures interrupt control consists of two sets |
1996 | * of registers. The first set pertains to the ring generating the | |
1997 | * interrupt. The second control is for the functional block generating the | |
1998 | * interrupt. These are PM, GT, DE, etc. | |
1999 | * | |
2000 | * Luckily *knocks on wood* all the ring interrupt bits match up with the | |
2001 | * GT interrupt bits, so we don't need to duplicate the defines. | |
2002 | * | |
2003 | * These defines should cover us well from SNB->HSW with minor exceptions | |
2004 | * it can also work on ILK. | |
2005 | */ | |
2006 | #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) | |
2007 | #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) | |
2008 | #define GT_BLT_USER_INTERRUPT (1 << 22) | |
2009 | #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) | |
2010 | #define GT_BSD_USER_INTERRUPT (1 << 12) | |
35a85ac6 | 2011 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ |
73d477f6 | 2012 | #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
cc609d5d BW |
2013 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ |
2014 | #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) | |
2015 | #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) | |
2016 | #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) | |
2017 | #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) | |
2018 | #define GT_RENDER_USER_INTERRUPT (1 << 0) | |
2019 | ||
12638c57 BW |
2020 | #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ |
2021 | #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ | |
2022 | ||
35a85ac6 BW |
2023 | #define GT_PARITY_ERROR(dev) \ |
2024 | (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ | |
45f80d53 | 2025 | (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) |
35a85ac6 | 2026 | |
cc609d5d BW |
2027 | /* These are all the "old" interrupts */ |
2028 | #define ILK_BSD_USER_INTERRUPT (1<<5) | |
fac12f6c VS |
2029 | |
2030 | #define I915_PM_INTERRUPT (1<<31) | |
2031 | #define I915_ISP_INTERRUPT (1<<22) | |
2032 | #define I915_LPE_PIPE_B_INTERRUPT (1<<21) | |
2033 | #define I915_LPE_PIPE_A_INTERRUPT (1<<20) | |
e7d7cad0 | 2034 | #define I915_MIPIC_INTERRUPT (1<<19) |
fac12f6c | 2035 | #define I915_MIPIA_INTERRUPT (1<<18) |
cc609d5d BW |
2036 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
2037 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) | |
fac12f6c VS |
2038 | #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) |
2039 | #define I915_MASTER_ERROR_INTERRUPT (1<<15) | |
cc609d5d | 2040 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) |
fac12f6c | 2041 | #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) |
cc609d5d | 2042 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ |
fac12f6c | 2043 | #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) |
cc609d5d | 2044 | #define I915_HWB_OOM_INTERRUPT (1<<13) |
fac12f6c | 2045 | #define I915_LPE_PIPE_C_INTERRUPT (1<<12) |
cc609d5d | 2046 | #define I915_SYNC_STATUS_INTERRUPT (1<<12) |
fac12f6c | 2047 | #define I915_MISC_INTERRUPT (1<<11) |
cc609d5d | 2048 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) |
fac12f6c | 2049 | #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) |
cc609d5d | 2050 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) |
fac12f6c | 2051 | #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) |
cc609d5d | 2052 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) |
fac12f6c | 2053 | #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) |
cc609d5d BW |
2054 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) |
2055 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) | |
2056 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) | |
2057 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) | |
2058 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) | |
fac12f6c VS |
2059 | #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) |
2060 | #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) | |
cc609d5d | 2061 | #define I915_DEBUG_INTERRUPT (1<<2) |
fac12f6c | 2062 | #define I915_WINVALID_INTERRUPT (1<<1) |
cc609d5d BW |
2063 | #define I915_USER_INTERRUPT (1<<1) |
2064 | #define I915_ASLE_INTERRUPT (1<<0) | |
fac12f6c | 2065 | #define I915_BSD_USER_INTERRUPT (1<<25) |
881f47b6 | 2066 | |
f0f59a00 | 2067 | #define GEN6_BSD_RNCID _MMIO(0x12198) |
881f47b6 | 2068 | |
f0f59a00 | 2069 | #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) |
a1e969e0 | 2070 | #define GEN7_FF_SCHED_MASK 0x0077070 |
ab57fff1 | 2071 | #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) |
a1e969e0 BW |
2072 | #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) |
2073 | #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) | |
2074 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) | |
2075 | #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ | |
41c0b3a8 | 2076 | #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) |
a1e969e0 BW |
2077 | #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) |
2078 | #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) | |
2079 | #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ | |
2080 | #define GEN7_FF_VS_SCHED_HW (0x0<<12) | |
2081 | #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) | |
2082 | #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) | |
2083 | #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ | |
2084 | #define GEN7_FF_DS_SCHED_HW (0x0<<4) | |
2085 | ||
585fb111 JB |
2086 | /* |
2087 | * Framebuffer compression (915+ only) | |
2088 | */ | |
2089 | ||
f0f59a00 VS |
2090 | #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ |
2091 | #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ | |
2092 | #define FBC_CONTROL _MMIO(0x3208) | |
585fb111 JB |
2093 | #define FBC_CTL_EN (1<<31) |
2094 | #define FBC_CTL_PERIODIC (1<<30) | |
2095 | #define FBC_CTL_INTERVAL_SHIFT (16) | |
2096 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) | |
49677901 | 2097 | #define FBC_CTL_C3_IDLE (1<<13) |
585fb111 | 2098 | #define FBC_CTL_STRIDE_SHIFT (5) |
82f34496 | 2099 | #define FBC_CTL_FENCENO_SHIFT (0) |
f0f59a00 | 2100 | #define FBC_COMMAND _MMIO(0x320c) |
585fb111 | 2101 | #define FBC_CMD_COMPRESS (1<<0) |
f0f59a00 | 2102 | #define FBC_STATUS _MMIO(0x3210) |
585fb111 JB |
2103 | #define FBC_STAT_COMPRESSING (1<<31) |
2104 | #define FBC_STAT_COMPRESSED (1<<30) | |
2105 | #define FBC_STAT_MODIFIED (1<<29) | |
82f34496 | 2106 | #define FBC_STAT_CURRENT_LINE_SHIFT (0) |
f0f59a00 | 2107 | #define FBC_CONTROL2 _MMIO(0x3214) |
585fb111 JB |
2108 | #define FBC_CTL_FENCE_DBL (0<<4) |
2109 | #define FBC_CTL_IDLE_IMM (0<<2) | |
2110 | #define FBC_CTL_IDLE_FULL (1<<2) | |
2111 | #define FBC_CTL_IDLE_LINE (2<<2) | |
2112 | #define FBC_CTL_IDLE_DEBUG (3<<2) | |
2113 | #define FBC_CTL_CPU_FENCE (1<<1) | |
7f2cf220 | 2114 | #define FBC_CTL_PLANE(plane) ((plane)<<0) |
f0f59a00 VS |
2115 | #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ |
2116 | #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) | |
585fb111 | 2117 | |
f0f59a00 | 2118 | #define FBC_STATUS2 _MMIO(0x43214) |
31b9df10 PZ |
2119 | #define FBC_COMPRESSION_MASK 0x7ff |
2120 | ||
585fb111 JB |
2121 | #define FBC_LL_SIZE (1536) |
2122 | ||
74dff282 | 2123 | /* Framebuffer compression for GM45+ */ |
f0f59a00 VS |
2124 | #define DPFC_CB_BASE _MMIO(0x3200) |
2125 | #define DPFC_CONTROL _MMIO(0x3208) | |
74dff282 | 2126 | #define DPFC_CTL_EN (1<<31) |
7f2cf220 VS |
2127 | #define DPFC_CTL_PLANE(plane) ((plane)<<30) |
2128 | #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) | |
74dff282 | 2129 | #define DPFC_CTL_FENCE_EN (1<<29) |
abe959c7 | 2130 | #define IVB_DPFC_CTL_FENCE_EN (1<<28) |
9ce9d069 | 2131 | #define DPFC_CTL_PERSISTENT_MODE (1<<25) |
74dff282 JB |
2132 | #define DPFC_SR_EN (1<<10) |
2133 | #define DPFC_CTL_LIMIT_1X (0<<6) | |
2134 | #define DPFC_CTL_LIMIT_2X (1<<6) | |
2135 | #define DPFC_CTL_LIMIT_4X (2<<6) | |
f0f59a00 | 2136 | #define DPFC_RECOMP_CTL _MMIO(0x320c) |
74dff282 JB |
2137 | #define DPFC_RECOMP_STALL_EN (1<<27) |
2138 | #define DPFC_RECOMP_STALL_WM_SHIFT (16) | |
2139 | #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) | |
2140 | #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) | |
2141 | #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) | |
f0f59a00 | 2142 | #define DPFC_STATUS _MMIO(0x3210) |
74dff282 JB |
2143 | #define DPFC_INVAL_SEG_SHIFT (16) |
2144 | #define DPFC_INVAL_SEG_MASK (0x07ff0000) | |
2145 | #define DPFC_COMP_SEG_SHIFT (0) | |
2146 | #define DPFC_COMP_SEG_MASK (0x000003ff) | |
f0f59a00 VS |
2147 | #define DPFC_STATUS2 _MMIO(0x3214) |
2148 | #define DPFC_FENCE_YOFF _MMIO(0x3218) | |
2149 | #define DPFC_CHICKEN _MMIO(0x3224) | |
74dff282 JB |
2150 | #define DPFC_HT_MODIFY (1<<31) |
2151 | ||
b52eb4dc | 2152 | /* Framebuffer compression for Ironlake */ |
f0f59a00 VS |
2153 | #define ILK_DPFC_CB_BASE _MMIO(0x43200) |
2154 | #define ILK_DPFC_CONTROL _MMIO(0x43208) | |
da46f936 | 2155 | #define FBC_CTL_FALSE_COLOR (1<<10) |
b52eb4dc ZY |
2156 | /* The bit 28-8 is reserved */ |
2157 | #define DPFC_RESERVED (0x1FFFFF00) | |
f0f59a00 VS |
2158 | #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) |
2159 | #define ILK_DPFC_STATUS _MMIO(0x43210) | |
2160 | #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) | |
2161 | #define ILK_DPFC_CHICKEN _MMIO(0x43224) | |
2162 | #define ILK_FBC_RT_BASE _MMIO(0x2128) | |
b52eb4dc | 2163 | #define ILK_FBC_RT_VALID (1<<0) |
abe959c7 | 2164 | #define SNB_FBC_FRONT_BUFFER (1<<1) |
b52eb4dc | 2165 | |
f0f59a00 | 2166 | #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) |
b52eb4dc | 2167 | #define ILK_FBCQ_DIS (1<<22) |
0206e353 | 2168 | #define ILK_PABSTRETCH_DIS (1<<21) |
1398261a | 2169 | |
b52eb4dc | 2170 | |
9c04f015 YL |
2171 | /* |
2172 | * Framebuffer compression for Sandybridge | |
2173 | * | |
2174 | * The following two registers are of type GTTMMADR | |
2175 | */ | |
f0f59a00 | 2176 | #define SNB_DPFC_CTL_SA _MMIO(0x100100) |
9c04f015 | 2177 | #define SNB_CPU_FENCE_ENABLE (1<<29) |
f0f59a00 | 2178 | #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) |
9c04f015 | 2179 | |
abe959c7 | 2180 | /* Framebuffer compression for Ivybridge */ |
f0f59a00 | 2181 | #define IVB_FBC_RT_BASE _MMIO(0x7020) |
abe959c7 | 2182 | |
f0f59a00 | 2183 | #define IPS_CTL _MMIO(0x43408) |
42db64ef | 2184 | #define IPS_ENABLE (1 << 31) |
9c04f015 | 2185 | |
f0f59a00 | 2186 | #define MSG_FBC_REND_STATE _MMIO(0x50380) |
fd3da6c9 RV |
2187 | #define FBC_REND_NUKE (1<<2) |
2188 | #define FBC_REND_CACHE_CLEAN (1<<1) | |
2189 | ||
585fb111 JB |
2190 | /* |
2191 | * GPIO regs | |
2192 | */ | |
f0f59a00 VS |
2193 | #define GPIOA _MMIO(0x5010) |
2194 | #define GPIOB _MMIO(0x5014) | |
2195 | #define GPIOC _MMIO(0x5018) | |
2196 | #define GPIOD _MMIO(0x501c) | |
2197 | #define GPIOE _MMIO(0x5020) | |
2198 | #define GPIOF _MMIO(0x5024) | |
2199 | #define GPIOG _MMIO(0x5028) | |
2200 | #define GPIOH _MMIO(0x502c) | |
585fb111 JB |
2201 | # define GPIO_CLOCK_DIR_MASK (1 << 0) |
2202 | # define GPIO_CLOCK_DIR_IN (0 << 1) | |
2203 | # define GPIO_CLOCK_DIR_OUT (1 << 1) | |
2204 | # define GPIO_CLOCK_VAL_MASK (1 << 2) | |
2205 | # define GPIO_CLOCK_VAL_OUT (1 << 3) | |
2206 | # define GPIO_CLOCK_VAL_IN (1 << 4) | |
2207 | # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) | |
2208 | # define GPIO_DATA_DIR_MASK (1 << 8) | |
2209 | # define GPIO_DATA_DIR_IN (0 << 9) | |
2210 | # define GPIO_DATA_DIR_OUT (1 << 9) | |
2211 | # define GPIO_DATA_VAL_MASK (1 << 10) | |
2212 | # define GPIO_DATA_VAL_OUT (1 << 11) | |
2213 | # define GPIO_DATA_VAL_IN (1 << 12) | |
2214 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) | |
2215 | ||
f0f59a00 | 2216 | #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ |
f899fc64 CW |
2217 | #define GMBUS_RATE_100KHZ (0<<8) |
2218 | #define GMBUS_RATE_50KHZ (1<<8) | |
2219 | #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ | |
2220 | #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ | |
2221 | #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ | |
988c7015 JN |
2222 | #define GMBUS_PIN_DISABLED 0 |
2223 | #define GMBUS_PIN_SSC 1 | |
2224 | #define GMBUS_PIN_VGADDC 2 | |
2225 | #define GMBUS_PIN_PANEL 3 | |
2226 | #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ | |
2227 | #define GMBUS_PIN_DPC 4 /* HDMIC */ | |
2228 | #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ | |
2229 | #define GMBUS_PIN_DPD 6 /* HDMID */ | |
2230 | #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ | |
4c272834 JN |
2231 | #define GMBUS_PIN_1_BXT 1 |
2232 | #define GMBUS_PIN_2_BXT 2 | |
2233 | #define GMBUS_PIN_3_BXT 3 | |
5ea6e5e3 | 2234 | #define GMBUS_NUM_PINS 7 /* including 0 */ |
f0f59a00 | 2235 | #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ |
f899fc64 CW |
2236 | #define GMBUS_SW_CLR_INT (1<<31) |
2237 | #define GMBUS_SW_RDY (1<<30) | |
2238 | #define GMBUS_ENT (1<<29) /* enable timeout */ | |
2239 | #define GMBUS_CYCLE_NONE (0<<25) | |
2240 | #define GMBUS_CYCLE_WAIT (1<<25) | |
2241 | #define GMBUS_CYCLE_INDEX (2<<25) | |
2242 | #define GMBUS_CYCLE_STOP (4<<25) | |
2243 | #define GMBUS_BYTE_COUNT_SHIFT 16 | |
9535c475 | 2244 | #define GMBUS_BYTE_COUNT_MAX 256U |
f899fc64 CW |
2245 | #define GMBUS_SLAVE_INDEX_SHIFT 8 |
2246 | #define GMBUS_SLAVE_ADDR_SHIFT 1 | |
2247 | #define GMBUS_SLAVE_READ (1<<0) | |
2248 | #define GMBUS_SLAVE_WRITE (0<<0) | |
f0f59a00 | 2249 | #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ |
f899fc64 CW |
2250 | #define GMBUS_INUSE (1<<15) |
2251 | #define GMBUS_HW_WAIT_PHASE (1<<14) | |
2252 | #define GMBUS_STALL_TIMEOUT (1<<13) | |
2253 | #define GMBUS_INT (1<<12) | |
2254 | #define GMBUS_HW_RDY (1<<11) | |
2255 | #define GMBUS_SATOER (1<<10) | |
2256 | #define GMBUS_ACTIVE (1<<9) | |
f0f59a00 VS |
2257 | #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ |
2258 | #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ | |
f899fc64 CW |
2259 | #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) |
2260 | #define GMBUS_NAK_EN (1<<3) | |
2261 | #define GMBUS_IDLE_EN (1<<2) | |
2262 | #define GMBUS_HW_WAIT_EN (1<<1) | |
2263 | #define GMBUS_HW_RDY_EN (1<<0) | |
f0f59a00 | 2264 | #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ |
f899fc64 | 2265 | #define GMBUS_2BYTE_INDEX_EN (1<<31) |
f0217c42 | 2266 | |
585fb111 JB |
2267 | /* |
2268 | * Clock control & power management | |
2269 | */ | |
2d401b17 VS |
2270 | #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) |
2271 | #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) | |
2272 | #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) | |
f0f59a00 | 2273 | #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) |
585fb111 | 2274 | |
f0f59a00 VS |
2275 | #define VGA0 _MMIO(0x6000) |
2276 | #define VGA1 _MMIO(0x6004) | |
2277 | #define VGA_PD _MMIO(0x6010) | |
585fb111 JB |
2278 | #define VGA0_PD_P2_DIV_4 (1 << 7) |
2279 | #define VGA0_PD_P1_DIV_2 (1 << 5) | |
2280 | #define VGA0_PD_P1_SHIFT 0 | |
2281 | #define VGA0_PD_P1_MASK (0x1f << 0) | |
2282 | #define VGA1_PD_P2_DIV_4 (1 << 15) | |
2283 | #define VGA1_PD_P1_DIV_2 (1 << 13) | |
2284 | #define VGA1_PD_P1_SHIFT 8 | |
2285 | #define VGA1_PD_P1_MASK (0x1f << 8) | |
585fb111 | 2286 | #define DPLL_VCO_ENABLE (1 << 31) |
4a33e48d DV |
2287 | #define DPLL_SDVO_HIGH_SPEED (1 << 30) |
2288 | #define DPLL_DVO_2X_MODE (1 << 30) | |
25eb05fc | 2289 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
585fb111 | 2290 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
60bfe44f | 2291 | #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) |
585fb111 JB |
2292 | #define DPLL_VGA_MODE_DIS (1 << 28) |
2293 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ | |
2294 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ | |
2295 | #define DPLL_MODE_MASK (3 << 26) | |
2296 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ | |
2297 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ | |
2298 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ | |
2299 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ | |
2300 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ | |
2301 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ | |
f2b115e6 | 2302 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
a0c4da24 | 2303 | #define DPLL_LOCK_VLV (1<<15) |
598fac6b | 2304 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) |
60bfe44f VS |
2305 | #define DPLL_INTEGRATED_REF_CLK_VLV (1<<13) |
2306 | #define DPLL_SSC_REF_CLK_CHV (1<<13) | |
598fac6b DV |
2307 | #define DPLL_PORTC_READY_MASK (0xf << 4) |
2308 | #define DPLL_PORTB_READY_MASK (0xf) | |
585fb111 | 2309 | |
585fb111 | 2310 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
00fc31b7 CML |
2311 | |
2312 | /* Additional CHV pll/phy registers */ | |
f0f59a00 | 2313 | #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) |
00fc31b7 | 2314 | #define DPLL_PORTD_READY_MASK (0xf) |
f0f59a00 | 2315 | #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) |
e0fce78f | 2316 | #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27)) |
bc284542 VS |
2317 | #define PHY_LDO_DELAY_0NS 0x0 |
2318 | #define PHY_LDO_DELAY_200NS 0x1 | |
2319 | #define PHY_LDO_DELAY_600NS 0x2 | |
2320 | #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23)) | |
e0fce78f | 2321 | #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11)) |
70722468 VS |
2322 | #define PHY_CH_SU_PSR 0x1 |
2323 | #define PHY_CH_DEEP_PSR 0x7 | |
2324 | #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2)) | |
2325 | #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) | |
f0f59a00 | 2326 | #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) |
efd814b7 | 2327 | #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) |
30142273 VS |
2328 | #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch)))) |
2329 | #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline)))) | |
076ed3b2 | 2330 | |
585fb111 JB |
2331 | /* |
2332 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within | |
2333 | * this field (only one bit may be set). | |
2334 | */ | |
2335 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 | |
2336 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 | |
f2b115e6 | 2337 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 |
585fb111 JB |
2338 | /* i830, required in DVO non-gang */ |
2339 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) | |
2340 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ | |
2341 | #define PLL_REF_INPUT_DREFCLK (0 << 13) | |
2342 | #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ | |
2343 | #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ | |
2344 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) | |
2345 | #define PLL_REF_INPUT_MASK (3 << 13) | |
2346 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 | |
f2b115e6 | 2347 | /* Ironlake */ |
b9055052 ZW |
2348 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 |
2349 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) | |
2350 | # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) | |
2351 | # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 | |
2352 | # define DPLL_FPA1_P1_POST_DIV_MASK 0xff | |
2353 | ||
585fb111 JB |
2354 | /* |
2355 | * Parallel to Serial Load Pulse phase selection. | |
2356 | * Selects the phase for the 10X DPLL clock for the PCIe | |
2357 | * digital display port. The range is 4 to 13; 10 or more | |
2358 | * is just a flip delay. The default is 6 | |
2359 | */ | |
2360 | #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) | |
2361 | #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) | |
2362 | /* | |
2363 | * SDVO multiplier for 945G/GM. Not used on 965. | |
2364 | */ | |
2365 | #define SDVO_MULTIPLIER_MASK 0x000000ff | |
2366 | #define SDVO_MULTIPLIER_SHIFT_HIRES 4 | |
2367 | #define SDVO_MULTIPLIER_SHIFT_VGA 0 | |
a57c774a | 2368 | |
2d401b17 VS |
2369 | #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) |
2370 | #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) | |
2371 | #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) | |
f0f59a00 | 2372 | #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) |
a57c774a | 2373 | |
585fb111 JB |
2374 | /* |
2375 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. | |
2376 | * | |
2377 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. | |
2378 | */ | |
2379 | #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 | |
2380 | #define DPLL_MD_UDI_DIVIDER_SHIFT 24 | |
2381 | /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ | |
2382 | #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 | |
2383 | #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 | |
2384 | /* | |
2385 | * SDVO/UDI pixel multiplier. | |
2386 | * | |
2387 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus | |
2388 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate | |
2389 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing | |
2390 | * dummy bytes in the datastream at an increased clock rate, with both sides of | |
2391 | * the link knowing how many bytes are fill. | |
2392 | * | |
2393 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock | |
2394 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be | |
2395 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and | |
2396 | * through an SDVO command. | |
2397 | * | |
2398 | * This register field has values of multiplication factor minus 1, with | |
2399 | * a maximum multiplier of 5 for SDVO. | |
2400 | */ | |
2401 | #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 | |
2402 | #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 | |
2403 | /* | |
2404 | * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. | |
2405 | * This best be set to the default value (3) or the CRT won't work. No, | |
2406 | * I don't entirely understand what this does... | |
2407 | */ | |
2408 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f | |
2409 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 | |
25eb05fc | 2410 | |
f0f59a00 VS |
2411 | #define _FPA0 0x6040 |
2412 | #define _FPA1 0x6044 | |
2413 | #define _FPB0 0x6048 | |
2414 | #define _FPB1 0x604c | |
2415 | #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) | |
2416 | #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) | |
585fb111 | 2417 | #define FP_N_DIV_MASK 0x003f0000 |
f2b115e6 | 2418 | #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 |
585fb111 JB |
2419 | #define FP_N_DIV_SHIFT 16 |
2420 | #define FP_M1_DIV_MASK 0x00003f00 | |
2421 | #define FP_M1_DIV_SHIFT 8 | |
2422 | #define FP_M2_DIV_MASK 0x0000003f | |
f2b115e6 | 2423 | #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff |
585fb111 | 2424 | #define FP_M2_DIV_SHIFT 0 |
f0f59a00 | 2425 | #define DPLL_TEST _MMIO(0x606c) |
585fb111 JB |
2426 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) |
2427 | #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) | |
2428 | #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) | |
2429 | #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) | |
2430 | #define DPLLB_TEST_N_BYPASS (1 << 19) | |
2431 | #define DPLLB_TEST_M_BYPASS (1 << 18) | |
2432 | #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) | |
2433 | #define DPLLA_TEST_N_BYPASS (1 << 3) | |
2434 | #define DPLLA_TEST_M_BYPASS (1 << 2) | |
2435 | #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) | |
f0f59a00 | 2436 | #define D_STATE _MMIO(0x6104) |
dc96e9b8 | 2437 | #define DSTATE_GFX_RESET_I830 (1<<6) |
652c393a JB |
2438 | #define DSTATE_PLL_D3_OFF (1<<3) |
2439 | #define DSTATE_GFX_CLOCK_GATING (1<<1) | |
2440 | #define DSTATE_DOT_CLOCK_GATING (1<<0) | |
f0f59a00 | 2441 | #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200) |
652c393a JB |
2442 | # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ |
2443 | # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ | |
2444 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ | |
2445 | # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ | |
2446 | # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ | |
2447 | # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ | |
2448 | # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ | |
2449 | # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ | |
2450 | # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ | |
2451 | # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ | |
2452 | # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ | |
2453 | # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ | |
2454 | # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ | |
2455 | # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ | |
2456 | # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ | |
2457 | # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ | |
2458 | # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ | |
2459 | # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ | |
2460 | # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ | |
2461 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) | |
2462 | # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) | |
2463 | # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) | |
2464 | # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) | |
2465 | # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ | |
2466 | # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ | |
2467 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ | |
2468 | # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) | |
2469 | # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) | |
646b4269 | 2470 | /* |
652c393a JB |
2471 | * This bit must be set on the 830 to prevent hangs when turning off the |
2472 | * overlay scaler. | |
2473 | */ | |
2474 | # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) | |
2475 | # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) | |
2476 | # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) | |
2477 | # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ | |
2478 | # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ | |
2479 | ||
f0f59a00 | 2480 | #define RENCLK_GATE_D1 _MMIO(0x6204) |
652c393a JB |
2481 | # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ |
2482 | # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ | |
2483 | # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) | |
2484 | # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) | |
2485 | # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) | |
2486 | # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) | |
2487 | # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) | |
2488 | # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) | |
2489 | # define MAG_CLOCK_GATE_DISABLE (1 << 5) | |
646b4269 | 2490 | /* This bit must be unset on 855,865 */ |
652c393a JB |
2491 | # define MECI_CLOCK_GATE_DISABLE (1 << 4) |
2492 | # define DCMP_CLOCK_GATE_DISABLE (1 << 3) | |
2493 | # define MEC_CLOCK_GATE_DISABLE (1 << 2) | |
2494 | # define MECO_CLOCK_GATE_DISABLE (1 << 1) | |
646b4269 | 2495 | /* This bit must be set on 855,865. */ |
652c393a JB |
2496 | # define SV_CLOCK_GATE_DISABLE (1 << 0) |
2497 | # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) | |
2498 | # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) | |
2499 | # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) | |
2500 | # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) | |
2501 | # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) | |
2502 | # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) | |
2503 | # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) | |
2504 | # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) | |
2505 | # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) | |
2506 | # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) | |
2507 | # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) | |
2508 | # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) | |
2509 | # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) | |
2510 | # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) | |
2511 | # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) | |
2512 | # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) | |
2513 | # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) | |
2514 | ||
2515 | # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) | |
646b4269 | 2516 | /* This bit must always be set on 965G/965GM */ |
652c393a JB |
2517 | # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) |
2518 | # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) | |
2519 | # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) | |
2520 | # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) | |
2521 | # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) | |
2522 | # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) | |
646b4269 | 2523 | /* This bit must always be set on 965G */ |
652c393a JB |
2524 | # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) |
2525 | # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) | |
2526 | # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) | |
2527 | # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) | |
2528 | # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) | |
2529 | # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) | |
2530 | # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) | |
2531 | # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) | |
2532 | # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) | |
2533 | # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) | |
2534 | # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) | |
2535 | # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) | |
2536 | # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) | |
2537 | # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) | |
2538 | # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) | |
2539 | # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) | |
2540 | # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) | |
2541 | # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) | |
2542 | # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) | |
2543 | ||
f0f59a00 | 2544 | #define RENCLK_GATE_D2 _MMIO(0x6208) |
652c393a JB |
2545 | #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) |
2546 | #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) | |
2547 | #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) | |
fa4f53c4 | 2548 | |
f0f59a00 | 2549 | #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ |
fa4f53c4 VS |
2550 | #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) |
2551 | ||
f0f59a00 VS |
2552 | #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ |
2553 | #define DEUC _MMIO(0x6214) /* CRL only */ | |
585fb111 | 2554 | |
f0f59a00 | 2555 | #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) |
ceb04246 JB |
2556 | #define FW_CSPWRDWNEN (1<<15) |
2557 | ||
f0f59a00 | 2558 | #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) |
e0d8d59b | 2559 | |
f0f59a00 | 2560 | #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) |
24eb2d59 CML |
2561 | #define CDCLK_FREQ_SHIFT 4 |
2562 | #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) | |
2563 | #define CZCLK_FREQ_MASK 0xf | |
1e69cd74 | 2564 | |
f0f59a00 | 2565 | #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) |
1e69cd74 VS |
2566 | #define PFI_CREDIT_63 (9 << 28) /* chv only */ |
2567 | #define PFI_CREDIT_31 (8 << 28) /* chv only */ | |
2568 | #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ | |
2569 | #define PFI_CREDIT_RESEND (1 << 27) | |
2570 | #define VGA_FAST_MODE_DISABLE (1 << 14) | |
2571 | ||
f0f59a00 | 2572 | #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) |
24eb2d59 | 2573 | |
585fb111 JB |
2574 | /* |
2575 | * Palette regs | |
2576 | */ | |
a57c774a AK |
2577 | #define PALETTE_A_OFFSET 0xa000 |
2578 | #define PALETTE_B_OFFSET 0xa800 | |
84fd4f4e | 2579 | #define CHV_PALETTE_C_OFFSET 0xc000 |
f0f59a00 VS |
2580 | #define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \ |
2581 | dev_priv->info.display_mmio_offset + (i) * 4) | |
585fb111 | 2582 | |
673a394b EA |
2583 | /* MCH MMIO space */ |
2584 | ||
2585 | /* | |
2586 | * MCHBAR mirror. | |
2587 | * | |
2588 | * This mirrors the MCHBAR MMIO space whose location is determined by | |
2589 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in | |
2590 | * every way. It is not accessible from the CP register read instructions. | |
2591 | * | |
515b2392 PZ |
2592 | * Starting from Haswell, you can't write registers using the MCHBAR mirror, |
2593 | * just read. | |
673a394b EA |
2594 | */ |
2595 | #define MCHBAR_MIRROR_BASE 0x10000 | |
2596 | ||
1398261a YL |
2597 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 |
2598 | ||
f0f59a00 VS |
2599 | #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) |
2600 | #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) | |
7d316aec VS |
2601 | #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) |
2602 | #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) | |
2603 | ||
3ebecd07 | 2604 | /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ |
f0f59a00 | 2605 | #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) |
3ebecd07 | 2606 | |
646b4269 | 2607 | /* 915-945 and GM965 MCH register controlling DRAM channel access */ |
f0f59a00 | 2608 | #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) |
673a394b EA |
2609 | #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) |
2610 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) | |
2611 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) | |
2612 | #define DCC_ADDRESSING_MODE_MASK (3 << 0) | |
2613 | #define DCC_CHANNEL_XOR_DISABLE (1 << 10) | |
a7f014f2 | 2614 | #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) |
f0f59a00 | 2615 | #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) |
656bfa3a | 2616 | #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) |
673a394b | 2617 | |
646b4269 | 2618 | /* Pineview MCH register contains DDR3 setting */ |
f0f59a00 | 2619 | #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) |
95534263 LP |
2620 | #define CSHRDDR3CTL_DDR3 (1 << 2) |
2621 | ||
646b4269 | 2622 | /* 965 MCH register controlling DRAM channel configuration */ |
f0f59a00 VS |
2623 | #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206) |
2624 | #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606) | |
673a394b | 2625 | |
646b4269 | 2626 | /* snb MCH registers for reading the DRAM channel configuration */ |
f0f59a00 VS |
2627 | #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) |
2628 | #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) | |
2629 | #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) | |
f691e2f4 DV |
2630 | #define MAD_DIMM_ECC_MASK (0x3 << 24) |
2631 | #define MAD_DIMM_ECC_OFF (0x0 << 24) | |
2632 | #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) | |
2633 | #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) | |
2634 | #define MAD_DIMM_ECC_ON (0x3 << 24) | |
2635 | #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) | |
2636 | #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) | |
2637 | #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ | |
2638 | #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ | |
2639 | #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) | |
2640 | #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) | |
2641 | #define MAD_DIMM_A_SELECT (0x1 << 16) | |
2642 | /* DIMM sizes are in multiples of 256mb. */ | |
2643 | #define MAD_DIMM_B_SIZE_SHIFT 8 | |
2644 | #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) | |
2645 | #define MAD_DIMM_A_SIZE_SHIFT 0 | |
2646 | #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) | |
2647 | ||
646b4269 | 2648 | /* snb MCH registers for priority tuning */ |
f0f59a00 | 2649 | #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) |
1d7aaa0c DV |
2650 | #define MCH_SSKPD_WM0_MASK 0x3f |
2651 | #define MCH_SSKPD_WM0_VAL 0xc | |
f691e2f4 | 2652 | |
f0f59a00 | 2653 | #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c) |
ec013e7f | 2654 | |
b11248df | 2655 | /* Clocking configuration register */ |
f0f59a00 | 2656 | #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) |
7662c8bd | 2657 | #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ |
b11248df KP |
2658 | #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ |
2659 | #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ | |
2660 | #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ | |
2661 | #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ | |
2662 | #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ | |
7662c8bd | 2663 | /* Note, below two are guess */ |
b11248df | 2664 | #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ |
7662c8bd | 2665 | #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ |
b11248df | 2666 | #define CLKCFG_FSB_MASK (7 << 0) |
7662c8bd SL |
2667 | #define CLKCFG_MEM_533 (1 << 4) |
2668 | #define CLKCFG_MEM_667 (2 << 4) | |
2669 | #define CLKCFG_MEM_800 (3 << 4) | |
2670 | #define CLKCFG_MEM_MASK (7 << 4) | |
2671 | ||
f0f59a00 VS |
2672 | #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) |
2673 | #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) | |
34edce2f | 2674 | |
f0f59a00 | 2675 | #define TSC1 _MMIO(0x11001) |
ea056c14 | 2676 | #define TSE (1<<0) |
f0f59a00 VS |
2677 | #define TR1 _MMIO(0x11006) |
2678 | #define TSFS _MMIO(0x11020) | |
7648fa99 JB |
2679 | #define TSFS_SLOPE_MASK 0x0000ff00 |
2680 | #define TSFS_SLOPE_SHIFT 8 | |
2681 | #define TSFS_INTR_MASK 0x000000ff | |
2682 | ||
f0f59a00 VS |
2683 | #define CRSTANDVID _MMIO(0x11100) |
2684 | #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ | |
f97108d1 JB |
2685 | #define PXVFREQ_PX_MASK 0x7f000000 |
2686 | #define PXVFREQ_PX_SHIFT 24 | |
f0f59a00 VS |
2687 | #define VIDFREQ_BASE _MMIO(0x11110) |
2688 | #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ | |
2689 | #define VIDFREQ2 _MMIO(0x11114) | |
2690 | #define VIDFREQ3 _MMIO(0x11118) | |
2691 | #define VIDFREQ4 _MMIO(0x1111c) | |
f97108d1 JB |
2692 | #define VIDFREQ_P0_MASK 0x1f000000 |
2693 | #define VIDFREQ_P0_SHIFT 24 | |
2694 | #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 | |
2695 | #define VIDFREQ_P0_CSCLK_SHIFT 20 | |
2696 | #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 | |
2697 | #define VIDFREQ_P0_CRCLK_SHIFT 16 | |
2698 | #define VIDFREQ_P1_MASK 0x00001f00 | |
2699 | #define VIDFREQ_P1_SHIFT 8 | |
2700 | #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 | |
2701 | #define VIDFREQ_P1_CSCLK_SHIFT 4 | |
2702 | #define VIDFREQ_P1_CRCLK_MASK 0x0000000f | |
f0f59a00 VS |
2703 | #define INTTOEXT_BASE_ILK _MMIO(0x11300) |
2704 | #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ | |
f97108d1 JB |
2705 | #define INTTOEXT_MAP3_SHIFT 24 |
2706 | #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) | |
2707 | #define INTTOEXT_MAP2_SHIFT 16 | |
2708 | #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) | |
2709 | #define INTTOEXT_MAP1_SHIFT 8 | |
2710 | #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) | |
2711 | #define INTTOEXT_MAP0_SHIFT 0 | |
2712 | #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) | |
f0f59a00 | 2713 | #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ |
f97108d1 JB |
2714 | #define MEMCTL_CMD_MASK 0xe000 |
2715 | #define MEMCTL_CMD_SHIFT 13 | |
2716 | #define MEMCTL_CMD_RCLK_OFF 0 | |
2717 | #define MEMCTL_CMD_RCLK_ON 1 | |
2718 | #define MEMCTL_CMD_CHFREQ 2 | |
2719 | #define MEMCTL_CMD_CHVID 3 | |
2720 | #define MEMCTL_CMD_VMMOFF 4 | |
2721 | #define MEMCTL_CMD_VMMON 5 | |
2722 | #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears | |
2723 | when command complete */ | |
2724 | #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ | |
2725 | #define MEMCTL_FREQ_SHIFT 8 | |
2726 | #define MEMCTL_SFCAVM (1<<7) | |
2727 | #define MEMCTL_TGT_VID_MASK 0x007f | |
f0f59a00 VS |
2728 | #define MEMIHYST _MMIO(0x1117c) |
2729 | #define MEMINTREN _MMIO(0x11180) /* 16 bits */ | |
f97108d1 JB |
2730 | #define MEMINT_RSEXIT_EN (1<<8) |
2731 | #define MEMINT_CX_SUPR_EN (1<<7) | |
2732 | #define MEMINT_CONT_BUSY_EN (1<<6) | |
2733 | #define MEMINT_AVG_BUSY_EN (1<<5) | |
2734 | #define MEMINT_EVAL_CHG_EN (1<<4) | |
2735 | #define MEMINT_MON_IDLE_EN (1<<3) | |
2736 | #define MEMINT_UP_EVAL_EN (1<<2) | |
2737 | #define MEMINT_DOWN_EVAL_EN (1<<1) | |
2738 | #define MEMINT_SW_CMD_EN (1<<0) | |
f0f59a00 | 2739 | #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ |
f97108d1 JB |
2740 | #define MEM_RSEXIT_MASK 0xc000 |
2741 | #define MEM_RSEXIT_SHIFT 14 | |
2742 | #define MEM_CONT_BUSY_MASK 0x3000 | |
2743 | #define MEM_CONT_BUSY_SHIFT 12 | |
2744 | #define MEM_AVG_BUSY_MASK 0x0c00 | |
2745 | #define MEM_AVG_BUSY_SHIFT 10 | |
2746 | #define MEM_EVAL_CHG_MASK 0x0300 | |
2747 | #define MEM_EVAL_BUSY_SHIFT 8 | |
2748 | #define MEM_MON_IDLE_MASK 0x00c0 | |
2749 | #define MEM_MON_IDLE_SHIFT 6 | |
2750 | #define MEM_UP_EVAL_MASK 0x0030 | |
2751 | #define MEM_UP_EVAL_SHIFT 4 | |
2752 | #define MEM_DOWN_EVAL_MASK 0x000c | |
2753 | #define MEM_DOWN_EVAL_SHIFT 2 | |
2754 | #define MEM_SW_CMD_MASK 0x0003 | |
2755 | #define MEM_INT_STEER_GFX 0 | |
2756 | #define MEM_INT_STEER_CMR 1 | |
2757 | #define MEM_INT_STEER_SMI 2 | |
2758 | #define MEM_INT_STEER_SCI 3 | |
f0f59a00 | 2759 | #define MEMINTRSTS _MMIO(0x11184) |
f97108d1 JB |
2760 | #define MEMINT_RSEXIT (1<<7) |
2761 | #define MEMINT_CONT_BUSY (1<<6) | |
2762 | #define MEMINT_AVG_BUSY (1<<5) | |
2763 | #define MEMINT_EVAL_CHG (1<<4) | |
2764 | #define MEMINT_MON_IDLE (1<<3) | |
2765 | #define MEMINT_UP_EVAL (1<<2) | |
2766 | #define MEMINT_DOWN_EVAL (1<<1) | |
2767 | #define MEMINT_SW_CMD (1<<0) | |
f0f59a00 | 2768 | #define MEMMODECTL _MMIO(0x11190) |
f97108d1 JB |
2769 | #define MEMMODE_BOOST_EN (1<<31) |
2770 | #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ | |
2771 | #define MEMMODE_BOOST_FREQ_SHIFT 24 | |
2772 | #define MEMMODE_IDLE_MODE_MASK 0x00030000 | |
2773 | #define MEMMODE_IDLE_MODE_SHIFT 16 | |
2774 | #define MEMMODE_IDLE_MODE_EVAL 0 | |
2775 | #define MEMMODE_IDLE_MODE_CONT 1 | |
2776 | #define MEMMODE_HWIDLE_EN (1<<15) | |
2777 | #define MEMMODE_SWMODE_EN (1<<14) | |
2778 | #define MEMMODE_RCLK_GATE (1<<13) | |
2779 | #define MEMMODE_HW_UPDATE (1<<12) | |
2780 | #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ | |
2781 | #define MEMMODE_FSTART_SHIFT 8 | |
2782 | #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ | |
2783 | #define MEMMODE_FMAX_SHIFT 4 | |
2784 | #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ | |
f0f59a00 VS |
2785 | #define RCBMAXAVG _MMIO(0x1119c) |
2786 | #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ | |
f97108d1 JB |
2787 | #define SWMEMCMD_RENDER_OFF (0 << 13) |
2788 | #define SWMEMCMD_RENDER_ON (1 << 13) | |
2789 | #define SWMEMCMD_SWFREQ (2 << 13) | |
2790 | #define SWMEMCMD_TARVID (3 << 13) | |
2791 | #define SWMEMCMD_VRM_OFF (4 << 13) | |
2792 | #define SWMEMCMD_VRM_ON (5 << 13) | |
2793 | #define CMDSTS (1<<12) | |
2794 | #define SFCAVM (1<<11) | |
2795 | #define SWFREQ_MASK 0x0380 /* P0-7 */ | |
2796 | #define SWFREQ_SHIFT 7 | |
2797 | #define TARVID_MASK 0x001f | |
f0f59a00 VS |
2798 | #define MEMSTAT_CTG _MMIO(0x111a0) |
2799 | #define RCBMINAVG _MMIO(0x111a0) | |
2800 | #define RCUPEI _MMIO(0x111b0) | |
2801 | #define RCDNEI _MMIO(0x111b4) | |
2802 | #define RSTDBYCTL _MMIO(0x111b8) | |
88271da3 JB |
2803 | #define RS1EN (1<<31) |
2804 | #define RS2EN (1<<30) | |
2805 | #define RS3EN (1<<29) | |
2806 | #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ | |
2807 | #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ | |
2808 | #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ | |
2809 | #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ | |
2810 | #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ | |
2811 | #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ | |
2812 | #define RSX_STATUS_MASK (7<<20) | |
2813 | #define RSX_STATUS_ON (0<<20) | |
2814 | #define RSX_STATUS_RC1 (1<<20) | |
2815 | #define RSX_STATUS_RC1E (2<<20) | |
2816 | #define RSX_STATUS_RS1 (3<<20) | |
2817 | #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ | |
2818 | #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ | |
2819 | #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ | |
2820 | #define RSX_STATUS_RSVD2 (7<<20) | |
2821 | #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ | |
2822 | #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ | |
2823 | #define JRSC (1<<17) /* rsx coupled to cpu c-state */ | |
2824 | #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ | |
2825 | #define RS1CONTSAV_MASK (3<<14) | |
2826 | #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ | |
2827 | #define RS1CONTSAV_RSVD (1<<14) | |
2828 | #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ | |
2829 | #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ | |
2830 | #define NORMSLEXLAT_MASK (3<<12) | |
2831 | #define SLOW_RS123 (0<<12) | |
2832 | #define SLOW_RS23 (1<<12) | |
2833 | #define SLOW_RS3 (2<<12) | |
2834 | #define NORMAL_RS123 (3<<12) | |
2835 | #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ | |
2836 | #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ | |
2837 | #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ | |
2838 | #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ | |
2839 | #define RS_CSTATE_MASK (3<<4) | |
2840 | #define RS_CSTATE_C367_RS1 (0<<4) | |
2841 | #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) | |
2842 | #define RS_CSTATE_RSVD (2<<4) | |
2843 | #define RS_CSTATE_C367_RS2 (3<<4) | |
2844 | #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ | |
2845 | #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ | |
f0f59a00 VS |
2846 | #define VIDCTL _MMIO(0x111c0) |
2847 | #define VIDSTS _MMIO(0x111c8) | |
2848 | #define VIDSTART _MMIO(0x111cc) /* 8 bits */ | |
2849 | #define MEMSTAT_ILK _MMIO(0x111f8) | |
f97108d1 JB |
2850 | #define MEMSTAT_VID_MASK 0x7f00 |
2851 | #define MEMSTAT_VID_SHIFT 8 | |
2852 | #define MEMSTAT_PSTATE_MASK 0x00f8 | |
2853 | #define MEMSTAT_PSTATE_SHIFT 3 | |
2854 | #define MEMSTAT_MON_ACTV (1<<2) | |
2855 | #define MEMSTAT_SRC_CTL_MASK 0x0003 | |
2856 | #define MEMSTAT_SRC_CTL_CORE 0 | |
2857 | #define MEMSTAT_SRC_CTL_TRB 1 | |
2858 | #define MEMSTAT_SRC_CTL_THM 2 | |
2859 | #define MEMSTAT_SRC_CTL_STDBY 3 | |
f0f59a00 VS |
2860 | #define RCPREVBSYTUPAVG _MMIO(0x113b8) |
2861 | #define RCPREVBSYTDNAVG _MMIO(0x113bc) | |
2862 | #define PMMISC _MMIO(0x11214) | |
ea056c14 | 2863 | #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ |
f0f59a00 VS |
2864 | #define SDEW _MMIO(0x1124c) |
2865 | #define CSIEW0 _MMIO(0x11250) | |
2866 | #define CSIEW1 _MMIO(0x11254) | |
2867 | #define CSIEW2 _MMIO(0x11258) | |
2868 | #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ | |
2869 | #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ | |
2870 | #define MCHAFE _MMIO(0x112c0) | |
2871 | #define CSIEC _MMIO(0x112e0) | |
2872 | #define DMIEC _MMIO(0x112e4) | |
2873 | #define DDREC _MMIO(0x112e8) | |
2874 | #define PEG0EC _MMIO(0x112ec) | |
2875 | #define PEG1EC _MMIO(0x112f0) | |
2876 | #define GFXEC _MMIO(0x112f4) | |
2877 | #define RPPREVBSYTUPAVG _MMIO(0x113b8) | |
2878 | #define RPPREVBSYTDNAVG _MMIO(0x113bc) | |
2879 | #define ECR _MMIO(0x11600) | |
7648fa99 JB |
2880 | #define ECR_GPFE (1<<31) |
2881 | #define ECR_IMONE (1<<30) | |
2882 | #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ | |
f0f59a00 VS |
2883 | #define OGW0 _MMIO(0x11608) |
2884 | #define OGW1 _MMIO(0x1160c) | |
2885 | #define EG0 _MMIO(0x11610) | |
2886 | #define EG1 _MMIO(0x11614) | |
2887 | #define EG2 _MMIO(0x11618) | |
2888 | #define EG3 _MMIO(0x1161c) | |
2889 | #define EG4 _MMIO(0x11620) | |
2890 | #define EG5 _MMIO(0x11624) | |
2891 | #define EG6 _MMIO(0x11628) | |
2892 | #define EG7 _MMIO(0x1162c) | |
2893 | #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ | |
2894 | #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ | |
2895 | #define LCFUSE02 _MMIO(0x116c0) | |
7648fa99 | 2896 | #define LCFUSE_HIV_MASK 0x000000ff |
f0f59a00 VS |
2897 | #define CSIPLL0 _MMIO(0x12c10) |
2898 | #define DDRMPLL1 _MMIO(0X12c20) | |
2899 | #define PEG_BAND_GAP_DATA _MMIO(0x14d68) | |
7d57382e | 2900 | |
f0f59a00 | 2901 | #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) |
c4de7b0f | 2902 | #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 |
c4de7b0f | 2903 | |
f0f59a00 VS |
2904 | #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) |
2905 | #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) | |
2906 | #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) | |
2907 | #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) | |
2908 | #define BXT_RP_STATE_CAP _MMIO(0x138170) | |
3b8d8d91 | 2909 | |
de43ae9d AG |
2910 | #define INTERVAL_1_28_US(us) (((us) * 100) >> 7) |
2911 | #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) | |
26148bd3 | 2912 | #define INTERVAL_0_833_US(us) (((us) * 6) / 5) |
de43ae9d | 2913 | #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \ |
26148bd3 AG |
2914 | (IS_BROXTON(dev_priv) ? \ |
2915 | INTERVAL_0_833_US(us) : \ | |
2916 | INTERVAL_1_33_US(us)) : \ | |
de43ae9d AG |
2917 | INTERVAL_1_28_US(us)) |
2918 | ||
aa40d6bb ZN |
2919 | /* |
2920 | * Logical Context regs | |
2921 | */ | |
f0f59a00 | 2922 | #define CCID _MMIO(0x2180) |
aa40d6bb | 2923 | #define CCID_EN (1<<0) |
e8016055 VS |
2924 | /* |
2925 | * Notes on SNB/IVB/VLV context size: | |
2926 | * - Power context is saved elsewhere (LLC or stolen) | |
2927 | * - Ring/execlist context is saved on SNB, not on IVB | |
2928 | * - Extended context size already includes render context size | |
2929 | * - We always need to follow the extended context size. | |
2930 | * SNB BSpec has comments indicating that we should use the | |
2931 | * render context size instead if execlists are disabled, but | |
2932 | * based on empirical testing that's just nonsense. | |
2933 | * - Pipelined/VF state is saved on SNB/IVB respectively | |
2934 | * - GT1 size just indicates how much of render context | |
2935 | * doesn't need saving on GT1 | |
2936 | */ | |
f0f59a00 | 2937 | #define CXT_SIZE _MMIO(0x21a0) |
68d97538 VS |
2938 | #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) |
2939 | #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) | |
2940 | #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) | |
2941 | #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) | |
2942 | #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) | |
e8016055 | 2943 | #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ |
fe1cc68f BW |
2944 | GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ |
2945 | GEN6_CXT_PIPELINE_SIZE(cxt_reg)) | |
f0f59a00 | 2946 | #define GEN7_CXT_SIZE _MMIO(0x21a8) |
68d97538 VS |
2947 | #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) |
2948 | #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) | |
2949 | #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) | |
2950 | #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) | |
2951 | #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) | |
2952 | #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) | |
e8016055 | 2953 | #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ |
4f91dd6f | 2954 | GEN7_CXT_VFSTATE_SIZE(ctx_reg)) |
a0de80a0 BW |
2955 | /* Haswell does have the CXT_SIZE register however it does not appear to be |
2956 | * valid. Now, docs explain in dwords what is in the context object. The full | |
2957 | * size is 70720 bytes, however, the power context and execlist context will | |
2958 | * never be saved (power context is stored elsewhere, and execlists don't work | |
4c436d55 AJ |
2959 | * on HSW) - so the final size, including the extra state required for the |
2960 | * Resource Streamer, is 66944 bytes, which rounds to 17 pages. | |
a0de80a0 BW |
2961 | */ |
2962 | #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) | |
8897644a BW |
2963 | /* Same as Haswell, but 72064 bytes now. */ |
2964 | #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) | |
2965 | ||
f0f59a00 VS |
2966 | #define CHV_CLK_CTL1 _MMIO(0x101100) |
2967 | #define VLV_CLK_CTL2 _MMIO(0x101104) | |
e454a05d JB |
2968 | #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 |
2969 | ||
585fb111 JB |
2970 | /* |
2971 | * Overlay regs | |
2972 | */ | |
2973 | ||
f0f59a00 VS |
2974 | #define OVADD _MMIO(0x30000) |
2975 | #define DOVSTA _MMIO(0x30008) | |
585fb111 | 2976 | #define OC_BUF (0x3<<20) |
f0f59a00 VS |
2977 | #define OGAMC5 _MMIO(0x30010) |
2978 | #define OGAMC4 _MMIO(0x30014) | |
2979 | #define OGAMC3 _MMIO(0x30018) | |
2980 | #define OGAMC2 _MMIO(0x3001c) | |
2981 | #define OGAMC1 _MMIO(0x30020) | |
2982 | #define OGAMC0 _MMIO(0x30024) | |
585fb111 | 2983 | |
d965e7ac ID |
2984 | /* |
2985 | * GEN9 clock gating regs | |
2986 | */ | |
2987 | #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) | |
2988 | #define PWM2_GATING_DIS (1 << 14) | |
2989 | #define PWM1_GATING_DIS (1 << 13) | |
2990 | ||
585fb111 JB |
2991 | /* |
2992 | * Display engine regs | |
2993 | */ | |
2994 | ||
8bf1e9f1 | 2995 | /* Pipe A CRC regs */ |
a57c774a | 2996 | #define _PIPE_CRC_CTL_A 0x60050 |
8bf1e9f1 | 2997 | #define PIPE_CRC_ENABLE (1 << 31) |
b4437a41 | 2998 | /* ivb+ source selection */ |
8bf1e9f1 SH |
2999 | #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) |
3000 | #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) | |
3001 | #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) | |
b4437a41 | 3002 | /* ilk+ source selection */ |
5a6b5c84 DV |
3003 | #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) |
3004 | #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) | |
3005 | #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) | |
3006 | /* embedded DP port on the north display block, reserved on ivb */ | |
3007 | #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) | |
3008 | #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ | |
b4437a41 DV |
3009 | /* vlv source selection */ |
3010 | #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) | |
3011 | #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) | |
3012 | #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) | |
3013 | /* with DP port the pipe source is invalid */ | |
3014 | #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) | |
3015 | #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) | |
3016 | #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) | |
3017 | /* gen3+ source selection */ | |
3018 | #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) | |
3019 | #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) | |
3020 | #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) | |
3021 | /* with DP/TV port the pipe source is invalid */ | |
3022 | #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) | |
3023 | #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) | |
3024 | #define PIPE_CRC_SOURCE_TV_POST (5 << 28) | |
3025 | #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) | |
3026 | #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) | |
3027 | /* gen2 doesn't have source selection bits */ | |
52f843f6 | 3028 | #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) |
b4437a41 | 3029 | |
5a6b5c84 DV |
3030 | #define _PIPE_CRC_RES_1_A_IVB 0x60064 |
3031 | #define _PIPE_CRC_RES_2_A_IVB 0x60068 | |
3032 | #define _PIPE_CRC_RES_3_A_IVB 0x6006c | |
3033 | #define _PIPE_CRC_RES_4_A_IVB 0x60070 | |
3034 | #define _PIPE_CRC_RES_5_A_IVB 0x60074 | |
3035 | ||
a57c774a AK |
3036 | #define _PIPE_CRC_RES_RED_A 0x60060 |
3037 | #define _PIPE_CRC_RES_GREEN_A 0x60064 | |
3038 | #define _PIPE_CRC_RES_BLUE_A 0x60068 | |
3039 | #define _PIPE_CRC_RES_RES1_A_I915 0x6006c | |
3040 | #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 | |
8bf1e9f1 SH |
3041 | |
3042 | /* Pipe B CRC regs */ | |
5a6b5c84 DV |
3043 | #define _PIPE_CRC_RES_1_B_IVB 0x61064 |
3044 | #define _PIPE_CRC_RES_2_B_IVB 0x61068 | |
3045 | #define _PIPE_CRC_RES_3_B_IVB 0x6106c | |
3046 | #define _PIPE_CRC_RES_4_B_IVB 0x61070 | |
3047 | #define _PIPE_CRC_RES_5_B_IVB 0x61074 | |
8bf1e9f1 | 3048 | |
f0f59a00 VS |
3049 | #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) |
3050 | #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) | |
3051 | #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) | |
3052 | #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) | |
3053 | #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) | |
3054 | #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) | |
3055 | ||
3056 | #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) | |
3057 | #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) | |
3058 | #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) | |
3059 | #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) | |
3060 | #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) | |
5a6b5c84 | 3061 | |
585fb111 | 3062 | /* Pipe A timing regs */ |
a57c774a AK |
3063 | #define _HTOTAL_A 0x60000 |
3064 | #define _HBLANK_A 0x60004 | |
3065 | #define _HSYNC_A 0x60008 | |
3066 | #define _VTOTAL_A 0x6000c | |
3067 | #define _VBLANK_A 0x60010 | |
3068 | #define _VSYNC_A 0x60014 | |
3069 | #define _PIPEASRC 0x6001c | |
3070 | #define _BCLRPAT_A 0x60020 | |
3071 | #define _VSYNCSHIFT_A 0x60028 | |
ebb69c95 | 3072 | #define _PIPE_MULT_A 0x6002c |
585fb111 JB |
3073 | |
3074 | /* Pipe B timing regs */ | |
a57c774a AK |
3075 | #define _HTOTAL_B 0x61000 |
3076 | #define _HBLANK_B 0x61004 | |
3077 | #define _HSYNC_B 0x61008 | |
3078 | #define _VTOTAL_B 0x6100c | |
3079 | #define _VBLANK_B 0x61010 | |
3080 | #define _VSYNC_B 0x61014 | |
3081 | #define _PIPEBSRC 0x6101c | |
3082 | #define _BCLRPAT_B 0x61020 | |
3083 | #define _VSYNCSHIFT_B 0x61028 | |
ebb69c95 | 3084 | #define _PIPE_MULT_B 0x6102c |
a57c774a AK |
3085 | |
3086 | #define TRANSCODER_A_OFFSET 0x60000 | |
3087 | #define TRANSCODER_B_OFFSET 0x61000 | |
3088 | #define TRANSCODER_C_OFFSET 0x62000 | |
84fd4f4e | 3089 | #define CHV_TRANSCODER_C_OFFSET 0x63000 |
a57c774a AK |
3090 | #define TRANSCODER_EDP_OFFSET 0x6f000 |
3091 | ||
f0f59a00 | 3092 | #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ |
5c969aa7 DL |
3093 | dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ |
3094 | dev_priv->info.display_mmio_offset) | |
a57c774a | 3095 | |
f0f59a00 VS |
3096 | #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) |
3097 | #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) | |
3098 | #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) | |
3099 | #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) | |
3100 | #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) | |
3101 | #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) | |
3102 | #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) | |
3103 | #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) | |
3104 | #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) | |
3105 | #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) | |
5eddb70b | 3106 | |
c8f7df58 RV |
3107 | /* VLV eDP PSR registers */ |
3108 | #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090) | |
3109 | #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090) | |
3110 | #define VLV_EDP_PSR_ENABLE (1<<0) | |
3111 | #define VLV_EDP_PSR_RESET (1<<1) | |
3112 | #define VLV_EDP_PSR_MODE_MASK (7<<2) | |
3113 | #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3) | |
3114 | #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2) | |
3115 | #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7) | |
3116 | #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8) | |
3117 | #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9) | |
3118 | #define VLV_EDP_PSR_DBL_FRAME (1<<10) | |
3119 | #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16) | |
3120 | #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16 | |
f0f59a00 | 3121 | #define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB) |
c8f7df58 RV |
3122 | |
3123 | #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0) | |
3124 | #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0) | |
3125 | #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30) | |
3126 | #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31) | |
3127 | #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30) | |
f0f59a00 | 3128 | #define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB) |
c8f7df58 RV |
3129 | |
3130 | #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094) | |
3131 | #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094) | |
3132 | #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3) | |
3133 | #define VLV_EDP_PSR_CURR_STATE_MASK 7 | |
3134 | #define VLV_EDP_PSR_DISABLED (0<<0) | |
3135 | #define VLV_EDP_PSR_INACTIVE (1<<0) | |
3136 | #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0) | |
3137 | #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0) | |
3138 | #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0) | |
3139 | #define VLV_EDP_PSR_EXIT (5<<0) | |
3140 | #define VLV_EDP_PSR_IN_TRANS (1<<7) | |
f0f59a00 | 3141 | #define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB) |
c8f7df58 | 3142 | |
ed8546ac | 3143 | /* HSW+ eDP PSR registers */ |
443a389f VS |
3144 | #define HSW_EDP_PSR_BASE 0x64800 |
3145 | #define BDW_EDP_PSR_BASE 0x6f800 | |
f0f59a00 | 3146 | #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) |
2b28bb1b | 3147 | #define EDP_PSR_ENABLE (1<<31) |
82c56254 | 3148 | #define BDW_PSR_SINGLE_FRAME (1<<30) |
2b28bb1b RV |
3149 | #define EDP_PSR_LINK_STANDBY (1<<27) |
3150 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) | |
3151 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) | |
3152 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) | |
3153 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) | |
3154 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) | |
3155 | #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 | |
3156 | #define EDP_PSR_SKIP_AUX_EXIT (1<<12) | |
3157 | #define EDP_PSR_TP1_TP2_SEL (0<<11) | |
3158 | #define EDP_PSR_TP1_TP3_SEL (1<<11) | |
3159 | #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) | |
3160 | #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) | |
3161 | #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) | |
3162 | #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) | |
3163 | #define EDP_PSR_TP1_TIME_500us (0<<4) | |
3164 | #define EDP_PSR_TP1_TIME_100us (1<<4) | |
3165 | #define EDP_PSR_TP1_TIME_2500us (2<<4) | |
3166 | #define EDP_PSR_TP1_TIME_0us (3<<4) | |
3167 | #define EDP_PSR_IDLE_FRAME_SHIFT 0 | |
3168 | ||
f0f59a00 VS |
3169 | #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) |
3170 | #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */ | |
2b28bb1b | 3171 | |
f0f59a00 | 3172 | #define EDP_PSR_STATUS_CTL _MMIO(dev_priv->psr_mmio_base + 0x40) |
2b28bb1b | 3173 | #define EDP_PSR_STATUS_STATE_MASK (7<<29) |
e91fd8c6 RV |
3174 | #define EDP_PSR_STATUS_STATE_IDLE (0<<29) |
3175 | #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) | |
3176 | #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) | |
3177 | #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) | |
3178 | #define EDP_PSR_STATUS_STATE_BUFON (4<<29) | |
3179 | #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) | |
3180 | #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) | |
3181 | #define EDP_PSR_STATUS_LINK_MASK (3<<26) | |
3182 | #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) | |
3183 | #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) | |
3184 | #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) | |
3185 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 | |
3186 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f | |
3187 | #define EDP_PSR_STATUS_COUNT_SHIFT 16 | |
3188 | #define EDP_PSR_STATUS_COUNT_MASK 0xf | |
3189 | #define EDP_PSR_STATUS_AUX_ERROR (1<<15) | |
3190 | #define EDP_PSR_STATUS_AUX_SENDING (1<<12) | |
3191 | #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) | |
3192 | #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) | |
3193 | #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) | |
3194 | #define EDP_PSR_STATUS_IDLE_MASK 0xf | |
3195 | ||
f0f59a00 | 3196 | #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44) |
e91fd8c6 | 3197 | #define EDP_PSR_PERF_CNT_MASK 0xffffff |
2b28bb1b | 3198 | |
f0f59a00 | 3199 | #define EDP_PSR_DEBUG_CTL _MMIO(dev_priv->psr_mmio_base + 0x60) |
2b28bb1b RV |
3200 | #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) |
3201 | #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) | |
3202 | #define EDP_PSR_DEBUG_MASK_HPD (1<<25) | |
3203 | ||
f0f59a00 | 3204 | #define EDP_PSR2_CTL _MMIO(0x6f900) |
474d1ec4 SJ |
3205 | #define EDP_PSR2_ENABLE (1<<31) |
3206 | #define EDP_SU_TRACK_ENABLE (1<<30) | |
3207 | #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20) | |
3208 | #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20) | |
3209 | #define EDP_PSR2_TP2_TIME_500 (0<<8) | |
3210 | #define EDP_PSR2_TP2_TIME_100 (1<<8) | |
3211 | #define EDP_PSR2_TP2_TIME_2500 (2<<8) | |
3212 | #define EDP_PSR2_TP2_TIME_50 (3<<8) | |
3213 | #define EDP_PSR2_TP2_TIME_MASK (3<<8) | |
3214 | #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 | |
3215 | #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) | |
3216 | #define EDP_PSR2_IDLE_MASK 0xf | |
3217 | ||
585fb111 | 3218 | /* VGA port control */ |
f0f59a00 VS |
3219 | #define ADPA _MMIO(0x61100) |
3220 | #define PCH_ADPA _MMIO(0xe1100) | |
3221 | #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) | |
ebc0fd88 | 3222 | |
585fb111 JB |
3223 | #define ADPA_DAC_ENABLE (1<<31) |
3224 | #define ADPA_DAC_DISABLE 0 | |
3225 | #define ADPA_PIPE_SELECT_MASK (1<<30) | |
3226 | #define ADPA_PIPE_A_SELECT 0 | |
3227 | #define ADPA_PIPE_B_SELECT (1<<30) | |
1519b995 | 3228 | #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) |
ebc0fd88 DV |
3229 | /* CPT uses bits 29:30 for pch transcoder select */ |
3230 | #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ | |
3231 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) | |
3232 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) | |
3233 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) | |
3234 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) | |
3235 | #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) | |
3236 | #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) | |
3237 | #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) | |
3238 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) | |
3239 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) | |
3240 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) | |
3241 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) | |
3242 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) | |
3243 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) | |
3244 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) | |
3245 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) | |
3246 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) | |
3247 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) | |
3248 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) | |
585fb111 JB |
3249 | #define ADPA_USE_VGA_HVPOLARITY (1<<15) |
3250 | #define ADPA_SETS_HVPOLARITY 0 | |
60222c0c | 3251 | #define ADPA_VSYNC_CNTL_DISABLE (1<<10) |
585fb111 | 3252 | #define ADPA_VSYNC_CNTL_ENABLE 0 |
60222c0c | 3253 | #define ADPA_HSYNC_CNTL_DISABLE (1<<11) |
585fb111 JB |
3254 | #define ADPA_HSYNC_CNTL_ENABLE 0 |
3255 | #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) | |
3256 | #define ADPA_VSYNC_ACTIVE_LOW 0 | |
3257 | #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) | |
3258 | #define ADPA_HSYNC_ACTIVE_LOW 0 | |
3259 | #define ADPA_DPMS_MASK (~(3<<10)) | |
3260 | #define ADPA_DPMS_ON (0<<10) | |
3261 | #define ADPA_DPMS_SUSPEND (1<<10) | |
3262 | #define ADPA_DPMS_STANDBY (2<<10) | |
3263 | #define ADPA_DPMS_OFF (3<<10) | |
3264 | ||
939fe4d7 | 3265 | |
585fb111 | 3266 | /* Hotplug control (945+ only) */ |
f0f59a00 | 3267 | #define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110) |
26739f12 DV |
3268 | #define PORTB_HOTPLUG_INT_EN (1 << 29) |
3269 | #define PORTC_HOTPLUG_INT_EN (1 << 28) | |
3270 | #define PORTD_HOTPLUG_INT_EN (1 << 27) | |
585fb111 JB |
3271 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
3272 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) | |
3273 | #define TV_HOTPLUG_INT_EN (1 << 18) | |
3274 | #define CRT_HOTPLUG_INT_EN (1 << 9) | |
e5868a31 EE |
3275 | #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ |
3276 | PORTC_HOTPLUG_INT_EN | \ | |
3277 | PORTD_HOTPLUG_INT_EN | \ | |
3278 | SDVOC_HOTPLUG_INT_EN | \ | |
3279 | SDVOB_HOTPLUG_INT_EN | \ | |
3280 | CRT_HOTPLUG_INT_EN) | |
585fb111 | 3281 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) |
771cb081 ZY |
3282 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
3283 | /* must use period 64 on GM45 according to docs */ | |
3284 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) | |
3285 | #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) | |
3286 | #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) | |
3287 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) | |
3288 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) | |
3289 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) | |
3290 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) | |
3291 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) | |
3292 | #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) | |
3293 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) | |
3294 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) | |
3295 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) | |
585fb111 | 3296 | |
f0f59a00 | 3297 | #define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114) |
0ce99f74 | 3298 | /* |
0780cd36 | 3299 | * HDMI/DP bits are g4x+ |
0ce99f74 DV |
3300 | * |
3301 | * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. | |
3302 | * Please check the detailed lore in the commit message for for experimental | |
3303 | * evidence. | |
3304 | */ | |
0780cd36 VS |
3305 | /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ |
3306 | #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) | |
3307 | #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) | |
3308 | #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) | |
3309 | /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ | |
3310 | #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) | |
232a6ee9 | 3311 | #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) |
0780cd36 | 3312 | #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) |
26739f12 | 3313 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
a211b497 DV |
3314 | #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) |
3315 | #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) | |
26739f12 | 3316 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
a211b497 DV |
3317 | #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) |
3318 | #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) | |
26739f12 | 3319 | #define PORTB_HOTPLUG_INT_STATUS (3 << 17) |
a211b497 DV |
3320 | #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) |
3321 | #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) | |
084b612e | 3322 | /* CRT/TV common between gen3+ */ |
585fb111 JB |
3323 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
3324 | #define TV_HOTPLUG_INT_STATUS (1 << 10) | |
3325 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) | |
3326 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) | |
3327 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) | |
3328 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) | |
4aeebd74 DV |
3329 | #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) |
3330 | #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) | |
3331 | #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) | |
bfbdb420 ID |
3332 | #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) |
3333 | ||
084b612e CW |
3334 | /* SDVO is different across gen3/4 */ |
3335 | #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) | |
3336 | #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) | |
4f7fd709 DV |
3337 | /* |
3338 | * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, | |
3339 | * since reality corrobates that they're the same as on gen3. But keep these | |
3340 | * bits here (and the comment!) to help any other lost wanderers back onto the | |
3341 | * right tracks. | |
3342 | */ | |
084b612e CW |
3343 | #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) |
3344 | #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) | |
3345 | #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) | |
3346 | #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) | |
e5868a31 EE |
3347 | #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ |
3348 | SDVOB_HOTPLUG_INT_STATUS_G4X | \ | |
3349 | SDVOC_HOTPLUG_INT_STATUS_G4X | \ | |
3350 | PORTB_HOTPLUG_INT_STATUS | \ | |
3351 | PORTC_HOTPLUG_INT_STATUS | \ | |
3352 | PORTD_HOTPLUG_INT_STATUS) | |
e5868a31 EE |
3353 | |
3354 | #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ | |
3355 | SDVOB_HOTPLUG_INT_STATUS_I915 | \ | |
3356 | SDVOC_HOTPLUG_INT_STATUS_I915 | \ | |
3357 | PORTB_HOTPLUG_INT_STATUS | \ | |
3358 | PORTC_HOTPLUG_INT_STATUS | \ | |
3359 | PORTD_HOTPLUG_INT_STATUS) | |
585fb111 | 3360 | |
c20cd312 PZ |
3361 | /* SDVO and HDMI port control. |
3362 | * The same register may be used for SDVO or HDMI */ | |
f0f59a00 VS |
3363 | #define _GEN3_SDVOB 0x61140 |
3364 | #define _GEN3_SDVOC 0x61160 | |
3365 | #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) | |
3366 | #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) | |
c20cd312 PZ |
3367 | #define GEN4_HDMIB GEN3_SDVOB |
3368 | #define GEN4_HDMIC GEN3_SDVOC | |
f0f59a00 VS |
3369 | #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) |
3370 | #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) | |
3371 | #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) | |
3372 | #define PCH_SDVOB _MMIO(0xe1140) | |
c20cd312 | 3373 | #define PCH_HDMIB PCH_SDVOB |
f0f59a00 VS |
3374 | #define PCH_HDMIC _MMIO(0xe1150) |
3375 | #define PCH_HDMID _MMIO(0xe1160) | |
c20cd312 | 3376 | |
f0f59a00 | 3377 | #define PORT_DFT_I9XX _MMIO(0x61150) |
84093603 | 3378 | #define DC_BALANCE_RESET (1 << 25) |
f0f59a00 | 3379 | #define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154) |
84093603 | 3380 | #define DC_BALANCE_RESET_VLV (1 << 31) |
eb736679 VS |
3381 | #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) |
3382 | #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ | |
84093603 DV |
3383 | #define PIPE_B_SCRAMBLE_RESET (1 << 1) |
3384 | #define PIPE_A_SCRAMBLE_RESET (1 << 0) | |
3385 | ||
c20cd312 PZ |
3386 | /* Gen 3 SDVO bits: */ |
3387 | #define SDVO_ENABLE (1 << 31) | |
dc0fa718 PZ |
3388 | #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) |
3389 | #define SDVO_PIPE_SEL_MASK (1 << 30) | |
c20cd312 PZ |
3390 | #define SDVO_PIPE_B_SELECT (1 << 30) |
3391 | #define SDVO_STALL_SELECT (1 << 29) | |
3392 | #define SDVO_INTERRUPT_ENABLE (1 << 26) | |
646b4269 | 3393 | /* |
585fb111 | 3394 | * 915G/GM SDVO pixel multiplier. |
585fb111 | 3395 | * Programmed value is multiplier - 1, up to 5x. |
585fb111 JB |
3396 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK |
3397 | */ | |
c20cd312 | 3398 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) |
585fb111 | 3399 | #define SDVO_PORT_MULTIPLY_SHIFT 23 |
c20cd312 PZ |
3400 | #define SDVO_PHASE_SELECT_MASK (15 << 19) |
3401 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) | |
3402 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) | |
3403 | #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ | |
3404 | #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ | |
3405 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ | |
3406 | #define SDVO_DETECTED (1 << 2) | |
585fb111 | 3407 | /* Bits to be preserved when writing */ |
c20cd312 PZ |
3408 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ |
3409 | SDVO_INTERRUPT_ENABLE) | |
3410 | #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) | |
3411 | ||
3412 | /* Gen 4 SDVO/HDMI bits: */ | |
4f3a8bc7 | 3413 | #define SDVO_COLOR_FORMAT_8bpc (0 << 26) |
18442d08 | 3414 | #define SDVO_COLOR_FORMAT_MASK (7 << 26) |
c20cd312 PZ |
3415 | #define SDVO_ENCODING_SDVO (0 << 10) |
3416 | #define SDVO_ENCODING_HDMI (2 << 10) | |
dc0fa718 PZ |
3417 | #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ |
3418 | #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ | |
4f3a8bc7 | 3419 | #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ |
c20cd312 PZ |
3420 | #define SDVO_AUDIO_ENABLE (1 << 6) |
3421 | /* VSYNC/HSYNC bits new with 965, default is to be set */ | |
3422 | #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) | |
3423 | #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) | |
3424 | ||
3425 | /* Gen 5 (IBX) SDVO/HDMI bits: */ | |
4f3a8bc7 | 3426 | #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ |
c20cd312 PZ |
3427 | #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ |
3428 | ||
3429 | /* Gen 6 (CPT) SDVO/HDMI bits: */ | |
dc0fa718 PZ |
3430 | #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) |
3431 | #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) | |
c20cd312 | 3432 | |
44f37d1f CML |
3433 | /* CHV SDVO/HDMI bits: */ |
3434 | #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) | |
3435 | #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) | |
3436 | ||
585fb111 JB |
3437 | |
3438 | /* DVO port control */ | |
f0f59a00 VS |
3439 | #define _DVOA 0x61120 |
3440 | #define DVOA _MMIO(_DVOA) | |
3441 | #define _DVOB 0x61140 | |
3442 | #define DVOB _MMIO(_DVOB) | |
3443 | #define _DVOC 0x61160 | |
3444 | #define DVOC _MMIO(_DVOC) | |
585fb111 JB |
3445 | #define DVO_ENABLE (1 << 31) |
3446 | #define DVO_PIPE_B_SELECT (1 << 30) | |
3447 | #define DVO_PIPE_STALL_UNUSED (0 << 28) | |
3448 | #define DVO_PIPE_STALL (1 << 28) | |
3449 | #define DVO_PIPE_STALL_TV (2 << 28) | |
3450 | #define DVO_PIPE_STALL_MASK (3 << 28) | |
3451 | #define DVO_USE_VGA_SYNC (1 << 15) | |
3452 | #define DVO_DATA_ORDER_I740 (0 << 14) | |
3453 | #define DVO_DATA_ORDER_FP (1 << 14) | |
3454 | #define DVO_VSYNC_DISABLE (1 << 11) | |
3455 | #define DVO_HSYNC_DISABLE (1 << 10) | |
3456 | #define DVO_VSYNC_TRISTATE (1 << 9) | |
3457 | #define DVO_HSYNC_TRISTATE (1 << 8) | |
3458 | #define DVO_BORDER_ENABLE (1 << 7) | |
3459 | #define DVO_DATA_ORDER_GBRG (1 << 6) | |
3460 | #define DVO_DATA_ORDER_RGGB (0 << 6) | |
3461 | #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) | |
3462 | #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) | |
3463 | #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) | |
3464 | #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) | |
3465 | #define DVO_BLANK_ACTIVE_HIGH (1 << 2) | |
3466 | #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ | |
3467 | #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ | |
3468 | #define DVO_PRESERVE_MASK (0x7<<24) | |
f0f59a00 VS |
3469 | #define DVOA_SRCDIM _MMIO(0x61124) |
3470 | #define DVOB_SRCDIM _MMIO(0x61144) | |
3471 | #define DVOC_SRCDIM _MMIO(0x61164) | |
585fb111 JB |
3472 | #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 |
3473 | #define DVO_SRCDIM_VERTICAL_SHIFT 0 | |
3474 | ||
3475 | /* LVDS port control */ | |
f0f59a00 | 3476 | #define LVDS _MMIO(0x61180) |
585fb111 JB |
3477 | /* |
3478 | * Enables the LVDS port. This bit must be set before DPLLs are enabled, as | |
3479 | * the DPLL semantics change when the LVDS is assigned to that pipe. | |
3480 | */ | |
3481 | #define LVDS_PORT_EN (1 << 31) | |
3482 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ | |
3483 | #define LVDS_PIPEB_SELECT (1 << 30) | |
47a05eca | 3484 | #define LVDS_PIPE_MASK (1 << 30) |
1519b995 | 3485 | #define LVDS_PIPE(pipe) ((pipe) << 30) |
898822ce ZY |
3486 | /* LVDS dithering flag on 965/g4x platform */ |
3487 | #define LVDS_ENABLE_DITHER (1 << 25) | |
aa9b500d BF |
3488 | /* LVDS sync polarity flags. Set to invert (i.e. negative) */ |
3489 | #define LVDS_VSYNC_POLARITY (1 << 21) | |
3490 | #define LVDS_HSYNC_POLARITY (1 << 20) | |
3491 | ||
a3e17eb8 ZY |
3492 | /* Enable border for unscaled (or aspect-scaled) display */ |
3493 | #define LVDS_BORDER_ENABLE (1 << 15) | |
585fb111 JB |
3494 | /* |
3495 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per | |
3496 | * pixel. | |
3497 | */ | |
3498 | #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) | |
3499 | #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) | |
3500 | #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) | |
3501 | /* | |
3502 | * Controls the A3 data pair, which contains the additional LSBs for 24 bit | |
3503 | * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be | |
3504 | * on. | |
3505 | */ | |
3506 | #define LVDS_A3_POWER_MASK (3 << 6) | |
3507 | #define LVDS_A3_POWER_DOWN (0 << 6) | |
3508 | #define LVDS_A3_POWER_UP (3 << 6) | |
3509 | /* | |
3510 | * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP | |
3511 | * is set. | |
3512 | */ | |
3513 | #define LVDS_CLKB_POWER_MASK (3 << 4) | |
3514 | #define LVDS_CLKB_POWER_DOWN (0 << 4) | |
3515 | #define LVDS_CLKB_POWER_UP (3 << 4) | |
3516 | /* | |
3517 | * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 | |
3518 | * setting for whether we are in dual-channel mode. The B3 pair will | |
3519 | * additionally only be powered up when LVDS_A3_POWER_UP is set. | |
3520 | */ | |
3521 | #define LVDS_B0B3_POWER_MASK (3 << 2) | |
3522 | #define LVDS_B0B3_POWER_DOWN (0 << 2) | |
3523 | #define LVDS_B0B3_POWER_UP (3 << 2) | |
3524 | ||
3c17fe4b | 3525 | /* Video Data Island Packet control */ |
f0f59a00 | 3526 | #define VIDEO_DIP_DATA _MMIO(0x61178) |
fd0753cf | 3527 | /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC |
adf00b26 PZ |
3528 | * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte |
3529 | * of the infoframe structure specified by CEA-861. */ | |
3530 | #define VIDEO_DIP_DATA_SIZE 32 | |
2b28bb1b | 3531 | #define VIDEO_DIP_VSC_DATA_SIZE 36 |
f0f59a00 | 3532 | #define VIDEO_DIP_CTL _MMIO(0x61170) |
2da8af54 | 3533 | /* Pre HSW: */ |
3c17fe4b | 3534 | #define VIDEO_DIP_ENABLE (1 << 31) |
822cdc52 | 3535 | #define VIDEO_DIP_PORT(port) ((port) << 29) |
3e6e6395 | 3536 | #define VIDEO_DIP_PORT_MASK (3 << 29) |
0dd87d20 | 3537 | #define VIDEO_DIP_ENABLE_GCP (1 << 25) |
3c17fe4b DH |
3538 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) |
3539 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) | |
0dd87d20 | 3540 | #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) |
3c17fe4b DH |
3541 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) |
3542 | #define VIDEO_DIP_SELECT_AVI (0 << 19) | |
3543 | #define VIDEO_DIP_SELECT_VENDOR (1 << 19) | |
3544 | #define VIDEO_DIP_SELECT_SPD (3 << 19) | |
45187ace | 3545 | #define VIDEO_DIP_SELECT_MASK (3 << 19) |
3c17fe4b DH |
3546 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) |
3547 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) | |
3548 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) | |
60c5ea2d | 3549 | #define VIDEO_DIP_FREQ_MASK (3 << 16) |
2da8af54 | 3550 | /* HSW and later: */ |
0dd87d20 PZ |
3551 | #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) |
3552 | #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) | |
2da8af54 | 3553 | #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) |
0dd87d20 PZ |
3554 | #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) |
3555 | #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) | |
2da8af54 | 3556 | #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) |
3c17fe4b | 3557 | |
585fb111 | 3558 | /* Panel power sequencing */ |
f0f59a00 | 3559 | #define PP_STATUS _MMIO(0x61200) |
585fb111 JB |
3560 | #define PP_ON (1 << 31) |
3561 | /* | |
3562 | * Indicates that all dependencies of the panel are on: | |
3563 | * | |
3564 | * - PLL enabled | |
3565 | * - pipe enabled | |
3566 | * - LVDS/DVOB/DVOC on | |
3567 | */ | |
3568 | #define PP_READY (1 << 30) | |
3569 | #define PP_SEQUENCE_NONE (0 << 28) | |
99ea7127 KP |
3570 | #define PP_SEQUENCE_POWER_UP (1 << 28) |
3571 | #define PP_SEQUENCE_POWER_DOWN (2 << 28) | |
3572 | #define PP_SEQUENCE_MASK (3 << 28) | |
3573 | #define PP_SEQUENCE_SHIFT 28 | |
01cb9ea6 | 3574 | #define PP_CYCLE_DELAY_ACTIVE (1 << 27) |
01cb9ea6 | 3575 | #define PP_SEQUENCE_STATE_MASK 0x0000000f |
99ea7127 KP |
3576 | #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) |
3577 | #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) | |
3578 | #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) | |
3579 | #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) | |
3580 | #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) | |
3581 | #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) | |
3582 | #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) | |
3583 | #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) | |
3584 | #define PP_SEQUENCE_STATE_RESET (0xf << 0) | |
f0f59a00 | 3585 | #define PP_CONTROL _MMIO(0x61204) |
585fb111 | 3586 | #define POWER_TARGET_ON (1 << 0) |
f0f59a00 VS |
3587 | #define PP_ON_DELAYS _MMIO(0x61208) |
3588 | #define PP_OFF_DELAYS _MMIO(0x6120c) | |
3589 | #define PP_DIVISOR _MMIO(0x61210) | |
585fb111 JB |
3590 | |
3591 | /* Panel fitting */ | |
f0f59a00 | 3592 | #define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230) |
585fb111 JB |
3593 | #define PFIT_ENABLE (1 << 31) |
3594 | #define PFIT_PIPE_MASK (3 << 29) | |
3595 | #define PFIT_PIPE_SHIFT 29 | |
3596 | #define VERT_INTERP_DISABLE (0 << 10) | |
3597 | #define VERT_INTERP_BILINEAR (1 << 10) | |
3598 | #define VERT_INTERP_MASK (3 << 10) | |
3599 | #define VERT_AUTO_SCALE (1 << 9) | |
3600 | #define HORIZ_INTERP_DISABLE (0 << 6) | |
3601 | #define HORIZ_INTERP_BILINEAR (1 << 6) | |
3602 | #define HORIZ_INTERP_MASK (3 << 6) | |
3603 | #define HORIZ_AUTO_SCALE (1 << 5) | |
3604 | #define PANEL_8TO6_DITHER_ENABLE (1 << 3) | |
3fbe18d6 ZY |
3605 | #define PFIT_FILTER_FUZZY (0 << 24) |
3606 | #define PFIT_SCALING_AUTO (0 << 26) | |
3607 | #define PFIT_SCALING_PROGRAMMED (1 << 26) | |
3608 | #define PFIT_SCALING_PILLAR (2 << 26) | |
3609 | #define PFIT_SCALING_LETTER (3 << 26) | |
f0f59a00 | 3610 | #define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234) |
3fbe18d6 ZY |
3611 | /* Pre-965 */ |
3612 | #define PFIT_VERT_SCALE_SHIFT 20 | |
3613 | #define PFIT_VERT_SCALE_MASK 0xfff00000 | |
3614 | #define PFIT_HORIZ_SCALE_SHIFT 4 | |
3615 | #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 | |
3616 | /* 965+ */ | |
3617 | #define PFIT_VERT_SCALE_SHIFT_965 16 | |
3618 | #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 | |
3619 | #define PFIT_HORIZ_SCALE_SHIFT_965 0 | |
3620 | #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff | |
3621 | ||
f0f59a00 | 3622 | #define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238) |
585fb111 | 3623 | |
5c969aa7 DL |
3624 | #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) |
3625 | #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) | |
f0f59a00 VS |
3626 | #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ |
3627 | _VLV_BLC_PWM_CTL2_B) | |
07bf139b | 3628 | |
5c969aa7 DL |
3629 | #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) |
3630 | #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) | |
f0f59a00 VS |
3631 | #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ |
3632 | _VLV_BLC_PWM_CTL_B) | |
07bf139b | 3633 | |
5c969aa7 DL |
3634 | #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) |
3635 | #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) | |
f0f59a00 VS |
3636 | #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ |
3637 | _VLV_BLC_HIST_CTL_B) | |
07bf139b | 3638 | |
585fb111 | 3639 | /* Backlight control */ |
f0f59a00 | 3640 | #define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ |
7cf41601 DV |
3641 | #define BLM_PWM_ENABLE (1 << 31) |
3642 | #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ | |
3643 | #define BLM_PIPE_SELECT (1 << 29) | |
3644 | #define BLM_PIPE_SELECT_IVB (3 << 29) | |
3645 | #define BLM_PIPE_A (0 << 29) | |
3646 | #define BLM_PIPE_B (1 << 29) | |
3647 | #define BLM_PIPE_C (2 << 29) /* ivb + */ | |
35ffda48 JN |
3648 | #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ |
3649 | #define BLM_TRANSCODER_B BLM_PIPE_B | |
3650 | #define BLM_TRANSCODER_C BLM_PIPE_C | |
3651 | #define BLM_TRANSCODER_EDP (3 << 29) | |
7cf41601 DV |
3652 | #define BLM_PIPE(pipe) ((pipe) << 29) |
3653 | #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ | |
3654 | #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) | |
3655 | #define BLM_PHASE_IN_ENABLE (1 << 25) | |
3656 | #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) | |
3657 | #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) | |
3658 | #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) | |
3659 | #define BLM_PHASE_IN_COUNT_SHIFT (8) | |
3660 | #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) | |
3661 | #define BLM_PHASE_IN_INCR_SHIFT (0) | |
3662 | #define BLM_PHASE_IN_INCR_MASK (0xff << 0) | |
f0f59a00 | 3663 | #define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254) |
ba3820ad TI |
3664 | /* |
3665 | * This is the most significant 15 bits of the number of backlight cycles in a | |
3666 | * complete cycle of the modulated backlight control. | |
3667 | * | |
3668 | * The actual value is this field multiplied by two. | |
3669 | */ | |
7cf41601 DV |
3670 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
3671 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) | |
3672 | #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ | |
585fb111 JB |
3673 | /* |
3674 | * This is the number of cycles out of the backlight modulation cycle for which | |
3675 | * the backlight is on. | |
3676 | * | |
3677 | * This field must be no greater than the number of cycles in the complete | |
3678 | * backlight modulation cycle. | |
3679 | */ | |
3680 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) | |
3681 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) | |
534b5a53 DV |
3682 | #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
3683 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ | |
585fb111 | 3684 | |
f0f59a00 | 3685 | #define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260) |
2059ac3b | 3686 | #define BLM_HISTOGRAM_ENABLE (1 << 31) |
0eb96d6e | 3687 | |
7cf41601 DV |
3688 | /* New registers for PCH-split platforms. Safe where new bits show up, the |
3689 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ | |
f0f59a00 VS |
3690 | #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) |
3691 | #define BLC_PWM_CPU_CTL _MMIO(0x48254) | |
7cf41601 | 3692 | |
f0f59a00 | 3693 | #define HSW_BLC_PWM2_CTL _MMIO(0x48350) |
be256dc7 | 3694 | |
7cf41601 DV |
3695 | /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is |
3696 | * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ | |
f0f59a00 | 3697 | #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) |
4b4147c3 | 3698 | #define BLM_PCH_PWM_ENABLE (1 << 31) |
7cf41601 DV |
3699 | #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) |
3700 | #define BLM_PCH_POLARITY (1 << 29) | |
f0f59a00 | 3701 | #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) |
7cf41601 | 3702 | |
f0f59a00 | 3703 | #define UTIL_PIN_CTL _MMIO(0x48400) |
be256dc7 PZ |
3704 | #define UTIL_PIN_ENABLE (1 << 31) |
3705 | ||
022e4e52 SK |
3706 | #define UTIL_PIN_PIPE(x) ((x) << 29) |
3707 | #define UTIL_PIN_PIPE_MASK (3 << 29) | |
3708 | #define UTIL_PIN_MODE_PWM (1 << 24) | |
3709 | #define UTIL_PIN_MODE_MASK (0xf << 24) | |
3710 | #define UTIL_PIN_POLARITY (1 << 22) | |
3711 | ||
0fb890c0 | 3712 | /* BXT backlight register definition. */ |
022e4e52 | 3713 | #define _BXT_BLC_PWM_CTL1 0xC8250 |
0fb890c0 VK |
3714 | #define BXT_BLC_PWM_ENABLE (1 << 31) |
3715 | #define BXT_BLC_PWM_POLARITY (1 << 29) | |
022e4e52 SK |
3716 | #define _BXT_BLC_PWM_FREQ1 0xC8254 |
3717 | #define _BXT_BLC_PWM_DUTY1 0xC8258 | |
3718 | ||
3719 | #define _BXT_BLC_PWM_CTL2 0xC8350 | |
3720 | #define _BXT_BLC_PWM_FREQ2 0xC8354 | |
3721 | #define _BXT_BLC_PWM_DUTY2 0xC8358 | |
3722 | ||
f0f59a00 | 3723 | #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ |
022e4e52 | 3724 | _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) |
f0f59a00 | 3725 | #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ |
022e4e52 | 3726 | _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) |
f0f59a00 | 3727 | #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ |
022e4e52 | 3728 | _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) |
0fb890c0 | 3729 | |
f0f59a00 | 3730 | #define PCH_GTC_CTL _MMIO(0xe7000) |
be256dc7 PZ |
3731 | #define PCH_GTC_ENABLE (1 << 31) |
3732 | ||
585fb111 | 3733 | /* TV port control */ |
f0f59a00 | 3734 | #define TV_CTL _MMIO(0x68000) |
646b4269 | 3735 | /* Enables the TV encoder */ |
585fb111 | 3736 | # define TV_ENC_ENABLE (1 << 31) |
646b4269 | 3737 | /* Sources the TV encoder input from pipe B instead of A. */ |
585fb111 | 3738 | # define TV_ENC_PIPEB_SELECT (1 << 30) |
646b4269 | 3739 | /* Outputs composite video (DAC A only) */ |
585fb111 | 3740 | # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) |
646b4269 | 3741 | /* Outputs SVideo video (DAC B/C) */ |
585fb111 | 3742 | # define TV_ENC_OUTPUT_SVIDEO (1 << 28) |
646b4269 | 3743 | /* Outputs Component video (DAC A/B/C) */ |
585fb111 | 3744 | # define TV_ENC_OUTPUT_COMPONENT (2 << 28) |
646b4269 | 3745 | /* Outputs Composite and SVideo (DAC A/B/C) */ |
585fb111 JB |
3746 | # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) |
3747 | # define TV_TRILEVEL_SYNC (1 << 21) | |
646b4269 | 3748 | /* Enables slow sync generation (945GM only) */ |
585fb111 | 3749 | # define TV_SLOW_SYNC (1 << 20) |
646b4269 | 3750 | /* Selects 4x oversampling for 480i and 576p */ |
585fb111 | 3751 | # define TV_OVERSAMPLE_4X (0 << 18) |
646b4269 | 3752 | /* Selects 2x oversampling for 720p and 1080i */ |
585fb111 | 3753 | # define TV_OVERSAMPLE_2X (1 << 18) |
646b4269 | 3754 | /* Selects no oversampling for 1080p */ |
585fb111 | 3755 | # define TV_OVERSAMPLE_NONE (2 << 18) |
646b4269 | 3756 | /* Selects 8x oversampling */ |
585fb111 | 3757 | # define TV_OVERSAMPLE_8X (3 << 18) |
646b4269 | 3758 | /* Selects progressive mode rather than interlaced */ |
585fb111 | 3759 | # define TV_PROGRESSIVE (1 << 17) |
646b4269 | 3760 | /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ |
585fb111 | 3761 | # define TV_PAL_BURST (1 << 16) |
646b4269 | 3762 | /* Field for setting delay of Y compared to C */ |
585fb111 | 3763 | # define TV_YC_SKEW_MASK (7 << 12) |
646b4269 | 3764 | /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ |
585fb111 | 3765 | # define TV_ENC_SDP_FIX (1 << 11) |
646b4269 | 3766 | /* |
585fb111 JB |
3767 | * Enables a fix for the 915GM only. |
3768 | * | |
3769 | * Not sure what it does. | |
3770 | */ | |
3771 | # define TV_ENC_C0_FIX (1 << 10) | |
646b4269 | 3772 | /* Bits that must be preserved by software */ |
d2d9f232 | 3773 | # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) |
585fb111 | 3774 | # define TV_FUSE_STATE_MASK (3 << 4) |
646b4269 | 3775 | /* Read-only state that reports all features enabled */ |
585fb111 | 3776 | # define TV_FUSE_STATE_ENABLED (0 << 4) |
646b4269 | 3777 | /* Read-only state that reports that Macrovision is disabled in hardware*/ |
585fb111 | 3778 | # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) |
646b4269 | 3779 | /* Read-only state that reports that TV-out is disabled in hardware. */ |
585fb111 | 3780 | # define TV_FUSE_STATE_DISABLED (2 << 4) |
646b4269 | 3781 | /* Normal operation */ |
585fb111 | 3782 | # define TV_TEST_MODE_NORMAL (0 << 0) |
646b4269 | 3783 | /* Encoder test pattern 1 - combo pattern */ |
585fb111 | 3784 | # define TV_TEST_MODE_PATTERN_1 (1 << 0) |
646b4269 | 3785 | /* Encoder test pattern 2 - full screen vertical 75% color bars */ |
585fb111 | 3786 | # define TV_TEST_MODE_PATTERN_2 (2 << 0) |
646b4269 | 3787 | /* Encoder test pattern 3 - full screen horizontal 75% color bars */ |
585fb111 | 3788 | # define TV_TEST_MODE_PATTERN_3 (3 << 0) |
646b4269 | 3789 | /* Encoder test pattern 4 - random noise */ |
585fb111 | 3790 | # define TV_TEST_MODE_PATTERN_4 (4 << 0) |
646b4269 | 3791 | /* Encoder test pattern 5 - linear color ramps */ |
585fb111 | 3792 | # define TV_TEST_MODE_PATTERN_5 (5 << 0) |
646b4269 | 3793 | /* |
585fb111 JB |
3794 | * This test mode forces the DACs to 50% of full output. |
3795 | * | |
3796 | * This is used for load detection in combination with TVDAC_SENSE_MASK | |
3797 | */ | |
3798 | # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) | |
3799 | # define TV_TEST_MODE_MASK (7 << 0) | |
3800 | ||
f0f59a00 | 3801 | #define TV_DAC _MMIO(0x68004) |
b8ed2a4f | 3802 | # define TV_DAC_SAVE 0x00ffff00 |
646b4269 | 3803 | /* |
585fb111 JB |
3804 | * Reports that DAC state change logic has reported change (RO). |
3805 | * | |
3806 | * This gets cleared when TV_DAC_STATE_EN is cleared | |
3807 | */ | |
3808 | # define TVDAC_STATE_CHG (1 << 31) | |
3809 | # define TVDAC_SENSE_MASK (7 << 28) | |
646b4269 | 3810 | /* Reports that DAC A voltage is above the detect threshold */ |
585fb111 | 3811 | # define TVDAC_A_SENSE (1 << 30) |
646b4269 | 3812 | /* Reports that DAC B voltage is above the detect threshold */ |
585fb111 | 3813 | # define TVDAC_B_SENSE (1 << 29) |
646b4269 | 3814 | /* Reports that DAC C voltage is above the detect threshold */ |
585fb111 | 3815 | # define TVDAC_C_SENSE (1 << 28) |
646b4269 | 3816 | /* |
585fb111 JB |
3817 | * Enables DAC state detection logic, for load-based TV detection. |
3818 | * | |
3819 | * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set | |
3820 | * to off, for load detection to work. | |
3821 | */ | |
3822 | # define TVDAC_STATE_CHG_EN (1 << 27) | |
646b4269 | 3823 | /* Sets the DAC A sense value to high */ |
585fb111 | 3824 | # define TVDAC_A_SENSE_CTL (1 << 26) |
646b4269 | 3825 | /* Sets the DAC B sense value to high */ |
585fb111 | 3826 | # define TVDAC_B_SENSE_CTL (1 << 25) |
646b4269 | 3827 | /* Sets the DAC C sense value to high */ |
585fb111 | 3828 | # define TVDAC_C_SENSE_CTL (1 << 24) |
646b4269 | 3829 | /* Overrides the ENC_ENABLE and DAC voltage levels */ |
585fb111 | 3830 | # define DAC_CTL_OVERRIDE (1 << 7) |
646b4269 | 3831 | /* Sets the slew rate. Must be preserved in software */ |
585fb111 JB |
3832 | # define ENC_TVDAC_SLEW_FAST (1 << 6) |
3833 | # define DAC_A_1_3_V (0 << 4) | |
3834 | # define DAC_A_1_1_V (1 << 4) | |
3835 | # define DAC_A_0_7_V (2 << 4) | |
cb66c692 | 3836 | # define DAC_A_MASK (3 << 4) |
585fb111 JB |
3837 | # define DAC_B_1_3_V (0 << 2) |
3838 | # define DAC_B_1_1_V (1 << 2) | |
3839 | # define DAC_B_0_7_V (2 << 2) | |
cb66c692 | 3840 | # define DAC_B_MASK (3 << 2) |
585fb111 JB |
3841 | # define DAC_C_1_3_V (0 << 0) |
3842 | # define DAC_C_1_1_V (1 << 0) | |
3843 | # define DAC_C_0_7_V (2 << 0) | |
cb66c692 | 3844 | # define DAC_C_MASK (3 << 0) |
585fb111 | 3845 | |
646b4269 | 3846 | /* |
585fb111 JB |
3847 | * CSC coefficients are stored in a floating point format with 9 bits of |
3848 | * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, | |
3849 | * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with | |
3850 | * -1 (0x3) being the only legal negative value. | |
3851 | */ | |
f0f59a00 | 3852 | #define TV_CSC_Y _MMIO(0x68010) |
585fb111 JB |
3853 | # define TV_RY_MASK 0x07ff0000 |
3854 | # define TV_RY_SHIFT 16 | |
3855 | # define TV_GY_MASK 0x00000fff | |
3856 | # define TV_GY_SHIFT 0 | |
3857 | ||
f0f59a00 | 3858 | #define TV_CSC_Y2 _MMIO(0x68014) |
585fb111 JB |
3859 | # define TV_BY_MASK 0x07ff0000 |
3860 | # define TV_BY_SHIFT 16 | |
646b4269 | 3861 | /* |
585fb111 JB |
3862 | * Y attenuation for component video. |
3863 | * | |
3864 | * Stored in 1.9 fixed point. | |
3865 | */ | |
3866 | # define TV_AY_MASK 0x000003ff | |
3867 | # define TV_AY_SHIFT 0 | |
3868 | ||
f0f59a00 | 3869 | #define TV_CSC_U _MMIO(0x68018) |
585fb111 JB |
3870 | # define TV_RU_MASK 0x07ff0000 |
3871 | # define TV_RU_SHIFT 16 | |
3872 | # define TV_GU_MASK 0x000007ff | |
3873 | # define TV_GU_SHIFT 0 | |
3874 | ||
f0f59a00 | 3875 | #define TV_CSC_U2 _MMIO(0x6801c) |
585fb111 JB |
3876 | # define TV_BU_MASK 0x07ff0000 |
3877 | # define TV_BU_SHIFT 16 | |
646b4269 | 3878 | /* |
585fb111 JB |
3879 | * U attenuation for component video. |
3880 | * | |
3881 | * Stored in 1.9 fixed point. | |
3882 | */ | |
3883 | # define TV_AU_MASK 0x000003ff | |
3884 | # define TV_AU_SHIFT 0 | |
3885 | ||
f0f59a00 | 3886 | #define TV_CSC_V _MMIO(0x68020) |
585fb111 JB |
3887 | # define TV_RV_MASK 0x0fff0000 |
3888 | # define TV_RV_SHIFT 16 | |
3889 | # define TV_GV_MASK 0x000007ff | |
3890 | # define TV_GV_SHIFT 0 | |
3891 | ||
f0f59a00 | 3892 | #define TV_CSC_V2 _MMIO(0x68024) |
585fb111 JB |
3893 | # define TV_BV_MASK 0x07ff0000 |
3894 | # define TV_BV_SHIFT 16 | |
646b4269 | 3895 | /* |
585fb111 JB |
3896 | * V attenuation for component video. |
3897 | * | |
3898 | * Stored in 1.9 fixed point. | |
3899 | */ | |
3900 | # define TV_AV_MASK 0x000007ff | |
3901 | # define TV_AV_SHIFT 0 | |
3902 | ||
f0f59a00 | 3903 | #define TV_CLR_KNOBS _MMIO(0x68028) |
646b4269 | 3904 | /* 2s-complement brightness adjustment */ |
585fb111 JB |
3905 | # define TV_BRIGHTNESS_MASK 0xff000000 |
3906 | # define TV_BRIGHTNESS_SHIFT 24 | |
646b4269 | 3907 | /* Contrast adjustment, as a 2.6 unsigned floating point number */ |
585fb111 JB |
3908 | # define TV_CONTRAST_MASK 0x00ff0000 |
3909 | # define TV_CONTRAST_SHIFT 16 | |
646b4269 | 3910 | /* Saturation adjustment, as a 2.6 unsigned floating point number */ |
585fb111 JB |
3911 | # define TV_SATURATION_MASK 0x0000ff00 |
3912 | # define TV_SATURATION_SHIFT 8 | |
646b4269 | 3913 | /* Hue adjustment, as an integer phase angle in degrees */ |
585fb111 JB |
3914 | # define TV_HUE_MASK 0x000000ff |
3915 | # define TV_HUE_SHIFT 0 | |
3916 | ||
f0f59a00 | 3917 | #define TV_CLR_LEVEL _MMIO(0x6802c) |
646b4269 | 3918 | /* Controls the DAC level for black */ |
585fb111 JB |
3919 | # define TV_BLACK_LEVEL_MASK 0x01ff0000 |
3920 | # define TV_BLACK_LEVEL_SHIFT 16 | |
646b4269 | 3921 | /* Controls the DAC level for blanking */ |
585fb111 JB |
3922 | # define TV_BLANK_LEVEL_MASK 0x000001ff |
3923 | # define TV_BLANK_LEVEL_SHIFT 0 | |
3924 | ||
f0f59a00 | 3925 | #define TV_H_CTL_1 _MMIO(0x68030) |
646b4269 | 3926 | /* Number of pixels in the hsync. */ |
585fb111 JB |
3927 | # define TV_HSYNC_END_MASK 0x1fff0000 |
3928 | # define TV_HSYNC_END_SHIFT 16 | |
646b4269 | 3929 | /* Total number of pixels minus one in the line (display and blanking). */ |
585fb111 JB |
3930 | # define TV_HTOTAL_MASK 0x00001fff |
3931 | # define TV_HTOTAL_SHIFT 0 | |
3932 | ||
f0f59a00 | 3933 | #define TV_H_CTL_2 _MMIO(0x68034) |
646b4269 | 3934 | /* Enables the colorburst (needed for non-component color) */ |
585fb111 | 3935 | # define TV_BURST_ENA (1 << 31) |
646b4269 | 3936 | /* Offset of the colorburst from the start of hsync, in pixels minus one. */ |
585fb111 JB |
3937 | # define TV_HBURST_START_SHIFT 16 |
3938 | # define TV_HBURST_START_MASK 0x1fff0000 | |
646b4269 | 3939 | /* Length of the colorburst */ |
585fb111 JB |
3940 | # define TV_HBURST_LEN_SHIFT 0 |
3941 | # define TV_HBURST_LEN_MASK 0x0001fff | |
3942 | ||
f0f59a00 | 3943 | #define TV_H_CTL_3 _MMIO(0x68038) |
646b4269 | 3944 | /* End of hblank, measured in pixels minus one from start of hsync */ |
585fb111 JB |
3945 | # define TV_HBLANK_END_SHIFT 16 |
3946 | # define TV_HBLANK_END_MASK 0x1fff0000 | |
646b4269 | 3947 | /* Start of hblank, measured in pixels minus one from start of hsync */ |
585fb111 JB |
3948 | # define TV_HBLANK_START_SHIFT 0 |
3949 | # define TV_HBLANK_START_MASK 0x0001fff | |
3950 | ||
f0f59a00 | 3951 | #define TV_V_CTL_1 _MMIO(0x6803c) |
646b4269 | 3952 | /* XXX */ |
585fb111 JB |
3953 | # define TV_NBR_END_SHIFT 16 |
3954 | # define TV_NBR_END_MASK 0x07ff0000 | |
646b4269 | 3955 | /* XXX */ |
585fb111 JB |
3956 | # define TV_VI_END_F1_SHIFT 8 |
3957 | # define TV_VI_END_F1_MASK 0x00003f00 | |
646b4269 | 3958 | /* XXX */ |
585fb111 JB |
3959 | # define TV_VI_END_F2_SHIFT 0 |
3960 | # define TV_VI_END_F2_MASK 0x0000003f | |
3961 | ||
f0f59a00 | 3962 | #define TV_V_CTL_2 _MMIO(0x68040) |
646b4269 | 3963 | /* Length of vsync, in half lines */ |
585fb111 JB |
3964 | # define TV_VSYNC_LEN_MASK 0x07ff0000 |
3965 | # define TV_VSYNC_LEN_SHIFT 16 | |
646b4269 | 3966 | /* Offset of the start of vsync in field 1, measured in one less than the |
585fb111 JB |
3967 | * number of half lines. |
3968 | */ | |
3969 | # define TV_VSYNC_START_F1_MASK 0x00007f00 | |
3970 | # define TV_VSYNC_START_F1_SHIFT 8 | |
646b4269 | 3971 | /* |
585fb111 JB |
3972 | * Offset of the start of vsync in field 2, measured in one less than the |
3973 | * number of half lines. | |
3974 | */ | |
3975 | # define TV_VSYNC_START_F2_MASK 0x0000007f | |
3976 | # define TV_VSYNC_START_F2_SHIFT 0 | |
3977 | ||
f0f59a00 | 3978 | #define TV_V_CTL_3 _MMIO(0x68044) |
646b4269 | 3979 | /* Enables generation of the equalization signal */ |
585fb111 | 3980 | # define TV_EQUAL_ENA (1 << 31) |
646b4269 | 3981 | /* Length of vsync, in half lines */ |
585fb111 JB |
3982 | # define TV_VEQ_LEN_MASK 0x007f0000 |
3983 | # define TV_VEQ_LEN_SHIFT 16 | |
646b4269 | 3984 | /* Offset of the start of equalization in field 1, measured in one less than |
585fb111 JB |
3985 | * the number of half lines. |
3986 | */ | |
3987 | # define TV_VEQ_START_F1_MASK 0x0007f00 | |
3988 | # define TV_VEQ_START_F1_SHIFT 8 | |
646b4269 | 3989 | /* |
585fb111 JB |
3990 | * Offset of the start of equalization in field 2, measured in one less than |
3991 | * the number of half lines. | |
3992 | */ | |
3993 | # define TV_VEQ_START_F2_MASK 0x000007f | |
3994 | # define TV_VEQ_START_F2_SHIFT 0 | |
3995 | ||
f0f59a00 | 3996 | #define TV_V_CTL_4 _MMIO(0x68048) |
646b4269 | 3997 | /* |
585fb111 JB |
3998 | * Offset to start of vertical colorburst, measured in one less than the |
3999 | * number of lines from vertical start. | |
4000 | */ | |
4001 | # define TV_VBURST_START_F1_MASK 0x003f0000 | |
4002 | # define TV_VBURST_START_F1_SHIFT 16 | |
646b4269 | 4003 | /* |
585fb111 JB |
4004 | * Offset to the end of vertical colorburst, measured in one less than the |
4005 | * number of lines from the start of NBR. | |
4006 | */ | |
4007 | # define TV_VBURST_END_F1_MASK 0x000000ff | |
4008 | # define TV_VBURST_END_F1_SHIFT 0 | |
4009 | ||
f0f59a00 | 4010 | #define TV_V_CTL_5 _MMIO(0x6804c) |
646b4269 | 4011 | /* |
585fb111 JB |
4012 | * Offset to start of vertical colorburst, measured in one less than the |
4013 | * number of lines from vertical start. | |
4014 | */ | |
4015 | # define TV_VBURST_START_F2_MASK 0x003f0000 | |
4016 | # define TV_VBURST_START_F2_SHIFT 16 | |
646b4269 | 4017 | /* |
585fb111 JB |
4018 | * Offset to the end of vertical colorburst, measured in one less than the |
4019 | * number of lines from the start of NBR. | |
4020 | */ | |
4021 | # define TV_VBURST_END_F2_MASK 0x000000ff | |
4022 | # define TV_VBURST_END_F2_SHIFT 0 | |
4023 | ||
f0f59a00 | 4024 | #define TV_V_CTL_6 _MMIO(0x68050) |
646b4269 | 4025 | /* |
585fb111 JB |
4026 | * Offset to start of vertical colorburst, measured in one less than the |
4027 | * number of lines from vertical start. | |
4028 | */ | |
4029 | # define TV_VBURST_START_F3_MASK 0x003f0000 | |
4030 | # define TV_VBURST_START_F3_SHIFT 16 | |
646b4269 | 4031 | /* |
585fb111 JB |
4032 | * Offset to the end of vertical colorburst, measured in one less than the |
4033 | * number of lines from the start of NBR. | |
4034 | */ | |
4035 | # define TV_VBURST_END_F3_MASK 0x000000ff | |
4036 | # define TV_VBURST_END_F3_SHIFT 0 | |
4037 | ||
f0f59a00 | 4038 | #define TV_V_CTL_7 _MMIO(0x68054) |
646b4269 | 4039 | /* |
585fb111 JB |
4040 | * Offset to start of vertical colorburst, measured in one less than the |
4041 | * number of lines from vertical start. | |
4042 | */ | |
4043 | # define TV_VBURST_START_F4_MASK 0x003f0000 | |
4044 | # define TV_VBURST_START_F4_SHIFT 16 | |
646b4269 | 4045 | /* |
585fb111 JB |
4046 | * Offset to the end of vertical colorburst, measured in one less than the |
4047 | * number of lines from the start of NBR. | |
4048 | */ | |
4049 | # define TV_VBURST_END_F4_MASK 0x000000ff | |
4050 | # define TV_VBURST_END_F4_SHIFT 0 | |
4051 | ||
f0f59a00 | 4052 | #define TV_SC_CTL_1 _MMIO(0x68060) |
646b4269 | 4053 | /* Turns on the first subcarrier phase generation DDA */ |
585fb111 | 4054 | # define TV_SC_DDA1_EN (1 << 31) |
646b4269 | 4055 | /* Turns on the first subcarrier phase generation DDA */ |
585fb111 | 4056 | # define TV_SC_DDA2_EN (1 << 30) |
646b4269 | 4057 | /* Turns on the first subcarrier phase generation DDA */ |
585fb111 | 4058 | # define TV_SC_DDA3_EN (1 << 29) |
646b4269 | 4059 | /* Sets the subcarrier DDA to reset frequency every other field */ |
585fb111 | 4060 | # define TV_SC_RESET_EVERY_2 (0 << 24) |
646b4269 | 4061 | /* Sets the subcarrier DDA to reset frequency every fourth field */ |
585fb111 | 4062 | # define TV_SC_RESET_EVERY_4 (1 << 24) |
646b4269 | 4063 | /* Sets the subcarrier DDA to reset frequency every eighth field */ |
585fb111 | 4064 | # define TV_SC_RESET_EVERY_8 (2 << 24) |
646b4269 | 4065 | /* Sets the subcarrier DDA to never reset the frequency */ |
585fb111 | 4066 | # define TV_SC_RESET_NEVER (3 << 24) |
646b4269 | 4067 | /* Sets the peak amplitude of the colorburst.*/ |
585fb111 JB |
4068 | # define TV_BURST_LEVEL_MASK 0x00ff0000 |
4069 | # define TV_BURST_LEVEL_SHIFT 16 | |
646b4269 | 4070 | /* Sets the increment of the first subcarrier phase generation DDA */ |
585fb111 JB |
4071 | # define TV_SCDDA1_INC_MASK 0x00000fff |
4072 | # define TV_SCDDA1_INC_SHIFT 0 | |
4073 | ||
f0f59a00 | 4074 | #define TV_SC_CTL_2 _MMIO(0x68064) |
646b4269 | 4075 | /* Sets the rollover for the second subcarrier phase generation DDA */ |
585fb111 JB |
4076 | # define TV_SCDDA2_SIZE_MASK 0x7fff0000 |
4077 | # define TV_SCDDA2_SIZE_SHIFT 16 | |
646b4269 | 4078 | /* Sets the increent of the second subcarrier phase generation DDA */ |
585fb111 JB |
4079 | # define TV_SCDDA2_INC_MASK 0x00007fff |
4080 | # define TV_SCDDA2_INC_SHIFT 0 | |
4081 | ||
f0f59a00 | 4082 | #define TV_SC_CTL_3 _MMIO(0x68068) |
646b4269 | 4083 | /* Sets the rollover for the third subcarrier phase generation DDA */ |
585fb111 JB |
4084 | # define TV_SCDDA3_SIZE_MASK 0x7fff0000 |
4085 | # define TV_SCDDA3_SIZE_SHIFT 16 | |
646b4269 | 4086 | /* Sets the increent of the third subcarrier phase generation DDA */ |
585fb111 JB |
4087 | # define TV_SCDDA3_INC_MASK 0x00007fff |
4088 | # define TV_SCDDA3_INC_SHIFT 0 | |
4089 | ||
f0f59a00 | 4090 | #define TV_WIN_POS _MMIO(0x68070) |
646b4269 | 4091 | /* X coordinate of the display from the start of horizontal active */ |
585fb111 JB |
4092 | # define TV_XPOS_MASK 0x1fff0000 |
4093 | # define TV_XPOS_SHIFT 16 | |
646b4269 | 4094 | /* Y coordinate of the display from the start of vertical active (NBR) */ |
585fb111 JB |
4095 | # define TV_YPOS_MASK 0x00000fff |
4096 | # define TV_YPOS_SHIFT 0 | |
4097 | ||
f0f59a00 | 4098 | #define TV_WIN_SIZE _MMIO(0x68074) |
646b4269 | 4099 | /* Horizontal size of the display window, measured in pixels*/ |
585fb111 JB |
4100 | # define TV_XSIZE_MASK 0x1fff0000 |
4101 | # define TV_XSIZE_SHIFT 16 | |
646b4269 | 4102 | /* |
585fb111 JB |
4103 | * Vertical size of the display window, measured in pixels. |
4104 | * | |
4105 | * Must be even for interlaced modes. | |
4106 | */ | |
4107 | # define TV_YSIZE_MASK 0x00000fff | |
4108 | # define TV_YSIZE_SHIFT 0 | |
4109 | ||
f0f59a00 | 4110 | #define TV_FILTER_CTL_1 _MMIO(0x68080) |
646b4269 | 4111 | /* |
585fb111 JB |
4112 | * Enables automatic scaling calculation. |
4113 | * | |
4114 | * If set, the rest of the registers are ignored, and the calculated values can | |
4115 | * be read back from the register. | |
4116 | */ | |
4117 | # define TV_AUTO_SCALE (1 << 31) | |
646b4269 | 4118 | /* |
585fb111 JB |
4119 | * Disables the vertical filter. |
4120 | * | |
4121 | * This is required on modes more than 1024 pixels wide */ | |
4122 | # define TV_V_FILTER_BYPASS (1 << 29) | |
646b4269 | 4123 | /* Enables adaptive vertical filtering */ |
585fb111 JB |
4124 | # define TV_VADAPT (1 << 28) |
4125 | # define TV_VADAPT_MODE_MASK (3 << 26) | |
646b4269 | 4126 | /* Selects the least adaptive vertical filtering mode */ |
585fb111 | 4127 | # define TV_VADAPT_MODE_LEAST (0 << 26) |
646b4269 | 4128 | /* Selects the moderately adaptive vertical filtering mode */ |
585fb111 | 4129 | # define TV_VADAPT_MODE_MODERATE (1 << 26) |
646b4269 | 4130 | /* Selects the most adaptive vertical filtering mode */ |
585fb111 | 4131 | # define TV_VADAPT_MODE_MOST (3 << 26) |
646b4269 | 4132 | /* |
585fb111 JB |
4133 | * Sets the horizontal scaling factor. |
4134 | * | |
4135 | * This should be the fractional part of the horizontal scaling factor divided | |
4136 | * by the oversampling rate. TV_HSCALE should be less than 1, and set to: | |
4137 | * | |
4138 | * (src width - 1) / ((oversample * dest width) - 1) | |
4139 | */ | |
4140 | # define TV_HSCALE_FRAC_MASK 0x00003fff | |
4141 | # define TV_HSCALE_FRAC_SHIFT 0 | |
4142 | ||
f0f59a00 | 4143 | #define TV_FILTER_CTL_2 _MMIO(0x68084) |
646b4269 | 4144 | /* |
585fb111 JB |
4145 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
4146 | * | |
4147 | * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) | |
4148 | */ | |
4149 | # define TV_VSCALE_INT_MASK 0x00038000 | |
4150 | # define TV_VSCALE_INT_SHIFT 15 | |
646b4269 | 4151 | /* |
585fb111 JB |
4152 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
4153 | * | |
4154 | * \sa TV_VSCALE_INT_MASK | |
4155 | */ | |
4156 | # define TV_VSCALE_FRAC_MASK 0x00007fff | |
4157 | # define TV_VSCALE_FRAC_SHIFT 0 | |
4158 | ||
f0f59a00 | 4159 | #define TV_FILTER_CTL_3 _MMIO(0x68088) |
646b4269 | 4160 | /* |
585fb111 JB |
4161 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
4162 | * | |
4163 | * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) | |
4164 | * | |
4165 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. | |
4166 | */ | |
4167 | # define TV_VSCALE_IP_INT_MASK 0x00038000 | |
4168 | # define TV_VSCALE_IP_INT_SHIFT 15 | |
646b4269 | 4169 | /* |
585fb111 JB |
4170 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
4171 | * | |
4172 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. | |
4173 | * | |
4174 | * \sa TV_VSCALE_IP_INT_MASK | |
4175 | */ | |
4176 | # define TV_VSCALE_IP_FRAC_MASK 0x00007fff | |
4177 | # define TV_VSCALE_IP_FRAC_SHIFT 0 | |
4178 | ||
f0f59a00 | 4179 | #define TV_CC_CONTROL _MMIO(0x68090) |
585fb111 | 4180 | # define TV_CC_ENABLE (1 << 31) |
646b4269 | 4181 | /* |
585fb111 JB |
4182 | * Specifies which field to send the CC data in. |
4183 | * | |
4184 | * CC data is usually sent in field 0. | |
4185 | */ | |
4186 | # define TV_CC_FID_MASK (1 << 27) | |
4187 | # define TV_CC_FID_SHIFT 27 | |
646b4269 | 4188 | /* Sets the horizontal position of the CC data. Usually 135. */ |
585fb111 JB |
4189 | # define TV_CC_HOFF_MASK 0x03ff0000 |
4190 | # define TV_CC_HOFF_SHIFT 16 | |
646b4269 | 4191 | /* Sets the vertical position of the CC data. Usually 21 */ |
585fb111 JB |
4192 | # define TV_CC_LINE_MASK 0x0000003f |
4193 | # define TV_CC_LINE_SHIFT 0 | |
4194 | ||
f0f59a00 | 4195 | #define TV_CC_DATA _MMIO(0x68094) |
585fb111 | 4196 | # define TV_CC_RDY (1 << 31) |
646b4269 | 4197 | /* Second word of CC data to be transmitted. */ |
585fb111 JB |
4198 | # define TV_CC_DATA_2_MASK 0x007f0000 |
4199 | # define TV_CC_DATA_2_SHIFT 16 | |
646b4269 | 4200 | /* First word of CC data to be transmitted. */ |
585fb111 JB |
4201 | # define TV_CC_DATA_1_MASK 0x0000007f |
4202 | # define TV_CC_DATA_1_SHIFT 0 | |
4203 | ||
f0f59a00 VS |
4204 | #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ |
4205 | #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ | |
4206 | #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ | |
4207 | #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ | |
585fb111 | 4208 | |
040d87f1 | 4209 | /* Display Port */ |
f0f59a00 VS |
4210 | #define DP_A _MMIO(0x64000) /* eDP */ |
4211 | #define DP_B _MMIO(0x64100) | |
4212 | #define DP_C _MMIO(0x64200) | |
4213 | #define DP_D _MMIO(0x64300) | |
040d87f1 | 4214 | |
f0f59a00 VS |
4215 | #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) |
4216 | #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) | |
4217 | #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) | |
e66eb81d | 4218 | |
040d87f1 KP |
4219 | #define DP_PORT_EN (1 << 31) |
4220 | #define DP_PIPEB_SELECT (1 << 30) | |
47a05eca | 4221 | #define DP_PIPE_MASK (1 << 30) |
44f37d1f CML |
4222 | #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) |
4223 | #define DP_PIPE_MASK_CHV (3 << 16) | |
47a05eca | 4224 | |
040d87f1 KP |
4225 | /* Link training mode - select a suitable mode for each stage */ |
4226 | #define DP_LINK_TRAIN_PAT_1 (0 << 28) | |
4227 | #define DP_LINK_TRAIN_PAT_2 (1 << 28) | |
4228 | #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) | |
4229 | #define DP_LINK_TRAIN_OFF (3 << 28) | |
4230 | #define DP_LINK_TRAIN_MASK (3 << 28) | |
4231 | #define DP_LINK_TRAIN_SHIFT 28 | |
aad3d14d VS |
4232 | #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) |
4233 | #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) | |
040d87f1 | 4234 | |
8db9d77b ZW |
4235 | /* CPT Link training mode */ |
4236 | #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) | |
4237 | #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) | |
4238 | #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) | |
4239 | #define DP_LINK_TRAIN_OFF_CPT (3 << 8) | |
4240 | #define DP_LINK_TRAIN_MASK_CPT (7 << 8) | |
4241 | #define DP_LINK_TRAIN_SHIFT_CPT 8 | |
4242 | ||
040d87f1 KP |
4243 | /* Signal voltages. These are mostly controlled by the other end */ |
4244 | #define DP_VOLTAGE_0_4 (0 << 25) | |
4245 | #define DP_VOLTAGE_0_6 (1 << 25) | |
4246 | #define DP_VOLTAGE_0_8 (2 << 25) | |
4247 | #define DP_VOLTAGE_1_2 (3 << 25) | |
4248 | #define DP_VOLTAGE_MASK (7 << 25) | |
4249 | #define DP_VOLTAGE_SHIFT 25 | |
4250 | ||
4251 | /* Signal pre-emphasis levels, like voltages, the other end tells us what | |
4252 | * they want | |
4253 | */ | |
4254 | #define DP_PRE_EMPHASIS_0 (0 << 22) | |
4255 | #define DP_PRE_EMPHASIS_3_5 (1 << 22) | |
4256 | #define DP_PRE_EMPHASIS_6 (2 << 22) | |
4257 | #define DP_PRE_EMPHASIS_9_5 (3 << 22) | |
4258 | #define DP_PRE_EMPHASIS_MASK (7 << 22) | |
4259 | #define DP_PRE_EMPHASIS_SHIFT 22 | |
4260 | ||
4261 | /* How many wires to use. I guess 3 was too hard */ | |
17aa6be9 | 4262 | #define DP_PORT_WIDTH(width) (((width) - 1) << 19) |
040d87f1 | 4263 | #define DP_PORT_WIDTH_MASK (7 << 19) |
90a6b7b0 | 4264 | #define DP_PORT_WIDTH_SHIFT 19 |
040d87f1 KP |
4265 | |
4266 | /* Mystic DPCD version 1.1 special mode */ | |
4267 | #define DP_ENHANCED_FRAMING (1 << 18) | |
4268 | ||
32f9d658 ZW |
4269 | /* eDP */ |
4270 | #define DP_PLL_FREQ_270MHZ (0 << 16) | |
b377e0df | 4271 | #define DP_PLL_FREQ_162MHZ (1 << 16) |
32f9d658 ZW |
4272 | #define DP_PLL_FREQ_MASK (3 << 16) |
4273 | ||
646b4269 | 4274 | /* locked once port is enabled */ |
040d87f1 KP |
4275 | #define DP_PORT_REVERSAL (1 << 15) |
4276 | ||
32f9d658 ZW |
4277 | /* eDP */ |
4278 | #define DP_PLL_ENABLE (1 << 14) | |
4279 | ||
646b4269 | 4280 | /* sends the clock on lane 15 of the PEG for debug */ |
040d87f1 KP |
4281 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) |
4282 | ||
4283 | #define DP_SCRAMBLING_DISABLE (1 << 12) | |
f2b115e6 | 4284 | #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
040d87f1 | 4285 | |
646b4269 | 4286 | /* limit RGB values to avoid confusing TVs */ |
040d87f1 KP |
4287 | #define DP_COLOR_RANGE_16_235 (1 << 8) |
4288 | ||
646b4269 | 4289 | /* Turn on the audio link */ |
040d87f1 KP |
4290 | #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) |
4291 | ||
646b4269 | 4292 | /* vs and hs sync polarity */ |
040d87f1 KP |
4293 | #define DP_SYNC_VS_HIGH (1 << 4) |
4294 | #define DP_SYNC_HS_HIGH (1 << 3) | |
4295 | ||
646b4269 | 4296 | /* A fantasy */ |
040d87f1 KP |
4297 | #define DP_DETECTED (1 << 2) |
4298 | ||
646b4269 | 4299 | /* The aux channel provides a way to talk to the |
040d87f1 KP |
4300 | * signal sink for DDC etc. Max packet size supported |
4301 | * is 20 bytes in each direction, hence the 5 fixed | |
4302 | * data registers | |
4303 | */ | |
da00bdcf VS |
4304 | #define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010) |
4305 | #define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014) | |
4306 | #define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018) | |
4307 | #define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c) | |
4308 | #define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020) | |
4309 | #define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024) | |
4310 | ||
4311 | #define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110) | |
4312 | #define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114) | |
4313 | #define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118) | |
4314 | #define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c) | |
4315 | #define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120) | |
4316 | #define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124) | |
4317 | ||
4318 | #define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210) | |
4319 | #define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214) | |
4320 | #define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218) | |
4321 | #define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c) | |
4322 | #define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220) | |
4323 | #define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224) | |
4324 | ||
4325 | #define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310) | |
4326 | #define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314) | |
4327 | #define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318) | |
4328 | #define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c) | |
4329 | #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320) | |
4330 | #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324) | |
750a951f | 4331 | |
f0f59a00 VS |
4332 | #define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) |
4333 | #define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ | |
040d87f1 KP |
4334 | |
4335 | #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) | |
4336 | #define DP_AUX_CH_CTL_DONE (1 << 30) | |
4337 | #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) | |
4338 | #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) | |
4339 | #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) | |
4340 | #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) | |
4341 | #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) | |
4342 | #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) | |
4343 | #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) | |
4344 | #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) | |
4345 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) | |
4346 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 | |
4347 | #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) | |
4348 | #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 | |
4349 | #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) | |
4350 | #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) | |
4351 | #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) | |
4352 | #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) | |
4353 | #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) | |
4354 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) | |
4355 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 | |
e3d99845 SJ |
4356 | #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) |
4357 | #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) | |
4358 | #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) | |
395b2913 | 4359 | #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) |
e3d99845 | 4360 | #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) |
b9ca5fad | 4361 | #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) |
040d87f1 KP |
4362 | |
4363 | /* | |
4364 | * Computing GMCH M and N values for the Display Port link | |
4365 | * | |
4366 | * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes | |
4367 | * | |
4368 | * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) | |
4369 | * | |
4370 | * The GMCH value is used internally | |
4371 | * | |
4372 | * bytes_per_pixel is the number of bytes coming out of the plane, | |
4373 | * which is after the LUTs, so we want the bytes for our color format. | |
4374 | * For our current usage, this is always 3, one byte for R, G and B. | |
4375 | */ | |
e3b95f1e DV |
4376 | #define _PIPEA_DATA_M_G4X 0x70050 |
4377 | #define _PIPEB_DATA_M_G4X 0x71050 | |
040d87f1 KP |
4378 | |
4379 | /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ | |
a65851af | 4380 | #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ |
72419203 | 4381 | #define TU_SIZE_SHIFT 25 |
a65851af | 4382 | #define TU_SIZE_MASK (0x3f << 25) |
040d87f1 | 4383 | |
a65851af VS |
4384 | #define DATA_LINK_M_N_MASK (0xffffff) |
4385 | #define DATA_LINK_N_MAX (0x800000) | |
040d87f1 | 4386 | |
e3b95f1e DV |
4387 | #define _PIPEA_DATA_N_G4X 0x70054 |
4388 | #define _PIPEB_DATA_N_G4X 0x71054 | |
040d87f1 KP |
4389 | #define PIPE_GMCH_DATA_N_MASK (0xffffff) |
4390 | ||
4391 | /* | |
4392 | * Computing Link M and N values for the Display Port link | |
4393 | * | |
4394 | * Link M / N = pixel_clock / ls_clk | |
4395 | * | |
4396 | * (the DP spec calls pixel_clock the 'strm_clk') | |
4397 | * | |
4398 | * The Link value is transmitted in the Main Stream | |
4399 | * Attributes and VB-ID. | |
4400 | */ | |
4401 | ||
e3b95f1e DV |
4402 | #define _PIPEA_LINK_M_G4X 0x70060 |
4403 | #define _PIPEB_LINK_M_G4X 0x71060 | |
040d87f1 KP |
4404 | #define PIPEA_DP_LINK_M_MASK (0xffffff) |
4405 | ||
e3b95f1e DV |
4406 | #define _PIPEA_LINK_N_G4X 0x70064 |
4407 | #define _PIPEB_LINK_N_G4X 0x71064 | |
040d87f1 KP |
4408 | #define PIPEA_DP_LINK_N_MASK (0xffffff) |
4409 | ||
f0f59a00 VS |
4410 | #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) |
4411 | #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) | |
4412 | #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) | |
4413 | #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) | |
9db4a9c7 | 4414 | |
585fb111 JB |
4415 | /* Display & cursor control */ |
4416 | ||
4417 | /* Pipe A */ | |
a57c774a | 4418 | #define _PIPEADSL 0x70000 |
837ba00f PZ |
4419 | #define DSL_LINEMASK_GEN2 0x00000fff |
4420 | #define DSL_LINEMASK_GEN3 0x00001fff | |
a57c774a | 4421 | #define _PIPEACONF 0x70008 |
5eddb70b CW |
4422 | #define PIPECONF_ENABLE (1<<31) |
4423 | #define PIPECONF_DISABLE 0 | |
4424 | #define PIPECONF_DOUBLE_WIDE (1<<30) | |
585fb111 | 4425 | #define I965_PIPECONF_ACTIVE (1<<30) |
b6ec10b3 | 4426 | #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ |
f47166d2 | 4427 | #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) |
5eddb70b CW |
4428 | #define PIPECONF_SINGLE_WIDE 0 |
4429 | #define PIPECONF_PIPE_UNLOCKED 0 | |
4430 | #define PIPECONF_PIPE_LOCKED (1<<25) | |
4431 | #define PIPECONF_PALETTE 0 | |
4432 | #define PIPECONF_GAMMA (1<<24) | |
585fb111 | 4433 | #define PIPECONF_FORCE_BORDER (1<<25) |
59df7b17 | 4434 | #define PIPECONF_INTERLACE_MASK (7 << 21) |
ee2b0b38 | 4435 | #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) |
d442ae18 DV |
4436 | /* Note that pre-gen3 does not support interlaced display directly. Panel |
4437 | * fitting must be disabled on pre-ilk for interlaced. */ | |
4438 | #define PIPECONF_PROGRESSIVE (0 << 21) | |
4439 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ | |
4440 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ | |
4441 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) | |
4442 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ | |
4443 | /* Ironlake and later have a complete new set of values for interlaced. PFIT | |
4444 | * means panel fitter required, PF means progressive fetch, DBL means power | |
4445 | * saving pixel doubling. */ | |
4446 | #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) | |
4447 | #define PIPECONF_INTERLACED_ILK (3 << 21) | |
4448 | #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ | |
4449 | #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ | |
1bd1bd80 | 4450 | #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) |
439d7ac0 | 4451 | #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) |
652c393a | 4452 | #define PIPECONF_CXSR_DOWNCLOCK (1<<16) |
6fa7aec1 | 4453 | #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) |
3685a8f3 | 4454 | #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) |
dfd07d72 DV |
4455 | #define PIPECONF_BPC_MASK (0x7 << 5) |
4456 | #define PIPECONF_8BPC (0<<5) | |
4457 | #define PIPECONF_10BPC (1<<5) | |
4458 | #define PIPECONF_6BPC (2<<5) | |
4459 | #define PIPECONF_12BPC (3<<5) | |
4f0d1aff JB |
4460 | #define PIPECONF_DITHER_EN (1<<4) |
4461 | #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) | |
4462 | #define PIPECONF_DITHER_TYPE_SP (0<<2) | |
4463 | #define PIPECONF_DITHER_TYPE_ST1 (1<<2) | |
4464 | #define PIPECONF_DITHER_TYPE_ST2 (2<<2) | |
4465 | #define PIPECONF_DITHER_TYPE_TEMP (3<<2) | |
a57c774a | 4466 | #define _PIPEASTAT 0x70024 |
585fb111 | 4467 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
579a9b0e | 4468 | #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) |
585fb111 JB |
4469 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) |
4470 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) | |
8cc96e7c | 4471 | #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) |
585fb111 | 4472 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) |
c46ce4d7 | 4473 | #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) |
585fb111 JB |
4474 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
4475 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) | |
4476 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) | |
4477 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) | |
c70af1e4 | 4478 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) |
585fb111 JB |
4479 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
4480 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) | |
4481 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) | |
10c59c51 | 4482 | #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) |
8cc96e7c | 4483 | #define PERF_COUNTER_INTERRUPT_EN (1UL<<19) |
585fb111 JB |
4484 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ |
4485 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ | |
8cc96e7c | 4486 | #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) |
585fb111 | 4487 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
c46ce4d7 | 4488 | #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) |
585fb111 | 4489 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
579a9b0e ID |
4490 | #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) |
4491 | #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) | |
585fb111 JB |
4492 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
4493 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) | |
8cc96e7c | 4494 | #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) |
585fb111 | 4495 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |
579a9b0e | 4496 | #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) |
585fb111 JB |
4497 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
4498 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) | |
4499 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) | |
4500 | #define PIPE_DPST_EVENT_STATUS (1UL<<7) | |
10c59c51 | 4501 | #define PIPE_A_PSR_STATUS_VLV (1UL<<6) |
8cc96e7c | 4502 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
585fb111 JB |
4503 | #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) |
4504 | #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) | |
10c59c51 | 4505 | #define PIPE_B_PSR_STATUS_VLV (1UL<<3) |
8cc96e7c | 4506 | #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) |
585fb111 JB |
4507 | #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ |
4508 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ | |
8cc96e7c | 4509 | #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) |
585fb111 | 4510 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) |
8cc96e7c | 4511 | #define PIPE_HBLANK_INT_STATUS (1UL<<0) |
585fb111 JB |
4512 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) |
4513 | ||
755e9019 ID |
4514 | #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 |
4515 | #define PIPESTAT_INT_STATUS_MASK 0x0000ffff | |
4516 | ||
84fd4f4e RB |
4517 | #define PIPE_A_OFFSET 0x70000 |
4518 | #define PIPE_B_OFFSET 0x71000 | |
4519 | #define PIPE_C_OFFSET 0x72000 | |
4520 | #define CHV_PIPE_C_OFFSET 0x74000 | |
a57c774a AK |
4521 | /* |
4522 | * There's actually no pipe EDP. Some pipe registers have | |
4523 | * simply shifted from the pipe to the transcoder, while | |
4524 | * keeping their original offset. Thus we need PIPE_EDP_OFFSET | |
4525 | * to access such registers in transcoder EDP. | |
4526 | */ | |
4527 | #define PIPE_EDP_OFFSET 0x7f000 | |
4528 | ||
f0f59a00 | 4529 | #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ |
5c969aa7 DL |
4530 | dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ |
4531 | dev_priv->info.display_mmio_offset) | |
a57c774a | 4532 | |
f0f59a00 VS |
4533 | #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) |
4534 | #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) | |
4535 | #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) | |
4536 | #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) | |
4537 | #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) | |
5eddb70b | 4538 | |
756f85cf PZ |
4539 | #define _PIPE_MISC_A 0x70030 |
4540 | #define _PIPE_MISC_B 0x71030 | |
4541 | #define PIPEMISC_DITHER_BPC_MASK (7<<5) | |
4542 | #define PIPEMISC_DITHER_8_BPC (0<<5) | |
4543 | #define PIPEMISC_DITHER_10_BPC (1<<5) | |
4544 | #define PIPEMISC_DITHER_6_BPC (2<<5) | |
4545 | #define PIPEMISC_DITHER_12_BPC (3<<5) | |
4546 | #define PIPEMISC_DITHER_ENABLE (1<<4) | |
4547 | #define PIPEMISC_DITHER_TYPE_MASK (3<<2) | |
4548 | #define PIPEMISC_DITHER_TYPE_SP (0<<2) | |
f0f59a00 | 4549 | #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) |
756f85cf | 4550 | |
f0f59a00 | 4551 | #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) |
7983117f | 4552 | #define PIPEB_LINE_COMPARE_INT_EN (1<<29) |
c46ce4d7 JB |
4553 | #define PIPEB_HLINE_INT_EN (1<<28) |
4554 | #define PIPEB_VBLANK_INT_EN (1<<27) | |
579a9b0e ID |
4555 | #define SPRITED_FLIP_DONE_INT_EN (1<<26) |
4556 | #define SPRITEC_FLIP_DONE_INT_EN (1<<25) | |
4557 | #define PLANEB_FLIP_DONE_INT_EN (1<<24) | |
f3c67fdd | 4558 | #define PIPE_PSR_INT_EN (1<<22) |
7983117f | 4559 | #define PIPEA_LINE_COMPARE_INT_EN (1<<21) |
c46ce4d7 JB |
4560 | #define PIPEA_HLINE_INT_EN (1<<20) |
4561 | #define PIPEA_VBLANK_INT_EN (1<<19) | |
579a9b0e ID |
4562 | #define SPRITEB_FLIP_DONE_INT_EN (1<<18) |
4563 | #define SPRITEA_FLIP_DONE_INT_EN (1<<17) | |
c46ce4d7 | 4564 | #define PLANEA_FLIPDONE_INT_EN (1<<16) |
f3c67fdd VS |
4565 | #define PIPEC_LINE_COMPARE_INT_EN (1<<13) |
4566 | #define PIPEC_HLINE_INT_EN (1<<12) | |
4567 | #define PIPEC_VBLANK_INT_EN (1<<11) | |
4568 | #define SPRITEF_FLIPDONE_INT_EN (1<<10) | |
4569 | #define SPRITEE_FLIPDONE_INT_EN (1<<9) | |
4570 | #define PLANEC_FLIPDONE_INT_EN (1<<8) | |
c46ce4d7 | 4571 | |
f0f59a00 | 4572 | #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ |
bf67a6fd VS |
4573 | #define SPRITEF_INVALID_GTT_INT_EN (1<<27) |
4574 | #define SPRITEE_INVALID_GTT_INT_EN (1<<26) | |
4575 | #define PLANEC_INVALID_GTT_INT_EN (1<<25) | |
4576 | #define CURSORC_INVALID_GTT_INT_EN (1<<24) | |
c46ce4d7 JB |
4577 | #define CURSORB_INVALID_GTT_INT_EN (1<<23) |
4578 | #define CURSORA_INVALID_GTT_INT_EN (1<<22) | |
4579 | #define SPRITED_INVALID_GTT_INT_EN (1<<21) | |
4580 | #define SPRITEC_INVALID_GTT_INT_EN (1<<20) | |
4581 | #define PLANEB_INVALID_GTT_INT_EN (1<<19) | |
4582 | #define SPRITEB_INVALID_GTT_INT_EN (1<<18) | |
4583 | #define SPRITEA_INVALID_GTT_INT_EN (1<<17) | |
4584 | #define PLANEA_INVALID_GTT_INT_EN (1<<16) | |
4585 | #define DPINVGTT_EN_MASK 0xff0000 | |
bf67a6fd VS |
4586 | #define DPINVGTT_EN_MASK_CHV 0xfff0000 |
4587 | #define SPRITEF_INVALID_GTT_STATUS (1<<11) | |
4588 | #define SPRITEE_INVALID_GTT_STATUS (1<<10) | |
4589 | #define PLANEC_INVALID_GTT_STATUS (1<<9) | |
4590 | #define CURSORC_INVALID_GTT_STATUS (1<<8) | |
c46ce4d7 JB |
4591 | #define CURSORB_INVALID_GTT_STATUS (1<<7) |
4592 | #define CURSORA_INVALID_GTT_STATUS (1<<6) | |
4593 | #define SPRITED_INVALID_GTT_STATUS (1<<5) | |
4594 | #define SPRITEC_INVALID_GTT_STATUS (1<<4) | |
4595 | #define PLANEB_INVALID_GTT_STATUS (1<<3) | |
4596 | #define SPRITEB_INVALID_GTT_STATUS (1<<2) | |
4597 | #define SPRITEA_INVALID_GTT_STATUS (1<<1) | |
4598 | #define PLANEA_INVALID_GTT_STATUS (1<<0) | |
4599 | #define DPINVGTT_STATUS_MASK 0xff | |
bf67a6fd | 4600 | #define DPINVGTT_STATUS_MASK_CHV 0xfff |
c46ce4d7 | 4601 | |
f0f59a00 | 4602 | #define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030) |
585fb111 JB |
4603 | #define DSPARB_CSTART_MASK (0x7f << 7) |
4604 | #define DSPARB_CSTART_SHIFT 7 | |
4605 | #define DSPARB_BSTART_MASK (0x7f) | |
4606 | #define DSPARB_BSTART_SHIFT 0 | |
7662c8bd SL |
4607 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
4608 | #define DSPARB_AEND_SHIFT 0 | |
54f1b6e1 VS |
4609 | #define DSPARB_SPRITEA_SHIFT_VLV 0 |
4610 | #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) | |
4611 | #define DSPARB_SPRITEB_SHIFT_VLV 8 | |
4612 | #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) | |
4613 | #define DSPARB_SPRITEC_SHIFT_VLV 16 | |
4614 | #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) | |
4615 | #define DSPARB_SPRITED_SHIFT_VLV 24 | |
4616 | #define DSPARB_SPRITED_MASK_VLV (0xff << 24) | |
f0f59a00 | 4617 | #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ |
54f1b6e1 VS |
4618 | #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 |
4619 | #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) | |
4620 | #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 | |
4621 | #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) | |
4622 | #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 | |
4623 | #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) | |
4624 | #define DSPARB_SPRITED_HI_SHIFT_VLV 12 | |
4625 | #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) | |
4626 | #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 | |
4627 | #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) | |
4628 | #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 | |
4629 | #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) | |
f0f59a00 | 4630 | #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ |
54f1b6e1 VS |
4631 | #define DSPARB_SPRITEE_SHIFT_VLV 0 |
4632 | #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) | |
4633 | #define DSPARB_SPRITEF_SHIFT_VLV 8 | |
4634 | #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) | |
b5004720 | 4635 | |
0a560674 | 4636 | /* pnv/gen4/g4x/vlv/chv */ |
f0f59a00 | 4637 | #define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034) |
0a560674 VS |
4638 | #define DSPFW_SR_SHIFT 23 |
4639 | #define DSPFW_SR_MASK (0x1ff<<23) | |
4640 | #define DSPFW_CURSORB_SHIFT 16 | |
4641 | #define DSPFW_CURSORB_MASK (0x3f<<16) | |
4642 | #define DSPFW_PLANEB_SHIFT 8 | |
4643 | #define DSPFW_PLANEB_MASK (0x7f<<8) | |
4644 | #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */ | |
4645 | #define DSPFW_PLANEA_SHIFT 0 | |
4646 | #define DSPFW_PLANEA_MASK (0x7f<<0) | |
4647 | #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */ | |
f0f59a00 | 4648 | #define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038) |
0a560674 VS |
4649 | #define DSPFW_FBC_SR_EN (1<<31) /* g4x */ |
4650 | #define DSPFW_FBC_SR_SHIFT 28 | |
4651 | #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */ | |
4652 | #define DSPFW_FBC_HPLL_SR_SHIFT 24 | |
4653 | #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */ | |
4654 | #define DSPFW_SPRITEB_SHIFT (16) | |
4655 | #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ | |
4656 | #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ | |
4657 | #define DSPFW_CURSORA_SHIFT 8 | |
4658 | #define DSPFW_CURSORA_MASK (0x3f<<8) | |
f4998963 VS |
4659 | #define DSPFW_PLANEC_OLD_SHIFT 0 |
4660 | #define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */ | |
0a560674 VS |
4661 | #define DSPFW_SPRITEA_SHIFT 0 |
4662 | #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ | |
4663 | #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ | |
f0f59a00 | 4664 | #define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c) |
0a560674 | 4665 | #define DSPFW_HPLL_SR_EN (1<<31) |
f2b115e6 | 4666 | #define PINEVIEW_SELF_REFRESH_EN (1<<30) |
0a560674 | 4667 | #define DSPFW_CURSOR_SR_SHIFT 24 |
d4294342 ZY |
4668 | #define DSPFW_CURSOR_SR_MASK (0x3f<<24) |
4669 | #define DSPFW_HPLL_CURSOR_SHIFT 16 | |
4670 | #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) | |
0a560674 VS |
4671 | #define DSPFW_HPLL_SR_SHIFT 0 |
4672 | #define DSPFW_HPLL_SR_MASK (0x1ff<<0) | |
4673 | ||
4674 | /* vlv/chv */ | |
f0f59a00 | 4675 | #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) |
0a560674 VS |
4676 | #define DSPFW_SPRITEB_WM1_SHIFT 16 |
4677 | #define DSPFW_SPRITEB_WM1_MASK (0xff<<16) | |
4678 | #define DSPFW_CURSORA_WM1_SHIFT 8 | |
4679 | #define DSPFW_CURSORA_WM1_MASK (0x3f<<8) | |
4680 | #define DSPFW_SPRITEA_WM1_SHIFT 0 | |
4681 | #define DSPFW_SPRITEA_WM1_MASK (0xff<<0) | |
f0f59a00 | 4682 | #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) |
0a560674 VS |
4683 | #define DSPFW_PLANEB_WM1_SHIFT 24 |
4684 | #define DSPFW_PLANEB_WM1_MASK (0xff<<24) | |
4685 | #define DSPFW_PLANEA_WM1_SHIFT 16 | |
4686 | #define DSPFW_PLANEA_WM1_MASK (0xff<<16) | |
4687 | #define DSPFW_CURSORB_WM1_SHIFT 8 | |
4688 | #define DSPFW_CURSORB_WM1_MASK (0x3f<<8) | |
4689 | #define DSPFW_CURSOR_SR_WM1_SHIFT 0 | |
4690 | #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0) | |
f0f59a00 | 4691 | #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) |
0a560674 VS |
4692 | #define DSPFW_SR_WM1_SHIFT 0 |
4693 | #define DSPFW_SR_WM1_MASK (0x1ff<<0) | |
f0f59a00 VS |
4694 | #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) |
4695 | #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ | |
0a560674 VS |
4696 | #define DSPFW_SPRITED_WM1_SHIFT 24 |
4697 | #define DSPFW_SPRITED_WM1_MASK (0xff<<24) | |
4698 | #define DSPFW_SPRITED_SHIFT 16 | |
15665979 | 4699 | #define DSPFW_SPRITED_MASK_VLV (0xff<<16) |
0a560674 VS |
4700 | #define DSPFW_SPRITEC_WM1_SHIFT 8 |
4701 | #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) | |
4702 | #define DSPFW_SPRITEC_SHIFT 0 | |
15665979 | 4703 | #define DSPFW_SPRITEC_MASK_VLV (0xff<<0) |
f0f59a00 | 4704 | #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) |
0a560674 VS |
4705 | #define DSPFW_SPRITEF_WM1_SHIFT 24 |
4706 | #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) | |
4707 | #define DSPFW_SPRITEF_SHIFT 16 | |
15665979 | 4708 | #define DSPFW_SPRITEF_MASK_VLV (0xff<<16) |
0a560674 VS |
4709 | #define DSPFW_SPRITEE_WM1_SHIFT 8 |
4710 | #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) | |
4711 | #define DSPFW_SPRITEE_SHIFT 0 | |
15665979 | 4712 | #define DSPFW_SPRITEE_MASK_VLV (0xff<<0) |
f0f59a00 | 4713 | #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ |
0a560674 VS |
4714 | #define DSPFW_PLANEC_WM1_SHIFT 24 |
4715 | #define DSPFW_PLANEC_WM1_MASK (0xff<<24) | |
4716 | #define DSPFW_PLANEC_SHIFT 16 | |
15665979 | 4717 | #define DSPFW_PLANEC_MASK_VLV (0xff<<16) |
0a560674 VS |
4718 | #define DSPFW_CURSORC_WM1_SHIFT 8 |
4719 | #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) | |
4720 | #define DSPFW_CURSORC_SHIFT 0 | |
4721 | #define DSPFW_CURSORC_MASK (0x3f<<0) | |
4722 | ||
4723 | /* vlv/chv high order bits */ | |
f0f59a00 | 4724 | #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) |
0a560674 | 4725 | #define DSPFW_SR_HI_SHIFT 24 |
ae80152d | 4726 | #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ |
0a560674 VS |
4727 | #define DSPFW_SPRITEF_HI_SHIFT 23 |
4728 | #define DSPFW_SPRITEF_HI_MASK (1<<23) | |
4729 | #define DSPFW_SPRITEE_HI_SHIFT 22 | |
4730 | #define DSPFW_SPRITEE_HI_MASK (1<<22) | |
4731 | #define DSPFW_PLANEC_HI_SHIFT 21 | |
4732 | #define DSPFW_PLANEC_HI_MASK (1<<21) | |
4733 | #define DSPFW_SPRITED_HI_SHIFT 20 | |
4734 | #define DSPFW_SPRITED_HI_MASK (1<<20) | |
4735 | #define DSPFW_SPRITEC_HI_SHIFT 16 | |
4736 | #define DSPFW_SPRITEC_HI_MASK (1<<16) | |
4737 | #define DSPFW_PLANEB_HI_SHIFT 12 | |
4738 | #define DSPFW_PLANEB_HI_MASK (1<<12) | |
4739 | #define DSPFW_SPRITEB_HI_SHIFT 8 | |
4740 | #define DSPFW_SPRITEB_HI_MASK (1<<8) | |
4741 | #define DSPFW_SPRITEA_HI_SHIFT 4 | |
4742 | #define DSPFW_SPRITEA_HI_MASK (1<<4) | |
4743 | #define DSPFW_PLANEA_HI_SHIFT 0 | |
4744 | #define DSPFW_PLANEA_HI_MASK (1<<0) | |
f0f59a00 | 4745 | #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) |
0a560674 | 4746 | #define DSPFW_SR_WM1_HI_SHIFT 24 |
ae80152d | 4747 | #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ |
0a560674 VS |
4748 | #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 |
4749 | #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) | |
4750 | #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 | |
4751 | #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) | |
4752 | #define DSPFW_PLANEC_WM1_HI_SHIFT 21 | |
4753 | #define DSPFW_PLANEC_WM1_HI_MASK (1<<21) | |
4754 | #define DSPFW_SPRITED_WM1_HI_SHIFT 20 | |
4755 | #define DSPFW_SPRITED_WM1_HI_MASK (1<<20) | |
4756 | #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 | |
4757 | #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16) | |
4758 | #define DSPFW_PLANEB_WM1_HI_SHIFT 12 | |
4759 | #define DSPFW_PLANEB_WM1_HI_MASK (1<<12) | |
4760 | #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 | |
4761 | #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8) | |
4762 | #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 | |
4763 | #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) | |
4764 | #define DSPFW_PLANEA_WM1_HI_SHIFT 0 | |
4765 | #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) | |
7662c8bd | 4766 | |
12a3c055 | 4767 | /* drain latency register values*/ |
f0f59a00 | 4768 | #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) |
1abc4dc7 | 4769 | #define DDL_CURSOR_SHIFT 24 |
01e184cc | 4770 | #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) |
1abc4dc7 | 4771 | #define DDL_PLANE_SHIFT 0 |
341c526f VS |
4772 | #define DDL_PRECISION_HIGH (1<<7) |
4773 | #define DDL_PRECISION_LOW (0<<7) | |
0948c265 | 4774 | #define DRAIN_LATENCY_MASK 0x7f |
12a3c055 | 4775 | |
f0f59a00 | 4776 | #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) |
c6beb13e | 4777 | #define CBR_PND_DEADLINE_DISABLE (1<<31) |
aa17cdb4 | 4778 | #define CBR_PWM_CLOCK_MUX_SELECT (1<<30) |
c6beb13e | 4779 | |
7662c8bd | 4780 | /* FIFO watermark sizes etc */ |
0e442c60 | 4781 | #define G4X_FIFO_LINE_SIZE 64 |
7662c8bd SL |
4782 | #define I915_FIFO_LINE_SIZE 64 |
4783 | #define I830_FIFO_LINE_SIZE 32 | |
0e442c60 | 4784 | |
ceb04246 | 4785 | #define VALLEYVIEW_FIFO_SIZE 255 |
0e442c60 | 4786 | #define G4X_FIFO_SIZE 127 |
1b07e04e ZY |
4787 | #define I965_FIFO_SIZE 512 |
4788 | #define I945_FIFO_SIZE 127 | |
7662c8bd | 4789 | #define I915_FIFO_SIZE 95 |
dff33cfc | 4790 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
7662c8bd | 4791 | #define I830_FIFO_SIZE 95 |
0e442c60 | 4792 | |
ceb04246 | 4793 | #define VALLEYVIEW_MAX_WM 0xff |
0e442c60 | 4794 | #define G4X_MAX_WM 0x3f |
7662c8bd SL |
4795 | #define I915_MAX_WM 0x3f |
4796 | ||
f2b115e6 AJ |
4797 | #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
4798 | #define PINEVIEW_FIFO_LINE_SIZE 64 | |
4799 | #define PINEVIEW_MAX_WM 0x1ff | |
4800 | #define PINEVIEW_DFT_WM 0x3f | |
4801 | #define PINEVIEW_DFT_HPLLOFF_WM 0 | |
4802 | #define PINEVIEW_GUARD_WM 10 | |
4803 | #define PINEVIEW_CURSOR_FIFO 64 | |
4804 | #define PINEVIEW_CURSOR_MAX_WM 0x3f | |
4805 | #define PINEVIEW_CURSOR_DFT_WM 0 | |
4806 | #define PINEVIEW_CURSOR_GUARD_WM 5 | |
7662c8bd | 4807 | |
ceb04246 | 4808 | #define VALLEYVIEW_CURSOR_MAX_WM 64 |
4fe5e611 ZY |
4809 | #define I965_CURSOR_FIFO 64 |
4810 | #define I965_CURSOR_MAX_WM 32 | |
4811 | #define I965_CURSOR_DFT_WM 8 | |
7f8a8569 | 4812 | |
fae1267d | 4813 | /* Watermark register definitions for SKL */ |
086f8e84 VS |
4814 | #define _CUR_WM_A_0 0x70140 |
4815 | #define _CUR_WM_B_0 0x71140 | |
4816 | #define _PLANE_WM_1_A_0 0x70240 | |
4817 | #define _PLANE_WM_1_B_0 0x71240 | |
4818 | #define _PLANE_WM_2_A_0 0x70340 | |
4819 | #define _PLANE_WM_2_B_0 0x71340 | |
4820 | #define _PLANE_WM_TRANS_1_A_0 0x70268 | |
4821 | #define _PLANE_WM_TRANS_1_B_0 0x71268 | |
4822 | #define _PLANE_WM_TRANS_2_A_0 0x70368 | |
4823 | #define _PLANE_WM_TRANS_2_B_0 0x71368 | |
4824 | #define _CUR_WM_TRANS_A_0 0x70168 | |
4825 | #define _CUR_WM_TRANS_B_0 0x71168 | |
fae1267d PB |
4826 | #define PLANE_WM_EN (1 << 31) |
4827 | #define PLANE_WM_LINES_SHIFT 14 | |
4828 | #define PLANE_WM_LINES_MASK 0x1f | |
4829 | #define PLANE_WM_BLOCKS_MASK 0x3ff | |
4830 | ||
086f8e84 | 4831 | #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) |
f0f59a00 VS |
4832 | #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) |
4833 | #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0) | |
fae1267d | 4834 | |
086f8e84 VS |
4835 | #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) |
4836 | #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) | |
fae1267d PB |
4837 | #define _PLANE_WM_BASE(pipe, plane) \ |
4838 | _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) | |
4839 | #define PLANE_WM(pipe, plane, level) \ | |
f0f59a00 | 4840 | _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) |
fae1267d | 4841 | #define _PLANE_WM_TRANS_1(pipe) \ |
086f8e84 | 4842 | _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0) |
fae1267d | 4843 | #define _PLANE_WM_TRANS_2(pipe) \ |
086f8e84 | 4844 | _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0) |
fae1267d | 4845 | #define PLANE_WM_TRANS(pipe, plane) \ |
f0f59a00 | 4846 | _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) |
fae1267d | 4847 | |
7f8a8569 | 4848 | /* define the Watermark register on Ironlake */ |
f0f59a00 | 4849 | #define WM0_PIPEA_ILK _MMIO(0x45100) |
1996d624 | 4850 | #define WM0_PIPE_PLANE_MASK (0xffff<<16) |
7f8a8569 | 4851 | #define WM0_PIPE_PLANE_SHIFT 16 |
1996d624 | 4852 | #define WM0_PIPE_SPRITE_MASK (0xff<<8) |
7f8a8569 | 4853 | #define WM0_PIPE_SPRITE_SHIFT 8 |
1996d624 | 4854 | #define WM0_PIPE_CURSOR_MASK (0xff) |
7f8a8569 | 4855 | |
f0f59a00 VS |
4856 | #define WM0_PIPEB_ILK _MMIO(0x45104) |
4857 | #define WM0_PIPEC_IVB _MMIO(0x45200) | |
4858 | #define WM1_LP_ILK _MMIO(0x45108) | |
7f8a8569 ZW |
4859 | #define WM1_LP_SR_EN (1<<31) |
4860 | #define WM1_LP_LATENCY_SHIFT 24 | |
4861 | #define WM1_LP_LATENCY_MASK (0x7f<<24) | |
4ed765f9 CW |
4862 | #define WM1_LP_FBC_MASK (0xf<<20) |
4863 | #define WM1_LP_FBC_SHIFT 20 | |
416f4727 | 4864 | #define WM1_LP_FBC_SHIFT_BDW 19 |
1996d624 | 4865 | #define WM1_LP_SR_MASK (0x7ff<<8) |
7f8a8569 | 4866 | #define WM1_LP_SR_SHIFT 8 |
1996d624 | 4867 | #define WM1_LP_CURSOR_MASK (0xff) |
f0f59a00 | 4868 | #define WM2_LP_ILK _MMIO(0x4510c) |
dd8849c8 | 4869 | #define WM2_LP_EN (1<<31) |
f0f59a00 | 4870 | #define WM3_LP_ILK _MMIO(0x45110) |
dd8849c8 | 4871 | #define WM3_LP_EN (1<<31) |
f0f59a00 VS |
4872 | #define WM1S_LP_ILK _MMIO(0x45120) |
4873 | #define WM2S_LP_IVB _MMIO(0x45124) | |
4874 | #define WM3S_LP_IVB _MMIO(0x45128) | |
dd8849c8 | 4875 | #define WM1S_LP_EN (1<<31) |
7f8a8569 | 4876 | |
cca32e9a PZ |
4877 | #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ |
4878 | (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ | |
4879 | ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) | |
4880 | ||
7f8a8569 | 4881 | /* Memory latency timer register */ |
f0f59a00 | 4882 | #define MLTR_ILK _MMIO(0x11222) |
b79d4990 JB |
4883 | #define MLTR_WM1_SHIFT 0 |
4884 | #define MLTR_WM2_SHIFT 8 | |
7f8a8569 ZW |
4885 | /* the unit of memory self-refresh latency time is 0.5us */ |
4886 | #define ILK_SRLT_MASK 0x3f | |
4887 | ||
1398261a YL |
4888 | |
4889 | /* the address where we get all kinds of latency value */ | |
f0f59a00 | 4890 | #define SSKPD _MMIO(0x5d10) |
1398261a YL |
4891 | #define SSKPD_WM_MASK 0x3f |
4892 | #define SSKPD_WM0_SHIFT 0 | |
4893 | #define SSKPD_WM1_SHIFT 8 | |
4894 | #define SSKPD_WM2_SHIFT 16 | |
4895 | #define SSKPD_WM3_SHIFT 24 | |
4896 | ||
585fb111 JB |
4897 | /* |
4898 | * The two pipe frame counter registers are not synchronized, so | |
4899 | * reading a stable value is somewhat tricky. The following code | |
4900 | * should work: | |
4901 | * | |
4902 | * do { | |
4903 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
4904 | * PIPE_FRAME_HIGH_SHIFT; | |
4905 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> | |
4906 | * PIPE_FRAME_LOW_SHIFT); | |
4907 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
4908 | * PIPE_FRAME_HIGH_SHIFT); | |
4909 | * } while (high1 != high2); | |
4910 | * frame = (high1 << 8) | low1; | |
4911 | */ | |
25a2e2d0 | 4912 | #define _PIPEAFRAMEHIGH 0x70040 |
585fb111 JB |
4913 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff |
4914 | #define PIPE_FRAME_HIGH_SHIFT 0 | |
25a2e2d0 | 4915 | #define _PIPEAFRAMEPIXEL 0x70044 |
585fb111 JB |
4916 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
4917 | #define PIPE_FRAME_LOW_SHIFT 24 | |
4918 | #define PIPE_PIXEL_MASK 0x00ffffff | |
4919 | #define PIPE_PIXEL_SHIFT 0 | |
9880b7a5 | 4920 | /* GM45+ just has to be different */ |
fd8f507c VS |
4921 | #define _PIPEA_FRMCOUNT_G4X 0x70040 |
4922 | #define _PIPEA_FLIPCOUNT_G4X 0x70044 | |
f0f59a00 VS |
4923 | #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) |
4924 | #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) | |
585fb111 JB |
4925 | |
4926 | /* Cursor A & B regs */ | |
5efb3e28 | 4927 | #define _CURACNTR 0x70080 |
14b60391 JB |
4928 | /* Old style CUR*CNTR flags (desktop 8xx) */ |
4929 | #define CURSOR_ENABLE 0x80000000 | |
4930 | #define CURSOR_GAMMA_ENABLE 0x40000000 | |
dc41c154 VS |
4931 | #define CURSOR_STRIDE_SHIFT 28 |
4932 | #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ | |
86d3efce | 4933 | #define CURSOR_PIPE_CSC_ENABLE (1<<24) |
14b60391 JB |
4934 | #define CURSOR_FORMAT_SHIFT 24 |
4935 | #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) | |
4936 | #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) | |
4937 | #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) | |
4938 | #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) | |
4939 | #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) | |
4940 | #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) | |
4941 | /* New style CUR*CNTR flags */ | |
4942 | #define CURSOR_MODE 0x27 | |
585fb111 | 4943 | #define CURSOR_MODE_DISABLE 0x00 |
4726e0b0 SK |
4944 | #define CURSOR_MODE_128_32B_AX 0x02 |
4945 | #define CURSOR_MODE_256_32B_AX 0x03 | |
585fb111 | 4946 | #define CURSOR_MODE_64_32B_AX 0x07 |
4726e0b0 SK |
4947 | #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) |
4948 | #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) | |
585fb111 | 4949 | #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) |
14b60391 JB |
4950 | #define MCURSOR_PIPE_SELECT (1 << 28) |
4951 | #define MCURSOR_PIPE_A 0x00 | |
4952 | #define MCURSOR_PIPE_B (1 << 28) | |
585fb111 | 4953 | #define MCURSOR_GAMMA_ENABLE (1 << 26) |
4398ad45 | 4954 | #define CURSOR_ROTATE_180 (1<<15) |
1f5d76db | 4955 | #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) |
5efb3e28 VS |
4956 | #define _CURABASE 0x70084 |
4957 | #define _CURAPOS 0x70088 | |
585fb111 JB |
4958 | #define CURSOR_POS_MASK 0x007FF |
4959 | #define CURSOR_POS_SIGN 0x8000 | |
4960 | #define CURSOR_X_SHIFT 0 | |
4961 | #define CURSOR_Y_SHIFT 16 | |
f0f59a00 | 4962 | #define CURSIZE _MMIO(0x700a0) |
5efb3e28 VS |
4963 | #define _CURBCNTR 0x700c0 |
4964 | #define _CURBBASE 0x700c4 | |
4965 | #define _CURBPOS 0x700c8 | |
585fb111 | 4966 | |
65a21cd6 JB |
4967 | #define _CURBCNTR_IVB 0x71080 |
4968 | #define _CURBBASE_IVB 0x71084 | |
4969 | #define _CURBPOS_IVB 0x71088 | |
4970 | ||
f0f59a00 | 4971 | #define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \ |
5efb3e28 VS |
4972 | dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ |
4973 | dev_priv->info.display_mmio_offset) | |
4974 | ||
4975 | #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) | |
4976 | #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) | |
4977 | #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) | |
c4a1d9e4 | 4978 | |
5efb3e28 VS |
4979 | #define CURSOR_A_OFFSET 0x70080 |
4980 | #define CURSOR_B_OFFSET 0x700c0 | |
4981 | #define CHV_CURSOR_C_OFFSET 0x700e0 | |
4982 | #define IVB_CURSOR_B_OFFSET 0x71080 | |
4983 | #define IVB_CURSOR_C_OFFSET 0x72080 | |
65a21cd6 | 4984 | |
585fb111 | 4985 | /* Display A control */ |
a57c774a | 4986 | #define _DSPACNTR 0x70180 |
585fb111 JB |
4987 | #define DISPLAY_PLANE_ENABLE (1<<31) |
4988 | #define DISPLAY_PLANE_DISABLE 0 | |
4989 | #define DISPPLANE_GAMMA_ENABLE (1<<30) | |
4990 | #define DISPPLANE_GAMMA_DISABLE 0 | |
4991 | #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) | |
57779d06 | 4992 | #define DISPPLANE_YUV422 (0x0<<26) |
585fb111 | 4993 | #define DISPPLANE_8BPP (0x2<<26) |
57779d06 VS |
4994 | #define DISPPLANE_BGRA555 (0x3<<26) |
4995 | #define DISPPLANE_BGRX555 (0x4<<26) | |
4996 | #define DISPPLANE_BGRX565 (0x5<<26) | |
4997 | #define DISPPLANE_BGRX888 (0x6<<26) | |
4998 | #define DISPPLANE_BGRA888 (0x7<<26) | |
4999 | #define DISPPLANE_RGBX101010 (0x8<<26) | |
5000 | #define DISPPLANE_RGBA101010 (0x9<<26) | |
5001 | #define DISPPLANE_BGRX101010 (0xa<<26) | |
5002 | #define DISPPLANE_RGBX161616 (0xc<<26) | |
5003 | #define DISPPLANE_RGBX888 (0xe<<26) | |
5004 | #define DISPPLANE_RGBA888 (0xf<<26) | |
585fb111 JB |
5005 | #define DISPPLANE_STEREO_ENABLE (1<<25) |
5006 | #define DISPPLANE_STEREO_DISABLE 0 | |
86d3efce | 5007 | #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) |
b24e7179 JB |
5008 | #define DISPPLANE_SEL_PIPE_SHIFT 24 |
5009 | #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) | |
585fb111 | 5010 | #define DISPPLANE_SEL_PIPE_A 0 |
b24e7179 | 5011 | #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) |
585fb111 JB |
5012 | #define DISPPLANE_SRC_KEY_ENABLE (1<<22) |
5013 | #define DISPPLANE_SRC_KEY_DISABLE 0 | |
5014 | #define DISPPLANE_LINE_DOUBLE (1<<20) | |
5015 | #define DISPPLANE_NO_LINE_DOUBLE 0 | |
5016 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 | |
5017 | #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) | |
c14b0485 VS |
5018 | #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */ |
5019 | #define DISPPLANE_ROTATE_180 (1<<15) | |
f2b115e6 | 5020 | #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ |
f544847f | 5021 | #define DISPPLANE_TILED (1<<10) |
c14b0485 | 5022 | #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */ |
a57c774a AK |
5023 | #define _DSPAADDR 0x70184 |
5024 | #define _DSPASTRIDE 0x70188 | |
5025 | #define _DSPAPOS 0x7018C /* reserved */ | |
5026 | #define _DSPASIZE 0x70190 | |
5027 | #define _DSPASURF 0x7019C /* 965+ only */ | |
5028 | #define _DSPATILEOFF 0x701A4 /* 965+ only */ | |
5029 | #define _DSPAOFFSET 0x701A4 /* HSW */ | |
5030 | #define _DSPASURFLIVE 0x701AC | |
5031 | ||
f0f59a00 VS |
5032 | #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) |
5033 | #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) | |
5034 | #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) | |
5035 | #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) | |
5036 | #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) | |
5037 | #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) | |
5038 | #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) | |
5039 | #define DSPLINOFF(plane) DSPADDR(plane) | |
5040 | #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) | |
5041 | #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) | |
5eddb70b | 5042 | |
c14b0485 VS |
5043 | /* CHV pipe B blender and primary plane */ |
5044 | #define _CHV_BLEND_A 0x60a00 | |
5045 | #define CHV_BLEND_LEGACY (0<<30) | |
5046 | #define CHV_BLEND_ANDROID (1<<30) | |
5047 | #define CHV_BLEND_MPO (2<<30) | |
5048 | #define CHV_BLEND_MASK (3<<30) | |
5049 | #define _CHV_CANVAS_A 0x60a04 | |
5050 | #define _PRIMPOS_A 0x60a08 | |
5051 | #define _PRIMSIZE_A 0x60a0c | |
5052 | #define _PRIMCNSTALPHA_A 0x60a10 | |
5053 | #define PRIM_CONST_ALPHA_ENABLE (1<<31) | |
5054 | ||
f0f59a00 VS |
5055 | #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) |
5056 | #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) | |
5057 | #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) | |
5058 | #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) | |
5059 | #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) | |
c14b0485 | 5060 | |
446f2545 AR |
5061 | /* Display/Sprite base address macros */ |
5062 | #define DISP_BASEADDR_MASK (0xfffff000) | |
5063 | #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) | |
5064 | #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) | |
446f2545 | 5065 | |
85fa792b VS |
5066 | /* |
5067 | * VBIOS flags | |
5068 | * gen2: | |
5069 | * [00:06] alm,mgm | |
5070 | * [10:16] all | |
5071 | * [30:32] alm,mgm | |
5072 | * gen3+: | |
5073 | * [00:0f] all | |
5074 | * [10:1f] all | |
5075 | * [30:32] all | |
5076 | */ | |
f0f59a00 VS |
5077 | #define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4) |
5078 | #define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4) | |
5079 | #define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4) | |
5080 | #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) | |
585fb111 JB |
5081 | |
5082 | /* Pipe B */ | |
5c969aa7 DL |
5083 | #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) |
5084 | #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) | |
5085 | #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) | |
25a2e2d0 VS |
5086 | #define _PIPEBFRAMEHIGH 0x71040 |
5087 | #define _PIPEBFRAMEPIXEL 0x71044 | |
fd8f507c VS |
5088 | #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040) |
5089 | #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044) | |
9880b7a5 | 5090 | |
585fb111 JB |
5091 | |
5092 | /* Display B control */ | |
5c969aa7 | 5093 | #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) |
585fb111 JB |
5094 | #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) |
5095 | #define DISPPLANE_ALPHA_TRANS_DISABLE 0 | |
5096 | #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 | |
5097 | #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) | |
5c969aa7 DL |
5098 | #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) |
5099 | #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) | |
5100 | #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) | |
5101 | #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) | |
5102 | #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) | |
5103 | #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) | |
5104 | #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) | |
5105 | #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) | |
585fb111 | 5106 | |
b840d907 JB |
5107 | /* Sprite A control */ |
5108 | #define _DVSACNTR 0x72180 | |
5109 | #define DVS_ENABLE (1<<31) | |
5110 | #define DVS_GAMMA_ENABLE (1<<30) | |
5111 | #define DVS_PIXFORMAT_MASK (3<<25) | |
5112 | #define DVS_FORMAT_YUV422 (0<<25) | |
5113 | #define DVS_FORMAT_RGBX101010 (1<<25) | |
5114 | #define DVS_FORMAT_RGBX888 (2<<25) | |
5115 | #define DVS_FORMAT_RGBX161616 (3<<25) | |
86d3efce | 5116 | #define DVS_PIPE_CSC_ENABLE (1<<24) |
b840d907 | 5117 | #define DVS_SOURCE_KEY (1<<22) |
ab2f9df1 | 5118 | #define DVS_RGB_ORDER_XBGR (1<<20) |
b840d907 JB |
5119 | #define DVS_YUV_BYTE_ORDER_MASK (3<<16) |
5120 | #define DVS_YUV_ORDER_YUYV (0<<16) | |
5121 | #define DVS_YUV_ORDER_UYVY (1<<16) | |
5122 | #define DVS_YUV_ORDER_YVYU (2<<16) | |
5123 | #define DVS_YUV_ORDER_VYUY (3<<16) | |
76eebda7 | 5124 | #define DVS_ROTATE_180 (1<<15) |
b840d907 JB |
5125 | #define DVS_DEST_KEY (1<<2) |
5126 | #define DVS_TRICKLE_FEED_DISABLE (1<<14) | |
5127 | #define DVS_TILED (1<<10) | |
5128 | #define _DVSALINOFF 0x72184 | |
5129 | #define _DVSASTRIDE 0x72188 | |
5130 | #define _DVSAPOS 0x7218c | |
5131 | #define _DVSASIZE 0x72190 | |
5132 | #define _DVSAKEYVAL 0x72194 | |
5133 | #define _DVSAKEYMSK 0x72198 | |
5134 | #define _DVSASURF 0x7219c | |
5135 | #define _DVSAKEYMAXVAL 0x721a0 | |
5136 | #define _DVSATILEOFF 0x721a4 | |
5137 | #define _DVSASURFLIVE 0x721ac | |
5138 | #define _DVSASCALE 0x72204 | |
5139 | #define DVS_SCALE_ENABLE (1<<31) | |
5140 | #define DVS_FILTER_MASK (3<<29) | |
5141 | #define DVS_FILTER_MEDIUM (0<<29) | |
5142 | #define DVS_FILTER_ENHANCING (1<<29) | |
5143 | #define DVS_FILTER_SOFTENING (2<<29) | |
5144 | #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ | |
5145 | #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) | |
5146 | #define _DVSAGAMC 0x72300 | |
5147 | ||
5148 | #define _DVSBCNTR 0x73180 | |
5149 | #define _DVSBLINOFF 0x73184 | |
5150 | #define _DVSBSTRIDE 0x73188 | |
5151 | #define _DVSBPOS 0x7318c | |
5152 | #define _DVSBSIZE 0x73190 | |
5153 | #define _DVSBKEYVAL 0x73194 | |
5154 | #define _DVSBKEYMSK 0x73198 | |
5155 | #define _DVSBSURF 0x7319c | |
5156 | #define _DVSBKEYMAXVAL 0x731a0 | |
5157 | #define _DVSBTILEOFF 0x731a4 | |
5158 | #define _DVSBSURFLIVE 0x731ac | |
5159 | #define _DVSBSCALE 0x73204 | |
5160 | #define _DVSBGAMC 0x73300 | |
5161 | ||
f0f59a00 VS |
5162 | #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) |
5163 | #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) | |
5164 | #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) | |
5165 | #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) | |
5166 | #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) | |
5167 | #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) | |
5168 | #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) | |
5169 | #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) | |
5170 | #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) | |
5171 | #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) | |
5172 | #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) | |
5173 | #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) | |
b840d907 JB |
5174 | |
5175 | #define _SPRA_CTL 0x70280 | |
5176 | #define SPRITE_ENABLE (1<<31) | |
5177 | #define SPRITE_GAMMA_ENABLE (1<<30) | |
5178 | #define SPRITE_PIXFORMAT_MASK (7<<25) | |
5179 | #define SPRITE_FORMAT_YUV422 (0<<25) | |
5180 | #define SPRITE_FORMAT_RGBX101010 (1<<25) | |
5181 | #define SPRITE_FORMAT_RGBX888 (2<<25) | |
5182 | #define SPRITE_FORMAT_RGBX161616 (3<<25) | |
5183 | #define SPRITE_FORMAT_YUV444 (4<<25) | |
5184 | #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ | |
86d3efce | 5185 | #define SPRITE_PIPE_CSC_ENABLE (1<<24) |
b840d907 JB |
5186 | #define SPRITE_SOURCE_KEY (1<<22) |
5187 | #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ | |
5188 | #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) | |
5189 | #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ | |
5190 | #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) | |
5191 | #define SPRITE_YUV_ORDER_YUYV (0<<16) | |
5192 | #define SPRITE_YUV_ORDER_UYVY (1<<16) | |
5193 | #define SPRITE_YUV_ORDER_YVYU (2<<16) | |
5194 | #define SPRITE_YUV_ORDER_VYUY (3<<16) | |
76eebda7 | 5195 | #define SPRITE_ROTATE_180 (1<<15) |
b840d907 JB |
5196 | #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) |
5197 | #define SPRITE_INT_GAMMA_ENABLE (1<<13) | |
5198 | #define SPRITE_TILED (1<<10) | |
5199 | #define SPRITE_DEST_KEY (1<<2) | |
5200 | #define _SPRA_LINOFF 0x70284 | |
5201 | #define _SPRA_STRIDE 0x70288 | |
5202 | #define _SPRA_POS 0x7028c | |
5203 | #define _SPRA_SIZE 0x70290 | |
5204 | #define _SPRA_KEYVAL 0x70294 | |
5205 | #define _SPRA_KEYMSK 0x70298 | |
5206 | #define _SPRA_SURF 0x7029c | |
5207 | #define _SPRA_KEYMAX 0x702a0 | |
5208 | #define _SPRA_TILEOFF 0x702a4 | |
c54173a8 | 5209 | #define _SPRA_OFFSET 0x702a4 |
32ae46bf | 5210 | #define _SPRA_SURFLIVE 0x702ac |
b840d907 JB |
5211 | #define _SPRA_SCALE 0x70304 |
5212 | #define SPRITE_SCALE_ENABLE (1<<31) | |
5213 | #define SPRITE_FILTER_MASK (3<<29) | |
5214 | #define SPRITE_FILTER_MEDIUM (0<<29) | |
5215 | #define SPRITE_FILTER_ENHANCING (1<<29) | |
5216 | #define SPRITE_FILTER_SOFTENING (2<<29) | |
5217 | #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ | |
5218 | #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) | |
5219 | #define _SPRA_GAMC 0x70400 | |
5220 | ||
5221 | #define _SPRB_CTL 0x71280 | |
5222 | #define _SPRB_LINOFF 0x71284 | |
5223 | #define _SPRB_STRIDE 0x71288 | |
5224 | #define _SPRB_POS 0x7128c | |
5225 | #define _SPRB_SIZE 0x71290 | |
5226 | #define _SPRB_KEYVAL 0x71294 | |
5227 | #define _SPRB_KEYMSK 0x71298 | |
5228 | #define _SPRB_SURF 0x7129c | |
5229 | #define _SPRB_KEYMAX 0x712a0 | |
5230 | #define _SPRB_TILEOFF 0x712a4 | |
c54173a8 | 5231 | #define _SPRB_OFFSET 0x712a4 |
32ae46bf | 5232 | #define _SPRB_SURFLIVE 0x712ac |
b840d907 JB |
5233 | #define _SPRB_SCALE 0x71304 |
5234 | #define _SPRB_GAMC 0x71400 | |
5235 | ||
f0f59a00 VS |
5236 | #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) |
5237 | #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) | |
5238 | #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) | |
5239 | #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) | |
5240 | #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) | |
5241 | #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) | |
5242 | #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) | |
5243 | #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) | |
5244 | #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) | |
5245 | #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) | |
5246 | #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) | |
5247 | #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) | |
5248 | #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) | |
5249 | #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) | |
b840d907 | 5250 | |
921c3b67 | 5251 | #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) |
7f1f3851 | 5252 | #define SP_ENABLE (1<<31) |
4ea67bc7 | 5253 | #define SP_GAMMA_ENABLE (1<<30) |
7f1f3851 JB |
5254 | #define SP_PIXFORMAT_MASK (0xf<<26) |
5255 | #define SP_FORMAT_YUV422 (0<<26) | |
5256 | #define SP_FORMAT_BGR565 (5<<26) | |
5257 | #define SP_FORMAT_BGRX8888 (6<<26) | |
5258 | #define SP_FORMAT_BGRA8888 (7<<26) | |
5259 | #define SP_FORMAT_RGBX1010102 (8<<26) | |
5260 | #define SP_FORMAT_RGBA1010102 (9<<26) | |
5261 | #define SP_FORMAT_RGBX8888 (0xe<<26) | |
5262 | #define SP_FORMAT_RGBA8888 (0xf<<26) | |
c14b0485 | 5263 | #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */ |
7f1f3851 JB |
5264 | #define SP_SOURCE_KEY (1<<22) |
5265 | #define SP_YUV_BYTE_ORDER_MASK (3<<16) | |
5266 | #define SP_YUV_ORDER_YUYV (0<<16) | |
5267 | #define SP_YUV_ORDER_UYVY (1<<16) | |
5268 | #define SP_YUV_ORDER_YVYU (2<<16) | |
5269 | #define SP_YUV_ORDER_VYUY (3<<16) | |
76eebda7 | 5270 | #define SP_ROTATE_180 (1<<15) |
7f1f3851 | 5271 | #define SP_TILED (1<<10) |
c14b0485 | 5272 | #define SP_MIRROR (1<<8) /* CHV pipe B */ |
921c3b67 VS |
5273 | #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) |
5274 | #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) | |
5275 | #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) | |
5276 | #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) | |
5277 | #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) | |
5278 | #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) | |
5279 | #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) | |
5280 | #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) | |
5281 | #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) | |
5282 | #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) | |
c14b0485 | 5283 | #define SP_CONST_ALPHA_ENABLE (1<<31) |
921c3b67 VS |
5284 | #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) |
5285 | ||
5286 | #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) | |
5287 | #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) | |
5288 | #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) | |
5289 | #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) | |
5290 | #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) | |
5291 | #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) | |
5292 | #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) | |
5293 | #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) | |
5294 | #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) | |
5295 | #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) | |
5296 | #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) | |
5297 | #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) | |
7f1f3851 | 5298 | |
f0f59a00 VS |
5299 | #define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR) |
5300 | #define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF) | |
5301 | #define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE) | |
5302 | #define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS) | |
5303 | #define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE) | |
5304 | #define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL) | |
5305 | #define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK) | |
5306 | #define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF) | |
5307 | #define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL) | |
5308 | #define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF) | |
5309 | #define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA) | |
5310 | #define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC) | |
7f1f3851 | 5311 | |
6ca2aeb2 VS |
5312 | /* |
5313 | * CHV pipe B sprite CSC | |
5314 | * | |
5315 | * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| | |
5316 | * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| | |
5317 | * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| | |
5318 | */ | |
f0f59a00 VS |
5319 | #define SPCSCYGOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000) |
5320 | #define SPCSCCBOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000) | |
5321 | #define SPCSCCROFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000) | |
6ca2aeb2 VS |
5322 | #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ |
5323 | #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ | |
5324 | ||
f0f59a00 VS |
5325 | #define SPCSCC01(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000) |
5326 | #define SPCSCC23(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000) | |
5327 | #define SPCSCC45(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000) | |
5328 | #define SPCSCC67(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000) | |
5329 | #define SPCSCC8(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000) | |
6ca2aeb2 VS |
5330 | #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ |
5331 | #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ | |
5332 | ||
f0f59a00 VS |
5333 | #define SPCSCYGICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000) |
5334 | #define SPCSCCBICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000) | |
5335 | #define SPCSCCRICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000) | |
6ca2aeb2 VS |
5336 | #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ |
5337 | #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ | |
5338 | ||
f0f59a00 VS |
5339 | #define SPCSCYGOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000) |
5340 | #define SPCSCCBOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000) | |
5341 | #define SPCSCCROCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000) | |
6ca2aeb2 VS |
5342 | #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ |
5343 | #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ | |
5344 | ||
70d21f0e DL |
5345 | /* Skylake plane registers */ |
5346 | ||
5347 | #define _PLANE_CTL_1_A 0x70180 | |
5348 | #define _PLANE_CTL_2_A 0x70280 | |
5349 | #define _PLANE_CTL_3_A 0x70380 | |
5350 | #define PLANE_CTL_ENABLE (1 << 31) | |
5351 | #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) | |
5352 | #define PLANE_CTL_FORMAT_MASK (0xf << 24) | |
5353 | #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24) | |
5354 | #define PLANE_CTL_FORMAT_NV12 ( 1 << 24) | |
5355 | #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24) | |
5356 | #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24) | |
5357 | #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24) | |
5358 | #define PLANE_CTL_FORMAT_AYUV ( 8 << 24) | |
5359 | #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24) | |
5360 | #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24) | |
5361 | #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) | |
dc2a41b4 DL |
5362 | #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) |
5363 | #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21) | |
5364 | #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21) | |
70d21f0e DL |
5365 | #define PLANE_CTL_ORDER_BGRX (0 << 20) |
5366 | #define PLANE_CTL_ORDER_RGBX (1 << 20) | |
5367 | #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) | |
5368 | #define PLANE_CTL_YUV422_YUYV ( 0 << 16) | |
5369 | #define PLANE_CTL_YUV422_UYVY ( 1 << 16) | |
5370 | #define PLANE_CTL_YUV422_YVYU ( 2 << 16) | |
5371 | #define PLANE_CTL_YUV422_VYUY ( 3 << 16) | |
5372 | #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15) | |
5373 | #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) | |
5374 | #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) | |
5375 | #define PLANE_CTL_TILED_MASK (0x7 << 10) | |
5376 | #define PLANE_CTL_TILED_LINEAR ( 0 << 10) | |
5377 | #define PLANE_CTL_TILED_X ( 1 << 10) | |
5378 | #define PLANE_CTL_TILED_Y ( 4 << 10) | |
5379 | #define PLANE_CTL_TILED_YF ( 5 << 10) | |
5380 | #define PLANE_CTL_ALPHA_MASK (0x3 << 4) | |
5381 | #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) | |
5382 | #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) | |
5383 | #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) | |
1447dde0 SJ |
5384 | #define PLANE_CTL_ROTATE_MASK 0x3 |
5385 | #define PLANE_CTL_ROTATE_0 0x0 | |
3b7a5119 | 5386 | #define PLANE_CTL_ROTATE_90 0x1 |
1447dde0 | 5387 | #define PLANE_CTL_ROTATE_180 0x2 |
3b7a5119 | 5388 | #define PLANE_CTL_ROTATE_270 0x3 |
70d21f0e DL |
5389 | #define _PLANE_STRIDE_1_A 0x70188 |
5390 | #define _PLANE_STRIDE_2_A 0x70288 | |
5391 | #define _PLANE_STRIDE_3_A 0x70388 | |
5392 | #define _PLANE_POS_1_A 0x7018c | |
5393 | #define _PLANE_POS_2_A 0x7028c | |
5394 | #define _PLANE_POS_3_A 0x7038c | |
5395 | #define _PLANE_SIZE_1_A 0x70190 | |
5396 | #define _PLANE_SIZE_2_A 0x70290 | |
5397 | #define _PLANE_SIZE_3_A 0x70390 | |
5398 | #define _PLANE_SURF_1_A 0x7019c | |
5399 | #define _PLANE_SURF_2_A 0x7029c | |
5400 | #define _PLANE_SURF_3_A 0x7039c | |
5401 | #define _PLANE_OFFSET_1_A 0x701a4 | |
5402 | #define _PLANE_OFFSET_2_A 0x702a4 | |
5403 | #define _PLANE_OFFSET_3_A 0x703a4 | |
dc2a41b4 DL |
5404 | #define _PLANE_KEYVAL_1_A 0x70194 |
5405 | #define _PLANE_KEYVAL_2_A 0x70294 | |
5406 | #define _PLANE_KEYMSK_1_A 0x70198 | |
5407 | #define _PLANE_KEYMSK_2_A 0x70298 | |
5408 | #define _PLANE_KEYMAX_1_A 0x701a0 | |
5409 | #define _PLANE_KEYMAX_2_A 0x702a0 | |
8211bd5b DL |
5410 | #define _PLANE_BUF_CFG_1_A 0x7027c |
5411 | #define _PLANE_BUF_CFG_2_A 0x7037c | |
2cd601c6 CK |
5412 | #define _PLANE_NV12_BUF_CFG_1_A 0x70278 |
5413 | #define _PLANE_NV12_BUF_CFG_2_A 0x70378 | |
70d21f0e DL |
5414 | |
5415 | #define _PLANE_CTL_1_B 0x71180 | |
5416 | #define _PLANE_CTL_2_B 0x71280 | |
5417 | #define _PLANE_CTL_3_B 0x71380 | |
5418 | #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) | |
5419 | #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) | |
5420 | #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) | |
5421 | #define PLANE_CTL(pipe, plane) \ | |
f0f59a00 | 5422 | _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) |
70d21f0e DL |
5423 | |
5424 | #define _PLANE_STRIDE_1_B 0x71188 | |
5425 | #define _PLANE_STRIDE_2_B 0x71288 | |
5426 | #define _PLANE_STRIDE_3_B 0x71388 | |
5427 | #define _PLANE_STRIDE_1(pipe) \ | |
5428 | _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) | |
5429 | #define _PLANE_STRIDE_2(pipe) \ | |
5430 | _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) | |
5431 | #define _PLANE_STRIDE_3(pipe) \ | |
5432 | _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) | |
5433 | #define PLANE_STRIDE(pipe, plane) \ | |
f0f59a00 | 5434 | _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) |
70d21f0e DL |
5435 | |
5436 | #define _PLANE_POS_1_B 0x7118c | |
5437 | #define _PLANE_POS_2_B 0x7128c | |
5438 | #define _PLANE_POS_3_B 0x7138c | |
5439 | #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) | |
5440 | #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) | |
5441 | #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) | |
5442 | #define PLANE_POS(pipe, plane) \ | |
f0f59a00 | 5443 | _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) |
70d21f0e DL |
5444 | |
5445 | #define _PLANE_SIZE_1_B 0x71190 | |
5446 | #define _PLANE_SIZE_2_B 0x71290 | |
5447 | #define _PLANE_SIZE_3_B 0x71390 | |
5448 | #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) | |
5449 | #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) | |
5450 | #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) | |
5451 | #define PLANE_SIZE(pipe, plane) \ | |
f0f59a00 | 5452 | _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) |
70d21f0e DL |
5453 | |
5454 | #define _PLANE_SURF_1_B 0x7119c | |
5455 | #define _PLANE_SURF_2_B 0x7129c | |
5456 | #define _PLANE_SURF_3_B 0x7139c | |
5457 | #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) | |
5458 | #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) | |
5459 | #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) | |
5460 | #define PLANE_SURF(pipe, plane) \ | |
f0f59a00 | 5461 | _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) |
70d21f0e DL |
5462 | |
5463 | #define _PLANE_OFFSET_1_B 0x711a4 | |
5464 | #define _PLANE_OFFSET_2_B 0x712a4 | |
5465 | #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) | |
5466 | #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) | |
5467 | #define PLANE_OFFSET(pipe, plane) \ | |
f0f59a00 | 5468 | _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) |
70d21f0e | 5469 | |
dc2a41b4 DL |
5470 | #define _PLANE_KEYVAL_1_B 0x71194 |
5471 | #define _PLANE_KEYVAL_2_B 0x71294 | |
5472 | #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) | |
5473 | #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) | |
5474 | #define PLANE_KEYVAL(pipe, plane) \ | |
f0f59a00 | 5475 | _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) |
dc2a41b4 DL |
5476 | |
5477 | #define _PLANE_KEYMSK_1_B 0x71198 | |
5478 | #define _PLANE_KEYMSK_2_B 0x71298 | |
5479 | #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) | |
5480 | #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) | |
5481 | #define PLANE_KEYMSK(pipe, plane) \ | |
f0f59a00 | 5482 | _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) |
dc2a41b4 DL |
5483 | |
5484 | #define _PLANE_KEYMAX_1_B 0x711a0 | |
5485 | #define _PLANE_KEYMAX_2_B 0x712a0 | |
5486 | #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) | |
5487 | #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) | |
5488 | #define PLANE_KEYMAX(pipe, plane) \ | |
f0f59a00 | 5489 | _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) |
dc2a41b4 | 5490 | |
8211bd5b DL |
5491 | #define _PLANE_BUF_CFG_1_B 0x7127c |
5492 | #define _PLANE_BUF_CFG_2_B 0x7137c | |
5493 | #define _PLANE_BUF_CFG_1(pipe) \ | |
5494 | _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) | |
5495 | #define _PLANE_BUF_CFG_2(pipe) \ | |
5496 | _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) | |
5497 | #define PLANE_BUF_CFG(pipe, plane) \ | |
f0f59a00 | 5498 | _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) |
8211bd5b | 5499 | |
2cd601c6 CK |
5500 | #define _PLANE_NV12_BUF_CFG_1_B 0x71278 |
5501 | #define _PLANE_NV12_BUF_CFG_2_B 0x71378 | |
5502 | #define _PLANE_NV12_BUF_CFG_1(pipe) \ | |
5503 | _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) | |
5504 | #define _PLANE_NV12_BUF_CFG_2(pipe) \ | |
5505 | _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) | |
5506 | #define PLANE_NV12_BUF_CFG(pipe, plane) \ | |
f0f59a00 | 5507 | _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) |
2cd601c6 | 5508 | |
8211bd5b DL |
5509 | /* SKL new cursor registers */ |
5510 | #define _CUR_BUF_CFG_A 0x7017c | |
5511 | #define _CUR_BUF_CFG_B 0x7117c | |
f0f59a00 | 5512 | #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) |
8211bd5b | 5513 | |
585fb111 | 5514 | /* VBIOS regs */ |
f0f59a00 | 5515 | #define VGACNTRL _MMIO(0x71400) |
585fb111 JB |
5516 | # define VGA_DISP_DISABLE (1 << 31) |
5517 | # define VGA_2X_MODE (1 << 30) | |
5518 | # define VGA_PIPE_B_SELECT (1 << 29) | |
5519 | ||
f0f59a00 | 5520 | #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) |
766aa1c4 | 5521 | |
f2b115e6 | 5522 | /* Ironlake */ |
b9055052 | 5523 | |
f0f59a00 | 5524 | #define CPU_VGACNTRL _MMIO(0x41000) |
b9055052 | 5525 | |
f0f59a00 | 5526 | #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) |
40bfd7a3 VS |
5527 | #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) |
5528 | #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ | |
5529 | #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ | |
5530 | #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ | |
5531 | #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ | |
5532 | #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ | |
5533 | #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) | |
5534 | #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) | |
5535 | #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) | |
5536 | #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) | |
b9055052 ZW |
5537 | |
5538 | /* refresh rate hardware control */ | |
f0f59a00 | 5539 | #define RR_HW_CTL _MMIO(0x45300) |
b9055052 ZW |
5540 | #define RR_HW_LOW_POWER_FRAMES_MASK 0xff |
5541 | #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 | |
5542 | ||
f0f59a00 | 5543 | #define FDI_PLL_BIOS_0 _MMIO(0x46000) |
021357ac | 5544 | #define FDI_PLL_FB_CLOCK_MASK 0xff |
f0f59a00 VS |
5545 | #define FDI_PLL_BIOS_1 _MMIO(0x46004) |
5546 | #define FDI_PLL_BIOS_2 _MMIO(0x46008) | |
5547 | #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) | |
5548 | #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) | |
5549 | #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) | |
b9055052 | 5550 | |
f0f59a00 | 5551 | #define PCH_3DCGDIS0 _MMIO(0x46020) |
8956c8bb EA |
5552 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) |
5553 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) | |
5554 | ||
f0f59a00 | 5555 | #define PCH_3DCGDIS1 _MMIO(0x46024) |
06f37751 EA |
5556 | # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) |
5557 | ||
f0f59a00 | 5558 | #define FDI_PLL_FREQ_CTL _MMIO(0x46030) |
b9055052 ZW |
5559 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) |
5560 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 | |
5561 | #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff | |
5562 | ||
5563 | ||
a57c774a | 5564 | #define _PIPEA_DATA_M1 0x60030 |
5eddb70b | 5565 | #define PIPE_DATA_M1_OFFSET 0 |
a57c774a | 5566 | #define _PIPEA_DATA_N1 0x60034 |
5eddb70b | 5567 | #define PIPE_DATA_N1_OFFSET 0 |
b9055052 | 5568 | |
a57c774a | 5569 | #define _PIPEA_DATA_M2 0x60038 |
5eddb70b | 5570 | #define PIPE_DATA_M2_OFFSET 0 |
a57c774a | 5571 | #define _PIPEA_DATA_N2 0x6003c |
5eddb70b | 5572 | #define PIPE_DATA_N2_OFFSET 0 |
b9055052 | 5573 | |
a57c774a | 5574 | #define _PIPEA_LINK_M1 0x60040 |
5eddb70b | 5575 | #define PIPE_LINK_M1_OFFSET 0 |
a57c774a | 5576 | #define _PIPEA_LINK_N1 0x60044 |
5eddb70b | 5577 | #define PIPE_LINK_N1_OFFSET 0 |
b9055052 | 5578 | |
a57c774a | 5579 | #define _PIPEA_LINK_M2 0x60048 |
5eddb70b | 5580 | #define PIPE_LINK_M2_OFFSET 0 |
a57c774a | 5581 | #define _PIPEA_LINK_N2 0x6004c |
5eddb70b | 5582 | #define PIPE_LINK_N2_OFFSET 0 |
b9055052 ZW |
5583 | |
5584 | /* PIPEB timing regs are same start from 0x61000 */ | |
5585 | ||
a57c774a AK |
5586 | #define _PIPEB_DATA_M1 0x61030 |
5587 | #define _PIPEB_DATA_N1 0x61034 | |
5588 | #define _PIPEB_DATA_M2 0x61038 | |
5589 | #define _PIPEB_DATA_N2 0x6103c | |
5590 | #define _PIPEB_LINK_M1 0x61040 | |
5591 | #define _PIPEB_LINK_N1 0x61044 | |
5592 | #define _PIPEB_LINK_M2 0x61048 | |
5593 | #define _PIPEB_LINK_N2 0x6104c | |
5594 | ||
f0f59a00 VS |
5595 | #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) |
5596 | #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) | |
5597 | #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) | |
5598 | #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) | |
5599 | #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) | |
5600 | #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) | |
5601 | #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) | |
5602 | #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) | |
b9055052 ZW |
5603 | |
5604 | /* CPU panel fitter */ | |
9db4a9c7 JB |
5605 | /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ |
5606 | #define _PFA_CTL_1 0x68080 | |
5607 | #define _PFB_CTL_1 0x68880 | |
b9055052 | 5608 | #define PF_ENABLE (1<<31) |
13888d78 PZ |
5609 | #define PF_PIPE_SEL_MASK_IVB (3<<29) |
5610 | #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) | |
b1f60b70 ZW |
5611 | #define PF_FILTER_MASK (3<<23) |
5612 | #define PF_FILTER_PROGRAMMED (0<<23) | |
5613 | #define PF_FILTER_MED_3x3 (1<<23) | |
5614 | #define PF_FILTER_EDGE_ENHANCE (2<<23) | |
5615 | #define PF_FILTER_EDGE_SOFTEN (3<<23) | |
9db4a9c7 JB |
5616 | #define _PFA_WIN_SZ 0x68074 |
5617 | #define _PFB_WIN_SZ 0x68874 | |
5618 | #define _PFA_WIN_POS 0x68070 | |
5619 | #define _PFB_WIN_POS 0x68870 | |
5620 | #define _PFA_VSCALE 0x68084 | |
5621 | #define _PFB_VSCALE 0x68884 | |
5622 | #define _PFA_HSCALE 0x68090 | |
5623 | #define _PFB_HSCALE 0x68890 | |
5624 | ||
f0f59a00 VS |
5625 | #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) |
5626 | #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) | |
5627 | #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) | |
5628 | #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) | |
5629 | #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) | |
b9055052 | 5630 | |
bd2e244f JB |
5631 | #define _PSA_CTL 0x68180 |
5632 | #define _PSB_CTL 0x68980 | |
5633 | #define PS_ENABLE (1<<31) | |
5634 | #define _PSA_WIN_SZ 0x68174 | |
5635 | #define _PSB_WIN_SZ 0x68974 | |
5636 | #define _PSA_WIN_POS 0x68170 | |
5637 | #define _PSB_WIN_POS 0x68970 | |
5638 | ||
f0f59a00 VS |
5639 | #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) |
5640 | #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) | |
5641 | #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) | |
bd2e244f | 5642 | |
1c9a2d4a CK |
5643 | /* |
5644 | * Skylake scalers | |
5645 | */ | |
5646 | #define _PS_1A_CTRL 0x68180 | |
5647 | #define _PS_2A_CTRL 0x68280 | |
5648 | #define _PS_1B_CTRL 0x68980 | |
5649 | #define _PS_2B_CTRL 0x68A80 | |
5650 | #define _PS_1C_CTRL 0x69180 | |
5651 | #define PS_SCALER_EN (1 << 31) | |
5652 | #define PS_SCALER_MODE_MASK (3 << 28) | |
5653 | #define PS_SCALER_MODE_DYN (0 << 28) | |
5654 | #define PS_SCALER_MODE_HQ (1 << 28) | |
5655 | #define PS_PLANE_SEL_MASK (7 << 25) | |
68d97538 | 5656 | #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) |
1c9a2d4a CK |
5657 | #define PS_FILTER_MASK (3 << 23) |
5658 | #define PS_FILTER_MEDIUM (0 << 23) | |
5659 | #define PS_FILTER_EDGE_ENHANCE (2 << 23) | |
5660 | #define PS_FILTER_BILINEAR (3 << 23) | |
5661 | #define PS_VERT3TAP (1 << 21) | |
5662 | #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) | |
5663 | #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) | |
5664 | #define PS_PWRUP_PROGRESS (1 << 17) | |
5665 | #define PS_V_FILTER_BYPASS (1 << 8) | |
5666 | #define PS_VADAPT_EN (1 << 7) | |
5667 | #define PS_VADAPT_MODE_MASK (3 << 5) | |
5668 | #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) | |
5669 | #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) | |
5670 | #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) | |
5671 | ||
5672 | #define _PS_PWR_GATE_1A 0x68160 | |
5673 | #define _PS_PWR_GATE_2A 0x68260 | |
5674 | #define _PS_PWR_GATE_1B 0x68960 | |
5675 | #define _PS_PWR_GATE_2B 0x68A60 | |
5676 | #define _PS_PWR_GATE_1C 0x69160 | |
5677 | #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) | |
5678 | #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) | |
5679 | #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) | |
5680 | #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) | |
5681 | #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) | |
5682 | #define PS_PWR_GATE_SLPEN_8 0 | |
5683 | #define PS_PWR_GATE_SLPEN_16 1 | |
5684 | #define PS_PWR_GATE_SLPEN_24 2 | |
5685 | #define PS_PWR_GATE_SLPEN_32 3 | |
5686 | ||
5687 | #define _PS_WIN_POS_1A 0x68170 | |
5688 | #define _PS_WIN_POS_2A 0x68270 | |
5689 | #define _PS_WIN_POS_1B 0x68970 | |
5690 | #define _PS_WIN_POS_2B 0x68A70 | |
5691 | #define _PS_WIN_POS_1C 0x69170 | |
5692 | ||
5693 | #define _PS_WIN_SZ_1A 0x68174 | |
5694 | #define _PS_WIN_SZ_2A 0x68274 | |
5695 | #define _PS_WIN_SZ_1B 0x68974 | |
5696 | #define _PS_WIN_SZ_2B 0x68A74 | |
5697 | #define _PS_WIN_SZ_1C 0x69174 | |
5698 | ||
5699 | #define _PS_VSCALE_1A 0x68184 | |
5700 | #define _PS_VSCALE_2A 0x68284 | |
5701 | #define _PS_VSCALE_1B 0x68984 | |
5702 | #define _PS_VSCALE_2B 0x68A84 | |
5703 | #define _PS_VSCALE_1C 0x69184 | |
5704 | ||
5705 | #define _PS_HSCALE_1A 0x68190 | |
5706 | #define _PS_HSCALE_2A 0x68290 | |
5707 | #define _PS_HSCALE_1B 0x68990 | |
5708 | #define _PS_HSCALE_2B 0x68A90 | |
5709 | #define _PS_HSCALE_1C 0x69190 | |
5710 | ||
5711 | #define _PS_VPHASE_1A 0x68188 | |
5712 | #define _PS_VPHASE_2A 0x68288 | |
5713 | #define _PS_VPHASE_1B 0x68988 | |
5714 | #define _PS_VPHASE_2B 0x68A88 | |
5715 | #define _PS_VPHASE_1C 0x69188 | |
5716 | ||
5717 | #define _PS_HPHASE_1A 0x68194 | |
5718 | #define _PS_HPHASE_2A 0x68294 | |
5719 | #define _PS_HPHASE_1B 0x68994 | |
5720 | #define _PS_HPHASE_2B 0x68A94 | |
5721 | #define _PS_HPHASE_1C 0x69194 | |
5722 | ||
5723 | #define _PS_ECC_STAT_1A 0x681D0 | |
5724 | #define _PS_ECC_STAT_2A 0x682D0 | |
5725 | #define _PS_ECC_STAT_1B 0x689D0 | |
5726 | #define _PS_ECC_STAT_2B 0x68AD0 | |
5727 | #define _PS_ECC_STAT_1C 0x691D0 | |
5728 | ||
5729 | #define _ID(id, a, b) ((a) + (id)*((b)-(a))) | |
f0f59a00 | 5730 | #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
5731 | _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ |
5732 | _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) | |
f0f59a00 | 5733 | #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
5734 | _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ |
5735 | _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) | |
f0f59a00 | 5736 | #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
5737 | _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ |
5738 | _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) | |
f0f59a00 | 5739 | #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
5740 | _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ |
5741 | _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) | |
f0f59a00 | 5742 | #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
5743 | _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ |
5744 | _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) | |
f0f59a00 | 5745 | #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
5746 | _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ |
5747 | _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) | |
f0f59a00 | 5748 | #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
5749 | _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ |
5750 | _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) | |
f0f59a00 | 5751 | #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
5752 | _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ |
5753 | _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) | |
f0f59a00 | 5754 | #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a | 5755 | _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ |
9bca5d0c | 5756 | _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) |
1c9a2d4a | 5757 | |
b9055052 | 5758 | /* legacy palette */ |
9db4a9c7 JB |
5759 | #define _LGC_PALETTE_A 0x4a000 |
5760 | #define _LGC_PALETTE_B 0x4a800 | |
f0f59a00 | 5761 | #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) |
b9055052 | 5762 | |
42db64ef PZ |
5763 | #define _GAMMA_MODE_A 0x4a480 |
5764 | #define _GAMMA_MODE_B 0x4ac80 | |
f0f59a00 | 5765 | #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) |
42db64ef | 5766 | #define GAMMA_MODE_MODE_MASK (3 << 0) |
3eff4faa DV |
5767 | #define GAMMA_MODE_MODE_8BIT (0 << 0) |
5768 | #define GAMMA_MODE_MODE_10BIT (1 << 0) | |
5769 | #define GAMMA_MODE_MODE_12BIT (2 << 0) | |
42db64ef PZ |
5770 | #define GAMMA_MODE_MODE_SPLIT (3 << 0) |
5771 | ||
8337206d | 5772 | /* DMC/CSR */ |
f0f59a00 | 5773 | #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) |
6fb403de MK |
5774 | #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 |
5775 | #define CSR_HTP_ADDR_SKL 0x00500034 | |
f0f59a00 VS |
5776 | #define CSR_SSP_BASE _MMIO(0x8F074) |
5777 | #define CSR_HTP_SKL _MMIO(0x8F004) | |
5778 | #define CSR_LAST_WRITE _MMIO(0x8F034) | |
6fb403de MK |
5779 | #define CSR_LAST_WRITE_VALUE 0xc003b400 |
5780 | /* MMIO address range for CSR program (0x80000 - 0x82FFF) */ | |
5781 | #define CSR_MMIO_START_RANGE 0x80000 | |
5782 | #define CSR_MMIO_END_RANGE 0x8FFFF | |
f0f59a00 VS |
5783 | #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) |
5784 | #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) | |
5785 | #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) | |
8337206d | 5786 | |
b9055052 ZW |
5787 | /* interrupts */ |
5788 | #define DE_MASTER_IRQ_CONTROL (1 << 31) | |
5789 | #define DE_SPRITEB_FLIP_DONE (1 << 29) | |
5790 | #define DE_SPRITEA_FLIP_DONE (1 << 28) | |
5791 | #define DE_PLANEB_FLIP_DONE (1 << 27) | |
5792 | #define DE_PLANEA_FLIP_DONE (1 << 26) | |
40da17c2 | 5793 | #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) |
b9055052 ZW |
5794 | #define DE_PCU_EVENT (1 << 25) |
5795 | #define DE_GTT_FAULT (1 << 24) | |
5796 | #define DE_POISON (1 << 23) | |
5797 | #define DE_PERFORM_COUNTER (1 << 22) | |
5798 | #define DE_PCH_EVENT (1 << 21) | |
5799 | #define DE_AUX_CHANNEL_A (1 << 20) | |
5800 | #define DE_DP_A_HOTPLUG (1 << 19) | |
5801 | #define DE_GSE (1 << 18) | |
5802 | #define DE_PIPEB_VBLANK (1 << 15) | |
5803 | #define DE_PIPEB_EVEN_FIELD (1 << 14) | |
5804 | #define DE_PIPEB_ODD_FIELD (1 << 13) | |
5805 | #define DE_PIPEB_LINE_COMPARE (1 << 12) | |
5806 | #define DE_PIPEB_VSYNC (1 << 11) | |
5b3a856b | 5807 | #define DE_PIPEB_CRC_DONE (1 << 10) |
b9055052 ZW |
5808 | #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) |
5809 | #define DE_PIPEA_VBLANK (1 << 7) | |
40da17c2 | 5810 | #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) |
b9055052 ZW |
5811 | #define DE_PIPEA_EVEN_FIELD (1 << 6) |
5812 | #define DE_PIPEA_ODD_FIELD (1 << 5) | |
5813 | #define DE_PIPEA_LINE_COMPARE (1 << 4) | |
5814 | #define DE_PIPEA_VSYNC (1 << 3) | |
5b3a856b | 5815 | #define DE_PIPEA_CRC_DONE (1 << 2) |
40da17c2 | 5816 | #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) |
b9055052 | 5817 | #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) |
40da17c2 | 5818 | #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) |
b9055052 | 5819 | |
b1f14ad0 | 5820 | /* More Ivybridge lolz */ |
8664281b | 5821 | #define DE_ERR_INT_IVB (1<<30) |
b1f14ad0 JB |
5822 | #define DE_GSE_IVB (1<<29) |
5823 | #define DE_PCH_EVENT_IVB (1<<28) | |
5824 | #define DE_DP_A_HOTPLUG_IVB (1<<27) | |
5825 | #define DE_AUX_CHANNEL_A_IVB (1<<26) | |
b615b57a CW |
5826 | #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) |
5827 | #define DE_PLANEC_FLIP_DONE_IVB (1<<13) | |
5828 | #define DE_PIPEC_VBLANK_IVB (1<<10) | |
b1f14ad0 | 5829 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
b1f14ad0 | 5830 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) |
b1f14ad0 | 5831 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
b615b57a CW |
5832 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
5833 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) | |
40da17c2 | 5834 | #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) |
b1f14ad0 | 5835 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
68d97538 | 5836 | #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) |
b518421f | 5837 | |
f0f59a00 | 5838 | #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ |
7eea1ddf JB |
5839 | #define MASTER_INTERRUPT_ENABLE (1<<31) |
5840 | ||
f0f59a00 VS |
5841 | #define DEISR _MMIO(0x44000) |
5842 | #define DEIMR _MMIO(0x44004) | |
5843 | #define DEIIR _MMIO(0x44008) | |
5844 | #define DEIER _MMIO(0x4400c) | |
b9055052 | 5845 | |
f0f59a00 VS |
5846 | #define GTISR _MMIO(0x44010) |
5847 | #define GTIMR _MMIO(0x44014) | |
5848 | #define GTIIR _MMIO(0x44018) | |
5849 | #define GTIER _MMIO(0x4401c) | |
b9055052 | 5850 | |
f0f59a00 | 5851 | #define GEN8_MASTER_IRQ _MMIO(0x44200) |
abd58f01 BW |
5852 | #define GEN8_MASTER_IRQ_CONTROL (1<<31) |
5853 | #define GEN8_PCU_IRQ (1<<30) | |
5854 | #define GEN8_DE_PCH_IRQ (1<<23) | |
5855 | #define GEN8_DE_MISC_IRQ (1<<22) | |
5856 | #define GEN8_DE_PORT_IRQ (1<<20) | |
5857 | #define GEN8_DE_PIPE_C_IRQ (1<<18) | |
5858 | #define GEN8_DE_PIPE_B_IRQ (1<<17) | |
5859 | #define GEN8_DE_PIPE_A_IRQ (1<<16) | |
68d97538 | 5860 | #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe))) |
abd58f01 | 5861 | #define GEN8_GT_VECS_IRQ (1<<6) |
0961021a | 5862 | #define GEN8_GT_PM_IRQ (1<<4) |
abd58f01 BW |
5863 | #define GEN8_GT_VCS2_IRQ (1<<3) |
5864 | #define GEN8_GT_VCS1_IRQ (1<<2) | |
5865 | #define GEN8_GT_BCS_IRQ (1<<1) | |
5866 | #define GEN8_GT_RCS_IRQ (1<<0) | |
abd58f01 | 5867 | |
f0f59a00 VS |
5868 | #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) |
5869 | #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) | |
5870 | #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) | |
5871 | #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) | |
abd58f01 | 5872 | |
abd58f01 | 5873 | #define GEN8_RCS_IRQ_SHIFT 0 |
4df001d3 | 5874 | #define GEN8_BCS_IRQ_SHIFT 16 |
abd58f01 | 5875 | #define GEN8_VCS1_IRQ_SHIFT 0 |
4df001d3 | 5876 | #define GEN8_VCS2_IRQ_SHIFT 16 |
abd58f01 | 5877 | #define GEN8_VECS_IRQ_SHIFT 0 |
4df001d3 | 5878 | #define GEN8_WD_IRQ_SHIFT 16 |
abd58f01 | 5879 | |
f0f59a00 VS |
5880 | #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) |
5881 | #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) | |
5882 | #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) | |
5883 | #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) | |
38d83c96 | 5884 | #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) |
abd58f01 BW |
5885 | #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) |
5886 | #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) | |
5887 | #define GEN8_PIPE_CURSOR_FAULT (1 << 10) | |
5888 | #define GEN8_PIPE_SPRITE_FAULT (1 << 9) | |
5889 | #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) | |
5890 | #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) | |
d0e1f1cb | 5891 | #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) |
abd58f01 BW |
5892 | #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) |
5893 | #define GEN8_PIPE_VSYNC (1 << 1) | |
5894 | #define GEN8_PIPE_VBLANK (1 << 0) | |
770de83d | 5895 | #define GEN9_PIPE_CURSOR_FAULT (1 << 11) |
b21249c9 | 5896 | #define GEN9_PIPE_PLANE4_FAULT (1 << 10) |
770de83d DL |
5897 | #define GEN9_PIPE_PLANE3_FAULT (1 << 9) |
5898 | #define GEN9_PIPE_PLANE2_FAULT (1 << 8) | |
5899 | #define GEN9_PIPE_PLANE1_FAULT (1 << 7) | |
b21249c9 | 5900 | #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) |
770de83d DL |
5901 | #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) |
5902 | #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) | |
5903 | #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) | |
68d97538 | 5904 | #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) |
30100f2b DV |
5905 | #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ |
5906 | (GEN8_PIPE_CURSOR_FAULT | \ | |
5907 | GEN8_PIPE_SPRITE_FAULT | \ | |
5908 | GEN8_PIPE_PRIMARY_FAULT) | |
770de83d DL |
5909 | #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ |
5910 | (GEN9_PIPE_CURSOR_FAULT | \ | |
b21249c9 | 5911 | GEN9_PIPE_PLANE4_FAULT | \ |
770de83d DL |
5912 | GEN9_PIPE_PLANE3_FAULT | \ |
5913 | GEN9_PIPE_PLANE2_FAULT | \ | |
5914 | GEN9_PIPE_PLANE1_FAULT) | |
abd58f01 | 5915 | |
f0f59a00 VS |
5916 | #define GEN8_DE_PORT_ISR _MMIO(0x44440) |
5917 | #define GEN8_DE_PORT_IMR _MMIO(0x44444) | |
5918 | #define GEN8_DE_PORT_IIR _MMIO(0x44448) | |
5919 | #define GEN8_DE_PORT_IER _MMIO(0x4444c) | |
88e04703 JB |
5920 | #define GEN9_AUX_CHANNEL_D (1 << 27) |
5921 | #define GEN9_AUX_CHANNEL_C (1 << 26) | |
5922 | #define GEN9_AUX_CHANNEL_B (1 << 25) | |
e0a20ad7 SS |
5923 | #define BXT_DE_PORT_HP_DDIC (1 << 5) |
5924 | #define BXT_DE_PORT_HP_DDIB (1 << 4) | |
5925 | #define BXT_DE_PORT_HP_DDIA (1 << 3) | |
5926 | #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ | |
5927 | BXT_DE_PORT_HP_DDIB | \ | |
5928 | BXT_DE_PORT_HP_DDIC) | |
5929 | #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) | |
9e63743e | 5930 | #define BXT_DE_PORT_GMBUS (1 << 1) |
6d766f02 | 5931 | #define GEN8_AUX_CHANNEL_A (1 << 0) |
abd58f01 | 5932 | |
f0f59a00 VS |
5933 | #define GEN8_DE_MISC_ISR _MMIO(0x44460) |
5934 | #define GEN8_DE_MISC_IMR _MMIO(0x44464) | |
5935 | #define GEN8_DE_MISC_IIR _MMIO(0x44468) | |
5936 | #define GEN8_DE_MISC_IER _MMIO(0x4446c) | |
abd58f01 BW |
5937 | #define GEN8_DE_MISC_GSE (1 << 27) |
5938 | ||
f0f59a00 VS |
5939 | #define GEN8_PCU_ISR _MMIO(0x444e0) |
5940 | #define GEN8_PCU_IMR _MMIO(0x444e4) | |
5941 | #define GEN8_PCU_IIR _MMIO(0x444e8) | |
5942 | #define GEN8_PCU_IER _MMIO(0x444ec) | |
abd58f01 | 5943 | |
f0f59a00 | 5944 | #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) |
67e92af0 EA |
5945 | /* Required on all Ironlake and Sandybridge according to the B-Spec. */ |
5946 | #define ILK_ELPIN_409_SELECT (1 << 25) | |
7f8a8569 ZW |
5947 | #define ILK_DPARB_GATE (1<<22) |
5948 | #define ILK_VSDPFD_FULL (1<<21) | |
f0f59a00 | 5949 | #define FUSE_STRAP _MMIO(0x42014) |
e3589908 DL |
5950 | #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) |
5951 | #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) | |
5952 | #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) | |
8c448cad | 5953 | #define IVB_PIPE_C_DISABLE (1 << 28) |
e3589908 DL |
5954 | #define ILK_HDCP_DISABLE (1 << 25) |
5955 | #define ILK_eDP_A_DISABLE (1 << 24) | |
5956 | #define HSW_CDCLK_LIMIT (1 << 24) | |
5957 | #define ILK_DESKTOP (1 << 23) | |
231e54f6 | 5958 | |
f0f59a00 | 5959 | #define ILK_DSPCLK_GATE_D _MMIO(0x42020) |
231e54f6 DL |
5960 | #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) |
5961 | #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) | |
5962 | #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) | |
5963 | #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) | |
5964 | #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) | |
7f8a8569 | 5965 | |
f0f59a00 | 5966 | #define IVB_CHICKEN3 _MMIO(0x4200c) |
116ac8d2 EA |
5967 | # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) |
5968 | # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) | |
5969 | ||
f0f59a00 | 5970 | #define CHICKEN_PAR1_1 _MMIO(0x42080) |
fe4ab3ce | 5971 | #define DPA_MASK_VBLANK_SRD (1 << 15) |
90a88643 PZ |
5972 | #define FORCE_ARB_IDLE_PLANES (1 << 14) |
5973 | ||
fe4ab3ce BW |
5974 | #define _CHICKEN_PIPESL_1_A 0x420b0 |
5975 | #define _CHICKEN_PIPESL_1_B 0x420b4 | |
8f670bb1 VS |
5976 | #define HSW_FBCQ_DIS (1 << 22) |
5977 | #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) | |
f0f59a00 | 5978 | #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) |
fe4ab3ce | 5979 | |
f0f59a00 | 5980 | #define DISP_ARB_CTL _MMIO(0x45000) |
553bd149 | 5981 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) |
7f8a8569 | 5982 | #define DISP_FBC_WM_DIS (1<<15) |
f0f59a00 | 5983 | #define DISP_ARB_CTL2 _MMIO(0x45004) |
ac9545fd | 5984 | #define DISP_DATA_PARTITION_5_6 (1<<6) |
f0f59a00 | 5985 | #define DBUF_CTL _MMIO(0x45008) |
f8437dd1 VK |
5986 | #define DBUF_POWER_REQUEST (1<<31) |
5987 | #define DBUF_POWER_STATE (1<<30) | |
f0f59a00 | 5988 | #define GEN7_MSG_CTL _MMIO(0x45010) |
88a2b2a3 BW |
5989 | #define WAIT_FOR_PCH_RESET_ACK (1<<1) |
5990 | #define WAIT_FOR_PCH_FLR_ACK (1<<0) | |
f0f59a00 | 5991 | #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) |
6ba844b0 | 5992 | #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) |
553bd149 | 5993 | |
f0f59a00 | 5994 | #define SKL_DFSM _MMIO(0x51000) |
a9419e84 DL |
5995 | #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) |
5996 | #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) | |
5997 | #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) | |
5998 | #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) | |
5999 | #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) | |
bf4f2fb0 PJ |
6000 | #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) |
6001 | #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) | |
6002 | #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) | |
a9419e84 | 6003 | |
a78536e7 AS |
6004 | #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) |
6005 | #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14) | |
6006 | ||
f0f59a00 | 6007 | #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) |
2caa3b26 DL |
6008 | #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) |
6009 | ||
2c8580e4 | 6010 | #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) |
e0f3fa09 AS |
6011 | #define GEN8_CS_CHICKEN1 _MMIO(0x2580) |
6012 | ||
e4e0c058 | 6013 | /* GEN7 chicken */ |
f0f59a00 | 6014 | #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) |
d71de14d | 6015 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
183c6dac | 6016 | # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) |
f0f59a00 | 6017 | #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) |
a75f3628 | 6018 | # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) |
d71de14d | 6019 | |
f0f59a00 | 6020 | #define HIZ_CHICKEN _MMIO(0x7018) |
d0bbbc4f DL |
6021 | # define CHV_HZ_8X8_MODE_IN_1X (1<<15) |
6022 | # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3) | |
d60de81d | 6023 | |
f0f59a00 | 6024 | #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) |
183c6dac DL |
6025 | #define DISABLE_PIXEL_MASK_CAMMING (1<<14) |
6026 | ||
f0f59a00 | 6027 | #define GEN7_L3SQCREG1 _MMIO(0xB010) |
031994ee VS |
6028 | #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 |
6029 | ||
f0f59a00 | 6030 | #define GEN8_L3SQCREG1 _MMIO(0xB100) |
51ce4db1 RV |
6031 | #define BDW_WA_L3SQCREG1_DEFAULT 0x784000 |
6032 | ||
f0f59a00 | 6033 | #define GEN7_L3CNTLREG1 _MMIO(0xB01C) |
1af8452f | 6034 | #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C |
d0cf5ead | 6035 | #define GEN7_L3AGDIS (1<<19) |
f0f59a00 VS |
6036 | #define GEN7_L3CNTLREG2 _MMIO(0xB020) |
6037 | #define GEN7_L3CNTLREG3 _MMIO(0xB024) | |
e4e0c058 | 6038 | |
f0f59a00 | 6039 | #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030) |
e4e0c058 ED |
6040 | #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 |
6041 | ||
f0f59a00 | 6042 | #define GEN7_L3SQCREG4 _MMIO(0xb034) |
61939d97 JB |
6043 | #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) |
6044 | ||
f0f59a00 | 6045 | #define GEN8_L3SQCREG4 _MMIO(0xb118) |
8bc0ccf6 | 6046 | #define GEN8_LQSC_RO_PERF_DIS (1<<27) |
c82435bb | 6047 | #define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21) |
8bc0ccf6 | 6048 | |
63801f21 | 6049 | /* GEN8 chicken */ |
f0f59a00 | 6050 | #define HDC_CHICKEN0 _MMIO(0x7300) |
2a0ee94f | 6051 | #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) |
da09654d | 6052 | #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) |
35cb6f3b DL |
6053 | #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) |
6054 | #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5) | |
6055 | #define HDC_FORCE_NON_COHERENT (1<<4) | |
65ca7514 | 6056 | #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10) |
63801f21 | 6057 | |
3669ab61 AS |
6058 | #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) |
6059 | ||
38a39a7b | 6060 | /* GEN9 chicken */ |
f0f59a00 | 6061 | #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) |
38a39a7b BW |
6062 | #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) |
6063 | ||
db099c8f | 6064 | /* WaCatErrorRejectionIssue */ |
f0f59a00 | 6065 | #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) |
db099c8f ED |
6066 | #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) |
6067 | ||
f0f59a00 | 6068 | #define HSW_SCRATCH1 _MMIO(0xb038) |
f3fc4884 FJ |
6069 | #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) |
6070 | ||
f0f59a00 | 6071 | #define BDW_SCRATCH1 _MMIO(0xb11c) |
77719d28 DL |
6072 | #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2) |
6073 | ||
b9055052 ZW |
6074 | /* PCH */ |
6075 | ||
23e81d69 | 6076 | /* south display engine interrupt: IBX */ |
776ad806 JB |
6077 | #define SDE_AUDIO_POWER_D (1 << 27) |
6078 | #define SDE_AUDIO_POWER_C (1 << 26) | |
6079 | #define SDE_AUDIO_POWER_B (1 << 25) | |
6080 | #define SDE_AUDIO_POWER_SHIFT (25) | |
6081 | #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) | |
6082 | #define SDE_GMBUS (1 << 24) | |
6083 | #define SDE_AUDIO_HDCP_TRANSB (1 << 23) | |
6084 | #define SDE_AUDIO_HDCP_TRANSA (1 << 22) | |
6085 | #define SDE_AUDIO_HDCP_MASK (3 << 22) | |
6086 | #define SDE_AUDIO_TRANSB (1 << 21) | |
6087 | #define SDE_AUDIO_TRANSA (1 << 20) | |
6088 | #define SDE_AUDIO_TRANS_MASK (3 << 20) | |
6089 | #define SDE_POISON (1 << 19) | |
6090 | /* 18 reserved */ | |
6091 | #define SDE_FDI_RXB (1 << 17) | |
6092 | #define SDE_FDI_RXA (1 << 16) | |
6093 | #define SDE_FDI_MASK (3 << 16) | |
6094 | #define SDE_AUXD (1 << 15) | |
6095 | #define SDE_AUXC (1 << 14) | |
6096 | #define SDE_AUXB (1 << 13) | |
6097 | #define SDE_AUX_MASK (7 << 13) | |
6098 | /* 12 reserved */ | |
b9055052 ZW |
6099 | #define SDE_CRT_HOTPLUG (1 << 11) |
6100 | #define SDE_PORTD_HOTPLUG (1 << 10) | |
6101 | #define SDE_PORTC_HOTPLUG (1 << 9) | |
6102 | #define SDE_PORTB_HOTPLUG (1 << 8) | |
6103 | #define SDE_SDVOB_HOTPLUG (1 << 6) | |
e5868a31 EE |
6104 | #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ |
6105 | SDE_SDVOB_HOTPLUG | \ | |
6106 | SDE_PORTB_HOTPLUG | \ | |
6107 | SDE_PORTC_HOTPLUG | \ | |
6108 | SDE_PORTD_HOTPLUG) | |
776ad806 JB |
6109 | #define SDE_TRANSB_CRC_DONE (1 << 5) |
6110 | #define SDE_TRANSB_CRC_ERR (1 << 4) | |
6111 | #define SDE_TRANSB_FIFO_UNDER (1 << 3) | |
6112 | #define SDE_TRANSA_CRC_DONE (1 << 2) | |
6113 | #define SDE_TRANSA_CRC_ERR (1 << 1) | |
6114 | #define SDE_TRANSA_FIFO_UNDER (1 << 0) | |
6115 | #define SDE_TRANS_MASK (0x3f) | |
23e81d69 AJ |
6116 | |
6117 | /* south display engine interrupt: CPT/PPT */ | |
6118 | #define SDE_AUDIO_POWER_D_CPT (1 << 31) | |
6119 | #define SDE_AUDIO_POWER_C_CPT (1 << 30) | |
6120 | #define SDE_AUDIO_POWER_B_CPT (1 << 29) | |
6121 | #define SDE_AUDIO_POWER_SHIFT_CPT 29 | |
6122 | #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) | |
6123 | #define SDE_AUXD_CPT (1 << 27) | |
6124 | #define SDE_AUXC_CPT (1 << 26) | |
6125 | #define SDE_AUXB_CPT (1 << 25) | |
6126 | #define SDE_AUX_MASK_CPT (7 << 25) | |
26951caf | 6127 | #define SDE_PORTE_HOTPLUG_SPT (1 << 25) |
74c0b395 | 6128 | #define SDE_PORTA_HOTPLUG_SPT (1 << 24) |
8db9d77b ZW |
6129 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
6130 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) | |
6131 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) | |
23e81d69 | 6132 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
73c352a2 | 6133 | #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) |
2d7b8366 | 6134 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ |
73c352a2 | 6135 | SDE_SDVOB_HOTPLUG_CPT | \ |
2d7b8366 YL |
6136 | SDE_PORTD_HOTPLUG_CPT | \ |
6137 | SDE_PORTC_HOTPLUG_CPT | \ | |
6138 | SDE_PORTB_HOTPLUG_CPT) | |
26951caf XZ |
6139 | #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ |
6140 | SDE_PORTD_HOTPLUG_CPT | \ | |
6141 | SDE_PORTC_HOTPLUG_CPT | \ | |
74c0b395 VS |
6142 | SDE_PORTB_HOTPLUG_CPT | \ |
6143 | SDE_PORTA_HOTPLUG_SPT) | |
23e81d69 | 6144 | #define SDE_GMBUS_CPT (1 << 17) |
8664281b | 6145 | #define SDE_ERROR_CPT (1 << 16) |
23e81d69 AJ |
6146 | #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) |
6147 | #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) | |
6148 | #define SDE_FDI_RXC_CPT (1 << 8) | |
6149 | #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) | |
6150 | #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) | |
6151 | #define SDE_FDI_RXB_CPT (1 << 4) | |
6152 | #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) | |
6153 | #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) | |
6154 | #define SDE_FDI_RXA_CPT (1 << 0) | |
6155 | #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ | |
6156 | SDE_AUDIO_CP_REQ_B_CPT | \ | |
6157 | SDE_AUDIO_CP_REQ_A_CPT) | |
6158 | #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ | |
6159 | SDE_AUDIO_CP_CHG_B_CPT | \ | |
6160 | SDE_AUDIO_CP_CHG_A_CPT) | |
6161 | #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ | |
6162 | SDE_FDI_RXB_CPT | \ | |
6163 | SDE_FDI_RXA_CPT) | |
b9055052 | 6164 | |
f0f59a00 VS |
6165 | #define SDEISR _MMIO(0xc4000) |
6166 | #define SDEIMR _MMIO(0xc4004) | |
6167 | #define SDEIIR _MMIO(0xc4008) | |
6168 | #define SDEIER _MMIO(0xc400c) | |
b9055052 | 6169 | |
f0f59a00 | 6170 | #define SERR_INT _MMIO(0xc4040) |
de032bf4 | 6171 | #define SERR_INT_POISON (1<<31) |
8664281b PZ |
6172 | #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) |
6173 | #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) | |
6174 | #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) | |
68d97538 | 6175 | #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3)) |
8664281b | 6176 | |
b9055052 | 6177 | /* digital port hotplug */ |
f0f59a00 | 6178 | #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ |
195baa06 VS |
6179 | #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ |
6180 | #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ | |
6181 | #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ | |
6182 | #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ | |
6183 | #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ | |
40bfd7a3 VS |
6184 | #define PORTD_HOTPLUG_ENABLE (1 << 20) |
6185 | #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ | |
6186 | #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ | |
6187 | #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ | |
6188 | #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ | |
6189 | #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ | |
6190 | #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) | |
b696519e DL |
6191 | #define PORTD_HOTPLUG_NO_DETECT (0 << 16) |
6192 | #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) | |
6193 | #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) | |
40bfd7a3 VS |
6194 | #define PORTC_HOTPLUG_ENABLE (1 << 12) |
6195 | #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ | |
6196 | #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ | |
6197 | #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ | |
6198 | #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ | |
6199 | #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ | |
6200 | #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) | |
b696519e DL |
6201 | #define PORTC_HOTPLUG_NO_DETECT (0 << 8) |
6202 | #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) | |
6203 | #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) | |
40bfd7a3 VS |
6204 | #define PORTB_HOTPLUG_ENABLE (1 << 4) |
6205 | #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ | |
6206 | #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ | |
6207 | #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ | |
6208 | #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ | |
6209 | #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ | |
6210 | #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) | |
b696519e DL |
6211 | #define PORTB_HOTPLUG_NO_DETECT (0 << 0) |
6212 | #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) | |
6213 | #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) | |
b9055052 | 6214 | |
f0f59a00 | 6215 | #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ |
40bfd7a3 VS |
6216 | #define PORTE_HOTPLUG_ENABLE (1 << 4) |
6217 | #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) | |
26951caf XZ |
6218 | #define PORTE_HOTPLUG_NO_DETECT (0 << 0) |
6219 | #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) | |
6220 | #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) | |
b9055052 | 6221 | |
f0f59a00 VS |
6222 | #define PCH_GPIOA _MMIO(0xc5010) |
6223 | #define PCH_GPIOB _MMIO(0xc5014) | |
6224 | #define PCH_GPIOC _MMIO(0xc5018) | |
6225 | #define PCH_GPIOD _MMIO(0xc501c) | |
6226 | #define PCH_GPIOE _MMIO(0xc5020) | |
6227 | #define PCH_GPIOF _MMIO(0xc5024) | |
b9055052 | 6228 | |
f0f59a00 VS |
6229 | #define PCH_GMBUS0 _MMIO(0xc5100) |
6230 | #define PCH_GMBUS1 _MMIO(0xc5104) | |
6231 | #define PCH_GMBUS2 _MMIO(0xc5108) | |
6232 | #define PCH_GMBUS3 _MMIO(0xc510c) | |
6233 | #define PCH_GMBUS4 _MMIO(0xc5110) | |
6234 | #define PCH_GMBUS5 _MMIO(0xc5120) | |
f0217c42 | 6235 | |
9db4a9c7 JB |
6236 | #define _PCH_DPLL_A 0xc6014 |
6237 | #define _PCH_DPLL_B 0xc6018 | |
f0f59a00 | 6238 | #define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
b9055052 | 6239 | |
9db4a9c7 | 6240 | #define _PCH_FPA0 0xc6040 |
c1858123 | 6241 | #define FP_CB_TUNE (0x3<<22) |
9db4a9c7 JB |
6242 | #define _PCH_FPA1 0xc6044 |
6243 | #define _PCH_FPB0 0xc6048 | |
6244 | #define _PCH_FPB1 0xc604c | |
f0f59a00 VS |
6245 | #define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0) |
6246 | #define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1) | |
b9055052 | 6247 | |
f0f59a00 | 6248 | #define PCH_DPLL_TEST _MMIO(0xc606c) |
b9055052 | 6249 | |
f0f59a00 | 6250 | #define PCH_DREF_CONTROL _MMIO(0xC6200) |
b9055052 ZW |
6251 | #define DREF_CONTROL_MASK 0x7fc3 |
6252 | #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) | |
6253 | #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) | |
6254 | #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) | |
6255 | #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) | |
6256 | #define DREF_SSC_SOURCE_DISABLE (0<<11) | |
6257 | #define DREF_SSC_SOURCE_ENABLE (2<<11) | |
c038e51e | 6258 | #define DREF_SSC_SOURCE_MASK (3<<11) |
b9055052 ZW |
6259 | #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) |
6260 | #define DREF_NONSPREAD_CK505_ENABLE (1<<9) | |
6261 | #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) | |
c038e51e | 6262 | #define DREF_NONSPREAD_SOURCE_MASK (3<<9) |
b9055052 ZW |
6263 | #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) |
6264 | #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) | |
92f2584a | 6265 | #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) |
b9055052 ZW |
6266 | #define DREF_SSC4_DOWNSPREAD (0<<6) |
6267 | #define DREF_SSC4_CENTERSPREAD (1<<6) | |
6268 | #define DREF_SSC1_DISABLE (0<<1) | |
6269 | #define DREF_SSC1_ENABLE (1<<1) | |
6270 | #define DREF_SSC4_DISABLE (0) | |
6271 | #define DREF_SSC4_ENABLE (1) | |
6272 | ||
f0f59a00 | 6273 | #define PCH_RAWCLK_FREQ _MMIO(0xc6204) |
b9055052 ZW |
6274 | #define FDL_TP1_TIMER_SHIFT 12 |
6275 | #define FDL_TP1_TIMER_MASK (3<<12) | |
6276 | #define FDL_TP2_TIMER_SHIFT 10 | |
6277 | #define FDL_TP2_TIMER_MASK (3<<10) | |
6278 | #define RAWCLK_FREQ_MASK 0x3ff | |
6279 | ||
f0f59a00 | 6280 | #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) |
b9055052 | 6281 | |
f0f59a00 VS |
6282 | #define PCH_SSC4_PARMS _MMIO(0xc6210) |
6283 | #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) | |
b9055052 | 6284 | |
f0f59a00 | 6285 | #define PCH_DPLL_SEL _MMIO(0xc7000) |
68d97538 | 6286 | #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) |
11887397 | 6287 | #define TRANS_DPLLA_SEL(pipe) 0 |
68d97538 | 6288 | #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) |
8db9d77b | 6289 | |
b9055052 ZW |
6290 | /* transcoder */ |
6291 | ||
275f01b2 DV |
6292 | #define _PCH_TRANS_HTOTAL_A 0xe0000 |
6293 | #define TRANS_HTOTAL_SHIFT 16 | |
6294 | #define TRANS_HACTIVE_SHIFT 0 | |
6295 | #define _PCH_TRANS_HBLANK_A 0xe0004 | |
6296 | #define TRANS_HBLANK_END_SHIFT 16 | |
6297 | #define TRANS_HBLANK_START_SHIFT 0 | |
6298 | #define _PCH_TRANS_HSYNC_A 0xe0008 | |
6299 | #define TRANS_HSYNC_END_SHIFT 16 | |
6300 | #define TRANS_HSYNC_START_SHIFT 0 | |
6301 | #define _PCH_TRANS_VTOTAL_A 0xe000c | |
6302 | #define TRANS_VTOTAL_SHIFT 16 | |
6303 | #define TRANS_VACTIVE_SHIFT 0 | |
6304 | #define _PCH_TRANS_VBLANK_A 0xe0010 | |
6305 | #define TRANS_VBLANK_END_SHIFT 16 | |
6306 | #define TRANS_VBLANK_START_SHIFT 0 | |
6307 | #define _PCH_TRANS_VSYNC_A 0xe0014 | |
6308 | #define TRANS_VSYNC_END_SHIFT 16 | |
6309 | #define TRANS_VSYNC_START_SHIFT 0 | |
6310 | #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 | |
b9055052 | 6311 | |
e3b95f1e DV |
6312 | #define _PCH_TRANSA_DATA_M1 0xe0030 |
6313 | #define _PCH_TRANSA_DATA_N1 0xe0034 | |
6314 | #define _PCH_TRANSA_DATA_M2 0xe0038 | |
6315 | #define _PCH_TRANSA_DATA_N2 0xe003c | |
6316 | #define _PCH_TRANSA_LINK_M1 0xe0040 | |
6317 | #define _PCH_TRANSA_LINK_N1 0xe0044 | |
6318 | #define _PCH_TRANSA_LINK_M2 0xe0048 | |
6319 | #define _PCH_TRANSA_LINK_N2 0xe004c | |
9db4a9c7 | 6320 | |
2dcbc34d | 6321 | /* Per-transcoder DIP controls (PCH) */ |
b055c8f3 JB |
6322 | #define _VIDEO_DIP_CTL_A 0xe0200 |
6323 | #define _VIDEO_DIP_DATA_A 0xe0208 | |
6324 | #define _VIDEO_DIP_GCP_A 0xe0210 | |
6d67415f VS |
6325 | #define GCP_COLOR_INDICATION (1 << 2) |
6326 | #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) | |
6327 | #define GCP_AV_MUTE (1 << 0) | |
b055c8f3 JB |
6328 | |
6329 | #define _VIDEO_DIP_CTL_B 0xe1200 | |
6330 | #define _VIDEO_DIP_DATA_B 0xe1208 | |
6331 | #define _VIDEO_DIP_GCP_B 0xe1210 | |
6332 | ||
f0f59a00 VS |
6333 | #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) |
6334 | #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) | |
6335 | #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) | |
b055c8f3 | 6336 | |
2dcbc34d | 6337 | /* Per-transcoder DIP controls (VLV) */ |
086f8e84 VS |
6338 | #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) |
6339 | #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) | |
6340 | #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) | |
90b107c8 | 6341 | |
086f8e84 VS |
6342 | #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) |
6343 | #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) | |
6344 | #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) | |
90b107c8 | 6345 | |
086f8e84 VS |
6346 | #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) |
6347 | #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) | |
6348 | #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) | |
2dcbc34d | 6349 | |
90b107c8 | 6350 | #define VLV_TVIDEO_DIP_CTL(pipe) \ |
f0f59a00 | 6351 | _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ |
086f8e84 | 6352 | _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) |
90b107c8 | 6353 | #define VLV_TVIDEO_DIP_DATA(pipe) \ |
f0f59a00 | 6354 | _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ |
086f8e84 | 6355 | _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) |
90b107c8 | 6356 | #define VLV_TVIDEO_DIP_GCP(pipe) \ |
f0f59a00 | 6357 | _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ |
086f8e84 | 6358 | _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) |
90b107c8 | 6359 | |
8c5f5f7c | 6360 | /* Haswell DIP controls */ |
f0f59a00 | 6361 | |
086f8e84 VS |
6362 | #define _HSW_VIDEO_DIP_CTL_A 0x60200 |
6363 | #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 | |
6364 | #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 | |
6365 | #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 | |
6366 | #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 | |
6367 | #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 | |
6368 | #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 | |
6369 | #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 | |
6370 | #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 | |
6371 | #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 | |
6372 | #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 | |
6373 | #define _HSW_VIDEO_DIP_GCP_A 0x60210 | |
6374 | ||
6375 | #define _HSW_VIDEO_DIP_CTL_B 0x61200 | |
6376 | #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 | |
6377 | #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 | |
6378 | #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 | |
6379 | #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 | |
6380 | #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 | |
6381 | #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 | |
6382 | #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 | |
6383 | #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 | |
6384 | #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 | |
6385 | #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 | |
6386 | #define _HSW_VIDEO_DIP_GCP_B 0x61210 | |
8c5f5f7c | 6387 | |
f0f59a00 VS |
6388 | #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) |
6389 | #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) | |
6390 | #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) | |
6391 | #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) | |
6392 | #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) | |
6393 | #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) | |
6394 | ||
6395 | #define _HSW_STEREO_3D_CTL_A 0x70020 | |
6396 | #define S3D_ENABLE (1<<31) | |
6397 | #define _HSW_STEREO_3D_CTL_B 0x71020 | |
6398 | ||
6399 | #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) | |
3f51e471 | 6400 | |
275f01b2 DV |
6401 | #define _PCH_TRANS_HTOTAL_B 0xe1000 |
6402 | #define _PCH_TRANS_HBLANK_B 0xe1004 | |
6403 | #define _PCH_TRANS_HSYNC_B 0xe1008 | |
6404 | #define _PCH_TRANS_VTOTAL_B 0xe100c | |
6405 | #define _PCH_TRANS_VBLANK_B 0xe1010 | |
6406 | #define _PCH_TRANS_VSYNC_B 0xe1014 | |
f0f59a00 | 6407 | #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 |
275f01b2 | 6408 | |
f0f59a00 VS |
6409 | #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) |
6410 | #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) | |
6411 | #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) | |
6412 | #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) | |
6413 | #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) | |
6414 | #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) | |
6415 | #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) | |
9db4a9c7 | 6416 | |
e3b95f1e DV |
6417 | #define _PCH_TRANSB_DATA_M1 0xe1030 |
6418 | #define _PCH_TRANSB_DATA_N1 0xe1034 | |
6419 | #define _PCH_TRANSB_DATA_M2 0xe1038 | |
6420 | #define _PCH_TRANSB_DATA_N2 0xe103c | |
6421 | #define _PCH_TRANSB_LINK_M1 0xe1040 | |
6422 | #define _PCH_TRANSB_LINK_N1 0xe1044 | |
6423 | #define _PCH_TRANSB_LINK_M2 0xe1048 | |
6424 | #define _PCH_TRANSB_LINK_N2 0xe104c | |
6425 | ||
f0f59a00 VS |
6426 | #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) |
6427 | #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) | |
6428 | #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) | |
6429 | #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) | |
6430 | #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) | |
6431 | #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) | |
6432 | #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) | |
6433 | #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) | |
9db4a9c7 | 6434 | |
ab9412ba DV |
6435 | #define _PCH_TRANSACONF 0xf0008 |
6436 | #define _PCH_TRANSBCONF 0xf1008 | |
f0f59a00 VS |
6437 | #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) |
6438 | #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ | |
b9055052 ZW |
6439 | #define TRANS_DISABLE (0<<31) |
6440 | #define TRANS_ENABLE (1<<31) | |
6441 | #define TRANS_STATE_MASK (1<<30) | |
6442 | #define TRANS_STATE_DISABLE (0<<30) | |
6443 | #define TRANS_STATE_ENABLE (1<<30) | |
6444 | #define TRANS_FSYNC_DELAY_HB1 (0<<27) | |
6445 | #define TRANS_FSYNC_DELAY_HB2 (1<<27) | |
6446 | #define TRANS_FSYNC_DELAY_HB3 (2<<27) | |
6447 | #define TRANS_FSYNC_DELAY_HB4 (3<<27) | |
5f7f726d | 6448 | #define TRANS_INTERLACE_MASK (7<<21) |
b9055052 | 6449 | #define TRANS_PROGRESSIVE (0<<21) |
5f7f726d | 6450 | #define TRANS_INTERLACED (3<<21) |
7c26e5c6 | 6451 | #define TRANS_LEGACY_INTERLACED_ILK (2<<21) |
b9055052 ZW |
6452 | #define TRANS_8BPC (0<<5) |
6453 | #define TRANS_10BPC (1<<5) | |
6454 | #define TRANS_6BPC (2<<5) | |
6455 | #define TRANS_12BPC (3<<5) | |
6456 | ||
ce40141f DV |
6457 | #define _TRANSA_CHICKEN1 0xf0060 |
6458 | #define _TRANSB_CHICKEN1 0xf1060 | |
f0f59a00 | 6459 | #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) |
d1b1589c | 6460 | #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10) |
ce40141f | 6461 | #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) |
3bcf603f JB |
6462 | #define _TRANSA_CHICKEN2 0xf0064 |
6463 | #define _TRANSB_CHICKEN2 0xf1064 | |
f0f59a00 | 6464 | #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) |
dc4bd2d1 PZ |
6465 | #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) |
6466 | #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) | |
6467 | #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) | |
6468 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) | |
6469 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) | |
3bcf603f | 6470 | |
f0f59a00 | 6471 | #define SOUTH_CHICKEN1 _MMIO(0xc2000) |
291427f5 JB |
6472 | #define FDIA_PHASE_SYNC_SHIFT_OVR 19 |
6473 | #define FDIA_PHASE_SYNC_SHIFT_EN 18 | |
01a415fd DV |
6474 | #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) |
6475 | #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) | |
6476 | #define FDI_BC_BIFURCATION_SELECT (1 << 12) | |
aa17cdb4 | 6477 | #define SPT_PWM_GRANULARITY (1<<0) |
f0f59a00 | 6478 | #define SOUTH_CHICKEN2 _MMIO(0xc2004) |
dde86e2d PZ |
6479 | #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) |
6480 | #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) | |
aa17cdb4 | 6481 | #define LPT_PWM_GRANULARITY (1<<5) |
dde86e2d | 6482 | #define DPLS_EDP_PPS_FIX_DIS (1<<0) |
645c62a5 | 6483 | |
f0f59a00 VS |
6484 | #define _FDI_RXA_CHICKEN 0xc200c |
6485 | #define _FDI_RXB_CHICKEN 0xc2010 | |
6f06ce18 JB |
6486 | #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) |
6487 | #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) | |
f0f59a00 | 6488 | #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) |
b9055052 | 6489 | |
f0f59a00 | 6490 | #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) |
cd664078 | 6491 | #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) |
382b0936 | 6492 | #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) |
cd664078 | 6493 | #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) |
17a303ec | 6494 | #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) |
382b0936 | 6495 | |
b9055052 | 6496 | /* CPU: FDI_TX */ |
f0f59a00 VS |
6497 | #define _FDI_TXA_CTL 0x60100 |
6498 | #define _FDI_TXB_CTL 0x61100 | |
6499 | #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) | |
b9055052 ZW |
6500 | #define FDI_TX_DISABLE (0<<31) |
6501 | #define FDI_TX_ENABLE (1<<31) | |
6502 | #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) | |
6503 | #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) | |
6504 | #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) | |
6505 | #define FDI_LINK_TRAIN_NONE (3<<28) | |
6506 | #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) | |
6507 | #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) | |
6508 | #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) | |
6509 | #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) | |
6510 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) | |
6511 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) | |
6512 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) | |
6513 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) | |
8db9d77b ZW |
6514 | /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. |
6515 | SNB has different settings. */ | |
6516 | /* SNB A-stepping */ | |
6517 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) | |
6518 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) | |
6519 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) | |
6520 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) | |
6521 | /* SNB B-stepping */ | |
6522 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) | |
6523 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) | |
6524 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) | |
6525 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) | |
6526 | #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) | |
627eb5a3 DV |
6527 | #define FDI_DP_PORT_WIDTH_SHIFT 19 |
6528 | #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) | |
6529 | #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) | |
b9055052 | 6530 | #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) |
f2b115e6 | 6531 | /* Ironlake: hardwired to 1 */ |
b9055052 | 6532 | #define FDI_TX_PLL_ENABLE (1<<14) |
357555c0 JB |
6533 | |
6534 | /* Ivybridge has different bits for lolz */ | |
6535 | #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) | |
6536 | #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) | |
6537 | #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) | |
6538 | #define FDI_LINK_TRAIN_NONE_IVB (3<<8) | |
6539 | ||
b9055052 | 6540 | /* both Tx and Rx */ |
c4f9c4c2 | 6541 | #define FDI_COMPOSITE_SYNC (1<<11) |
357555c0 | 6542 | #define FDI_LINK_TRAIN_AUTO (1<<10) |
b9055052 ZW |
6543 | #define FDI_SCRAMBLING_ENABLE (0<<7) |
6544 | #define FDI_SCRAMBLING_DISABLE (1<<7) | |
6545 | ||
6546 | /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ | |
9db4a9c7 JB |
6547 | #define _FDI_RXA_CTL 0xf000c |
6548 | #define _FDI_RXB_CTL 0xf100c | |
f0f59a00 | 6549 | #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) |
b9055052 | 6550 | #define FDI_RX_ENABLE (1<<31) |
b9055052 | 6551 | /* train, dp width same as FDI_TX */ |
357555c0 JB |
6552 | #define FDI_FS_ERRC_ENABLE (1<<27) |
6553 | #define FDI_FE_ERRC_ENABLE (1<<26) | |
68d18ad7 | 6554 | #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) |
b9055052 ZW |
6555 | #define FDI_8BPC (0<<16) |
6556 | #define FDI_10BPC (1<<16) | |
6557 | #define FDI_6BPC (2<<16) | |
6558 | #define FDI_12BPC (3<<16) | |
3e68320e | 6559 | #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) |
b9055052 ZW |
6560 | #define FDI_DMI_LINK_REVERSE_MASK (1<<14) |
6561 | #define FDI_RX_PLL_ENABLE (1<<13) | |
6562 | #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) | |
6563 | #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) | |
6564 | #define FDI_FS_ERR_REPORT_ENABLE (1<<9) | |
6565 | #define FDI_FE_ERR_REPORT_ENABLE (1<<8) | |
6566 | #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) | |
5eddb70b | 6567 | #define FDI_PCDCLK (1<<4) |
8db9d77b ZW |
6568 | /* CPT */ |
6569 | #define FDI_AUTO_TRAINING (1<<10) | |
6570 | #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) | |
6571 | #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) | |
6572 | #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) | |
6573 | #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) | |
6574 | #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) | |
b9055052 | 6575 | |
04945641 PZ |
6576 | #define _FDI_RXA_MISC 0xf0010 |
6577 | #define _FDI_RXB_MISC 0xf1010 | |
6578 | #define FDI_RX_PWRDN_LANE1_MASK (3<<26) | |
6579 | #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) | |
6580 | #define FDI_RX_PWRDN_LANE0_MASK (3<<24) | |
6581 | #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) | |
6582 | #define FDI_RX_TP1_TO_TP2_48 (2<<20) | |
6583 | #define FDI_RX_TP1_TO_TP2_64 (3<<20) | |
6584 | #define FDI_RX_FDI_DELAY_90 (0x90<<0) | |
f0f59a00 | 6585 | #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) |
04945641 | 6586 | |
f0f59a00 VS |
6587 | #define _FDI_RXA_TUSIZE1 0xf0030 |
6588 | #define _FDI_RXA_TUSIZE2 0xf0038 | |
6589 | #define _FDI_RXB_TUSIZE1 0xf1030 | |
6590 | #define _FDI_RXB_TUSIZE2 0xf1038 | |
6591 | #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) | |
6592 | #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) | |
b9055052 ZW |
6593 | |
6594 | /* FDI_RX interrupt register format */ | |
6595 | #define FDI_RX_INTER_LANE_ALIGN (1<<10) | |
6596 | #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ | |
6597 | #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ | |
6598 | #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) | |
6599 | #define FDI_RX_FS_CODE_ERR (1<<6) | |
6600 | #define FDI_RX_FE_CODE_ERR (1<<5) | |
6601 | #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) | |
6602 | #define FDI_RX_HDCP_LINK_FAIL (1<<3) | |
6603 | #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) | |
6604 | #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) | |
6605 | #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) | |
6606 | ||
f0f59a00 VS |
6607 | #define _FDI_RXA_IIR 0xf0014 |
6608 | #define _FDI_RXA_IMR 0xf0018 | |
6609 | #define _FDI_RXB_IIR 0xf1014 | |
6610 | #define _FDI_RXB_IMR 0xf1018 | |
6611 | #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) | |
6612 | #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) | |
b9055052 | 6613 | |
f0f59a00 VS |
6614 | #define FDI_PLL_CTL_1 _MMIO(0xfe000) |
6615 | #define FDI_PLL_CTL_2 _MMIO(0xfe004) | |
b9055052 | 6616 | |
f0f59a00 | 6617 | #define PCH_LVDS _MMIO(0xe1180) |
b9055052 ZW |
6618 | #define LVDS_DETECTED (1 << 1) |
6619 | ||
98364379 | 6620 | /* vlv has 2 sets of panel control regs. */ |
f0f59a00 VS |
6621 | #define _PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) |
6622 | #define _PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) | |
6623 | #define _PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) | |
ad933b56 | 6624 | #define PANEL_PORT_SELECT_VLV(port) ((port) << 30) |
f0f59a00 VS |
6625 | #define _PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) |
6626 | #define _PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) | |
6627 | ||
6628 | #define _PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) | |
6629 | #define _PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) | |
6630 | #define _PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) | |
6631 | #define _PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) | |
6632 | #define _PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) | |
6633 | ||
6634 | #define VLV_PIPE_PP_STATUS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_STATUS, _PIPEB_PP_STATUS) | |
6635 | #define VLV_PIPE_PP_CONTROL(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_CONTROL, _PIPEB_PP_CONTROL) | |
6636 | #define VLV_PIPE_PP_ON_DELAYS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_ON_DELAYS, _PIPEB_PP_ON_DELAYS) | |
6637 | #define VLV_PIPE_PP_OFF_DELAYS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_OFF_DELAYS, _PIPEB_PP_OFF_DELAYS) | |
6638 | #define VLV_PIPE_PP_DIVISOR(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_DIVISOR, _PIPEB_PP_DIVISOR) | |
6639 | ||
6640 | #define _PCH_PP_STATUS 0xc7200 | |
6641 | #define _PCH_PP_CONTROL 0xc7204 | |
4a655f04 | 6642 | #define PANEL_UNLOCK_REGS (0xabcd << 16) |
1c0ae80a | 6643 | #define PANEL_UNLOCK_MASK (0xffff << 16) |
b0a08bec VK |
6644 | #define BXT_POWER_CYCLE_DELAY_MASK (0x1f0) |
6645 | #define BXT_POWER_CYCLE_DELAY_SHIFT 4 | |
b9055052 ZW |
6646 | #define EDP_FORCE_VDD (1 << 3) |
6647 | #define EDP_BLC_ENABLE (1 << 2) | |
6648 | #define PANEL_POWER_RESET (1 << 1) | |
6649 | #define PANEL_POWER_OFF (0 << 0) | |
6650 | #define PANEL_POWER_ON (1 << 0) | |
f0f59a00 | 6651 | #define _PCH_PP_ON_DELAYS 0xc7208 |
f01eca2e KP |
6652 | #define PANEL_PORT_SELECT_MASK (3 << 30) |
6653 | #define PANEL_PORT_SELECT_LVDS (0 << 30) | |
6654 | #define PANEL_PORT_SELECT_DPA (1 << 30) | |
f01eca2e KP |
6655 | #define PANEL_PORT_SELECT_DPC (2 << 30) |
6656 | #define PANEL_PORT_SELECT_DPD (3 << 30) | |
6657 | #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) | |
6658 | #define PANEL_POWER_UP_DELAY_SHIFT 16 | |
6659 | #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) | |
6660 | #define PANEL_LIGHT_ON_DELAY_SHIFT 0 | |
6661 | ||
f0f59a00 | 6662 | #define _PCH_PP_OFF_DELAYS 0xc720c |
f01eca2e KP |
6663 | #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) |
6664 | #define PANEL_POWER_DOWN_DELAY_SHIFT 16 | |
6665 | #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) | |
6666 | #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 | |
6667 | ||
f0f59a00 | 6668 | #define _PCH_PP_DIVISOR 0xc7210 |
f01eca2e KP |
6669 | #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) |
6670 | #define PP_REFERENCE_DIVIDER_SHIFT 8 | |
6671 | #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) | |
6672 | #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 | |
b9055052 | 6673 | |
f0f59a00 VS |
6674 | #define PCH_PP_STATUS _MMIO(_PCH_PP_STATUS) |
6675 | #define PCH_PP_CONTROL _MMIO(_PCH_PP_CONTROL) | |
6676 | #define PCH_PP_ON_DELAYS _MMIO(_PCH_PP_ON_DELAYS) | |
6677 | #define PCH_PP_OFF_DELAYS _MMIO(_PCH_PP_OFF_DELAYS) | |
6678 | #define PCH_PP_DIVISOR _MMIO(_PCH_PP_DIVISOR) | |
6679 | ||
b0a08bec VK |
6680 | /* BXT PPS changes - 2nd set of PPS registers */ |
6681 | #define _BXT_PP_STATUS2 0xc7300 | |
6682 | #define _BXT_PP_CONTROL2 0xc7304 | |
6683 | #define _BXT_PP_ON_DELAYS2 0xc7308 | |
6684 | #define _BXT_PP_OFF_DELAYS2 0xc730c | |
6685 | ||
f0f59a00 VS |
6686 | #define BXT_PP_STATUS(n) _MMIO_PIPE(n, _PCH_PP_STATUS, _BXT_PP_STATUS2) |
6687 | #define BXT_PP_CONTROL(n) _MMIO_PIPE(n, _PCH_PP_CONTROL, _BXT_PP_CONTROL2) | |
6688 | #define BXT_PP_ON_DELAYS(n) _MMIO_PIPE(n, _PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2) | |
6689 | #define BXT_PP_OFF_DELAYS(n) _MMIO_PIPE(n, _PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2) | |
b0a08bec | 6690 | |
f0f59a00 VS |
6691 | #define _PCH_DP_B 0xe4100 |
6692 | #define PCH_DP_B _MMIO(_PCH_DP_B) | |
750a951f VS |
6693 | #define _PCH_DPB_AUX_CH_CTL 0xe4110 |
6694 | #define _PCH_DPB_AUX_CH_DATA1 0xe4114 | |
6695 | #define _PCH_DPB_AUX_CH_DATA2 0xe4118 | |
6696 | #define _PCH_DPB_AUX_CH_DATA3 0xe411c | |
6697 | #define _PCH_DPB_AUX_CH_DATA4 0xe4120 | |
6698 | #define _PCH_DPB_AUX_CH_DATA5 0xe4124 | |
5eb08b69 | 6699 | |
f0f59a00 VS |
6700 | #define _PCH_DP_C 0xe4200 |
6701 | #define PCH_DP_C _MMIO(_PCH_DP_C) | |
750a951f VS |
6702 | #define _PCH_DPC_AUX_CH_CTL 0xe4210 |
6703 | #define _PCH_DPC_AUX_CH_DATA1 0xe4214 | |
6704 | #define _PCH_DPC_AUX_CH_DATA2 0xe4218 | |
6705 | #define _PCH_DPC_AUX_CH_DATA3 0xe421c | |
6706 | #define _PCH_DPC_AUX_CH_DATA4 0xe4220 | |
6707 | #define _PCH_DPC_AUX_CH_DATA5 0xe4224 | |
5eb08b69 | 6708 | |
f0f59a00 VS |
6709 | #define _PCH_DP_D 0xe4300 |
6710 | #define PCH_DP_D _MMIO(_PCH_DP_D) | |
750a951f VS |
6711 | #define _PCH_DPD_AUX_CH_CTL 0xe4310 |
6712 | #define _PCH_DPD_AUX_CH_DATA1 0xe4314 | |
6713 | #define _PCH_DPD_AUX_CH_DATA2 0xe4318 | |
6714 | #define _PCH_DPD_AUX_CH_DATA3 0xe431c | |
6715 | #define _PCH_DPD_AUX_CH_DATA4 0xe4320 | |
6716 | #define _PCH_DPD_AUX_CH_DATA5 0xe4324 | |
6717 | ||
f0f59a00 VS |
6718 | #define PCH_DP_AUX_CH_CTL(port) _MMIO_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) |
6719 | #define PCH_DP_AUX_CH_DATA(port, i) _MMIO(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ | |
5eb08b69 | 6720 | |
8db9d77b ZW |
6721 | /* CPT */ |
6722 | #define PORT_TRANS_A_SEL_CPT 0 | |
6723 | #define PORT_TRANS_B_SEL_CPT (1<<29) | |
6724 | #define PORT_TRANS_C_SEL_CPT (2<<29) | |
6725 | #define PORT_TRANS_SEL_MASK (3<<29) | |
1519b995 | 6726 | #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) |
19d8fe15 DV |
6727 | #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) |
6728 | #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) | |
71485e0a VS |
6729 | #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) |
6730 | #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) | |
8db9d77b | 6731 | |
086f8e84 VS |
6732 | #define _TRANS_DP_CTL_A 0xe0300 |
6733 | #define _TRANS_DP_CTL_B 0xe1300 | |
6734 | #define _TRANS_DP_CTL_C 0xe2300 | |
f0f59a00 | 6735 | #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) |
8db9d77b ZW |
6736 | #define TRANS_DP_OUTPUT_ENABLE (1<<31) |
6737 | #define TRANS_DP_PORT_SEL_B (0<<29) | |
6738 | #define TRANS_DP_PORT_SEL_C (1<<29) | |
6739 | #define TRANS_DP_PORT_SEL_D (2<<29) | |
cb3543c6 | 6740 | #define TRANS_DP_PORT_SEL_NONE (3<<29) |
8db9d77b | 6741 | #define TRANS_DP_PORT_SEL_MASK (3<<29) |
adc289d7 | 6742 | #define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B) |
8db9d77b ZW |
6743 | #define TRANS_DP_AUDIO_ONLY (1<<26) |
6744 | #define TRANS_DP_ENH_FRAMING (1<<18) | |
6745 | #define TRANS_DP_8BPC (0<<9) | |
6746 | #define TRANS_DP_10BPC (1<<9) | |
6747 | #define TRANS_DP_6BPC (2<<9) | |
6748 | #define TRANS_DP_12BPC (3<<9) | |
220cad3c | 6749 | #define TRANS_DP_BPC_MASK (3<<9) |
8db9d77b ZW |
6750 | #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) |
6751 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 | |
6752 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) | |
6753 | #define TRANS_DP_HSYNC_ACTIVE_LOW 0 | |
94113cec | 6754 | #define TRANS_DP_SYNC_MASK (3<<3) |
8db9d77b ZW |
6755 | |
6756 | /* SNB eDP training params */ | |
6757 | /* SNB A-stepping */ | |
6758 | #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) | |
6759 | #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) | |
6760 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) | |
6761 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) | |
6762 | /* SNB B-stepping */ | |
3c5a62b5 YL |
6763 | #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) |
6764 | #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) | |
6765 | #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) | |
6766 | #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) | |
6767 | #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) | |
8db9d77b ZW |
6768 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) |
6769 | ||
1a2eb460 KP |
6770 | /* IVB */ |
6771 | #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) | |
6772 | #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) | |
6773 | #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) | |
6774 | #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) | |
6775 | #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) | |
6776 | #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) | |
77fa4cbd | 6777 | #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) |
1a2eb460 KP |
6778 | |
6779 | /* legacy values */ | |
6780 | #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) | |
6781 | #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) | |
6782 | #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) | |
6783 | #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) | |
6784 | #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) | |
6785 | ||
6786 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) | |
6787 | ||
f0f59a00 | 6788 | #define VLV_PMWGICZ _MMIO(0x1300a4) |
9e72b46c | 6789 | |
274008e8 SAK |
6790 | #define RC6_LOCATION _MMIO(0xD40) |
6791 | #define RC6_CTX_IN_DRAM (1 << 0) | |
6792 | #define RC6_CTX_BASE _MMIO(0xD48) | |
6793 | #define RC6_CTX_BASE_MASK 0xFFFFFFF0 | |
6794 | #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) | |
6795 | #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) | |
6796 | #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) | |
6797 | #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) | |
6798 | #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) | |
6799 | #define IDLE_TIME_MASK 0xFFFFF | |
f0f59a00 VS |
6800 | #define FORCEWAKE _MMIO(0xA18C) |
6801 | #define FORCEWAKE_VLV _MMIO(0x1300b0) | |
6802 | #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) | |
6803 | #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) | |
6804 | #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) | |
6805 | #define FORCEWAKE_ACK_HSW _MMIO(0x130044) | |
6806 | #define FORCEWAKE_ACK _MMIO(0x130090) | |
6807 | #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) | |
981a5aea ID |
6808 | #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) |
6809 | #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) | |
6810 | #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) | |
6811 | ||
f0f59a00 | 6812 | #define VLV_GTLC_PW_STATUS _MMIO(0x130094) |
981a5aea ID |
6813 | #define VLV_GTLC_ALLOWWAKEACK (1 << 0) |
6814 | #define VLV_GTLC_ALLOWWAKEERR (1 << 1) | |
6815 | #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) | |
6816 | #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) | |
f0f59a00 VS |
6817 | #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ |
6818 | #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) | |
6819 | #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) | |
6820 | #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) | |
6821 | #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) | |
6822 | #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) | |
6823 | #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) | |
c5836c27 CW |
6824 | #define FORCEWAKE_KERNEL 0x1 |
6825 | #define FORCEWAKE_USER 0x2 | |
f0f59a00 VS |
6826 | #define FORCEWAKE_MT_ACK _MMIO(0x130040) |
6827 | #define ECOBUS _MMIO(0xa180) | |
8d715f00 | 6828 | #define FORCEWAKE_MT_ENABLE (1<<5) |
f0f59a00 | 6829 | #define VLV_SPAREG2H _MMIO(0xA194) |
8fd26859 | 6830 | |
f0f59a00 | 6831 | #define GTFIFODBG _MMIO(0x120000) |
90f256b5 VS |
6832 | #define GT_FIFO_SBDROPERR (1<<6) |
6833 | #define GT_FIFO_BLOBDROPERR (1<<5) | |
6834 | #define GT_FIFO_SB_READ_ABORTERR (1<<4) | |
6835 | #define GT_FIFO_DROPERR (1<<3) | |
dd202c6d BW |
6836 | #define GT_FIFO_OVFERR (1<<2) |
6837 | #define GT_FIFO_IAWRERR (1<<1) | |
6838 | #define GT_FIFO_IARDERR (1<<0) | |
6839 | ||
f0f59a00 | 6840 | #define GTFIFOCTL _MMIO(0x120008) |
46520e2b | 6841 | #define GT_FIFO_FREE_ENTRIES_MASK 0x7f |
95736720 | 6842 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
a04f90a3 D |
6843 | #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) |
6844 | #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) | |
91355834 | 6845 | |
f0f59a00 | 6846 | #define HSW_IDICR _MMIO(0x9008) |
05e21cc4 | 6847 | #define IDIHASHMSK(x) (((x) & 0x3f) << 16) |
f0f59a00 | 6848 | #define HSW_EDRAM_PRESENT _MMIO(0x120010) |
2db59d53 | 6849 | #define EDRAM_ENABLED 0x1 |
05e21cc4 | 6850 | |
f0f59a00 | 6851 | #define GEN6_UCGCTL1 _MMIO(0x9400) |
e4443e45 | 6852 | # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) |
80e829fa | 6853 | # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
de4a8bd1 | 6854 | # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
80e829fa | 6855 | |
f0f59a00 | 6856 | #define GEN6_UCGCTL2 _MMIO(0x9404) |
f9fc42f4 | 6857 | # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) |
0f846f81 | 6858 | # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) |
6edaa7fc | 6859 | # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) |
eae66b50 | 6860 | # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) |
406478dc | 6861 | # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) |
9ca1d10d | 6862 | # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) |
406478dc | 6863 | |
f0f59a00 | 6864 | #define GEN6_UCGCTL3 _MMIO(0x9408) |
9e72b46c | 6865 | |
f0f59a00 | 6866 | #define GEN7_UCGCTL4 _MMIO(0x940c) |
e3f33d46 JB |
6867 | #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) |
6868 | ||
f0f59a00 VS |
6869 | #define GEN6_RCGCTL1 _MMIO(0x9410) |
6870 | #define GEN6_RCGCTL2 _MMIO(0x9414) | |
6871 | #define GEN6_RSTCTL _MMIO(0x9420) | |
9e72b46c | 6872 | |
f0f59a00 | 6873 | #define GEN8_UCGCTL6 _MMIO(0x9430) |
9253c2e5 | 6874 | #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24) |
4f1ca9e9 | 6875 | #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) |
868434c5 | 6876 | #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28) |
4f1ca9e9 | 6877 | |
f0f59a00 VS |
6878 | #define GEN6_GFXPAUSE _MMIO(0xA000) |
6879 | #define GEN6_RPNSWREQ _MMIO(0xA008) | |
8fd26859 CW |
6880 | #define GEN6_TURBO_DISABLE (1<<31) |
6881 | #define GEN6_FREQUENCY(x) ((x)<<25) | |
92bd1bf0 | 6882 | #define HSW_FREQUENCY(x) ((x)<<24) |
de43ae9d | 6883 | #define GEN9_FREQUENCY(x) ((x)<<23) |
8fd26859 CW |
6884 | #define GEN6_OFFSET(x) ((x)<<19) |
6885 | #define GEN6_AGGRESSIVE_TURBO (0<<15) | |
f0f59a00 VS |
6886 | #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) |
6887 | #define GEN6_RC_CONTROL _MMIO(0xA090) | |
8fd26859 CW |
6888 | #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) |
6889 | #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) | |
6890 | #define GEN6_RC_CTL_RC6_ENABLE (1<<18) | |
6891 | #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) | |
6892 | #define GEN6_RC_CTL_RC7_ENABLE (1<<22) | |
6b88f295 | 6893 | #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) |
0a073b84 | 6894 | #define GEN7_RC_CTL_TO_MODE (1<<28) |
8fd26859 CW |
6895 | #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) |
6896 | #define GEN6_RC_CTL_HW_ENABLE (1<<31) | |
f0f59a00 VS |
6897 | #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010) |
6898 | #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014) | |
6899 | #define GEN6_RPSTAT1 _MMIO(0xA01C) | |
ccab5c82 | 6900 | #define GEN6_CAGF_SHIFT 8 |
f82855d3 | 6901 | #define HSW_CAGF_SHIFT 7 |
de43ae9d | 6902 | #define GEN9_CAGF_SHIFT 23 |
ccab5c82 | 6903 | #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) |
f82855d3 | 6904 | #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) |
de43ae9d | 6905 | #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT) |
f0f59a00 | 6906 | #define GEN6_RP_CONTROL _MMIO(0xA024) |
8fd26859 | 6907 | #define GEN6_RP_MEDIA_TURBO (1<<11) |
6ed55ee7 BW |
6908 | #define GEN6_RP_MEDIA_MODE_MASK (3<<9) |
6909 | #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) | |
6910 | #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) | |
6911 | #define GEN6_RP_MEDIA_HW_MODE (1<<9) | |
6912 | #define GEN6_RP_MEDIA_SW_MODE (0<<9) | |
8fd26859 CW |
6913 | #define GEN6_RP_MEDIA_IS_GFX (1<<8) |
6914 | #define GEN6_RP_ENABLE (1<<7) | |
ccab5c82 JB |
6915 | #define GEN6_RP_UP_IDLE_MIN (0x1<<3) |
6916 | #define GEN6_RP_UP_BUSY_AVG (0x2<<3) | |
6917 | #define GEN6_RP_UP_BUSY_CONT (0x4<<3) | |
dd75fdc8 | 6918 | #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) |
ccab5c82 | 6919 | #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) |
f0f59a00 VS |
6920 | #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C) |
6921 | #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030) | |
6922 | #define GEN6_RP_CUR_UP_EI _MMIO(0xA050) | |
ccab5c82 | 6923 | #define GEN6_CURICONT_MASK 0xffffff |
f0f59a00 | 6924 | #define GEN6_RP_CUR_UP _MMIO(0xA054) |
ccab5c82 | 6925 | #define GEN6_CURBSYTAVG_MASK 0xffffff |
f0f59a00 VS |
6926 | #define GEN6_RP_PREV_UP _MMIO(0xA058) |
6927 | #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C) | |
ccab5c82 | 6928 | #define GEN6_CURIAVG_MASK 0xffffff |
f0f59a00 VS |
6929 | #define GEN6_RP_CUR_DOWN _MMIO(0xA060) |
6930 | #define GEN6_RP_PREV_DOWN _MMIO(0xA064) | |
6931 | #define GEN6_RP_UP_EI _MMIO(0xA068) | |
6932 | #define GEN6_RP_DOWN_EI _MMIO(0xA06C) | |
6933 | #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) | |
6934 | #define GEN6_RPDEUHWTC _MMIO(0xA080) | |
6935 | #define GEN6_RPDEUC _MMIO(0xA084) | |
6936 | #define GEN6_RPDEUCSW _MMIO(0xA088) | |
6937 | #define GEN6_RC_STATE _MMIO(0xA094) | |
274008e8 | 6938 | #define RC6_STATE (1 << 18) |
f0f59a00 VS |
6939 | #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) |
6940 | #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) | |
6941 | #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) | |
6942 | #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) | |
6943 | #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) | |
6944 | #define GEN6_RC_SLEEP _MMIO(0xA0B0) | |
6945 | #define GEN6_RCUBMABDTMR _MMIO(0xA0B0) | |
6946 | #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4) | |
6947 | #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8) | |
6948 | #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC) | |
6949 | #define VLV_RCEDATA _MMIO(0xA0BC) | |
6950 | #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0) | |
6951 | #define GEN6_PMINTRMSK _MMIO(0xA168) | |
baccd458 | 6952 | #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) |
f0f59a00 VS |
6953 | #define VLV_PWRDWNUPCTL _MMIO(0xA294) |
6954 | #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4) | |
6955 | #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8) | |
6956 | #define GEN9_PG_ENABLE _MMIO(0xA210) | |
a4104c55 SK |
6957 | #define GEN9_RENDER_PG_ENABLE (1<<0) |
6958 | #define GEN9_MEDIA_PG_ENABLE (1<<1) | |
8fd26859 | 6959 | |
f0f59a00 | 6960 | #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) |
a9da9bce GS |
6961 | #define PIXEL_OVERLAP_CNT_MASK (3 << 30) |
6962 | #define PIXEL_OVERLAP_CNT_SHIFT 30 | |
6963 | ||
f0f59a00 VS |
6964 | #define GEN6_PMISR _MMIO(0x44020) |
6965 | #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ | |
6966 | #define GEN6_PMIIR _MMIO(0x44028) | |
6967 | #define GEN6_PMIER _MMIO(0x4402C) | |
8fd26859 CW |
6968 | #define GEN6_PM_MBOX_EVENT (1<<25) |
6969 | #define GEN6_PM_THERMAL_EVENT (1<<24) | |
6970 | #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) | |
6971 | #define GEN6_PM_RP_UP_THRESHOLD (1<<5) | |
6972 | #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) | |
6973 | #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) | |
6974 | #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) | |
4848405c | 6975 | #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ |
4912d041 BW |
6976 | GEN6_PM_RP_DOWN_THRESHOLD | \ |
6977 | GEN6_PM_RP_DOWN_TIMEOUT) | |
8fd26859 | 6978 | |
f0f59a00 | 6979 | #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4) |
9e72b46c ID |
6980 | #define GEN7_GT_SCRATCH_REG_NUM 8 |
6981 | ||
f0f59a00 | 6982 | #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) |
76c3552f D |
6983 | #define VLV_GFX_CLK_STATUS_BIT (1<<3) |
6984 | #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) | |
6985 | ||
f0f59a00 VS |
6986 | #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) |
6987 | #define VLV_COUNTER_CONTROL _MMIO(0x138104) | |
49798eb2 | 6988 | #define VLV_COUNT_RANGE_HIGH (1<<15) |
31685c25 D |
6989 | #define VLV_MEDIA_RC0_COUNT_EN (1<<5) |
6990 | #define VLV_RENDER_RC0_COUNT_EN (1<<4) | |
49798eb2 JB |
6991 | #define VLV_MEDIA_RC6_COUNT_EN (1<<1) |
6992 | #define VLV_RENDER_RC6_COUNT_EN (1<<0) | |
f0f59a00 VS |
6993 | #define GEN6_GT_GFX_RC6 _MMIO(0x138108) |
6994 | #define VLV_GT_RENDER_RC6 _MMIO(0x138108) | |
6995 | #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C) | |
9cc19be5 | 6996 | |
f0f59a00 VS |
6997 | #define GEN6_GT_GFX_RC6p _MMIO(0x13810C) |
6998 | #define GEN6_GT_GFX_RC6pp _MMIO(0x138110) | |
6999 | #define VLV_RENDER_C0_COUNT _MMIO(0x138118) | |
7000 | #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) | |
cce66a28 | 7001 | |
f0f59a00 | 7002 | #define GEN6_PCODE_MAILBOX _MMIO(0x138124) |
8fd26859 | 7003 | #define GEN6_PCODE_READY (1<<31) |
31643d54 BW |
7004 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
7005 | #define GEN6_PCODE_READ_RC6VIDS 0x5 | |
9043ae02 DL |
7006 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
7007 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) | |
b432e5cf | 7008 | #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 |
57520bc5 DL |
7009 | #define GEN9_PCODE_READ_MEM_LATENCY 0x6 |
7010 | #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF | |
7011 | #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 | |
7012 | #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 | |
7013 | #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 | |
5d96d8af DL |
7014 | #define SKL_PCODE_CDCLK_CONTROL 0x7 |
7015 | #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 | |
7016 | #define SKL_CDCLK_READY_FOR_CHANGE 0x1 | |
9043ae02 DL |
7017 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
7018 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 | |
7019 | #define GEN6_READ_OC_PARAMS 0xc | |
515b2392 PZ |
7020 | #define GEN6_PCODE_READ_D_COMP 0x10 |
7021 | #define GEN6_PCODE_WRITE_D_COMP 0x11 | |
f8437dd1 | 7022 | #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 |
2a114cc1 | 7023 | #define DISPLAY_IPS_CONTROL 0x19 |
93ee2920 | 7024 | #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A |
f0f59a00 | 7025 | #define GEN6_PCODE_DATA _MMIO(0x138128) |
23b2f8bb | 7026 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
3ebecd07 | 7027 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
f0f59a00 | 7028 | #define GEN6_PCODE_DATA1 _MMIO(0x13812C) |
8fd26859 | 7029 | |
f0f59a00 | 7030 | #define GEN6_GT_CORE_STATUS _MMIO(0x138060) |
4d85529d BW |
7031 | #define GEN6_CORE_CPD_STATE_MASK (7<<4) |
7032 | #define GEN6_RCn_MASK 7 | |
7033 | #define GEN6_RC0 0 | |
7034 | #define GEN6_RC3 2 | |
7035 | #define GEN6_RC6 3 | |
7036 | #define GEN6_RC7 4 | |
7037 | ||
f0f59a00 | 7038 | #define GEN8_GT_SLICE_INFO _MMIO(0x138064) |
91bedd34 ŁD |
7039 | #define GEN8_LSLICESTAT_MASK 0x7 |
7040 | ||
f0f59a00 VS |
7041 | #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) |
7042 | #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) | |
5575f03a JM |
7043 | #define CHV_SS_PG_ENABLE (1<<1) |
7044 | #define CHV_EU08_PG_ENABLE (1<<9) | |
7045 | #define CHV_EU19_PG_ENABLE (1<<17) | |
7046 | #define CHV_EU210_PG_ENABLE (1<<25) | |
7047 | ||
f0f59a00 VS |
7048 | #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) |
7049 | #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) | |
5575f03a JM |
7050 | #define CHV_EU311_PG_ENABLE (1<<1) |
7051 | ||
f0f59a00 | 7052 | #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4) |
7f992aba | 7053 | #define GEN9_PGCTL_SLICE_ACK (1 << 0) |
1c046bc1 | 7054 | #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2)) |
7f992aba | 7055 | |
f0f59a00 VS |
7056 | #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8) |
7057 | #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8) | |
7f992aba JM |
7058 | #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) |
7059 | #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) | |
7060 | #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) | |
7061 | #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) | |
7062 | #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) | |
7063 | #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) | |
7064 | #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) | |
7065 | #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) | |
7066 | ||
f0f59a00 | 7067 | #define GEN7_MISCCPCTL _MMIO(0x9424) |
33a732f4 AD |
7068 | #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) |
7069 | #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2) | |
7070 | #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4) | |
5b88abac | 7071 | #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6) |
e3689190 | 7072 | |
f0f59a00 | 7073 | #define GEN8_GARBCNTL _MMIO(0xB004) |
245d9667 AS |
7074 | #define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7) |
7075 | ||
e3689190 | 7076 | /* IVYBRIDGE DPF */ |
f0f59a00 | 7077 | #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ |
e3689190 BW |
7078 | #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) |
7079 | #define GEN7_PARITY_ERROR_VALID (1<<13) | |
7080 | #define GEN7_L3CDERRST1_BANK_MASK (3<<11) | |
7081 | #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) | |
7082 | #define GEN7_PARITY_ERROR_ROW(reg) \ | |
7083 | ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) | |
7084 | #define GEN7_PARITY_ERROR_BANK(reg) \ | |
7085 | ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) | |
7086 | #define GEN7_PARITY_ERROR_SUBBANK(reg) \ | |
7087 | ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) | |
7088 | #define GEN7_L3CDERRST1_ENABLE (1<<7) | |
7089 | ||
f0f59a00 | 7090 | #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4) |
b9524a1e BW |
7091 | #define GEN7_L3LOG_SIZE 0x80 |
7092 | ||
f0f59a00 VS |
7093 | #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ |
7094 | #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100) | |
12f3382b | 7095 | #define GEN7_MAX_PS_THREAD_DEP (8<<12) |
4c2e7a5f | 7096 | #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) |
983b4b9d | 7097 | #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) |
12f3382b JB |
7098 | #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) |
7099 | ||
f0f59a00 | 7100 | #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188) |
3ca5da43 | 7101 | #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) |
e2db7071 | 7102 | #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3) |
3ca5da43 | 7103 | |
f0f59a00 | 7104 | #define GEN8_ROW_CHICKEN _MMIO(0xe4f0) |
c8966e10 | 7105 | #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) |
1411e6a5 | 7106 | #define STALL_DOP_GATING_DISABLE (1<<5) |
c8966e10 | 7107 | |
f0f59a00 VS |
7108 | #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) |
7109 | #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) | |
8ab43976 JB |
7110 | #define DOP_CLOCK_GATING_DISABLE (1<<0) |
7111 | ||
f0f59a00 | 7112 | #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) |
f3fc4884 FJ |
7113 | #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) |
7114 | ||
f0f59a00 | 7115 | #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) |
6b6d5626 RB |
7116 | #define GEN8_ST_PO_DISABLE (1<<13) |
7117 | ||
f0f59a00 | 7118 | #define HALF_SLICE_CHICKEN3 _MMIO(0xe184) |
94411593 | 7119 | #define HSW_SAMPLE_C_PERFORMANCE (1<<9) |
fd392b60 | 7120 | #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) |
8424171e | 7121 | #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5) |
bf66347c | 7122 | #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) |
fd392b60 | 7123 | |
f0f59a00 | 7124 | #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) |
cac23df4 NH |
7125 | #define GEN9_ENABLE_YV12_BUGFIX (1<<4) |
7126 | ||
c46f111f | 7127 | /* Audio */ |
f0f59a00 | 7128 | #define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020) |
c46f111f JN |
7129 | #define INTEL_AUDIO_DEVCL 0x808629FB |
7130 | #define INTEL_AUDIO_DEVBLC 0x80862801 | |
7131 | #define INTEL_AUDIO_DEVCTG 0x80862802 | |
e0dac65e | 7132 | |
f0f59a00 | 7133 | #define G4X_AUD_CNTL_ST _MMIO(0x620B4) |
c46f111f JN |
7134 | #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) |
7135 | #define G4X_ELDV_DEVCTG (1 << 14) | |
7136 | #define G4X_ELD_ADDR_MASK (0xf << 5) | |
7137 | #define G4X_ELD_ACK (1 << 4) | |
f0f59a00 | 7138 | #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) |
e0dac65e | 7139 | |
c46f111f JN |
7140 | #define _IBX_HDMIW_HDMIEDID_A 0xE2050 |
7141 | #define _IBX_HDMIW_HDMIEDID_B 0xE2150 | |
f0f59a00 VS |
7142 | #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ |
7143 | _IBX_HDMIW_HDMIEDID_B) | |
c46f111f JN |
7144 | #define _IBX_AUD_CNTL_ST_A 0xE20B4 |
7145 | #define _IBX_AUD_CNTL_ST_B 0xE21B4 | |
f0f59a00 VS |
7146 | #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ |
7147 | _IBX_AUD_CNTL_ST_B) | |
c46f111f JN |
7148 | #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) |
7149 | #define IBX_ELD_ADDRESS_MASK (0x1f << 5) | |
7150 | #define IBX_ELD_ACK (1 << 4) | |
f0f59a00 | 7151 | #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) |
82910ac6 JN |
7152 | #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) |
7153 | #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) | |
1202b4c6 | 7154 | |
c46f111f JN |
7155 | #define _CPT_HDMIW_HDMIEDID_A 0xE5050 |
7156 | #define _CPT_HDMIW_HDMIEDID_B 0xE5150 | |
f0f59a00 | 7157 | #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) |
c46f111f JN |
7158 | #define _CPT_AUD_CNTL_ST_A 0xE50B4 |
7159 | #define _CPT_AUD_CNTL_ST_B 0xE51B4 | |
f0f59a00 VS |
7160 | #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) |
7161 | #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) | |
e0dac65e | 7162 | |
c46f111f JN |
7163 | #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) |
7164 | #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) | |
f0f59a00 | 7165 | #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) |
c46f111f JN |
7166 | #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) |
7167 | #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) | |
f0f59a00 VS |
7168 | #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) |
7169 | #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) | |
9ca2fe73 | 7170 | |
ae662d31 EA |
7171 | /* These are the 4 32-bit write offset registers for each stream |
7172 | * output buffer. It determines the offset from the | |
7173 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. | |
7174 | */ | |
f0f59a00 | 7175 | #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) |
ae662d31 | 7176 | |
c46f111f JN |
7177 | #define _IBX_AUD_CONFIG_A 0xe2000 |
7178 | #define _IBX_AUD_CONFIG_B 0xe2100 | |
f0f59a00 | 7179 | #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) |
c46f111f JN |
7180 | #define _CPT_AUD_CONFIG_A 0xe5000 |
7181 | #define _CPT_AUD_CONFIG_B 0xe5100 | |
f0f59a00 | 7182 | #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) |
c46f111f JN |
7183 | #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) |
7184 | #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) | |
f0f59a00 | 7185 | #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) |
9ca2fe73 | 7186 | |
b6daa025 WF |
7187 | #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) |
7188 | #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) | |
7189 | #define AUD_CONFIG_UPPER_N_SHIFT 20 | |
c46f111f | 7190 | #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) |
b6daa025 | 7191 | #define AUD_CONFIG_LOWER_N_SHIFT 4 |
c46f111f | 7192 | #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) |
b6daa025 | 7193 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 |
1a91510d JN |
7194 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) |
7195 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) | |
7196 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) | |
7197 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) | |
7198 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) | |
7199 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) | |
7200 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) | |
7201 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) | |
7202 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) | |
7203 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) | |
7204 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) | |
b6daa025 WF |
7205 | #define AUD_CONFIG_DISABLE_NCTS (1 << 3) |
7206 | ||
9a78b6cc | 7207 | /* HSW Audio */ |
c46f111f JN |
7208 | #define _HSW_AUD_CONFIG_A 0x65000 |
7209 | #define _HSW_AUD_CONFIG_B 0x65100 | |
f0f59a00 | 7210 | #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) |
c46f111f JN |
7211 | |
7212 | #define _HSW_AUD_MISC_CTRL_A 0x65010 | |
7213 | #define _HSW_AUD_MISC_CTRL_B 0x65110 | |
f0f59a00 | 7214 | #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) |
c46f111f JN |
7215 | |
7216 | #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 | |
7217 | #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 | |
f0f59a00 | 7218 | #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) |
9a78b6cc WX |
7219 | |
7220 | /* Audio Digital Converter */ | |
c46f111f JN |
7221 | #define _HSW_AUD_DIG_CNVT_1 0x65080 |
7222 | #define _HSW_AUD_DIG_CNVT_2 0x65180 | |
f0f59a00 | 7223 | #define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) |
c46f111f JN |
7224 | #define DIP_PORT_SEL_MASK 0x3 |
7225 | ||
7226 | #define _HSW_AUD_EDID_DATA_A 0x65050 | |
7227 | #define _HSW_AUD_EDID_DATA_B 0x65150 | |
f0f59a00 | 7228 | #define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) |
c46f111f | 7229 | |
f0f59a00 VS |
7230 | #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) |
7231 | #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) | |
82910ac6 JN |
7232 | #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) |
7233 | #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) | |
7234 | #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) | |
7235 | #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) | |
9a78b6cc | 7236 | |
f0f59a00 | 7237 | #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) |
632f3ab9 LH |
7238 | #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) |
7239 | ||
9eb3a752 | 7240 | /* HSW Power Wells */ |
f0f59a00 VS |
7241 | #define HSW_PWR_WELL_BIOS _MMIO(0x45400) /* CTL1 */ |
7242 | #define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */ | |
7243 | #define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */ | |
7244 | #define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */ | |
6aedd1f5 PZ |
7245 | #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) |
7246 | #define HSW_PWR_WELL_STATE_ENABLED (1<<30) | |
f0f59a00 | 7247 | #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) |
9eb3a752 ED |
7248 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) |
7249 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) | |
5e49cea6 | 7250 | #define HSW_PWR_WELL_FORCE_ON (1<<19) |
f0f59a00 | 7251 | #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) |
9eb3a752 | 7252 | |
94dd5138 | 7253 | /* SKL Fuse Status */ |
f0f59a00 | 7254 | #define SKL_FUSE_STATUS _MMIO(0x42000) |
94dd5138 S |
7255 | #define SKL_FUSE_DOWNLOAD_STATUS (1<<31) |
7256 | #define SKL_FUSE_PG0_DIST_STATUS (1<<27) | |
7257 | #define SKL_FUSE_PG1_DIST_STATUS (1<<26) | |
7258 | #define SKL_FUSE_PG2_DIST_STATUS (1<<25) | |
7259 | ||
e7e104c3 | 7260 | /* Per-pipe DDI Function Control */ |
086f8e84 VS |
7261 | #define _TRANS_DDI_FUNC_CTL_A 0x60400 |
7262 | #define _TRANS_DDI_FUNC_CTL_B 0x61400 | |
7263 | #define _TRANS_DDI_FUNC_CTL_C 0x62400 | |
7264 | #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 | |
f0f59a00 | 7265 | #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) |
a57c774a | 7266 | |
ad80a810 | 7267 | #define TRANS_DDI_FUNC_ENABLE (1<<31) |
e7e104c3 | 7268 | /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ |
ad80a810 | 7269 | #define TRANS_DDI_PORT_MASK (7<<28) |
26804afd | 7270 | #define TRANS_DDI_PORT_SHIFT 28 |
ad80a810 PZ |
7271 | #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) |
7272 | #define TRANS_DDI_PORT_NONE (0<<28) | |
7273 | #define TRANS_DDI_MODE_SELECT_MASK (7<<24) | |
7274 | #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) | |
7275 | #define TRANS_DDI_MODE_SELECT_DVI (1<<24) | |
7276 | #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) | |
7277 | #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) | |
7278 | #define TRANS_DDI_MODE_SELECT_FDI (4<<24) | |
7279 | #define TRANS_DDI_BPC_MASK (7<<20) | |
7280 | #define TRANS_DDI_BPC_8 (0<<20) | |
7281 | #define TRANS_DDI_BPC_10 (1<<20) | |
7282 | #define TRANS_DDI_BPC_6 (2<<20) | |
7283 | #define TRANS_DDI_BPC_12 (3<<20) | |
7284 | #define TRANS_DDI_PVSYNC (1<<17) | |
7285 | #define TRANS_DDI_PHSYNC (1<<16) | |
7286 | #define TRANS_DDI_EDP_INPUT_MASK (7<<12) | |
7287 | #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) | |
7288 | #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) | |
7289 | #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) | |
7290 | #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) | |
01b887c3 | 7291 | #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) |
ad80a810 | 7292 | #define TRANS_DDI_BFI_ENABLE (1<<4) |
e7e104c3 | 7293 | |
0e87f667 | 7294 | /* DisplayPort Transport Control */ |
086f8e84 VS |
7295 | #define _DP_TP_CTL_A 0x64040 |
7296 | #define _DP_TP_CTL_B 0x64140 | |
f0f59a00 | 7297 | #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) |
5e49cea6 PZ |
7298 | #define DP_TP_CTL_ENABLE (1<<31) |
7299 | #define DP_TP_CTL_MODE_SST (0<<27) | |
7300 | #define DP_TP_CTL_MODE_MST (1<<27) | |
01b887c3 | 7301 | #define DP_TP_CTL_FORCE_ACT (1<<25) |
0e87f667 | 7302 | #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) |
5e49cea6 | 7303 | #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) |
0e87f667 ED |
7304 | #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) |
7305 | #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) | |
7306 | #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) | |
d6c0d722 PZ |
7307 | #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) |
7308 | #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) | |
5e49cea6 | 7309 | #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) |
d6c0d722 | 7310 | #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) |
0e87f667 | 7311 | |
e411b2c1 | 7312 | /* DisplayPort Transport Status */ |
086f8e84 VS |
7313 | #define _DP_TP_STATUS_A 0x64044 |
7314 | #define _DP_TP_STATUS_B 0x64144 | |
f0f59a00 | 7315 | #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) |
01b887c3 DA |
7316 | #define DP_TP_STATUS_IDLE_DONE (1<<25) |
7317 | #define DP_TP_STATUS_ACT_SENT (1<<24) | |
7318 | #define DP_TP_STATUS_MODE_STATUS_MST (1<<23) | |
7319 | #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) | |
7320 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) | |
7321 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) | |
7322 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) | |
e411b2c1 | 7323 | |
03f896a1 | 7324 | /* DDI Buffer Control */ |
086f8e84 VS |
7325 | #define _DDI_BUF_CTL_A 0x64000 |
7326 | #define _DDI_BUF_CTL_B 0x64100 | |
f0f59a00 | 7327 | #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) |
5e49cea6 | 7328 | #define DDI_BUF_CTL_ENABLE (1<<31) |
c5fe6a06 | 7329 | #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) |
5e49cea6 | 7330 | #define DDI_BUF_EMP_MASK (0xf<<24) |
876a8cdf | 7331 | #define DDI_BUF_PORT_REVERSAL (1<<16) |
5e49cea6 | 7332 | #define DDI_BUF_IS_IDLE (1<<7) |
79935fca | 7333 | #define DDI_A_4_LANES (1<<4) |
17aa6be9 | 7334 | #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) |
90a6b7b0 VS |
7335 | #define DDI_PORT_WIDTH_MASK (7 << 1) |
7336 | #define DDI_PORT_WIDTH_SHIFT 1 | |
03f896a1 ED |
7337 | #define DDI_INIT_DISPLAY_DETECTED (1<<0) |
7338 | ||
bb879a44 | 7339 | /* DDI Buffer Translations */ |
086f8e84 VS |
7340 | #define _DDI_BUF_TRANS_A 0x64E00 |
7341 | #define _DDI_BUF_TRANS_B 0x64E60 | |
f0f59a00 VS |
7342 | #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) |
7343 | #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) | |
bb879a44 | 7344 | |
7501a4d8 ED |
7345 | /* Sideband Interface (SBI) is programmed indirectly, via |
7346 | * SBI_ADDR, which contains the register offset; and SBI_DATA, | |
7347 | * which contains the payload */ | |
f0f59a00 VS |
7348 | #define SBI_ADDR _MMIO(0xC6000) |
7349 | #define SBI_DATA _MMIO(0xC6004) | |
7350 | #define SBI_CTL_STAT _MMIO(0xC6008) | |
988d6ee8 PZ |
7351 | #define SBI_CTL_DEST_ICLK (0x0<<16) |
7352 | #define SBI_CTL_DEST_MPHY (0x1<<16) | |
7353 | #define SBI_CTL_OP_IORD (0x2<<8) | |
7354 | #define SBI_CTL_OP_IOWR (0x3<<8) | |
7501a4d8 ED |
7355 | #define SBI_CTL_OP_CRRD (0x6<<8) |
7356 | #define SBI_CTL_OP_CRWR (0x7<<8) | |
7357 | #define SBI_RESPONSE_FAIL (0x1<<1) | |
5e49cea6 PZ |
7358 | #define SBI_RESPONSE_SUCCESS (0x0<<1) |
7359 | #define SBI_BUSY (0x1<<0) | |
7360 | #define SBI_READY (0x0<<0) | |
52f025ef | 7361 | |
ccf1c867 | 7362 | /* SBI offsets */ |
f7be2c21 | 7363 | #define SBI_SSCDIVINTPHASE 0x0200 |
5e49cea6 | 7364 | #define SBI_SSCDIVINTPHASE6 0x0600 |
ccf1c867 ED |
7365 | #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) |
7366 | #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) | |
7367 | #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) | |
7368 | #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) | |
5e49cea6 | 7369 | #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) |
ccf1c867 | 7370 | #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) |
f7be2c21 | 7371 | #define SBI_SSCDITHPHASE 0x0204 |
5e49cea6 | 7372 | #define SBI_SSCCTL 0x020c |
ccf1c867 | 7373 | #define SBI_SSCCTL6 0x060C |
dde86e2d | 7374 | #define SBI_SSCCTL_PATHALT (1<<3) |
5e49cea6 | 7375 | #define SBI_SSCCTL_DISABLE (1<<0) |
ccf1c867 ED |
7376 | #define SBI_SSCAUXDIV6 0x0610 |
7377 | #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) | |
5e49cea6 | 7378 | #define SBI_DBUFF0 0x2a00 |
2fa86a1f PZ |
7379 | #define SBI_GEN0 0x1f00 |
7380 | #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) | |
ccf1c867 | 7381 | |
52f025ef | 7382 | /* LPT PIXCLK_GATE */ |
f0f59a00 | 7383 | #define PIXCLK_GATE _MMIO(0xC6020) |
745ca3be PZ |
7384 | #define PIXCLK_GATE_UNGATE (1<<0) |
7385 | #define PIXCLK_GATE_GATE (0<<0) | |
52f025ef | 7386 | |
e93ea06a | 7387 | /* SPLL */ |
f0f59a00 | 7388 | #define SPLL_CTL _MMIO(0x46020) |
e93ea06a | 7389 | #define SPLL_PLL_ENABLE (1<<31) |
39bc66c9 DL |
7390 | #define SPLL_PLL_SSC (1<<28) |
7391 | #define SPLL_PLL_NON_SSC (2<<28) | |
11578553 JB |
7392 | #define SPLL_PLL_LCPLL (3<<28) |
7393 | #define SPLL_PLL_REF_MASK (3<<28) | |
5e49cea6 PZ |
7394 | #define SPLL_PLL_FREQ_810MHz (0<<26) |
7395 | #define SPLL_PLL_FREQ_1350MHz (1<<26) | |
11578553 JB |
7396 | #define SPLL_PLL_FREQ_2700MHz (2<<26) |
7397 | #define SPLL_PLL_FREQ_MASK (3<<26) | |
e93ea06a | 7398 | |
4dffc404 | 7399 | /* WRPLL */ |
086f8e84 VS |
7400 | #define _WRPLL_CTL1 0x46040 |
7401 | #define _WRPLL_CTL2 0x46060 | |
f0f59a00 | 7402 | #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) |
5e49cea6 | 7403 | #define WRPLL_PLL_ENABLE (1<<31) |
114fe488 DV |
7404 | #define WRPLL_PLL_SSC (1<<28) |
7405 | #define WRPLL_PLL_NON_SSC (2<<28) | |
7406 | #define WRPLL_PLL_LCPLL (3<<28) | |
7407 | #define WRPLL_PLL_REF_MASK (3<<28) | |
ef4d084f | 7408 | /* WRPLL divider programming */ |
5e49cea6 | 7409 | #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) |
11578553 | 7410 | #define WRPLL_DIVIDER_REF_MASK (0xff) |
5e49cea6 | 7411 | #define WRPLL_DIVIDER_POST(x) ((x)<<8) |
11578553 JB |
7412 | #define WRPLL_DIVIDER_POST_MASK (0x3f<<8) |
7413 | #define WRPLL_DIVIDER_POST_SHIFT 8 | |
5e49cea6 | 7414 | #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) |
11578553 JB |
7415 | #define WRPLL_DIVIDER_FB_SHIFT 16 |
7416 | #define WRPLL_DIVIDER_FB_MASK (0xff<<16) | |
4dffc404 | 7417 | |
fec9181c | 7418 | /* Port clock selection */ |
086f8e84 VS |
7419 | #define _PORT_CLK_SEL_A 0x46100 |
7420 | #define _PORT_CLK_SEL_B 0x46104 | |
f0f59a00 | 7421 | #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) |
fec9181c ED |
7422 | #define PORT_CLK_SEL_LCPLL_2700 (0<<29) |
7423 | #define PORT_CLK_SEL_LCPLL_1350 (1<<29) | |
7424 | #define PORT_CLK_SEL_LCPLL_810 (2<<29) | |
5e49cea6 | 7425 | #define PORT_CLK_SEL_SPLL (3<<29) |
716c2e55 | 7426 | #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) |
fec9181c ED |
7427 | #define PORT_CLK_SEL_WRPLL1 (4<<29) |
7428 | #define PORT_CLK_SEL_WRPLL2 (5<<29) | |
6441ab5f | 7429 | #define PORT_CLK_SEL_NONE (7<<29) |
11578553 | 7430 | #define PORT_CLK_SEL_MASK (7<<29) |
fec9181c | 7431 | |
bb523fc0 | 7432 | /* Transcoder clock selection */ |
086f8e84 VS |
7433 | #define _TRANS_CLK_SEL_A 0x46140 |
7434 | #define _TRANS_CLK_SEL_B 0x46144 | |
f0f59a00 | 7435 | #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) |
bb523fc0 PZ |
7436 | /* For each transcoder, we need to select the corresponding port clock */ |
7437 | #define TRANS_CLK_SEL_DISABLED (0x0<<29) | |
68d97538 | 7438 | #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29) |
fec9181c | 7439 | |
086f8e84 VS |
7440 | #define _TRANSA_MSA_MISC 0x60410 |
7441 | #define _TRANSB_MSA_MISC 0x61410 | |
7442 | #define _TRANSC_MSA_MISC 0x62410 | |
7443 | #define _TRANS_EDP_MSA_MISC 0x6f410 | |
f0f59a00 | 7444 | #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) |
a57c774a | 7445 | |
c9809791 PZ |
7446 | #define TRANS_MSA_SYNC_CLK (1<<0) |
7447 | #define TRANS_MSA_6_BPC (0<<5) | |
7448 | #define TRANS_MSA_8_BPC (1<<5) | |
7449 | #define TRANS_MSA_10_BPC (2<<5) | |
7450 | #define TRANS_MSA_12_BPC (3<<5) | |
7451 | #define TRANS_MSA_16_BPC (4<<5) | |
dae84799 | 7452 | |
90e8d31c | 7453 | /* LCPLL Control */ |
f0f59a00 | 7454 | #define LCPLL_CTL _MMIO(0x130040) |
90e8d31c ED |
7455 | #define LCPLL_PLL_DISABLE (1<<31) |
7456 | #define LCPLL_PLL_LOCK (1<<30) | |
79f689aa PZ |
7457 | #define LCPLL_CLK_FREQ_MASK (3<<26) |
7458 | #define LCPLL_CLK_FREQ_450 (0<<26) | |
e39bf98a PZ |
7459 | #define LCPLL_CLK_FREQ_54O_BDW (1<<26) |
7460 | #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) | |
7461 | #define LCPLL_CLK_FREQ_675_BDW (3<<26) | |
5e49cea6 | 7462 | #define LCPLL_CD_CLOCK_DISABLE (1<<25) |
b432e5cf | 7463 | #define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24) |
90e8d31c | 7464 | #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) |
be256dc7 | 7465 | #define LCPLL_POWER_DOWN_ALLOW (1<<22) |
79f689aa | 7466 | #define LCPLL_CD_SOURCE_FCLK (1<<21) |
be256dc7 PZ |
7467 | #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) |
7468 | ||
326ac39b S |
7469 | /* |
7470 | * SKL Clocks | |
7471 | */ | |
7472 | ||
7473 | /* CDCLK_CTL */ | |
f0f59a00 | 7474 | #define CDCLK_CTL _MMIO(0x46000) |
326ac39b S |
7475 | #define CDCLK_FREQ_SEL_MASK (3<<26) |
7476 | #define CDCLK_FREQ_450_432 (0<<26) | |
7477 | #define CDCLK_FREQ_540 (1<<26) | |
7478 | #define CDCLK_FREQ_337_308 (2<<26) | |
7479 | #define CDCLK_FREQ_675_617 (3<<26) | |
7480 | #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) | |
7481 | ||
f8437dd1 VK |
7482 | #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22) |
7483 | #define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22) | |
7484 | #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22) | |
7485 | #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22) | |
7486 | #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) | |
7487 | #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16) | |
7488 | ||
326ac39b | 7489 | /* LCPLL_CTL */ |
f0f59a00 VS |
7490 | #define LCPLL1_CTL _MMIO(0x46010) |
7491 | #define LCPLL2_CTL _MMIO(0x46014) | |
326ac39b S |
7492 | #define LCPLL_PLL_ENABLE (1<<31) |
7493 | ||
7494 | /* DPLL control1 */ | |
f0f59a00 | 7495 | #define DPLL_CTRL1 _MMIO(0x6C058) |
326ac39b S |
7496 | #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) |
7497 | #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) | |
71cd8423 DL |
7498 | #define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) |
7499 | #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1) | |
7500 | #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) | |
326ac39b | 7501 | #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) |
71cd8423 DL |
7502 | #define DPLL_CTRL1_LINK_RATE_2700 0 |
7503 | #define DPLL_CTRL1_LINK_RATE_1350 1 | |
7504 | #define DPLL_CTRL1_LINK_RATE_810 2 | |
7505 | #define DPLL_CTRL1_LINK_RATE_1620 3 | |
7506 | #define DPLL_CTRL1_LINK_RATE_1080 4 | |
7507 | #define DPLL_CTRL1_LINK_RATE_2160 5 | |
326ac39b S |
7508 | |
7509 | /* DPLL control2 */ | |
f0f59a00 | 7510 | #define DPLL_CTRL2 _MMIO(0x6C05C) |
68d97538 | 7511 | #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15)) |
326ac39b | 7512 | #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) |
540e732c | 7513 | #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) |
68d97538 | 7514 | #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1)) |
326ac39b S |
7515 | #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) |
7516 | ||
7517 | /* DPLL Status */ | |
f0f59a00 | 7518 | #define DPLL_STATUS _MMIO(0x6C060) |
326ac39b S |
7519 | #define DPLL_LOCK(id) (1<<((id)*8)) |
7520 | ||
7521 | /* DPLL cfg */ | |
086f8e84 VS |
7522 | #define _DPLL1_CFGCR1 0x6C040 |
7523 | #define _DPLL2_CFGCR1 0x6C048 | |
7524 | #define _DPLL3_CFGCR1 0x6C050 | |
326ac39b S |
7525 | #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) |
7526 | #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) | |
68d97538 | 7527 | #define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9) |
326ac39b S |
7528 | #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) |
7529 | ||
086f8e84 VS |
7530 | #define _DPLL1_CFGCR2 0x6C044 |
7531 | #define _DPLL2_CFGCR2 0x6C04C | |
7532 | #define _DPLL3_CFGCR2 0x6C054 | |
326ac39b | 7533 | #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) |
68d97538 VS |
7534 | #define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8) |
7535 | #define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7) | |
326ac39b | 7536 | #define DPLL_CFGCR2_KDIV_MASK (3<<5) |
68d97538 | 7537 | #define DPLL_CFGCR2_KDIV(x) ((x)<<5) |
326ac39b S |
7538 | #define DPLL_CFGCR2_KDIV_5 (0<<5) |
7539 | #define DPLL_CFGCR2_KDIV_2 (1<<5) | |
7540 | #define DPLL_CFGCR2_KDIV_3 (2<<5) | |
7541 | #define DPLL_CFGCR2_KDIV_1 (3<<5) | |
7542 | #define DPLL_CFGCR2_PDIV_MASK (7<<2) | |
68d97538 | 7543 | #define DPLL_CFGCR2_PDIV(x) ((x)<<2) |
326ac39b S |
7544 | #define DPLL_CFGCR2_PDIV_1 (0<<2) |
7545 | #define DPLL_CFGCR2_PDIV_2 (1<<2) | |
7546 | #define DPLL_CFGCR2_PDIV_3 (2<<2) | |
7547 | #define DPLL_CFGCR2_PDIV_7 (4<<2) | |
7548 | #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) | |
7549 | ||
da3b891b | 7550 | #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) |
f0f59a00 | 7551 | #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) |
540e732c | 7552 | |
f8437dd1 | 7553 | /* BXT display engine PLL */ |
f0f59a00 | 7554 | #define BXT_DE_PLL_CTL _MMIO(0x6d000) |
f8437dd1 VK |
7555 | #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ |
7556 | #define BXT_DE_PLL_RATIO_MASK 0xff | |
7557 | ||
f0f59a00 | 7558 | #define BXT_DE_PLL_ENABLE _MMIO(0x46070) |
f8437dd1 VK |
7559 | #define BXT_DE_PLL_PLL_ENABLE (1 << 31) |
7560 | #define BXT_DE_PLL_LOCK (1 << 30) | |
7561 | ||
664326f8 | 7562 | /* GEN9 DC */ |
f0f59a00 | 7563 | #define DC_STATE_EN _MMIO(0x45504) |
13ae3a0d | 7564 | #define DC_STATE_DISABLE 0 |
664326f8 SK |
7565 | #define DC_STATE_EN_UPTO_DC5 (1<<0) |
7566 | #define DC_STATE_EN_DC9 (1<<3) | |
6b457d31 SK |
7567 | #define DC_STATE_EN_UPTO_DC6 (2<<0) |
7568 | #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 | |
7569 | ||
f0f59a00 | 7570 | #define DC_STATE_DEBUG _MMIO(0x45520) |
6b457d31 SK |
7571 | #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) |
7572 | ||
9ccd5aeb PZ |
7573 | /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
7574 | * since on HSW we can't write to it using I915_WRITE. */ | |
f0f59a00 VS |
7575 | #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) |
7576 | #define D_COMP_BDW _MMIO(0x138144) | |
be256dc7 PZ |
7577 | #define D_COMP_RCOMP_IN_PROGRESS (1<<9) |
7578 | #define D_COMP_COMP_FORCE (1<<8) | |
7579 | #define D_COMP_COMP_DISABLE (1<<0) | |
90e8d31c | 7580 | |
69e94b7e | 7581 | /* Pipe WM_LINETIME - watermark line time */ |
086f8e84 VS |
7582 | #define _PIPE_WM_LINETIME_A 0x45270 |
7583 | #define _PIPE_WM_LINETIME_B 0x45274 | |
f0f59a00 | 7584 | #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B) |
5e49cea6 PZ |
7585 | #define PIPE_WM_LINETIME_MASK (0x1ff) |
7586 | #define PIPE_WM_LINETIME_TIME(x) ((x)) | |
69e94b7e | 7587 | #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) |
5e49cea6 | 7588 | #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) |
96d6e350 ED |
7589 | |
7590 | /* SFUSE_STRAP */ | |
f0f59a00 | 7591 | #define SFUSE_STRAP _MMIO(0xc2014) |
658ac4c6 DL |
7592 | #define SFUSE_STRAP_FUSE_LOCK (1<<13) |
7593 | #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) | |
65e472e4 | 7594 | #define SFUSE_STRAP_CRT_DISABLED (1<<6) |
96d6e350 ED |
7595 | #define SFUSE_STRAP_DDIB_DETECTED (1<<2) |
7596 | #define SFUSE_STRAP_DDIC_DETECTED (1<<1) | |
7597 | #define SFUSE_STRAP_DDID_DETECTED (1<<0) | |
7598 | ||
f0f59a00 | 7599 | #define WM_MISC _MMIO(0x45260) |
801bcfff PZ |
7600 | #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) |
7601 | ||
f0f59a00 | 7602 | #define WM_DBG _MMIO(0x45280) |
1544d9d5 ED |
7603 | #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) |
7604 | #define WM_DBG_DISALLOW_MAXFIFO (1<<1) | |
7605 | #define WM_DBG_DISALLOW_SPRITE (1<<2) | |
7606 | ||
86d3efce VS |
7607 | /* pipe CSC */ |
7608 | #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 | |
7609 | #define _PIPE_A_CSC_COEFF_BY 0x49014 | |
7610 | #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 | |
7611 | #define _PIPE_A_CSC_COEFF_BU 0x4901c | |
7612 | #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 | |
7613 | #define _PIPE_A_CSC_COEFF_BV 0x49024 | |
7614 | #define _PIPE_A_CSC_MODE 0x49028 | |
29a397ba VS |
7615 | #define CSC_BLACK_SCREEN_OFFSET (1 << 2) |
7616 | #define CSC_POSITION_BEFORE_GAMMA (1 << 1) | |
7617 | #define CSC_MODE_YUV_TO_RGB (1 << 0) | |
86d3efce VS |
7618 | #define _PIPE_A_CSC_PREOFF_HI 0x49030 |
7619 | #define _PIPE_A_CSC_PREOFF_ME 0x49034 | |
7620 | #define _PIPE_A_CSC_PREOFF_LO 0x49038 | |
7621 | #define _PIPE_A_CSC_POSTOFF_HI 0x49040 | |
7622 | #define _PIPE_A_CSC_POSTOFF_ME 0x49044 | |
7623 | #define _PIPE_A_CSC_POSTOFF_LO 0x49048 | |
7624 | ||
7625 | #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 | |
7626 | #define _PIPE_B_CSC_COEFF_BY 0x49114 | |
7627 | #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 | |
7628 | #define _PIPE_B_CSC_COEFF_BU 0x4911c | |
7629 | #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 | |
7630 | #define _PIPE_B_CSC_COEFF_BV 0x49124 | |
7631 | #define _PIPE_B_CSC_MODE 0x49128 | |
7632 | #define _PIPE_B_CSC_PREOFF_HI 0x49130 | |
7633 | #define _PIPE_B_CSC_PREOFF_ME 0x49134 | |
7634 | #define _PIPE_B_CSC_PREOFF_LO 0x49138 | |
7635 | #define _PIPE_B_CSC_POSTOFF_HI 0x49140 | |
7636 | #define _PIPE_B_CSC_POSTOFF_ME 0x49144 | |
7637 | #define _PIPE_B_CSC_POSTOFF_LO 0x49148 | |
7638 | ||
f0f59a00 VS |
7639 | #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) |
7640 | #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) | |
7641 | #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) | |
7642 | #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) | |
7643 | #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) | |
7644 | #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) | |
7645 | #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) | |
7646 | #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) | |
7647 | #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) | |
7648 | #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) | |
7649 | #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) | |
7650 | #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) | |
7651 | #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) | |
86d3efce | 7652 | |
e7d7cad0 JN |
7653 | /* MIPI DSI registers */ |
7654 | ||
7655 | #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */ | |
f0f59a00 | 7656 | #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) |
3230bf14 | 7657 | |
11b8e4f5 SS |
7658 | /* BXT MIPI clock controls */ |
7659 | #define BXT_MAX_VAR_OUTPUT_KHZ 39500 | |
7660 | ||
f0f59a00 | 7661 | #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090) |
11b8e4f5 SS |
7662 | #define BXT_MIPI1_DIV_SHIFT 26 |
7663 | #define BXT_MIPI2_DIV_SHIFT 10 | |
7664 | #define BXT_MIPI_DIV_SHIFT(port) \ | |
7665 | _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ | |
7666 | BXT_MIPI2_DIV_SHIFT) | |
7667 | /* Var clock divider to generate TX source. Result must be < 39.5 M */ | |
7668 | #define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26) | |
7669 | #define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10) | |
7670 | #define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \ | |
7671 | _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \ | |
7672 | BXT_MIPI2_ESCLK_VAR_DIV_MASK) | |
7673 | ||
7674 | #define BXT_MIPI_ESCLK_VAR_DIV(port, val) \ | |
7675 | (val << BXT_MIPI_DIV_SHIFT(port)) | |
7676 | /* TX control divider to select actual TX clock output from (8x/var) */ | |
7677 | #define BXT_MIPI1_TX_ESCLK_SHIFT 21 | |
7678 | #define BXT_MIPI2_TX_ESCLK_SHIFT 5 | |
7679 | #define BXT_MIPI_TX_ESCLK_SHIFT(port) \ | |
7680 | _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ | |
7681 | BXT_MIPI2_TX_ESCLK_SHIFT) | |
7682 | #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21) | |
7683 | #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5) | |
7684 | #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ | |
7685 | _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ | |
7686 | BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) | |
7687 | #define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \ | |
7688 | (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port)) | |
7689 | #define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \ | |
7690 | (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port)) | |
7691 | #define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \ | |
7692 | (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port)) | |
7693 | /* RX control divider to select actual RX clock output from 8x*/ | |
7694 | #define BXT_MIPI1_RX_ESCLK_SHIFT 19 | |
7695 | #define BXT_MIPI2_RX_ESCLK_SHIFT 3 | |
7696 | #define BXT_MIPI_RX_ESCLK_SHIFT(port) \ | |
7697 | _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \ | |
7698 | BXT_MIPI2_RX_ESCLK_SHIFT) | |
7699 | #define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19) | |
7700 | #define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3) | |
7701 | #define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \ | |
7702 | (3 << BXT_MIPI_RX_ESCLK_SHIFT(port)) | |
7703 | #define BXT_MIPI_RX_ESCLK_8X_BY2(port) \ | |
7704 | (1 << BXT_MIPI_RX_ESCLK_SHIFT(port)) | |
7705 | #define BXT_MIPI_RX_ESCLK_8X_BY3(port) \ | |
7706 | (2 << BXT_MIPI_RX_ESCLK_SHIFT(port)) | |
7707 | #define BXT_MIPI_RX_ESCLK_8X_BY4(port) \ | |
7708 | (3 << BXT_MIPI_RX_ESCLK_SHIFT(port)) | |
7709 | /* BXT-A WA: Always prog DPHY dividers to 00 */ | |
7710 | #define BXT_MIPI1_DPHY_DIV_SHIFT 16 | |
7711 | #define BXT_MIPI2_DPHY_DIV_SHIFT 0 | |
7712 | #define BXT_MIPI_DPHY_DIV_SHIFT(port) \ | |
7713 | _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \ | |
7714 | BXT_MIPI2_DPHY_DIV_SHIFT) | |
7715 | #define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16) | |
7716 | #define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0) | |
7717 | #define BXT_MIPI_DPHY_DIVIDER_MASK(port) \ | |
7718 | (3 << BXT_MIPI_DPHY_DIV_SHIFT(port)) | |
7719 | ||
d2e08c0f SS |
7720 | /* BXT MIPI mode configure */ |
7721 | #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 | |
7722 | #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 | |
f0f59a00 | 7723 | #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ |
d2e08c0f SS |
7724 | _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) |
7725 | ||
7726 | #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC | |
7727 | #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC | |
f0f59a00 | 7728 | #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ |
d2e08c0f SS |
7729 | _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) |
7730 | ||
7731 | #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 | |
7732 | #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 | |
f0f59a00 | 7733 | #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ |
d2e08c0f SS |
7734 | _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) |
7735 | ||
f0f59a00 | 7736 | #define BXT_DSI_PLL_CTL _MMIO(0x161000) |
cfe01a5e SS |
7737 | #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16 |
7738 | #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT) | |
7739 | #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT) | |
7740 | #define BXT_DSIC_16X_BY2 (1 << 10) | |
7741 | #define BXT_DSIC_16X_BY3 (2 << 10) | |
7742 | #define BXT_DSIC_16X_BY4 (3 << 10) | |
7743 | #define BXT_DSIA_16X_BY2 (1 << 8) | |
7744 | #define BXT_DSIA_16X_BY3 (2 << 8) | |
7745 | #define BXT_DSIA_16X_BY4 (3 << 8) | |
7746 | #define BXT_DSI_FREQ_SEL_SHIFT 8 | |
7747 | #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT) | |
7748 | ||
7749 | #define BXT_DSI_PLL_RATIO_MAX 0x7D | |
7750 | #define BXT_DSI_PLL_RATIO_MIN 0x22 | |
7751 | #define BXT_DSI_PLL_RATIO_MASK 0xFF | |
61ad9928 | 7752 | #define BXT_REF_CLOCK_KHZ 19200 |
cfe01a5e | 7753 | |
f0f59a00 | 7754 | #define BXT_DSI_PLL_ENABLE _MMIO(0x46080) |
cfe01a5e SS |
7755 | #define BXT_DSI_PLL_DO_ENABLE (1 << 31) |
7756 | #define BXT_DSI_PLL_LOCKED (1 << 30) | |
7757 | ||
3230bf14 | 7758 | #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) |
e7d7cad0 | 7759 | #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) |
f0f59a00 | 7760 | #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) |
37ab0810 SS |
7761 | |
7762 | /* BXT port control */ | |
7763 | #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 | |
7764 | #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 | |
f0f59a00 | 7765 | #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) |
37ab0810 | 7766 | |
e7d7cad0 | 7767 | #define DPI_ENABLE (1 << 31) /* A + C */ |
3230bf14 JN |
7768 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 |
7769 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) | |
369602d3 | 7770 | #define DUAL_LINK_MODE_SHIFT 26 |
3230bf14 JN |
7771 | #define DUAL_LINK_MODE_MASK (1 << 26) |
7772 | #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) | |
7773 | #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) | |
e7d7cad0 | 7774 | #define DITHERING_ENABLE (1 << 25) /* A + C */ |
3230bf14 JN |
7775 | #define FLOPPED_HSTX (1 << 23) |
7776 | #define DE_INVERT (1 << 19) /* XXX */ | |
7777 | #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 | |
7778 | #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) | |
7779 | #define AFE_LATCHOUT (1 << 17) | |
7780 | #define LP_OUTPUT_HOLD (1 << 16) | |
e7d7cad0 JN |
7781 | #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 |
7782 | #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) | |
7783 | #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 | |
7784 | #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) | |
3230bf14 JN |
7785 | #define CSB_SHIFT 9 |
7786 | #define CSB_MASK (3 << 9) | |
7787 | #define CSB_20MHZ (0 << 9) | |
7788 | #define CSB_10MHZ (1 << 9) | |
7789 | #define CSB_40MHZ (2 << 9) | |
7790 | #define BANDGAP_MASK (1 << 8) | |
7791 | #define BANDGAP_PNW_CIRCUIT (0 << 8) | |
7792 | #define BANDGAP_LNC_CIRCUIT (1 << 8) | |
e7d7cad0 JN |
7793 | #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 |
7794 | #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) | |
7795 | #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ | |
7796 | #define TEARING_EFFECT_SHIFT 2 /* A + C */ | |
3230bf14 JN |
7797 | #define TEARING_EFFECT_MASK (3 << 2) |
7798 | #define TEARING_EFFECT_OFF (0 << 2) | |
7799 | #define TEARING_EFFECT_DSI (1 << 2) | |
7800 | #define TEARING_EFFECT_GPIO (2 << 2) | |
7801 | #define LANE_CONFIGURATION_SHIFT 0 | |
7802 | #define LANE_CONFIGURATION_MASK (3 << 0) | |
7803 | #define LANE_CONFIGURATION_4LANE (0 << 0) | |
7804 | #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) | |
7805 | #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) | |
7806 | ||
7807 | #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) | |
e7d7cad0 | 7808 | #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) |
f0f59a00 | 7809 | #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) |
3230bf14 JN |
7810 | #define TEARING_EFFECT_DELAY_SHIFT 0 |
7811 | #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) | |
7812 | ||
7813 | /* XXX: all bits reserved */ | |
4ad83e94 | 7814 | #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) |
3230bf14 JN |
7815 | |
7816 | /* MIPI DSI Controller and D-PHY registers */ | |
7817 | ||
4ad83e94 | 7818 | #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) |
e7d7cad0 | 7819 | #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) |
f0f59a00 | 7820 | #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) |
3230bf14 JN |
7821 | #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ |
7822 | #define ULPS_STATE_MASK (3 << 1) | |
7823 | #define ULPS_STATE_ENTER (2 << 1) | |
7824 | #define ULPS_STATE_EXIT (1 << 1) | |
7825 | #define ULPS_STATE_NORMAL_OPERATION (0 << 1) | |
7826 | #define DEVICE_READY (1 << 0) | |
7827 | ||
4ad83e94 | 7828 | #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) |
e7d7cad0 | 7829 | #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) |
f0f59a00 | 7830 | #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) |
4ad83e94 | 7831 | #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) |
e7d7cad0 | 7832 | #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) |
f0f59a00 | 7833 | #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) |
3230bf14 JN |
7834 | #define TEARING_EFFECT (1 << 31) |
7835 | #define SPL_PKT_SENT_INTERRUPT (1 << 30) | |
7836 | #define GEN_READ_DATA_AVAIL (1 << 29) | |
7837 | #define LP_GENERIC_WR_FIFO_FULL (1 << 28) | |
7838 | #define HS_GENERIC_WR_FIFO_FULL (1 << 27) | |
7839 | #define RX_PROT_VIOLATION (1 << 26) | |
7840 | #define RX_INVALID_TX_LENGTH (1 << 25) | |
7841 | #define ACK_WITH_NO_ERROR (1 << 24) | |
7842 | #define TURN_AROUND_ACK_TIMEOUT (1 << 23) | |
7843 | #define LP_RX_TIMEOUT (1 << 22) | |
7844 | #define HS_TX_TIMEOUT (1 << 21) | |
7845 | #define DPI_FIFO_UNDERRUN (1 << 20) | |
7846 | #define LOW_CONTENTION (1 << 19) | |
7847 | #define HIGH_CONTENTION (1 << 18) | |
7848 | #define TXDSI_VC_ID_INVALID (1 << 17) | |
7849 | #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) | |
7850 | #define TXCHECKSUM_ERROR (1 << 15) | |
7851 | #define TXECC_MULTIBIT_ERROR (1 << 14) | |
7852 | #define TXECC_SINGLE_BIT_ERROR (1 << 13) | |
7853 | #define TXFALSE_CONTROL_ERROR (1 << 12) | |
7854 | #define RXDSI_VC_ID_INVALID (1 << 11) | |
7855 | #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) | |
7856 | #define RXCHECKSUM_ERROR (1 << 9) | |
7857 | #define RXECC_MULTIBIT_ERROR (1 << 8) | |
7858 | #define RXECC_SINGLE_BIT_ERROR (1 << 7) | |
7859 | #define RXFALSE_CONTROL_ERROR (1 << 6) | |
7860 | #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) | |
7861 | #define RX_LP_TX_SYNC_ERROR (1 << 4) | |
7862 | #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) | |
7863 | #define RXEOT_SYNC_ERROR (1 << 2) | |
7864 | #define RXSOT_SYNC_ERROR (1 << 1) | |
7865 | #define RXSOT_ERROR (1 << 0) | |
7866 | ||
4ad83e94 | 7867 | #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) |
e7d7cad0 | 7868 | #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) |
f0f59a00 | 7869 | #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) |
3230bf14 JN |
7870 | #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) |
7871 | #define CMD_MODE_NOT_SUPPORTED (0 << 13) | |
7872 | #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) | |
7873 | #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) | |
7874 | #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) | |
7875 | #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) | |
7876 | #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) | |
7877 | #define VID_MODE_FORMAT_MASK (0xf << 7) | |
7878 | #define VID_MODE_NOT_SUPPORTED (0 << 7) | |
7879 | #define VID_MODE_FORMAT_RGB565 (1 << 7) | |
7880 | #define VID_MODE_FORMAT_RGB666 (2 << 7) | |
7881 | #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7) | |
7882 | #define VID_MODE_FORMAT_RGB888 (4 << 7) | |
7883 | #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 | |
7884 | #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) | |
7885 | #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 | |
7886 | #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) | |
7887 | #define DATA_LANES_PRG_REG_SHIFT 0 | |
7888 | #define DATA_LANES_PRG_REG_MASK (7 << 0) | |
7889 | ||
4ad83e94 | 7890 | #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) |
e7d7cad0 | 7891 | #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) |
f0f59a00 | 7892 | #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) |
3230bf14 JN |
7893 | #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff |
7894 | ||
4ad83e94 | 7895 | #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) |
e7d7cad0 | 7896 | #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) |
f0f59a00 | 7897 | #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) |
3230bf14 JN |
7898 | #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff |
7899 | ||
4ad83e94 | 7900 | #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) |
e7d7cad0 | 7901 | #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) |
f0f59a00 | 7902 | #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) |
3230bf14 JN |
7903 | #define TURN_AROUND_TIMEOUT_MASK 0x3f |
7904 | ||
4ad83e94 | 7905 | #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) |
e7d7cad0 | 7906 | #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) |
f0f59a00 | 7907 | #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) |
3230bf14 JN |
7908 | #define DEVICE_RESET_TIMER_MASK 0xffff |
7909 | ||
4ad83e94 | 7910 | #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) |
e7d7cad0 | 7911 | #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) |
f0f59a00 | 7912 | #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) |
3230bf14 JN |
7913 | #define VERTICAL_ADDRESS_SHIFT 16 |
7914 | #define VERTICAL_ADDRESS_MASK (0xffff << 16) | |
7915 | #define HORIZONTAL_ADDRESS_SHIFT 0 | |
7916 | #define HORIZONTAL_ADDRESS_MASK 0xffff | |
7917 | ||
4ad83e94 | 7918 | #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) |
e7d7cad0 | 7919 | #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) |
f0f59a00 | 7920 | #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) |
3230bf14 JN |
7921 | #define DBI_FIFO_EMPTY_HALF (0 << 0) |
7922 | #define DBI_FIFO_EMPTY_QUARTER (1 << 0) | |
7923 | #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) | |
7924 | ||
7925 | /* regs below are bits 15:0 */ | |
4ad83e94 | 7926 | #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) |
e7d7cad0 | 7927 | #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) |
f0f59a00 | 7928 | #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) |
3230bf14 | 7929 | |
4ad83e94 | 7930 | #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) |
e7d7cad0 | 7931 | #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) |
f0f59a00 | 7932 | #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) |
3230bf14 | 7933 | |
4ad83e94 | 7934 | #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) |
e7d7cad0 | 7935 | #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) |
f0f59a00 | 7936 | #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) |
3230bf14 | 7937 | |
4ad83e94 | 7938 | #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) |
e7d7cad0 | 7939 | #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) |
f0f59a00 | 7940 | #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) |
3230bf14 | 7941 | |
4ad83e94 | 7942 | #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) |
e7d7cad0 | 7943 | #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) |
f0f59a00 | 7944 | #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) |
3230bf14 | 7945 | |
4ad83e94 | 7946 | #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) |
e7d7cad0 | 7947 | #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) |
f0f59a00 | 7948 | #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) |
3230bf14 | 7949 | |
4ad83e94 | 7950 | #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) |
e7d7cad0 | 7951 | #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) |
f0f59a00 | 7952 | #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) |
3230bf14 | 7953 | |
4ad83e94 | 7954 | #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) |
e7d7cad0 | 7955 | #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) |
f0f59a00 | 7956 | #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) |
4ad83e94 | 7957 | |
3230bf14 JN |
7958 | /* regs above are bits 15:0 */ |
7959 | ||
4ad83e94 | 7960 | #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) |
e7d7cad0 | 7961 | #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) |
f0f59a00 | 7962 | #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) |
3230bf14 JN |
7963 | #define DPI_LP_MODE (1 << 6) |
7964 | #define BACKLIGHT_OFF (1 << 5) | |
7965 | #define BACKLIGHT_ON (1 << 4) | |
7966 | #define COLOR_MODE_OFF (1 << 3) | |
7967 | #define COLOR_MODE_ON (1 << 2) | |
7968 | #define TURN_ON (1 << 1) | |
7969 | #define SHUTDOWN (1 << 0) | |
7970 | ||
4ad83e94 | 7971 | #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) |
e7d7cad0 | 7972 | #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) |
f0f59a00 | 7973 | #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) |
3230bf14 JN |
7974 | #define COMMAND_BYTE_SHIFT 0 |
7975 | #define COMMAND_BYTE_MASK (0x3f << 0) | |
7976 | ||
4ad83e94 | 7977 | #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) |
e7d7cad0 | 7978 | #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) |
f0f59a00 | 7979 | #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) |
3230bf14 JN |
7980 | #define MASTER_INIT_TIMER_SHIFT 0 |
7981 | #define MASTER_INIT_TIMER_MASK (0xffff << 0) | |
7982 | ||
4ad83e94 | 7983 | #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) |
e7d7cad0 | 7984 | #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) |
f0f59a00 | 7985 | #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ |
e7d7cad0 | 7986 | _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) |
3230bf14 JN |
7987 | #define MAX_RETURN_PKT_SIZE_SHIFT 0 |
7988 | #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) | |
7989 | ||
4ad83e94 | 7990 | #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) |
e7d7cad0 | 7991 | #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) |
f0f59a00 | 7992 | #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) |
3230bf14 JN |
7993 | #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) |
7994 | #define DISABLE_VIDEO_BTA (1 << 3) | |
7995 | #define IP_TG_CONFIG (1 << 2) | |
7996 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) | |
7997 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) | |
7998 | #define VIDEO_MODE_BURST (3 << 0) | |
7999 | ||
4ad83e94 | 8000 | #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) |
e7d7cad0 | 8001 | #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) |
f0f59a00 | 8002 | #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) |
3230bf14 JN |
8003 | #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) |
8004 | #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) | |
8005 | #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) | |
8006 | #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) | |
8007 | #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) | |
8008 | #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) | |
8009 | #define CLOCKSTOP (1 << 1) | |
8010 | #define EOT_DISABLE (1 << 0) | |
8011 | ||
4ad83e94 | 8012 | #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) |
e7d7cad0 | 8013 | #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) |
f0f59a00 | 8014 | #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) |
3230bf14 JN |
8015 | #define LP_BYTECLK_SHIFT 0 |
8016 | #define LP_BYTECLK_MASK (0xffff << 0) | |
8017 | ||
8018 | /* bits 31:0 */ | |
4ad83e94 | 8019 | #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) |
e7d7cad0 | 8020 | #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) |
f0f59a00 | 8021 | #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) |
3230bf14 JN |
8022 | |
8023 | /* bits 31:0 */ | |
4ad83e94 | 8024 | #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) |
e7d7cad0 | 8025 | #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) |
f0f59a00 | 8026 | #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) |
3230bf14 | 8027 | |
4ad83e94 | 8028 | #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) |
e7d7cad0 | 8029 | #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) |
f0f59a00 | 8030 | #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) |
4ad83e94 | 8031 | #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) |
e7d7cad0 | 8032 | #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) |
f0f59a00 | 8033 | #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) |
3230bf14 JN |
8034 | #define LONG_PACKET_WORD_COUNT_SHIFT 8 |
8035 | #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) | |
8036 | #define SHORT_PACKET_PARAM_SHIFT 8 | |
8037 | #define SHORT_PACKET_PARAM_MASK (0xffff << 8) | |
8038 | #define VIRTUAL_CHANNEL_SHIFT 6 | |
8039 | #define VIRTUAL_CHANNEL_MASK (3 << 6) | |
8040 | #define DATA_TYPE_SHIFT 0 | |
395b2913 | 8041 | #define DATA_TYPE_MASK (0x3f << 0) |
3230bf14 JN |
8042 | /* data type values, see include/video/mipi_display.h */ |
8043 | ||
4ad83e94 | 8044 | #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) |
e7d7cad0 | 8045 | #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) |
f0f59a00 | 8046 | #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) |
3230bf14 JN |
8047 | #define DPI_FIFO_EMPTY (1 << 28) |
8048 | #define DBI_FIFO_EMPTY (1 << 27) | |
8049 | #define LP_CTRL_FIFO_EMPTY (1 << 26) | |
8050 | #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) | |
8051 | #define LP_CTRL_FIFO_FULL (1 << 24) | |
8052 | #define HS_CTRL_FIFO_EMPTY (1 << 18) | |
8053 | #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) | |
8054 | #define HS_CTRL_FIFO_FULL (1 << 16) | |
8055 | #define LP_DATA_FIFO_EMPTY (1 << 10) | |
8056 | #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) | |
8057 | #define LP_DATA_FIFO_FULL (1 << 8) | |
8058 | #define HS_DATA_FIFO_EMPTY (1 << 2) | |
8059 | #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) | |
8060 | #define HS_DATA_FIFO_FULL (1 << 0) | |
8061 | ||
4ad83e94 | 8062 | #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) |
e7d7cad0 | 8063 | #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) |
f0f59a00 | 8064 | #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) |
3230bf14 JN |
8065 | #define DBI_HS_LP_MODE_MASK (1 << 0) |
8066 | #define DBI_LP_MODE (1 << 0) | |
8067 | #define DBI_HS_MODE (0 << 0) | |
8068 | ||
4ad83e94 | 8069 | #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) |
e7d7cad0 | 8070 | #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) |
f0f59a00 | 8071 | #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) |
3230bf14 JN |
8072 | #define EXIT_ZERO_COUNT_SHIFT 24 |
8073 | #define EXIT_ZERO_COUNT_MASK (0x3f << 24) | |
8074 | #define TRAIL_COUNT_SHIFT 16 | |
8075 | #define TRAIL_COUNT_MASK (0x1f << 16) | |
8076 | #define CLK_ZERO_COUNT_SHIFT 8 | |
8077 | #define CLK_ZERO_COUNT_MASK (0xff << 8) | |
8078 | #define PREPARE_COUNT_SHIFT 0 | |
8079 | #define PREPARE_COUNT_MASK (0x3f << 0) | |
8080 | ||
8081 | /* bits 31:0 */ | |
4ad83e94 | 8082 | #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) |
e7d7cad0 | 8083 | #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) |
f0f59a00 VS |
8084 | #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) |
8085 | ||
8086 | #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) | |
8087 | #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) | |
8088 | #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) | |
3230bf14 JN |
8089 | #define LP_HS_SSW_CNT_SHIFT 16 |
8090 | #define LP_HS_SSW_CNT_MASK (0xffff << 16) | |
8091 | #define HS_LP_PWR_SW_CNT_SHIFT 0 | |
8092 | #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) | |
8093 | ||
4ad83e94 | 8094 | #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) |
e7d7cad0 | 8095 | #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) |
f0f59a00 | 8096 | #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) |
3230bf14 JN |
8097 | #define STOP_STATE_STALL_COUNTER_SHIFT 0 |
8098 | #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) | |
8099 | ||
4ad83e94 | 8100 | #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) |
e7d7cad0 | 8101 | #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) |
f0f59a00 | 8102 | #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) |
4ad83e94 | 8103 | #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) |
e7d7cad0 | 8104 | #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) |
f0f59a00 | 8105 | #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) |
3230bf14 JN |
8106 | #define RX_CONTENTION_DETECTED (1 << 0) |
8107 | ||
8108 | /* XXX: only pipe A ?!? */ | |
4ad83e94 | 8109 | #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) |
3230bf14 JN |
8110 | #define DBI_TYPEC_ENABLE (1 << 31) |
8111 | #define DBI_TYPEC_WIP (1 << 30) | |
8112 | #define DBI_TYPEC_OPTION_SHIFT 28 | |
8113 | #define DBI_TYPEC_OPTION_MASK (3 << 28) | |
8114 | #define DBI_TYPEC_FREQ_SHIFT 24 | |
8115 | #define DBI_TYPEC_FREQ_MASK (0xf << 24) | |
8116 | #define DBI_TYPEC_OVERRIDE (1 << 8) | |
8117 | #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 | |
8118 | #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) | |
8119 | ||
8120 | ||
8121 | /* MIPI adapter registers */ | |
8122 | ||
4ad83e94 | 8123 | #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) |
e7d7cad0 | 8124 | #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) |
f0f59a00 | 8125 | #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) |
3230bf14 JN |
8126 | #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ |
8127 | #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) | |
8128 | #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) | |
8129 | #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) | |
8130 | #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) | |
8131 | #define READ_REQUEST_PRIORITY_SHIFT 3 | |
8132 | #define READ_REQUEST_PRIORITY_MASK (3 << 3) | |
8133 | #define READ_REQUEST_PRIORITY_LOW (0 << 3) | |
8134 | #define READ_REQUEST_PRIORITY_HIGH (3 << 3) | |
8135 | #define RGB_FLIP_TO_BGR (1 << 2) | |
8136 | ||
d2e08c0f | 8137 | #define BXT_PIPE_SELECT_MASK (7 << 7) |
56c48978 | 8138 | #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) |
d2e08c0f | 8139 | |
4ad83e94 | 8140 | #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) |
e7d7cad0 | 8141 | #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) |
f0f59a00 | 8142 | #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) |
3230bf14 JN |
8143 | #define DATA_MEM_ADDRESS_SHIFT 5 |
8144 | #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) | |
8145 | #define DATA_VALID (1 << 0) | |
8146 | ||
4ad83e94 | 8147 | #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) |
e7d7cad0 | 8148 | #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) |
f0f59a00 | 8149 | #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) |
3230bf14 JN |
8150 | #define DATA_LENGTH_SHIFT 0 |
8151 | #define DATA_LENGTH_MASK (0xfffff << 0) | |
8152 | ||
4ad83e94 | 8153 | #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) |
e7d7cad0 | 8154 | #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) |
f0f59a00 | 8155 | #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) |
3230bf14 JN |
8156 | #define COMMAND_MEM_ADDRESS_SHIFT 5 |
8157 | #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) | |
8158 | #define AUTO_PWG_ENABLE (1 << 2) | |
8159 | #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) | |
8160 | #define COMMAND_VALID (1 << 0) | |
8161 | ||
4ad83e94 | 8162 | #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) |
e7d7cad0 | 8163 | #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) |
f0f59a00 | 8164 | #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) |
3230bf14 JN |
8165 | #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ |
8166 | #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) | |
8167 | ||
4ad83e94 | 8168 | #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) |
e7d7cad0 | 8169 | #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) |
f0f59a00 | 8170 | #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ |
3230bf14 | 8171 | |
4ad83e94 | 8172 | #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) |
e7d7cad0 | 8173 | #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) |
f0f59a00 | 8174 | #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) |
3230bf14 JN |
8175 | #define READ_DATA_VALID(n) (1 << (n)) |
8176 | ||
a57c774a | 8177 | /* For UMS only (deprecated): */ |
5c969aa7 DL |
8178 | #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) |
8179 | #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) | |
a57c774a | 8180 | |
3bbaba0c | 8181 | /* MOCS (Memory Object Control State) registers */ |
f0f59a00 | 8182 | #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ |
3bbaba0c | 8183 | |
f0f59a00 VS |
8184 | #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */ |
8185 | #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */ | |
8186 | #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */ | |
8187 | #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */ | |
8188 | #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */ | |
3bbaba0c | 8189 | |
d5165ebd TG |
8190 | /* gamt regs */ |
8191 | #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) | |
8192 | #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ | |
8193 | #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ | |
8194 | #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ | |
8195 | #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ | |
8196 | ||
585fb111 | 8197 | #endif /* _I915_REG_H_ */ |