[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_suspend.c

/*
 *
 * Copyright 2008 (c) Intel Corporation
 *   Jesse Barnes <jbarnes@virtuousgeek.org>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "intel_drv.h"
#include "i915_reg.h"

static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE8(index_port, reg);
	return I915_READ8(data_port);
}

static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_READ8(st01);
	I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
	return I915_READ8(VGA_AR_DATA_READ);
}

static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_READ8(st01);
	I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
	I915_WRITE8(VGA_AR_DATA_WRITE, val);
}

static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE8(index_port, reg);
	I915_WRITE8(data_port, val);
}

static void i915_save_vga(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;
	u16 cr_index, cr_data, st01;

	/* VGA state */
	dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
	dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
	dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
	dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));

	/* VGA color palette registers */
	dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);

	/* MSR bits */
	dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
		cr_index = VGA_CR_INDEX_CGA;
		cr_data = VGA_CR_DATA_CGA;
		st01 = VGA_ST01_CGA;
	} else {
		cr_index = VGA_CR_INDEX_MDA;
		cr_data = VGA_CR_DATA_MDA;
		st01 = VGA_ST01_MDA;
	}

	/* CRT controller regs */
	i915_write_indexed(dev, cr_index, cr_data, 0x11,
			   i915_read_indexed(dev, cr_index, cr_data, 0x11) &
			   (~0x80));
	for (i = 0; i <= 0x24; i++)
		dev_priv->regfile.saveCR[i] =
			i915_read_indexed(dev, cr_index, cr_data, i);
	/* Make sure we don't turn off CR group 0 writes */
	dev_priv->regfile.saveCR[0x11] &= ~0x80;

	/* Attribute controller registers */
	I915_READ8(st01);
	dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
	for (i = 0; i <= 0x14; i++)
		dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
	I915_READ8(st01);
	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
	I915_READ8(st01);

	/* Graphics controller registers */
	for (i = 0; i < 9; i++)
		dev_priv->regfile.saveGR[i] =
			i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);

	dev_priv->regfile.saveGR[0x10] =
		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
	dev_priv->regfile.saveGR[0x11] =
		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
	dev_priv->regfile.saveGR[0x18] =
		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);

	/* Sequencer registers */
	for (i = 0; i < 8; i++)
		dev_priv->regfile.saveSR[i] =
			i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
}

static void i915_restore_vga(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;
	u16 cr_index, cr_data, st01;

	/* VGA state */
	I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);

	I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
	I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
	I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
	POSTING_READ(VGA_PD);
	udelay(150);

	/* MSR bits */
	I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
		cr_index = VGA_CR_INDEX_CGA;
		cr_data = VGA_CR_DATA_CGA;
		st01 = VGA_ST01_CGA;
	} else {
		cr_index = VGA_CR_INDEX_MDA;
		cr_data = VGA_CR_DATA_MDA;
		st01 = VGA_ST01_MDA;
	}

	/* Sequencer registers, don't write SR07 */
	for (i = 0; i < 7; i++)
		i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
				   dev_priv->regfile.saveSR[i]);

	/* CRT controller regs */
	/* Enable CR group 0 writes */
	i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
	for (i = 0; i <= 0x24; i++)
		i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);

	/* Graphics controller regs */
	for (i = 0; i < 9; i++)
		i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
				   dev_priv->regfile.saveGR[i]);

	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
			   dev_priv->regfile.saveGR[0x10]);
	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
			   dev_priv->regfile.saveGR[0x11]);
	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
			   dev_priv->regfile.saveGR[0x18]);

	/* Attribute controller registers */
	I915_READ8(st01); /* switch back to index mode */
	for (i = 0; i <= 0x14; i++)
		i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
	I915_READ8(st01); /* switch back to index mode */
	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
	I915_READ8(st01);

	/* VGA color palette registers */
	I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
}

static void i915_save_display(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long flags;

	/* Display arbitration control */
	if (INTEL_INFO(dev)->gen <= 4)
		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);

	/* This is only meaningful in non-KMS mode */
	/* Don't regfile.save them in KMS mode */
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		i915_save_display_reg(dev);

	spin_lock_irqsave(&dev_priv->backlight.lock, flags);

	/* LVDS state */
	if (HAS_PCH_SPLIT(dev)) {
		dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
		dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
		dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
		dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
		if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
			dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
	} else {
		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
		dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
		if (INTEL_INFO(dev)->gen >= 4)
			dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
		if (IS_MOBILE(dev) && !IS_I830(dev))
			dev_priv->regfile.saveLVDS = I915_READ(LVDS);
	}

	spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);

	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
		dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);

	if (HAS_PCH_SPLIT(dev)) {
		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
	} else {
		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
		dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
	}

	/* Only regfile.save FBC state on the platform that supports FBC */
	if (I915_HAS_FBC(dev)) {
		if (HAS_PCH_SPLIT(dev)) {
			dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
		} else if (IS_GM45(dev)) {
			dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
		} else {
			dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
			dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
			dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
			dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
		}
	}

	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		i915_save_vga(dev);
}

static void i915_restore_display(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 mask = 0xffffffff;
	unsigned long flags;

	/* Display arbitration */
	if (INTEL_INFO(dev)->gen <= 4)
		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);

	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		i915_restore_display_reg(dev);

	spin_lock_irqsave(&dev_priv->backlight.lock, flags);

	/* LVDS state */
	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
		I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);

	if (drm_core_check_feature(dev, DRIVER_MODESET))
		mask = ~LVDS_PORT_EN;

	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
		I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
	else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
		I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);

	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
		I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);

	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
		I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
		/* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
		 * otherwise we get blank eDP screen after S3 on some machines
		 */
		I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
		I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
		I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
		I915_WRITE(RSTDBYCTL,
			   dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
	} else {
		I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
		I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
		I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
		I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
		I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
		I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
		I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
	}

	spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);

	/* only restore FBC info on the platform that supports FBC*/
	intel_disable_fbc(dev);
	if (I915_HAS_FBC(dev)) {
		if (HAS_PCH_SPLIT(dev)) {
			I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
		} else if (IS_GM45(dev)) {
			I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
		} else {
			I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
			I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
			I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
			I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
		}
	}

	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		i915_restore_vga(dev);
	else
		i915_redisable_vga(dev);
}

int i915_save_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);

	mutex_lock(&dev->struct_mutex);

	i915_save_display(dev);

	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
		/* Interrupt state */
		if (HAS_PCH_SPLIT(dev)) {
			dev_priv->regfile.saveDEIER = I915_READ(DEIER);
			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
			dev_priv->regfile.saveGTIER = I915_READ(GTIER);
			dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
			dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
			dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
			dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
				I915_READ(RSTDBYCTL);
			dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
		} else {
			dev_priv->regfile.saveIER = I915_READ(IER);
			dev_priv->regfile.saveIMR = I915_READ(IMR);
		}
	}

	intel_disable_gt_powersave(dev);

	/* Cache mode state */
	dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);

	/* Memory Arbitration state */
	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);

	/* Scratch space */
	for (i = 0; i < 16; i++) {
		dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
		dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
	}
	for (i = 0; i < 3; i++)
		dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));

	mutex_unlock(&dev->struct_mutex);

	return 0;
}

int i915_restore_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);

	mutex_lock(&dev->struct_mutex);

	i915_restore_display(dev);

	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
		/* Interrupt state */
		if (HAS_PCH_SPLIT(dev)) {
			I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
			I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
			I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
			I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
			I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
			I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
			I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
		} else {
			I915_WRITE(IER, dev_priv->regfile.saveIER);
			I915_WRITE(IMR, dev_priv->regfile.saveIMR);
		}
	}

	/* Cache mode state */
	I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);

	/* Memory arbitration state */
	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);

	for (i = 0; i < 16; i++) {
		I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
		I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
	}
	for (i = 0; i < 3; i++)
		I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);

	mutex_unlock(&dev->struct_mutex);

	intel_i2c_reset(dev);

	return 0;
}
Commit	Line	Data
317c35d1 JB	1	/*
	2	*
	3	* Copyright 2008 (c) Intel Corporation
	4	* Jesse Barnes <jbarnes@virtuousgeek.org>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the
	8	* "Software"), to deal in the Software without restriction, including
	9	* without limitation the rights to use, copy, modify, merge, publish,
	10	* distribute, sub license, and/or sell copies of the Software, and to
	11	* permit persons to whom the Software is furnished to do so, subject to
	12	* the following conditions:
	13	*
	14	* The above copyright notice and this permission notice (including the
	15	* next paragraph) shall be included in all copies or substantial portions
	16	* of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	19	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	20	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
	21	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
	22	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
	23	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
	24	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	25	*/
	26
760285e7 DH	27	#include <drm/drmP.h>
760285e7 DH	28	#include <drm/i915_drm.h>
f0217c42	29	#include "intel_drv.h"
5e5b7fa2	30	#include "i915_reg.h"
317c35d1	31
317c35d1 JB	32	static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
	33	{
	34	struct drm_i915_private *dev_priv = dev->dev_private;
	35
	36	I915_WRITE8(index_port, reg);
	37	return I915_READ8(data_port);
	38	}
	39
	40	static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
	41	{
	42	struct drm_i915_private *dev_priv = dev->dev_private;
	43
	44	I915_READ8(st01);
	45	I915_WRITE8(VGA_AR_INDEX, palette_enable \| reg);
	46	return I915_READ8(VGA_AR_DATA_READ);
	47	}
	48
	49	static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
	50	{
	51	struct drm_i915_private *dev_priv = dev->dev_private;
	52
	53	I915_READ8(st01);
	54	I915_WRITE8(VGA_AR_INDEX, palette_enable \| reg);
	55	I915_WRITE8(VGA_AR_DATA_WRITE, val);
	56	}
	57
	58	static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
	59	{
	60	struct drm_i915_private *dev_priv = dev->dev_private;
	61
	62	I915_WRITE8(index_port, reg);
	63	I915_WRITE8(data_port, val);
	64	}
	65
	66	static void i915_save_vga(struct drm_device *dev)
	67	{
	68	struct drm_i915_private *dev_priv = dev->dev_private;
	69	int i;
	70	u16 cr_index, cr_data, st01;
	71
44cec740 DV	72	/* VGA state */
	73	dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
	74	dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
	75	dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
766aa1c4	76	dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
44cec740	77
317c35d1	78	/* VGA color palette registers */
f4c956ad	79	dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
317c35d1 JB	80
317c35d1 JB	81	/* MSR bits */
f4c956ad DV	82	dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
f4c956ad DV	83	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
317c35d1 JB	84	cr_index = VGA_CR_INDEX_CGA;
	85	cr_data = VGA_CR_DATA_CGA;
	86	st01 = VGA_ST01_CGA;
	87	} else {
	88	cr_index = VGA_CR_INDEX_MDA;
	89	cr_data = VGA_CR_DATA_MDA;
	90	st01 = VGA_ST01_MDA;
	91	}
	92
	93	/* CRT controller regs */
	94	i915_write_indexed(dev, cr_index, cr_data, 0x11,
	95	i915_read_indexed(dev, cr_index, cr_data, 0x11) &
	96	(~0x80));
	97	for (i = 0; i <= 0x24; i++)
f4c956ad	98	dev_priv->regfile.saveCR[i] =
317c35d1 JB	99	i915_read_indexed(dev, cr_index, cr_data, i);
317c35d1 JB	100	/* Make sure we don't turn off CR group 0 writes */
f4c956ad	101	dev_priv->regfile.saveCR[0x11] &= ~0x80;
317c35d1 JB	102
	103	/* Attribute controller registers */
	104	I915_READ8(st01);
f4c956ad	105	dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
317c35d1	106	for (i = 0; i <= 0x14; i++)
f4c956ad	107	dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
317c35d1	108	I915_READ8(st01);
f4c956ad	109	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
317c35d1 JB	110	I915_READ8(st01);
	111
	112	/* Graphics controller registers */
	113	for (i = 0; i < 9; i++)
f4c956ad	114	dev_priv->regfile.saveGR[i] =
317c35d1 JB	115	i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
317c35d1 JB	116
f4c956ad	117	dev_priv->regfile.saveGR[0x10] =
317c35d1	118	i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
f4c956ad	119	dev_priv->regfile.saveGR[0x11] =
317c35d1	120	i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
f4c956ad	121	dev_priv->regfile.saveGR[0x18] =
317c35d1 JB	122	i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
	123
	124	/* Sequencer registers */
	125	for (i = 0; i < 8; i++)
f4c956ad	126	dev_priv->regfile.saveSR[i] =
317c35d1 JB	127	i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
	128	}
	129
	130	static void i915_restore_vga(struct drm_device *dev)
	131	{
	132	struct drm_i915_private *dev_priv = dev->dev_private;
	133	int i;
	134	u16 cr_index, cr_data, st01;
	135
44cec740	136	/* VGA state */
766aa1c4	137	I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
44cec740 DV	138
	139	I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
	140	I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
	141	I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
	142	POSTING_READ(VGA_PD);
	143	udelay(150);
	144
317c35d1	145	/* MSR bits */
f4c956ad DV	146	I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
f4c956ad DV	147	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
317c35d1 JB	148	cr_index = VGA_CR_INDEX_CGA;
	149	cr_data = VGA_CR_DATA_CGA;
	150	st01 = VGA_ST01_CGA;
	151	} else {
	152	cr_index = VGA_CR_INDEX_MDA;
	153	cr_data = VGA_CR_DATA_MDA;
	154	st01 = VGA_ST01_MDA;
	155	}
	156
	157	/* Sequencer registers, don't write SR07 */
	158	for (i = 0; i < 7; i++)
	159	i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
f4c956ad	160	dev_priv->regfile.saveSR[i]);
317c35d1 JB	161
	162	/* CRT controller regs */
	163	/* Enable CR group 0 writes */
f4c956ad	164	i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
317c35d1	165	for (i = 0; i <= 0x24; i++)
f4c956ad	166	i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
317c35d1 JB	167
	168	/* Graphics controller regs */
	169	for (i = 0; i < 9; i++)
	170	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
f4c956ad	171	dev_priv->regfile.saveGR[i]);
317c35d1 JB	172
317c35d1 JB	173	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
f4c956ad	174	dev_priv->regfile.saveGR[0x10]);
317c35d1	175	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
f4c956ad	176	dev_priv->regfile.saveGR[0x11]);
317c35d1	177	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
f4c956ad	178	dev_priv->regfile.saveGR[0x18]);
317c35d1 JB	179
	180	/* Attribute controller registers */
	181	I915_READ8(st01); /* switch back to index mode */
	182	for (i = 0; i <= 0x14; i++)
f4c956ad	183	i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
317c35d1	184	I915_READ8(st01); /* switch back to index mode */
f4c956ad	185	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX \| 0x20);
317c35d1 JB	186	I915_READ8(st01);
	187
	188	/* VGA color palette registers */
f4c956ad	189	I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
317c35d1 JB	190	}
317c35d1 JB	191
d70bed19	192	static void i915_save_display(struct drm_device *dev)
fccdaba4 ZY	193	{
fccdaba4 ZY	194	struct drm_i915_private *dev_priv = dev->dev_private;
8ba2d185	195	unsigned long flags;
fccdaba4 ZY	196
fccdaba4 ZY	197	/* Display arbitration control */
8de0add7 PZ	198	if (INTEL_INFO(dev)->gen <= 4)
8de0add7 PZ	199	dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
fccdaba4 ZY	200
fccdaba4 ZY	201	/* This is only meaningful in non-KMS mode */
f4c956ad	202	/* Don't regfile.save them in KMS mode */
2e9723a3	203	if (!drm_core_check_feature(dev, DRIVER_MODESET))
d8157a36	204	i915_save_display_reg(dev);
1341d655	205
8ba2d185 JN	206	spin_lock_irqsave(&dev_priv->backlight.lock, flags);
8ba2d185 JN	207
317c35d1	208	/* LVDS state */
90eb77ba	209	if (HAS_PCH_SPLIT(dev)) {
f4c956ad DV	210	dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
	211	dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
	212	dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
	213	dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
	214	dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
4deb88a6 PZ	215	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
4deb88a6 PZ	216	dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
42048781	217	} else {
f4c956ad DV	218	dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
	219	dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
	220	dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
	221	dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
a6c45cf0	222	if (INTEL_INFO(dev)->gen >= 4)
f4c956ad	223	dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
42048781	224	if (IS_MOBILE(dev) && !IS_I830(dev))
f4c956ad	225	dev_priv->regfile.saveLVDS = I915_READ(LVDS);
42048781 ZW	226	}
42048781 ZW	227
8ba2d185 JN	228	spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
8ba2d185 JN	229
90eb77ba	230	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
f4c956ad	231	dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
42048781	232
90eb77ba	233	if (HAS_PCH_SPLIT(dev)) {
f4c956ad DV	234	dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
	235	dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
	236	dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
42048781	237	} else {
f4c956ad DV	238	dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
	239	dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
	240	dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
42048781	241	}
317c35d1	242
f4c956ad	243	/* Only regfile.save FBC state on the platform that supports FBC */
a2c459ee	244	if (I915_HAS_FBC(dev)) {
90eb77ba	245	if (HAS_PCH_SPLIT(dev)) {
f4c956ad	246	dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
b52eb4dc	247	} else if (IS_GM45(dev)) {
f4c956ad	248	dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
a2c459ee	249	} else {
f4c956ad DV	250	dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
	251	dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
	252	dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
	253	dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
a2c459ee	254	}
06027f91	255	}
317c35d1	256
44cec740 DV	257	if (!drm_core_check_feature(dev, DRIVER_MODESET))
44cec740 DV	258	i915_save_vga(dev);
317c35d1 JB	259	}
317c35d1 JB	260
d70bed19	261	static void i915_restore_display(struct drm_device *dev)
317c35d1 JB	262	{
317c35d1 JB	263	struct drm_i915_private *dev_priv = dev->dev_private;
2ec90668	264	u32 mask = 0xffffffff;
8ba2d185	265	unsigned long flags;
461cba2d	266
881ee988	267	/* Display arbitration */
8de0add7 PZ	268	if (INTEL_INFO(dev)->gen <= 4)
8de0add7 PZ	269	I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
317c35d1	270
2e9723a3	271	if (!drm_core_check_feature(dev, DRIVER_MODESET))
d8157a36	272	i915_restore_display_reg(dev);
1341d655	273
8ba2d185 JN	274	spin_lock_irqsave(&dev_priv->backlight.lock, flags);
8ba2d185 JN	275
317c35d1	276	/* LVDS state */
a6c45cf0	277	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
f4c956ad	278	I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
42048781	279
2ec90668 JB	280	if (drm_core_check_feature(dev, DRIVER_MODESET))
	281	mask = ~LVDS_PORT_EN;
	282
4deb88a6	283	if (HAS_PCH_IBX(dev) \|\| HAS_PCH_CPT(dev))
2ec90668	284	I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
4deb88a6	285	else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
2ec90668	286	I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
42048781	287
90eb77ba	288	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
f4c956ad	289	I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
317c35d1	290
90eb77ba	291	if (HAS_PCH_SPLIT(dev)) {
f4c956ad DV	292	I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
f4c956ad DV	293	I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
6db65cbb TI	294	/* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
	295	* otherwise we get blank eDP screen after S3 on some machines
	296	*/
f4c956ad DV	297	I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
	298	I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
	299	I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
	300	I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
	301	I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
	302	I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
88271da3	303	I915_WRITE(RSTDBYCTL,
f4c956ad	304	dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
42048781	305	} else {
f4c956ad DV	306	I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
	307	I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
	308	I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
	309	I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
	310	I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
	311	I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
	312	I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
42048781	313	}
317c35d1	314
8ba2d185 JN	315	spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
8ba2d185 JN	316
a2c459ee	317	/* only restore FBC info on the platform that supports FBC*/
43a9539f	318	intel_disable_fbc(dev);
a2c459ee	319	if (I915_HAS_FBC(dev)) {
90eb77ba	320	if (HAS_PCH_SPLIT(dev)) {
f4c956ad	321	I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
b52eb4dc	322	} else if (IS_GM45(dev)) {
f4c956ad	323	I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
a2c459ee	324	} else {
f4c956ad DV	325	I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
	326	I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
	327	I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
	328	I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
a2c459ee	329	}
06027f91	330	}
a65e827d	331
44cec740 DV	332	if (!drm_core_check_feature(dev, DRIVER_MODESET))
44cec740 DV	333	i915_restore_vga(dev);
42048781	334	else
44cec740	335	i915_redisable_vga(dev);
1341d655 BG	336	}
	337
	338	int i915_save_state(struct drm_device *dev)
	339	{
	340	struct drm_i915_private *dev_priv = dev->dev_private;
	341	int i;
	342
f4c956ad	343	pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);
1341d655	344
d70bed19 KP	345	mutex_lock(&dev->struct_mutex);
d70bed19 KP	346
1341d655 BG	347	i915_save_display(dev);
1341d655 BG	348
905c27bb DV	349	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
	350	/* Interrupt state */
	351	if (HAS_PCH_SPLIT(dev)) {
f4c956ad DV	352	dev_priv->regfile.saveDEIER = I915_READ(DEIER);
	353	dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
	354	dev_priv->regfile.saveGTIER = I915_READ(GTIER);
	355	dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
	356	dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
	357	dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
	358	dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
905c27bb	359	I915_READ(RSTDBYCTL);
f4c956ad	360	dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
905c27bb	361	} else {
f4c956ad DV	362	dev_priv->regfile.saveIER = I915_READ(IER);
f4c956ad DV	363	dev_priv->regfile.saveIMR = I915_READ(IMR);
905c27bb	364	}
42048781	365	}
1341d655	366
8090c6b9	367	intel_disable_gt_powersave(dev);
f97108d1	368
1341d655	369	/* Cache mode state */
f4c956ad	370	dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
1341d655 BG	371
1341d655 BG	372	/* Memory Arbitration state */
f4c956ad	373	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
1341d655 BG	374
	375	/* Scratch space */
	376	for (i = 0; i < 16; i++) {
f4c956ad DV	377	dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
f4c956ad DV	378	dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
1341d655 BG	379	}
1341d655 BG	380	for (i = 0; i < 3; i++)
f4c956ad	381	dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
1341d655	382
d70bed19 KP	383	mutex_unlock(&dev->struct_mutex);
d70bed19 KP	384
1341d655 BG	385	return 0;
	386	}
	387
	388	int i915_restore_state(struct drm_device *dev)
	389	{
	390	struct drm_i915_private *dev_priv = dev->dev_private;
	391	int i;
	392
f4c956ad	393	pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);
1341d655	394
d70bed19 KP	395	mutex_lock(&dev->struct_mutex);
d70bed19 KP	396
1341d655 BG	397	i915_restore_display(dev);
1341d655 BG	398
905c27bb DV	399	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
	400	/* Interrupt state */
	401	if (HAS_PCH_SPLIT(dev)) {
f4c956ad DV	402	I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
	403	I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
	404	I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
	405	I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
	406	I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
	407	I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
	408	I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
905c27bb	409	} else {
f4c956ad DV	410	I915_WRITE(IER, dev_priv->regfile.saveIER);
f4c956ad DV	411	I915_WRITE(IMR, dev_priv->regfile.saveIMR);
905c27bb	412	}
42048781	413	}
d70bed19	414
317c35d1	415	/* Cache mode state */
f4c956ad	416	I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 \| 0xffff0000);
317c35d1 JB	417
317c35d1 JB	418	/* Memory arbitration state */
f4c956ad	419	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE \| 0xffff0000);
317c35d1 JB	420
317c35d1 JB	421	for (i = 0; i < 16; i++) {
f4c956ad DV	422	I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
f4c956ad DV	423	I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
317c35d1 JB	424	}
317c35d1 JB	425	for (i = 0; i < 3; i++)
f4c956ad	426	I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
317c35d1	427
d70bed19 KP	428	mutex_unlock(&dev->struct_mutex);
d70bed19 KP	429
f899fc64	430	intel_i2c_reset(dev);
f0217c42	431
317c35d1 JB	432	return 0;
317c35d1 JB	433	}