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317c35d1 JB |
1 | /* |
2 | * | |
3 | * Copyright 2008 (c) Intel Corporation | |
4 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | */ | |
26 | ||
27 | #include "drmP.h" | |
28 | #include "drm.h" | |
29 | #include "i915_drm.h" | |
30 | #include "i915_drv.h" | |
31 | ||
32 | static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) | |
33 | { | |
34 | struct drm_i915_private *dev_priv = dev->dev_private; | |
35 | ||
36 | if (pipe == PIPE_A) | |
37 | return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE); | |
38 | else | |
39 | return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE); | |
40 | } | |
41 | ||
42 | static void i915_save_palette(struct drm_device *dev, enum pipe pipe) | |
43 | { | |
44 | struct drm_i915_private *dev_priv = dev->dev_private; | |
45 | unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); | |
46 | u32 *array; | |
47 | int i; | |
48 | ||
49 | if (!i915_pipe_enabled(dev, pipe)) | |
50 | return; | |
51 | ||
52 | if (pipe == PIPE_A) | |
53 | array = dev_priv->save_palette_a; | |
54 | else | |
55 | array = dev_priv->save_palette_b; | |
56 | ||
57 | for(i = 0; i < 256; i++) | |
58 | array[i] = I915_READ(reg + (i << 2)); | |
59 | } | |
60 | ||
61 | static void i915_restore_palette(struct drm_device *dev, enum pipe pipe) | |
62 | { | |
63 | struct drm_i915_private *dev_priv = dev->dev_private; | |
64 | unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); | |
65 | u32 *array; | |
66 | int i; | |
67 | ||
68 | if (!i915_pipe_enabled(dev, pipe)) | |
69 | return; | |
70 | ||
71 | if (pipe == PIPE_A) | |
72 | array = dev_priv->save_palette_a; | |
73 | else | |
74 | array = dev_priv->save_palette_b; | |
75 | ||
76 | for(i = 0; i < 256; i++) | |
77 | I915_WRITE(reg + (i << 2), array[i]); | |
78 | } | |
79 | ||
80 | static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg) | |
81 | { | |
82 | struct drm_i915_private *dev_priv = dev->dev_private; | |
83 | ||
84 | I915_WRITE8(index_port, reg); | |
85 | return I915_READ8(data_port); | |
86 | } | |
87 | ||
88 | static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable) | |
89 | { | |
90 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91 | ||
92 | I915_READ8(st01); | |
93 | I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); | |
94 | return I915_READ8(VGA_AR_DATA_READ); | |
95 | } | |
96 | ||
97 | static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable) | |
98 | { | |
99 | struct drm_i915_private *dev_priv = dev->dev_private; | |
100 | ||
101 | I915_READ8(st01); | |
102 | I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); | |
103 | I915_WRITE8(VGA_AR_DATA_WRITE, val); | |
104 | } | |
105 | ||
106 | static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val) | |
107 | { | |
108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
109 | ||
110 | I915_WRITE8(index_port, reg); | |
111 | I915_WRITE8(data_port, val); | |
112 | } | |
113 | ||
114 | static void i915_save_vga(struct drm_device *dev) | |
115 | { | |
116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
117 | int i; | |
118 | u16 cr_index, cr_data, st01; | |
119 | ||
120 | /* VGA color palette registers */ | |
121 | dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK); | |
317c35d1 JB |
122 | |
123 | /* MSR bits */ | |
124 | dev_priv->saveMSR = I915_READ8(VGA_MSR_READ); | |
125 | if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { | |
126 | cr_index = VGA_CR_INDEX_CGA; | |
127 | cr_data = VGA_CR_DATA_CGA; | |
128 | st01 = VGA_ST01_CGA; | |
129 | } else { | |
130 | cr_index = VGA_CR_INDEX_MDA; | |
131 | cr_data = VGA_CR_DATA_MDA; | |
132 | st01 = VGA_ST01_MDA; | |
133 | } | |
134 | ||
135 | /* CRT controller regs */ | |
136 | i915_write_indexed(dev, cr_index, cr_data, 0x11, | |
137 | i915_read_indexed(dev, cr_index, cr_data, 0x11) & | |
138 | (~0x80)); | |
139 | for (i = 0; i <= 0x24; i++) | |
140 | dev_priv->saveCR[i] = | |
141 | i915_read_indexed(dev, cr_index, cr_data, i); | |
142 | /* Make sure we don't turn off CR group 0 writes */ | |
143 | dev_priv->saveCR[0x11] &= ~0x80; | |
144 | ||
145 | /* Attribute controller registers */ | |
146 | I915_READ8(st01); | |
147 | dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX); | |
148 | for (i = 0; i <= 0x14; i++) | |
149 | dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0); | |
150 | I915_READ8(st01); | |
151 | I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX); | |
152 | I915_READ8(st01); | |
153 | ||
154 | /* Graphics controller registers */ | |
155 | for (i = 0; i < 9; i++) | |
156 | dev_priv->saveGR[i] = | |
157 | i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i); | |
158 | ||
159 | dev_priv->saveGR[0x10] = | |
160 | i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10); | |
161 | dev_priv->saveGR[0x11] = | |
162 | i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11); | |
163 | dev_priv->saveGR[0x18] = | |
164 | i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18); | |
165 | ||
166 | /* Sequencer registers */ | |
167 | for (i = 0; i < 8; i++) | |
168 | dev_priv->saveSR[i] = | |
169 | i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i); | |
170 | } | |
171 | ||
172 | static void i915_restore_vga(struct drm_device *dev) | |
173 | { | |
174 | struct drm_i915_private *dev_priv = dev->dev_private; | |
175 | int i; | |
176 | u16 cr_index, cr_data, st01; | |
177 | ||
178 | /* MSR bits */ | |
179 | I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR); | |
180 | if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { | |
181 | cr_index = VGA_CR_INDEX_CGA; | |
182 | cr_data = VGA_CR_DATA_CGA; | |
183 | st01 = VGA_ST01_CGA; | |
184 | } else { | |
185 | cr_index = VGA_CR_INDEX_MDA; | |
186 | cr_data = VGA_CR_DATA_MDA; | |
187 | st01 = VGA_ST01_MDA; | |
188 | } | |
189 | ||
190 | /* Sequencer registers, don't write SR07 */ | |
191 | for (i = 0; i < 7; i++) | |
192 | i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i, | |
193 | dev_priv->saveSR[i]); | |
194 | ||
195 | /* CRT controller regs */ | |
196 | /* Enable CR group 0 writes */ | |
197 | i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]); | |
198 | for (i = 0; i <= 0x24; i++) | |
199 | i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]); | |
200 | ||
201 | /* Graphics controller regs */ | |
202 | for (i = 0; i < 9; i++) | |
203 | i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i, | |
204 | dev_priv->saveGR[i]); | |
205 | ||
206 | i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10, | |
207 | dev_priv->saveGR[0x10]); | |
208 | i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11, | |
209 | dev_priv->saveGR[0x11]); | |
210 | i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18, | |
211 | dev_priv->saveGR[0x18]); | |
212 | ||
213 | /* Attribute controller registers */ | |
214 | I915_READ8(st01); /* switch back to index mode */ | |
215 | for (i = 0; i <= 0x14; i++) | |
216 | i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0); | |
217 | I915_READ8(st01); /* switch back to index mode */ | |
218 | I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20); | |
219 | I915_READ8(st01); | |
220 | ||
221 | /* VGA color palette registers */ | |
222 | I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK); | |
317c35d1 JB |
223 | } |
224 | ||
225 | int i915_save_state(struct drm_device *dev) | |
226 | { | |
227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
228 | int i; | |
229 | ||
230 | pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); | |
231 | ||
881ee988 KP |
232 | /* Render Standby */ |
233 | if (IS_I965G(dev) && IS_MOBILE(dev)) | |
234 | dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY); | |
235 | ||
461cba2d PL |
236 | /* Hardware status page */ |
237 | dev_priv->saveHWS = I915_READ(HWS_PGA); | |
238 | ||
317c35d1 JB |
239 | /* Display arbitration control */ |
240 | dev_priv->saveDSPARB = I915_READ(DSPARB); | |
241 | ||
242 | /* Pipe & plane A info */ | |
243 | dev_priv->savePIPEACONF = I915_READ(PIPEACONF); | |
244 | dev_priv->savePIPEASRC = I915_READ(PIPEASRC); | |
245 | dev_priv->saveFPA0 = I915_READ(FPA0); | |
246 | dev_priv->saveFPA1 = I915_READ(FPA1); | |
247 | dev_priv->saveDPLL_A = I915_READ(DPLL_A); | |
248 | if (IS_I965G(dev)) | |
249 | dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); | |
250 | dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); | |
251 | dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); | |
252 | dev_priv->saveHSYNC_A = I915_READ(HSYNC_A); | |
253 | dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); | |
254 | dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); | |
255 | dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); | |
256 | dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); | |
257 | ||
258 | dev_priv->saveDSPACNTR = I915_READ(DSPACNTR); | |
259 | dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); | |
260 | dev_priv->saveDSPASIZE = I915_READ(DSPASIZE); | |
261 | dev_priv->saveDSPAPOS = I915_READ(DSPAPOS); | |
262 | dev_priv->saveDSPAADDR = I915_READ(DSPAADDR); | |
263 | if (IS_I965G(dev)) { | |
264 | dev_priv->saveDSPASURF = I915_READ(DSPASURF); | |
265 | dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); | |
266 | } | |
267 | i915_save_palette(dev, PIPE_A); | |
268 | dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT); | |
269 | ||
270 | /* Pipe & plane B info */ | |
271 | dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); | |
272 | dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); | |
273 | dev_priv->saveFPB0 = I915_READ(FPB0); | |
274 | dev_priv->saveFPB1 = I915_READ(FPB1); | |
275 | dev_priv->saveDPLL_B = I915_READ(DPLL_B); | |
276 | if (IS_I965G(dev)) | |
277 | dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); | |
278 | dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); | |
279 | dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); | |
280 | dev_priv->saveHSYNC_B = I915_READ(HSYNC_B); | |
281 | dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); | |
282 | dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); | |
283 | dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); | |
284 | dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); | |
285 | ||
286 | dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR); | |
287 | dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); | |
288 | dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE); | |
289 | dev_priv->saveDSPBPOS = I915_READ(DSPBPOS); | |
290 | dev_priv->saveDSPBADDR = I915_READ(DSPBADDR); | |
b9bfdfe6 | 291 | if (IS_I965GM(dev) || IS_GM45(dev)) { |
317c35d1 JB |
292 | dev_priv->saveDSPBSURF = I915_READ(DSPBSURF); |
293 | dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); | |
294 | } | |
295 | i915_save_palette(dev, PIPE_B); | |
296 | dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT); | |
297 | ||
298 | /* CRT state */ | |
299 | dev_priv->saveADPA = I915_READ(ADPA); | |
300 | ||
301 | /* LVDS state */ | |
302 | dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL); | |
303 | dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); | |
304 | dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); | |
305 | if (IS_I965G(dev)) | |
306 | dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); | |
307 | if (IS_MOBILE(dev) && !IS_I830(dev)) | |
308 | dev_priv->saveLVDS = I915_READ(LVDS); | |
309 | if (!IS_I830(dev) && !IS_845G(dev)) | |
310 | dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); | |
311 | dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); | |
312 | dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); | |
313 | dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); | |
314 | ||
315 | /* FIXME: save TV & SDVO state */ | |
316 | ||
317 | /* FBC state */ | |
318 | dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); | |
319 | dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); | |
320 | dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); | |
321 | dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); | |
322 | ||
323 | /* Interrupt state */ | |
324 | dev_priv->saveIIR = I915_READ(IIR); | |
325 | dev_priv->saveIER = I915_READ(IER); | |
326 | dev_priv->saveIMR = I915_READ(IMR); | |
327 | ||
328 | /* VGA state */ | |
329 | dev_priv->saveVGA0 = I915_READ(VGA0); | |
330 | dev_priv->saveVGA1 = I915_READ(VGA1); | |
331 | dev_priv->saveVGA_PD = I915_READ(VGA_PD); | |
332 | dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); | |
333 | ||
334 | /* Clock gating state */ | |
335 | dev_priv->saveD_STATE = I915_READ(D_STATE); | |
336 | dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS); | |
337 | ||
338 | /* Cache mode state */ | |
339 | dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); | |
340 | ||
341 | /* Memory Arbitration state */ | |
342 | dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); | |
343 | ||
344 | /* Scratch space */ | |
345 | for (i = 0; i < 16; i++) { | |
346 | dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2)); | |
347 | dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2)); | |
348 | } | |
349 | for (i = 0; i < 3; i++) | |
350 | dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); | |
351 | ||
79f11c19 KP |
352 | /* Fences */ |
353 | if (IS_I965G(dev)) { | |
354 | for (i = 0; i < 16; i++) | |
355 | dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
356 | } else { | |
357 | for (i = 0; i < 8; i++) | |
358 | dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
359 | ||
360 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
361 | for (i = 0; i < 8; i++) | |
362 | dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
363 | } | |
317c35d1 JB |
364 | i915_save_vga(dev); |
365 | ||
366 | return 0; | |
367 | } | |
368 | ||
369 | int i915_restore_state(struct drm_device *dev) | |
370 | { | |
371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
372 | int i; | |
373 | ||
374 | pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); | |
375 | ||
881ee988 KP |
376 | /* Render Standby */ |
377 | if (IS_I965G(dev) && IS_MOBILE(dev)) | |
378 | I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY); | |
379 | ||
461cba2d PL |
380 | /* Hardware status page */ |
381 | I915_WRITE(HWS_PGA, dev_priv->saveHWS); | |
382 | ||
881ee988 | 383 | /* Display arbitration */ |
317c35d1 JB |
384 | I915_WRITE(DSPARB, dev_priv->saveDSPARB); |
385 | ||
79f11c19 KP |
386 | /* Fences */ |
387 | if (IS_I965G(dev)) { | |
388 | for (i = 0; i < 16; i++) | |
389 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]); | |
390 | } else { | |
391 | for (i = 0; i < 8; i++) | |
392 | I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]); | |
393 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
394 | for (i = 0; i < 8; i++) | |
395 | I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]); | |
396 | } | |
397 | ||
317c35d1 JB |
398 | /* Pipe & plane A info */ |
399 | /* Prime the clock */ | |
400 | if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { | |
401 | I915_WRITE(DPLL_A, dev_priv->saveDPLL_A & | |
402 | ~DPLL_VCO_ENABLE); | |
403 | DRM_UDELAY(150); | |
404 | } | |
405 | I915_WRITE(FPA0, dev_priv->saveFPA0); | |
406 | I915_WRITE(FPA1, dev_priv->saveFPA1); | |
407 | /* Actually enable it */ | |
408 | I915_WRITE(DPLL_A, dev_priv->saveDPLL_A); | |
409 | DRM_UDELAY(150); | |
410 | if (IS_I965G(dev)) | |
411 | I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); | |
412 | DRM_UDELAY(150); | |
413 | ||
414 | /* Restore mode */ | |
415 | I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A); | |
416 | I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A); | |
417 | I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A); | |
418 | I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); | |
419 | I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); | |
420 | I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); | |
421 | I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); | |
422 | ||
423 | /* Restore plane info */ | |
424 | I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); | |
425 | I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS); | |
426 | I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC); | |
427 | I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR); | |
428 | I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE); | |
429 | if (IS_I965G(dev)) { | |
430 | I915_WRITE(DSPASURF, dev_priv->saveDSPASURF); | |
431 | I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF); | |
432 | } | |
433 | ||
434 | I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF); | |
435 | ||
436 | i915_restore_palette(dev, PIPE_A); | |
437 | /* Enable the plane */ | |
438 | I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR); | |
439 | I915_WRITE(DSPAADDR, I915_READ(DSPAADDR)); | |
440 | ||
441 | /* Pipe & plane B info */ | |
442 | if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { | |
443 | I915_WRITE(DPLL_B, dev_priv->saveDPLL_B & | |
444 | ~DPLL_VCO_ENABLE); | |
445 | DRM_UDELAY(150); | |
446 | } | |
447 | I915_WRITE(FPB0, dev_priv->saveFPB0); | |
448 | I915_WRITE(FPB1, dev_priv->saveFPB1); | |
449 | /* Actually enable it */ | |
450 | I915_WRITE(DPLL_B, dev_priv->saveDPLL_B); | |
451 | DRM_UDELAY(150); | |
452 | if (IS_I965G(dev)) | |
453 | I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); | |
454 | DRM_UDELAY(150); | |
455 | ||
456 | /* Restore mode */ | |
457 | I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B); | |
458 | I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B); | |
459 | I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B); | |
460 | I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); | |
461 | I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); | |
462 | I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); | |
463 | I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); | |
464 | ||
465 | /* Restore plane info */ | |
466 | I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); | |
467 | I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS); | |
468 | I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC); | |
469 | I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR); | |
470 | I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); | |
471 | if (IS_I965G(dev)) { | |
472 | I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF); | |
473 | I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF); | |
474 | } | |
475 | ||
476 | I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF); | |
477 | ||
478 | i915_restore_palette(dev, PIPE_B); | |
479 | /* Enable the plane */ | |
480 | I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); | |
481 | I915_WRITE(DSPBADDR, I915_READ(DSPBADDR)); | |
482 | ||
483 | /* CRT state */ | |
484 | I915_WRITE(ADPA, dev_priv->saveADPA); | |
485 | ||
486 | /* LVDS state */ | |
487 | if (IS_I965G(dev)) | |
488 | I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); | |
489 | if (IS_MOBILE(dev) && !IS_I830(dev)) | |
490 | I915_WRITE(LVDS, dev_priv->saveLVDS); | |
491 | if (!IS_I830(dev) && !IS_845G(dev)) | |
492 | I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); | |
493 | ||
494 | I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); | |
495 | I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); | |
496 | I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); | |
497 | I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); | |
498 | I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); | |
499 | I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); | |
500 | ||
501 | /* FIXME: restore TV & SDVO state */ | |
502 | ||
503 | /* FBC info */ | |
504 | I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE); | |
505 | I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE); | |
506 | I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2); | |
507 | I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL); | |
508 | ||
509 | /* VGA state */ | |
510 | I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); | |
511 | I915_WRITE(VGA0, dev_priv->saveVGA0); | |
512 | I915_WRITE(VGA1, dev_priv->saveVGA1); | |
513 | I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); | |
514 | DRM_UDELAY(150); | |
515 | ||
516 | /* Clock gating state */ | |
517 | I915_WRITE (D_STATE, dev_priv->saveD_STATE); | |
518 | I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS); | |
519 | ||
520 | /* Cache mode state */ | |
521 | I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); | |
522 | ||
523 | /* Memory arbitration state */ | |
524 | I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); | |
525 | ||
526 | for (i = 0; i < 16; i++) { | |
527 | I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]); | |
528 | I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]); | |
529 | } | |
530 | for (i = 0; i < 3; i++) | |
531 | I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); | |
532 | ||
533 | i915_restore_vga(dev); | |
534 | ||
535 | return 0; | |
536 | } | |
537 |