[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_suspend.c

/*
 *
 * Copyright 2008 (c) Intel Corporation
 *   Jesse Barnes <jbarnes@virtuousgeek.org>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "intel_drv.h"
#include "i915_reg.h"

static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE8(index_port, reg);
	return I915_READ8(data_port);
}

static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_READ8(st01);
	I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
	return I915_READ8(VGA_AR_DATA_READ);
}

static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_READ8(st01);
	I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
	I915_WRITE8(VGA_AR_DATA_WRITE, val);
}

static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE8(index_port, reg);
	I915_WRITE8(data_port, val);
}

static void i915_save_vga(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;
	u16 cr_index, cr_data, st01;

	/* VGA state */
	dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
	dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
	dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
	if (HAS_PCH_SPLIT(dev))
		dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
	else
		dev_priv->regfile.saveVGACNTRL = I915_READ(VGACNTRL);

	/* VGA color palette registers */
	dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);

	/* MSR bits */
	dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
		cr_index = VGA_CR_INDEX_CGA;
		cr_data = VGA_CR_DATA_CGA;
		st01 = VGA_ST01_CGA;
	} else {
		cr_index = VGA_CR_INDEX_MDA;
		cr_data = VGA_CR_DATA_MDA;
		st01 = VGA_ST01_MDA;
	}

	/* CRT controller regs */
	i915_write_indexed(dev, cr_index, cr_data, 0x11,
			   i915_read_indexed(dev, cr_index, cr_data, 0x11) &
			   (~0x80));
	for (i = 0; i <= 0x24; i++)
		dev_priv->regfile.saveCR[i] =
			i915_read_indexed(dev, cr_index, cr_data, i);
	/* Make sure we don't turn off CR group 0 writes */
	dev_priv->regfile.saveCR[0x11] &= ~0x80;

	/* Attribute controller registers */
	I915_READ8(st01);
	dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
	for (i = 0; i <= 0x14; i++)
		dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
	I915_READ8(st01);
	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
	I915_READ8(st01);

	/* Graphics controller registers */
	for (i = 0; i < 9; i++)
		dev_priv->regfile.saveGR[i] =
			i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);

	dev_priv->regfile.saveGR[0x10] =
		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
	dev_priv->regfile.saveGR[0x11] =
		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
	dev_priv->regfile.saveGR[0x18] =
		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);

	/* Sequencer registers */
	for (i = 0; i < 8; i++)
		dev_priv->regfile.saveSR[i] =
			i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
}

static void i915_restore_vga(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;
	u16 cr_index, cr_data, st01;

	/* VGA state */
	if (HAS_PCH_SPLIT(dev))
		I915_WRITE(CPU_VGACNTRL, dev_priv->regfile.saveVGACNTRL);
	else
		I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);

	I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
	I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
	I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
	POSTING_READ(VGA_PD);
	udelay(150);

	/* MSR bits */
	I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
		cr_index = VGA_CR_INDEX_CGA;
		cr_data = VGA_CR_DATA_CGA;
		st01 = VGA_ST01_CGA;
	} else {
		cr_index = VGA_CR_INDEX_MDA;
		cr_data = VGA_CR_DATA_MDA;
		st01 = VGA_ST01_MDA;
	}

	/* Sequencer registers, don't write SR07 */
	for (i = 0; i < 7; i++)
		i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
				   dev_priv->regfile.saveSR[i]);

	/* CRT controller regs */
	/* Enable CR group 0 writes */
	i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
	for (i = 0; i <= 0x24; i++)
		i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);

	/* Graphics controller regs */
	for (i = 0; i < 9; i++)
		i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
				   dev_priv->regfile.saveGR[i]);

	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
			   dev_priv->regfile.saveGR[0x10]);
	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
			   dev_priv->regfile.saveGR[0x11]);
	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
			   dev_priv->regfile.saveGR[0x18]);

	/* Attribute controller registers */
	I915_READ8(st01); /* switch back to index mode */
	for (i = 0; i <= 0x14; i++)
		i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
	I915_READ8(st01); /* switch back to index mode */
	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
	I915_READ8(st01);

	/* VGA color palette registers */
	I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
}

static void i915_save_display(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* Display arbitration control */
	if (INTEL_INFO(dev)->gen <= 4)
		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);

	/* This is only meaningful in non-KMS mode */
	/* Don't regfile.save them in KMS mode */
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		i915_save_display_reg(dev);

	/* LVDS state */
	if (HAS_PCH_SPLIT(dev)) {
		dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
		dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
		dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
		dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
		dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
	} else {
		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
		dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
		if (INTEL_INFO(dev)->gen >= 4)
			dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
		if (IS_MOBILE(dev) && !IS_I830(dev))
			dev_priv->regfile.saveLVDS = I915_READ(LVDS);
	}

	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
		dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);

	if (HAS_PCH_SPLIT(dev)) {
		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
	} else {
		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
		dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
	}

	/* Only regfile.save FBC state on the platform that supports FBC */
	if (I915_HAS_FBC(dev)) {
		if (HAS_PCH_SPLIT(dev)) {
			dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
		} else if (IS_GM45(dev)) {
			dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
		} else {
			dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
			dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
			dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
			dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
		}
	}

	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		i915_save_vga(dev);
}

static void i915_restore_display(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* Display arbitration */
	if (INTEL_INFO(dev)->gen <= 4)
		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);

	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		i915_restore_display_reg(dev);

	/* LVDS state */
	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
		I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);

	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS);
	} else if (IS_MOBILE(dev) && !IS_I830(dev))
		I915_WRITE(LVDS, dev_priv->regfile.saveLVDS);

	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
		I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);

	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
		I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
		/* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
		 * otherwise we get blank eDP screen after S3 on some machines
		 */
		I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
		I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
		I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
		I915_WRITE(RSTDBYCTL,
			   dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
	} else {
		I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
		I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
		I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
		I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
		I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
		I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
		I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
	}

	/* only restore FBC info on the platform that supports FBC*/
	intel_disable_fbc(dev);
	if (I915_HAS_FBC(dev)) {
		if (HAS_PCH_SPLIT(dev)) {
			I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
		} else if (IS_GM45(dev)) {
			I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
		} else {
			I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
			I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
			I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
			I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
		}
	}

	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		i915_restore_vga(dev);
	else
		i915_redisable_vga(dev);
}

int i915_save_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);

	mutex_lock(&dev->struct_mutex);

	i915_save_display(dev);

	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
		/* Interrupt state */
		if (HAS_PCH_SPLIT(dev)) {
			dev_priv->regfile.saveDEIER = I915_READ(DEIER);
			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
			dev_priv->regfile.saveGTIER = I915_READ(GTIER);
			dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
			dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
			dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
			dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
				I915_READ(RSTDBYCTL);
			dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
		} else {
			dev_priv->regfile.saveIER = I915_READ(IER);
			dev_priv->regfile.saveIMR = I915_READ(IMR);
		}
	}

	intel_disable_gt_powersave(dev);

	/* Cache mode state */
	dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);

	/* Memory Arbitration state */
	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);

	/* Scratch space */
	for (i = 0; i < 16; i++) {
		dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
		dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
	}
	for (i = 0; i < 3; i++)
		dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));

	mutex_unlock(&dev->struct_mutex);

	return 0;
}

int i915_restore_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);

	mutex_lock(&dev->struct_mutex);

	i915_restore_display(dev);

	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
		/* Interrupt state */
		if (HAS_PCH_SPLIT(dev)) {
			I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
			I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
			I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
			I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
			I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
			I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
			I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
		} else {
			I915_WRITE(IER, dev_priv->regfile.saveIER);
			I915_WRITE(IMR, dev_priv->regfile.saveIMR);
		}
	}

	/* Cache mode state */
	I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);

	/* Memory arbitration state */
	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);

	for (i = 0; i < 16; i++) {
		I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
		I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
	}
	for (i = 0; i < 3; i++)
		I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);

	mutex_unlock(&dev->struct_mutex);

	intel_i2c_reset(dev);

	return 0;
}
Commit	Line	Data
317c35d1 JB	1	/*
	2	*
	3	* Copyright 2008 (c) Intel Corporation
	4	* Jesse Barnes <jbarnes@virtuousgeek.org>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the
	8	* "Software"), to deal in the Software without restriction, including
	9	* without limitation the rights to use, copy, modify, merge, publish,
	10	* distribute, sub license, and/or sell copies of the Software, and to
	11	* permit persons to whom the Software is furnished to do so, subject to
	12	* the following conditions:
	13	*
	14	* The above copyright notice and this permission notice (including the
	15	* next paragraph) shall be included in all copies or substantial portions
	16	* of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	19	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	20	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
	21	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
	22	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
	23	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
	24	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	25	*/
	26
760285e7 DH	27	#include <drm/drmP.h>
760285e7 DH	28	#include <drm/i915_drm.h>
f0217c42	29	#include "intel_drv.h"
5e5b7fa2	30	#include "i915_reg.h"
317c35d1	31
317c35d1 JB	32	static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
	33	{
	34	struct drm_i915_private *dev_priv = dev->dev_private;
	35
	36	I915_WRITE8(index_port, reg);
	37	return I915_READ8(data_port);
	38	}
	39
	40	static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
	41	{
	42	struct drm_i915_private *dev_priv = dev->dev_private;
	43
	44	I915_READ8(st01);
	45	I915_WRITE8(VGA_AR_INDEX, palette_enable \| reg);
	46	return I915_READ8(VGA_AR_DATA_READ);
	47	}
	48
	49	static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
	50	{
	51	struct drm_i915_private *dev_priv = dev->dev_private;
	52
	53	I915_READ8(st01);
	54	I915_WRITE8(VGA_AR_INDEX, palette_enable \| reg);
	55	I915_WRITE8(VGA_AR_DATA_WRITE, val);
	56	}
	57
	58	static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
	59	{
	60	struct drm_i915_private *dev_priv = dev->dev_private;
	61
	62	I915_WRITE8(index_port, reg);
	63	I915_WRITE8(data_port, val);
	64	}
	65
	66	static void i915_save_vga(struct drm_device *dev)
	67	{
	68	struct drm_i915_private *dev_priv = dev->dev_private;
	69	int i;
	70	u16 cr_index, cr_data, st01;
	71
44cec740 DV	72	/* VGA state */
	73	dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
	74	dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
	75	dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
	76	if (HAS_PCH_SPLIT(dev))
	77	dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
	78	else
	79	dev_priv->regfile.saveVGACNTRL = I915_READ(VGACNTRL);
	80
317c35d1	81	/* VGA color palette registers */
f4c956ad	82	dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
317c35d1 JB	83
317c35d1 JB	84	/* MSR bits */
f4c956ad DV	85	dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
f4c956ad DV	86	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
317c35d1 JB	87	cr_index = VGA_CR_INDEX_CGA;
	88	cr_data = VGA_CR_DATA_CGA;
	89	st01 = VGA_ST01_CGA;
	90	} else {
	91	cr_index = VGA_CR_INDEX_MDA;
	92	cr_data = VGA_CR_DATA_MDA;
	93	st01 = VGA_ST01_MDA;
	94	}
	95
	96	/* CRT controller regs */
	97	i915_write_indexed(dev, cr_index, cr_data, 0x11,
	98	i915_read_indexed(dev, cr_index, cr_data, 0x11) &
	99	(~0x80));
	100	for (i = 0; i <= 0x24; i++)
f4c956ad	101	dev_priv->regfile.saveCR[i] =
317c35d1 JB	102	i915_read_indexed(dev, cr_index, cr_data, i);
317c35d1 JB	103	/* Make sure we don't turn off CR group 0 writes */
f4c956ad	104	dev_priv->regfile.saveCR[0x11] &= ~0x80;
317c35d1 JB	105
	106	/* Attribute controller registers */
	107	I915_READ8(st01);
f4c956ad	108	dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
317c35d1	109	for (i = 0; i <= 0x14; i++)
f4c956ad	110	dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
317c35d1	111	I915_READ8(st01);
f4c956ad	112	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
317c35d1 JB	113	I915_READ8(st01);
	114
	115	/* Graphics controller registers */
	116	for (i = 0; i < 9; i++)
f4c956ad	117	dev_priv->regfile.saveGR[i] =
317c35d1 JB	118	i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
317c35d1 JB	119
f4c956ad	120	dev_priv->regfile.saveGR[0x10] =
317c35d1	121	i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
f4c956ad	122	dev_priv->regfile.saveGR[0x11] =
317c35d1	123	i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
f4c956ad	124	dev_priv->regfile.saveGR[0x18] =
317c35d1 JB	125	i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
	126
	127	/* Sequencer registers */
	128	for (i = 0; i < 8; i++)
f4c956ad	129	dev_priv->regfile.saveSR[i] =
317c35d1 JB	130	i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
	131	}
	132
	133	static void i915_restore_vga(struct drm_device *dev)
	134	{
	135	struct drm_i915_private *dev_priv = dev->dev_private;
	136	int i;
	137	u16 cr_index, cr_data, st01;
	138
44cec740 DV	139	/* VGA state */
	140	if (HAS_PCH_SPLIT(dev))
	141	I915_WRITE(CPU_VGACNTRL, dev_priv->regfile.saveVGACNTRL);
	142	else
	143	I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
	144
	145	I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
	146	I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
	147	I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
	148	POSTING_READ(VGA_PD);
	149	udelay(150);
	150
317c35d1	151	/* MSR bits */
f4c956ad DV	152	I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
f4c956ad DV	153	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
317c35d1 JB	154	cr_index = VGA_CR_INDEX_CGA;
	155	cr_data = VGA_CR_DATA_CGA;
	156	st01 = VGA_ST01_CGA;
	157	} else {
	158	cr_index = VGA_CR_INDEX_MDA;
	159	cr_data = VGA_CR_DATA_MDA;
	160	st01 = VGA_ST01_MDA;
	161	}
	162
	163	/* Sequencer registers, don't write SR07 */
	164	for (i = 0; i < 7; i++)
	165	i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
f4c956ad	166	dev_priv->regfile.saveSR[i]);
317c35d1 JB	167
	168	/* CRT controller regs */
	169	/* Enable CR group 0 writes */
f4c956ad	170	i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
317c35d1	171	for (i = 0; i <= 0x24; i++)
f4c956ad	172	i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
317c35d1 JB	173
	174	/* Graphics controller regs */
	175	for (i = 0; i < 9; i++)
	176	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
f4c956ad	177	dev_priv->regfile.saveGR[i]);
317c35d1 JB	178
317c35d1 JB	179	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
f4c956ad	180	dev_priv->regfile.saveGR[0x10]);
317c35d1	181	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
f4c956ad	182	dev_priv->regfile.saveGR[0x11]);
317c35d1	183	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
f4c956ad	184	dev_priv->regfile.saveGR[0x18]);
317c35d1 JB	185
	186	/* Attribute controller registers */
	187	I915_READ8(st01); /* switch back to index mode */
	188	for (i = 0; i <= 0x14; i++)
f4c956ad	189	i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
317c35d1	190	I915_READ8(st01); /* switch back to index mode */
f4c956ad	191	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX \| 0x20);
317c35d1 JB	192	I915_READ8(st01);
	193
	194	/* VGA color palette registers */
f4c956ad	195	I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
317c35d1 JB	196	}
317c35d1 JB	197
d70bed19	198	static void i915_save_display(struct drm_device *dev)
fccdaba4 ZY	199	{
fccdaba4 ZY	200	struct drm_i915_private *dev_priv = dev->dev_private;
fccdaba4 ZY	201
fccdaba4 ZY	202	/* Display arbitration control */
8de0add7 PZ	203	if (INTEL_INFO(dev)->gen <= 4)
8de0add7 PZ	204	dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
fccdaba4 ZY	205
fccdaba4 ZY	206	/* This is only meaningful in non-KMS mode */
f4c956ad	207	/* Don't regfile.save them in KMS mode */
2e9723a3	208	if (!drm_core_check_feature(dev, DRIVER_MODESET))
d8157a36	209	i915_save_display_reg(dev);
1341d655	210
317c35d1	211	/* LVDS state */
90eb77ba	212	if (HAS_PCH_SPLIT(dev)) {
f4c956ad DV	213	dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
	214	dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
	215	dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
	216	dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
	217	dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
	218	dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
42048781	219	} else {
f4c956ad DV	220	dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
	221	dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
	222	dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
	223	dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
a6c45cf0	224	if (INTEL_INFO(dev)->gen >= 4)
f4c956ad	225	dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
42048781	226	if (IS_MOBILE(dev) && !IS_I830(dev))
f4c956ad	227	dev_priv->regfile.saveLVDS = I915_READ(LVDS);
42048781 ZW	228	}
42048781 ZW	229
90eb77ba	230	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
f4c956ad	231	dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
42048781	232
90eb77ba	233	if (HAS_PCH_SPLIT(dev)) {
f4c956ad DV	234	dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
	235	dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
	236	dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
42048781	237	} else {
f4c956ad DV	238	dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
	239	dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
	240	dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
42048781	241	}
317c35d1	242
f4c956ad	243	/* Only regfile.save FBC state on the platform that supports FBC */
a2c459ee	244	if (I915_HAS_FBC(dev)) {
90eb77ba	245	if (HAS_PCH_SPLIT(dev)) {
f4c956ad	246	dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
b52eb4dc	247	} else if (IS_GM45(dev)) {
f4c956ad	248	dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
a2c459ee	249	} else {
f4c956ad DV	250	dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
	251	dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
	252	dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
	253	dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
a2c459ee	254	}
06027f91	255	}
317c35d1	256
44cec740 DV	257	if (!drm_core_check_feature(dev, DRIVER_MODESET))
44cec740 DV	258	i915_save_vga(dev);
317c35d1 JB	259	}
317c35d1 JB	260
d70bed19	261	static void i915_restore_display(struct drm_device *dev)
317c35d1 JB	262	{
317c35d1 JB	263	struct drm_i915_private *dev_priv = dev->dev_private;
461cba2d	264
881ee988	265	/* Display arbitration */
8de0add7 PZ	266	if (INTEL_INFO(dev)->gen <= 4)
8de0add7 PZ	267	I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
317c35d1	268
2e9723a3	269	if (!drm_core_check_feature(dev, DRIVER_MODESET))
d8157a36	270	i915_restore_display_reg(dev);
1341d655	271
317c35d1	272	/* LVDS state */
a6c45cf0	273	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
f4c956ad	274	I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
42048781	275
90eb77ba	276	if (HAS_PCH_SPLIT(dev)) {
f4c956ad	277	I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS);
42048781	278	} else if (IS_MOBILE(dev) && !IS_I830(dev))
f4c956ad	279	I915_WRITE(LVDS, dev_priv->regfile.saveLVDS);
42048781	280
90eb77ba	281	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
f4c956ad	282	I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
317c35d1	283
90eb77ba	284	if (HAS_PCH_SPLIT(dev)) {
f4c956ad DV	285	I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
f4c956ad DV	286	I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
6db65cbb TI	287	/* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
	288	* otherwise we get blank eDP screen after S3 on some machines
	289	*/
f4c956ad DV	290	I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
	291	I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
	292	I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
	293	I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
	294	I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
	295	I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
88271da3	296	I915_WRITE(RSTDBYCTL,
f4c956ad	297	dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
42048781	298	} else {
f4c956ad DV	299	I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
	300	I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
	301	I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
	302	I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
	303	I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
	304	I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
	305	I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
42048781	306	}
317c35d1	307
a2c459ee	308	/* only restore FBC info on the platform that supports FBC*/
43a9539f	309	intel_disable_fbc(dev);
a2c459ee	310	if (I915_HAS_FBC(dev)) {
90eb77ba	311	if (HAS_PCH_SPLIT(dev)) {
f4c956ad	312	I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
b52eb4dc	313	} else if (IS_GM45(dev)) {
f4c956ad	314	I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
a2c459ee	315	} else {
f4c956ad DV	316	I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
	317	I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
	318	I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
	319	I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
a2c459ee	320	}
06027f91	321	}
a65e827d	322
44cec740 DV	323	if (!drm_core_check_feature(dev, DRIVER_MODESET))
44cec740 DV	324	i915_restore_vga(dev);
42048781	325	else
44cec740	326	i915_redisable_vga(dev);
1341d655 BG	327	}
	328
	329	int i915_save_state(struct drm_device *dev)
	330	{
	331	struct drm_i915_private *dev_priv = dev->dev_private;
	332	int i;
	333
f4c956ad	334	pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);
1341d655	335
d70bed19 KP	336	mutex_lock(&dev->struct_mutex);
d70bed19 KP	337
1341d655 BG	338	i915_save_display(dev);
1341d655 BG	339
905c27bb DV	340	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
	341	/* Interrupt state */
	342	if (HAS_PCH_SPLIT(dev)) {
f4c956ad DV	343	dev_priv->regfile.saveDEIER = I915_READ(DEIER);
	344	dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
	345	dev_priv->regfile.saveGTIER = I915_READ(GTIER);
	346	dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
	347	dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
	348	dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
	349	dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
905c27bb	350	I915_READ(RSTDBYCTL);
f4c956ad	351	dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
905c27bb	352	} else {
f4c956ad DV	353	dev_priv->regfile.saveIER = I915_READ(IER);
f4c956ad DV	354	dev_priv->regfile.saveIMR = I915_READ(IMR);
905c27bb	355	}
42048781	356	}
1341d655	357
8090c6b9	358	intel_disable_gt_powersave(dev);
f97108d1	359
1341d655	360	/* Cache mode state */
f4c956ad	361	dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
1341d655 BG	362
1341d655 BG	363	/* Memory Arbitration state */
f4c956ad	364	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
1341d655 BG	365
	366	/* Scratch space */
	367	for (i = 0; i < 16; i++) {
f4c956ad DV	368	dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
f4c956ad DV	369	dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
1341d655 BG	370	}
1341d655 BG	371	for (i = 0; i < 3; i++)
f4c956ad	372	dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
1341d655	373
d70bed19 KP	374	mutex_unlock(&dev->struct_mutex);
d70bed19 KP	375
1341d655 BG	376	return 0;
	377	}
	378
	379	int i915_restore_state(struct drm_device *dev)
	380	{
	381	struct drm_i915_private *dev_priv = dev->dev_private;
	382	int i;
	383
f4c956ad	384	pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);
1341d655	385
d70bed19 KP	386	mutex_lock(&dev->struct_mutex);
d70bed19 KP	387
1341d655 BG	388	i915_restore_display(dev);
1341d655 BG	389
905c27bb DV	390	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
	391	/* Interrupt state */
	392	if (HAS_PCH_SPLIT(dev)) {
f4c956ad DV	393	I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
	394	I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
	395	I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
	396	I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
	397	I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
	398	I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
	399	I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
905c27bb	400	} else {
f4c956ad DV	401	I915_WRITE(IER, dev_priv->regfile.saveIER);
f4c956ad DV	402	I915_WRITE(IMR, dev_priv->regfile.saveIMR);
905c27bb	403	}
42048781	404	}
d70bed19	405
317c35d1	406	/* Cache mode state */
f4c956ad	407	I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 \| 0xffff0000);
317c35d1 JB	408
317c35d1 JB	409	/* Memory arbitration state */
f4c956ad	410	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE \| 0xffff0000);
317c35d1 JB	411
317c35d1 JB	412	for (i = 0; i < 16; i++) {
f4c956ad DV	413	I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
f4c956ad DV	414	I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
317c35d1 JB	415	}
317c35d1 JB	416	for (i = 0; i < 3; i++)
f4c956ad	417	I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
317c35d1	418
d70bed19 KP	419	mutex_unlock(&dev->struct_mutex);
d70bed19 KP	420
f899fc64	421	intel_i2c_reset(dev);
f0217c42	422
317c35d1 JB	423	return 0;
317c35d1 JB	424	}