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drm/i915: move the suspend/resume register file out of dev_priv
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_suspend.c
CommitLineData
317c35d1
JB		 1/*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/i915_drm.h>
f0217c42 29#include "intel_drv.h"
5e5b7fa2 30#include "i915_reg.h"
317c35d1
JB		 31
32static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
33{
34 struct drm_i915_private *dev_priv = dev->dev_private;
42048781 35 u32 dpll_reg;
317c35d1 36
07c1e8c1
ED		 37 /* On IVB, 3rd pipe shares PLL with another one */
38 if (pipe > 1)
39 return false;
40
9db4a9c7 41 if (HAS_PCH_SPLIT(dev))
ee7b9f93 42 dpll_reg = _PCH_DPLL(pipe);
9db4a9c7
JB		 43 else
44 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
42048781
ZW		 45
46 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
317c35d1
JB		 47}
48
49static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
50{
51 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 52 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
317c35d1
JB		 53 u32 *array;
54 int i;
55
56 if (!i915_pipe_enabled(dev, pipe))
57 return;
58
90eb77ba 59 if (HAS_PCH_SPLIT(dev))
9db4a9c7 60 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
42048781 61
317c35d1 62 if (pipe == PIPE_A)
f4c956ad 63 array = dev_priv->regfile.save_palette_a;
317c35d1 64 else
f4c956ad 65 array = dev_priv->regfile.save_palette_b;
317c35d1 66
0206e353 67 for (i = 0; i < 256; i++)
317c35d1
JB		 68 array[i] = I915_READ(reg + (i << 2));
69}
70
71static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
72{
73 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 74 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
317c35d1
JB		 75 u32 *array;
76 int i;
77
78 if (!i915_pipe_enabled(dev, pipe))
79 return;
80
90eb77ba 81 if (HAS_PCH_SPLIT(dev))
9db4a9c7 82 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
42048781 83
317c35d1 84 if (pipe == PIPE_A)
f4c956ad 85 array = dev_priv->regfile.save_palette_a;
317c35d1 86 else
f4c956ad 87 array = dev_priv->regfile.save_palette_b;
317c35d1 88
0206e353 89 for (i = 0; i < 256; i++)
317c35d1
JB		 90 I915_WRITE(reg + (i << 2), array[i]);
91}
92
93static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
94{
95 struct drm_i915_private *dev_priv = dev->dev_private;
96
97 I915_WRITE8(index_port, reg);
98 return I915_READ8(data_port);
99}
100
101static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
102{
103 struct drm_i915_private *dev_priv = dev->dev_private;
104
105 I915_READ8(st01);
106 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
107 return I915_READ8(VGA_AR_DATA_READ);
108}
109
110static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
111{
112 struct drm_i915_private *dev_priv = dev->dev_private;
113
114 I915_READ8(st01);
115 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
116 I915_WRITE8(VGA_AR_DATA_WRITE, val);
117}
118
119static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
120{
121 struct drm_i915_private *dev_priv = dev->dev_private;
122
123 I915_WRITE8(index_port, reg);
124 I915_WRITE8(data_port, val);
125}
126
127static void i915_save_vga(struct drm_device *dev)
128{
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 int i;
131 u16 cr_index, cr_data, st01;
132
133 /* VGA color palette registers */
f4c956ad 134 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
317c35d1
JB		 135
136 /* MSR bits */
f4c956ad
DV		 137 dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
138 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
317c35d1
JB		 139 cr_index = VGA_CR_INDEX_CGA;
140 cr_data = VGA_CR_DATA_CGA;
141 st01 = VGA_ST01_CGA;
142 } else {
143 cr_index = VGA_CR_INDEX_MDA;
144 cr_data = VGA_CR_DATA_MDA;
145 st01 = VGA_ST01_MDA;
146 }
147
148 /* CRT controller regs */
149 i915_write_indexed(dev, cr_index, cr_data, 0x11,
150 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
151 (~0x80));
152 for (i = 0; i <= 0x24; i++)
f4c956ad 153 dev_priv->regfile.saveCR[i] =
317c35d1
JB		 154 i915_read_indexed(dev, cr_index, cr_data, i);
155 /* Make sure we don't turn off CR group 0 writes */
f4c956ad 156 dev_priv->regfile.saveCR[0x11] &= ~0x80;
317c35d1
JB		 157
158 /* Attribute controller registers */
159 I915_READ8(st01);
f4c956ad 160 dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
317c35d1 161 for (i = 0; i <= 0x14; i++)
f4c956ad 162 dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
317c35d1 163 I915_READ8(st01);
f4c956ad 164 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
317c35d1
JB		 165 I915_READ8(st01);
166
167 /* Graphics controller registers */
168 for (i = 0; i < 9; i++)
f4c956ad 169 dev_priv->regfile.saveGR[i] =
317c35d1
JB		 170 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
171
f4c956ad 172 dev_priv->regfile.saveGR[0x10] =
317c35d1 173 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
f4c956ad 174 dev_priv->regfile.saveGR[0x11] =
317c35d1 175 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
f4c956ad 176 dev_priv->regfile.saveGR[0x18] =
317c35d1
JB		 177 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
178
179 /* Sequencer registers */
180 for (i = 0; i < 8; i++)
f4c956ad 181 dev_priv->regfile.saveSR[i] =
317c35d1
JB		 182 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
183}
184
185static void i915_restore_vga(struct drm_device *dev)
186{
187 struct drm_i915_private *dev_priv = dev->dev_private;
188 int i;
189 u16 cr_index, cr_data, st01;
190
191 /* MSR bits */
f4c956ad
DV		 192 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
193 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
317c35d1
JB		 194 cr_index = VGA_CR_INDEX_CGA;
195 cr_data = VGA_CR_DATA_CGA;
196 st01 = VGA_ST01_CGA;
197 } else {
198 cr_index = VGA_CR_INDEX_MDA;
199 cr_data = VGA_CR_DATA_MDA;
200 st01 = VGA_ST01_MDA;
201 }
202
203 /* Sequencer registers, don't write SR07 */
204 for (i = 0; i < 7; i++)
205 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
f4c956ad 206 dev_priv->regfile.saveSR[i]);
317c35d1
JB		 207
208 /* CRT controller regs */
209 /* Enable CR group 0 writes */
f4c956ad 210 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
317c35d1 211 for (i = 0; i <= 0x24; i++)
f4c956ad 212 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
317c35d1
JB		 213
214 /* Graphics controller regs */
215 for (i = 0; i < 9; i++)
216 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
f4c956ad 217 dev_priv->regfile.saveGR[i]);
317c35d1
JB		 218
219 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
f4c956ad 220 dev_priv->regfile.saveGR[0x10]);
317c35d1 221 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
f4c956ad 222 dev_priv->regfile.saveGR[0x11]);
317c35d1 223 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
f4c956ad 224 dev_priv->regfile.saveGR[0x18]);
317c35d1
JB		 225
226 /* Attribute controller registers */
227 I915_READ8(st01); /* switch back to index mode */
228 for (i = 0; i <= 0x14; i++)
f4c956ad 229 i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
317c35d1 230 I915_READ8(st01); /* switch back to index mode */
f4c956ad 231 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
317c35d1
JB		 232 I915_READ8(st01);
233
234 /* VGA color palette registers */
f4c956ad 235 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
317c35d1
JB		 236}
237
fccdaba4 238static void i915_save_modeset_reg(struct drm_device *dev)
317c35d1
JB		 239{
240 struct drm_i915_private *dev_priv = dev->dev_private;
312817a3 241 int i;
317c35d1 242
fccdaba4
ZY		 243 if (drm_core_check_feature(dev, DRIVER_MODESET))
244 return;
1341d655 245
f3c91c1d 246 /* Cursor state */
f4c956ad
DV		 247 dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
248 dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
249 dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
250 dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
251 dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
252 dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
f3c91c1d 253 if (IS_GEN2(dev))
f4c956ad 254 dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
f3c91c1d 255
90eb77ba 256 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 257 dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
258 dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
5586c8bc
ZW		 259 }
260
317c35d1 261 /* Pipe & plane A info */
f4c956ad
DV		 262 dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
263 dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
90eb77ba 264 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 265 dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
266 dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
267 dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
42048781 268 } else {
f4c956ad
DV		 269 dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
270 dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
271 dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
42048781 272 }
a6c45cf0 273 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
f4c956ad
DV		 274 dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
275 dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
276 dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
277 dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
278 dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
279 dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
280 dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
90eb77ba 281 if (!HAS_PCH_SPLIT(dev))
f4c956ad 282 dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
42048781 283
90eb77ba 284 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 285 dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
286 dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
287 dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
288 dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
289
290 dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
291 dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
292
293 dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
294 dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
295 dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
296
297 dev_priv->regfile.saveTRANSACONF = I915_READ(_TRANSACONF);
298 dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
299 dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
300 dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
301 dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
302 dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
303 dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
304 }
305
306 dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
307 dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
308 dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
309 dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
310 dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
a6c45cf0 311 if (INTEL_INFO(dev)->gen >= 4) {
f4c956ad
DV		 312 dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
313 dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
317c35d1
JB		 314 }
315 i915_save_palette(dev, PIPE_A);
f4c956ad 316 dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
317c35d1
JB		 317
318 /* Pipe & plane B info */
f4c956ad
DV		 319 dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
320 dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
90eb77ba 321 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 322 dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
323 dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
324 dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
42048781 325 } else {
f4c956ad
DV		 326 dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
327 dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
328 dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
42048781 329 }
a6c45cf0 330 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
f4c956ad
DV		 331 dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
332 dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
333 dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
334 dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
335 dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
336 dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
337 dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
90eb77ba 338 if (!HAS_PCH_SPLIT(dev))
f4c956ad 339 dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
42048781 340
90eb77ba 341 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 342 dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
343 dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
344 dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
345 dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
346
347 dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
348 dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
349
350 dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
351 dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
352 dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
353
354 dev_priv->regfile.saveTRANSBCONF = I915_READ(_TRANSBCONF);
355 dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
356 dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
357 dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
358 dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
359 dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
360 dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
361 }
362
363 dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
364 dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
365 dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
366 dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
367 dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
a6c45cf0 368 if (INTEL_INFO(dev)->gen >= 4) {
f4c956ad
DV		 369 dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
370 dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
317c35d1
JB		 371 }
372 i915_save_palette(dev, PIPE_B);
f4c956ad 373 dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
312817a3
CW		 374
375 /* Fences */
376 switch (INTEL_INFO(dev)->gen) {
775d17b6 377 case 7:
312817a3
CW		 378 case 6:
379 for (i = 0; i < 16; i++)
f4c956ad 380 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
312817a3
CW		 381 break;
382 case 5:
383 case 4:
384 for (i = 0; i < 16; i++)
f4c956ad 385 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
312817a3
CW		 386 break;
387 case 3:
388 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
389 for (i = 0; i < 8; i++)
f4c956ad 390 dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
312817a3
CW		 391 case 2:
392 for (i = 0; i < 8; i++)
f4c956ad 393 dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
312817a3
CW		 394 break;
395 }
396
7fdd74ab
DV		 397 /* CRT state */
398 if (HAS_PCH_SPLIT(dev))
f4c956ad 399 dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
7fdd74ab 400 else
f4c956ad 401 dev_priv->regfile.saveADPA = I915_READ(ADPA);
7fdd74ab 402
fccdaba4
ZY		 403 return;
404}
1341d655 405
fccdaba4
ZY		 406static void i915_restore_modeset_reg(struct drm_device *dev)
407{
408 struct drm_i915_private *dev_priv = dev->dev_private;
42048781
ZW		 409 int dpll_a_reg, fpa0_reg, fpa1_reg;
410 int dpll_b_reg, fpb0_reg, fpb1_reg;
312817a3 411 int i;
fccdaba4
ZY		 412
413 if (drm_core_check_feature(dev, DRIVER_MODESET))
414 return;
415
312817a3
CW		 416 /* Fences */
417 switch (INTEL_INFO(dev)->gen) {
775d17b6 418 case 7:
312817a3
CW		 419 case 6:
420 for (i = 0; i < 16; i++)
f4c956ad 421 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
312817a3
CW		 422 break;
423 case 5:
424 case 4:
425 for (i = 0; i < 16; i++)
f4c956ad 426 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
312817a3
CW		 427 break;
428 case 3:
429 case 2:
430 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
431 for (i = 0; i < 8; i++)
f4c956ad 432 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
312817a3 433 for (i = 0; i < 8; i++)
f4c956ad 434 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
312817a3
CW		 435 break;
436 }
437
438
90eb77ba 439 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 440 dpll_a_reg = _PCH_DPLL_A;
441 dpll_b_reg = _PCH_DPLL_B;
442 fpa0_reg = _PCH_FPA0;
443 fpb0_reg = _PCH_FPB0;
444 fpa1_reg = _PCH_FPA1;
445 fpb1_reg = _PCH_FPB1;
42048781 446 } else {
9db4a9c7
JB		 447 dpll_a_reg = _DPLL_A;
448 dpll_b_reg = _DPLL_B;
449 fpa0_reg = _FPA0;
450 fpb0_reg = _FPB0;
451 fpa1_reg = _FPA1;
452 fpb1_reg = _FPB1;
42048781
ZW		 453 }
454
90eb77ba 455 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 456 I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
457 I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
5586c8bc
ZW		 458 }
459
fccdaba4
ZY		 460 /* Pipe & plane A info */
461 /* Prime the clock */
f4c956ad
DV		 462 if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
463 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
fccdaba4 464 ~DPLL_VCO_ENABLE);
72bcb269
CW		 465 POSTING_READ(dpll_a_reg);
466 udelay(150);
fccdaba4 467 }
f4c956ad
DV		 468 I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
469 I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
fccdaba4 470 /* Actually enable it */
f4c956ad 471 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
72bcb269
CW		 472 POSTING_READ(dpll_a_reg);
473 udelay(150);
a6c45cf0 474 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
f4c956ad 475 I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
9db4a9c7 476 POSTING_READ(_DPLL_A_MD);
72bcb269
CW		 477 }
478 udelay(150);
fccdaba4
ZY		 479
480 /* Restore mode */
f4c956ad
DV		 481 I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
482 I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
483 I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
484 I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
485 I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
486 I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
90eb77ba 487 if (!HAS_PCH_SPLIT(dev))
f4c956ad 488 I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
42048781 489
90eb77ba 490 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 491 I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
492 I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
493 I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
494 I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
5586c8bc 495
f4c956ad
DV		 496 I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
497 I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
42048781 498
f4c956ad
DV		 499 I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
500 I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
501 I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
42048781 502
f4c956ad
DV		 503 I915_WRITE(_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
504 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
505 I915_WRITE(_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
506 I915_WRITE(_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
507 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
508 I915_WRITE(_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
509 I915_WRITE(_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
42048781 510 }
fccdaba4
ZY		 511
512 /* Restore plane info */
f4c956ad
DV		 513 I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
514 I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
515 I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
516 I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
517 I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
a6c45cf0 518 if (INTEL_INFO(dev)->gen >= 4) {
f4c956ad
DV		 519 I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
520 I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
fccdaba4
ZY		 521 }
522
f4c956ad 523 I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
fccdaba4
ZY		 524
525 i915_restore_palette(dev, PIPE_A);
526 /* Enable the plane */
f4c956ad 527 I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
9db4a9c7 528 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
fccdaba4
ZY		 529
530 /* Pipe & plane B info */
f4c956ad
DV		 531 if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
532 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
fccdaba4 533 ~DPLL_VCO_ENABLE);
72bcb269
CW		 534 POSTING_READ(dpll_b_reg);
535 udelay(150);
fccdaba4 536 }
f4c956ad
DV		 537 I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
538 I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
fccdaba4 539 /* Actually enable it */
f4c956ad 540 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
72bcb269
CW		 541 POSTING_READ(dpll_b_reg);
542 udelay(150);
a6c45cf0 543 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
f4c956ad 544 I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
9db4a9c7 545 POSTING_READ(_DPLL_B_MD);
72bcb269
CW		 546 }
547 udelay(150);
fccdaba4
ZY		 548
549 /* Restore mode */
f4c956ad
DV		 550 I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
551 I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
552 I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
553 I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
554 I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
555 I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
90eb77ba 556 if (!HAS_PCH_SPLIT(dev))
f4c956ad 557 I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
42048781 558
90eb77ba 559 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 560 I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
561 I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
562 I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
563 I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
5586c8bc 564
f4c956ad
DV		 565 I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
566 I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
42048781 567
f4c956ad
DV		 568 I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
569 I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
570 I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
42048781 571
f4c956ad
DV		 572 I915_WRITE(_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
573 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
574 I915_WRITE(_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
575 I915_WRITE(_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
576 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
577 I915_WRITE(_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
578 I915_WRITE(_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
42048781 579 }
fccdaba4
ZY		 580
581 /* Restore plane info */
f4c956ad
DV		 582 I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
583 I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
584 I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
585 I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
586 I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
a6c45cf0 587 if (INTEL_INFO(dev)->gen >= 4) {
f4c956ad
DV		 588 I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
589 I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
fccdaba4
ZY		 590 }
591
f4c956ad 592 I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
fccdaba4
ZY		 593
594 i915_restore_palette(dev, PIPE_B);
595 /* Enable the plane */
f4c956ad 596 I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
9db4a9c7 597 I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
317c35d1 598
f3c91c1d 599 /* Cursor state */
f4c956ad
DV		 600 I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
601 I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
602 I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
603 I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
604 I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
605 I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
f3c91c1d 606 if (IS_GEN2(dev))
f4c956ad 607 I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
f3c91c1d 608
7fdd74ab
DV		 609 /* CRT state */
610 if (HAS_PCH_SPLIT(dev))
f4c956ad 611 I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
7fdd74ab 612 else
f4c956ad 613 I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
7fdd74ab 614
fccdaba4
ZY		 615 return;
616}
1341d655 617
d70bed19 618static void i915_save_display(struct drm_device *dev)
fccdaba4
ZY		 619{
620 struct drm_i915_private *dev_priv = dev->dev_private;
fccdaba4
ZY		 621
622 /* Display arbitration control */
f4c956ad 623 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
fccdaba4
ZY		 624
625 /* This is only meaningful in non-KMS mode */
f4c956ad 626 /* Don't regfile.save them in KMS mode */
fccdaba4 627 i915_save_modeset_reg(dev);
1341d655 628
317c35d1 629 /* LVDS state */
90eb77ba 630 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 631 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
632 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
633 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
634 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
635 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
636 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
42048781 637 } else {
f4c956ad
DV		 638 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
639 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
640 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
641 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
a6c45cf0 642 if (INTEL_INFO(dev)->gen >= 4)
f4c956ad 643 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
42048781 644 if (IS_MOBILE(dev) && !IS_I830(dev))
f4c956ad 645 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
42048781
ZW		 646 }
647
90eb77ba 648 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
f4c956ad 649 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
42048781 650
90eb77ba 651 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 652 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
653 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
654 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
42048781 655 } else {
f4c956ad
DV		 656 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
657 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
658 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
42048781 659 }
317c35d1 660
f81183f7
DV		 661 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
662 /* Display Port state */
663 if (SUPPORTS_INTEGRATED_DP(dev)) {
f4c956ad
DV		 664 dev_priv->regfile.saveDP_B = I915_READ(DP_B);
665 dev_priv->regfile.saveDP_C = I915_READ(DP_C);
666 dev_priv->regfile.saveDP_D = I915_READ(DP_D);
667 dev_priv->regfile.savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
668 dev_priv->regfile.savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
669 dev_priv->regfile.savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
670 dev_priv->regfile.savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
671 dev_priv->regfile.savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
672 dev_priv->regfile.savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
673 dev_priv->regfile.savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
674 dev_priv->regfile.savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
f81183f7 675 }
f4c956ad 676 /* FIXME: regfile.save TV & SDVO state */
a4fc5ed6 677 }
317c35d1 678
f4c956ad 679 /* Only regfile.save FBC state on the platform that supports FBC */
a2c459ee 680 if (I915_HAS_FBC(dev)) {
90eb77ba 681 if (HAS_PCH_SPLIT(dev)) {
f4c956ad 682 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
b52eb4dc 683 } else if (IS_GM45(dev)) {
f4c956ad 684 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
a2c459ee 685 } else {
f4c956ad
DV		 686 dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
687 dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
688 dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
689 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
a2c459ee 690 }
06027f91 691 }
317c35d1 692
317c35d1 693 /* VGA state */
f4c956ad
DV		 694 dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
695 dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
696 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
90eb77ba 697 if (HAS_PCH_SPLIT(dev))
f4c956ad 698 dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
42048781 699 else
f4c956ad 700 dev_priv->regfile.saveVGACNTRL = I915_READ(VGACNTRL);
317c35d1 701
317c35d1 702 i915_save_vga(dev);
317c35d1
JB		 703}
704
d70bed19 705static void i915_restore_display(struct drm_device *dev)
317c35d1
JB		 706{
707 struct drm_i915_private *dev_priv = dev->dev_private;
461cba2d 708
881ee988 709 /* Display arbitration */
f4c956ad 710 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
317c35d1 711
f81183f7
DV		 712 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
713 /* Display port ratios (must be done before clock is set) */
714 if (SUPPORTS_INTEGRATED_DP(dev)) {
f4c956ad
DV		 715 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
716 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
717 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
718 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
719 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->regfile.savePIPEA_DP_LINK_M);
720 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->regfile.savePIPEB_DP_LINK_M);
721 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->regfile.savePIPEA_DP_LINK_N);
722 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->regfile.savePIPEB_DP_LINK_N);
f81183f7 723 }
a4fc5ed6 724 }
1341d655 725
fccdaba4
ZY		 726 /* This is only meaningful in non-KMS mode */
727 /* Don't restore them in KMS mode */
728 i915_restore_modeset_reg(dev);
1341d655 729
317c35d1 730 /* LVDS state */
a6c45cf0 731 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
f4c956ad 732 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
42048781 733
90eb77ba 734 if (HAS_PCH_SPLIT(dev)) {
f4c956ad 735 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS);
42048781 736 } else if (IS_MOBILE(dev) && !IS_I830(dev))
f4c956ad 737 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS);
42048781 738
90eb77ba 739 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
f4c956ad 740 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
317c35d1 741
90eb77ba 742 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 743 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
744 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
6db65cbb
TI		 745 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
746 * otherwise we get blank eDP screen after S3 on some machines
747 */
f4c956ad
DV		 748 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
749 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
750 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
751 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
752 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
753 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
88271da3 754 I915_WRITE(RSTDBYCTL,
f4c956ad 755 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
42048781 756 } else {
f4c956ad
DV		 757 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
758 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
759 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
760 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
761 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
762 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
763 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
42048781 764 }
317c35d1 765
f81183f7
DV		 766 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
767 /* Display Port state */
768 if (SUPPORTS_INTEGRATED_DP(dev)) {
f4c956ad
DV		 769 I915_WRITE(DP_B, dev_priv->regfile.saveDP_B);
770 I915_WRITE(DP_C, dev_priv->regfile.saveDP_C);
771 I915_WRITE(DP_D, dev_priv->regfile.saveDP_D);
f81183f7
DV		 772 }
773 /* FIXME: restore TV & SDVO state */
a4fc5ed6 774 }
317c35d1 775
a2c459ee 776 /* only restore FBC info on the platform that supports FBC*/
43a9539f 777 intel_disable_fbc(dev);
a2c459ee 778 if (I915_HAS_FBC(dev)) {
90eb77ba 779 if (HAS_PCH_SPLIT(dev)) {
f4c956ad 780 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
b52eb4dc 781 } else if (IS_GM45(dev)) {
f4c956ad 782 I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
a2c459ee 783 } else {
f4c956ad
DV		 784 I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
785 I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
786 I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
787 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
a2c459ee 788 }
06027f91 789 }
317c35d1 790 /* VGA state */
90eb77ba 791 if (HAS_PCH_SPLIT(dev))
f4c956ad 792 I915_WRITE(CPU_VGACNTRL, dev_priv->regfile.saveVGACNTRL);
42048781 793 else
f4c956ad 794 I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
483f1798 795
f4c956ad
DV		 796 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
797 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
798 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
72bcb269
CW		 799 POSTING_READ(VGA_PD);
800 udelay(150);
317c35d1 801
1341d655
BG		 802 i915_restore_vga(dev);
803}
804
805int i915_save_state(struct drm_device *dev)
806{
807 struct drm_i915_private *dev_priv = dev->dev_private;
808 int i;
809
f4c956ad 810 pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);
1341d655 811
d70bed19
KP		 812 mutex_lock(&dev->struct_mutex);
813
968b503e 814 /* Hardware status page */
c630119f 815 if (!drm_core_check_feature(dev, DRIVER_MODESET))
f4c956ad 816 dev_priv->regfile.saveHWS = I915_READ(HWS_PGA);
968b503e 817
1341d655
BG		 818 i915_save_display(dev);
819
905c27bb
DV		 820 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
821 /* Interrupt state */
822 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 823 dev_priv->regfile.saveDEIER = I915_READ(DEIER);
824 dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
825 dev_priv->regfile.saveGTIER = I915_READ(GTIER);
826 dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
827 dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
828 dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
829 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
905c27bb 830 I915_READ(RSTDBYCTL);
f4c956ad 831 dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
905c27bb 832 } else {
f4c956ad
DV		 833 dev_priv->regfile.saveIER = I915_READ(IER);
834 dev_priv->regfile.saveIMR = I915_READ(IMR);
905c27bb 835 }
42048781 836 }
1341d655 837
8090c6b9 838 intel_disable_gt_powersave(dev);
f97108d1 839
1341d655 840 /* Cache mode state */
f4c956ad 841 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
1341d655
BG		 842
843 /* Memory Arbitration state */
f4c956ad 844 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
1341d655
BG		 845
846 /* Scratch space */
847 for (i = 0; i < 16; i++) {
f4c956ad
DV		 848 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
849 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
1341d655
BG		 850 }
851 for (i = 0; i < 3; i++)
f4c956ad 852 dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
1341d655 853
d70bed19
KP		 854 mutex_unlock(&dev->struct_mutex);
855
1341d655
BG		 856 return 0;
857}
858
859int i915_restore_state(struct drm_device *dev)
860{
861 struct drm_i915_private *dev_priv = dev->dev_private;
862 int i;
863
f4c956ad 864 pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);
1341d655 865
d70bed19
KP		 866 mutex_lock(&dev->struct_mutex);
867
968b503e 868 /* Hardware status page */
c630119f 869 if (!drm_core_check_feature(dev, DRIVER_MODESET))
f4c956ad 870 I915_WRITE(HWS_PGA, dev_priv->regfile.saveHWS);
968b503e 871
1341d655
BG		 872 i915_restore_display(dev);
873
905c27bb
DV		 874 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
875 /* Interrupt state */
876 if (HAS_PCH_SPLIT(dev)) {
f4c956ad
DV		 877 I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
878 I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
879 I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
880 I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
881 I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
882 I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
883 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
905c27bb 884 } else {
f4c956ad
DV		 885 I915_WRITE(IER, dev_priv->regfile.saveIER);
886 I915_WRITE(IMR, dev_priv->regfile.saveIMR);
905c27bb 887 }
42048781 888 }
d70bed19 889
317c35d1 890 /* Cache mode state */
f4c956ad 891 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
317c35d1
JB		 892
893 /* Memory arbitration state */
f4c956ad 894 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
317c35d1
JB		 895
896 for (i = 0; i < 16; i++) {
f4c956ad
DV		 897 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
898 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
317c35d1
JB		 899 }
900 for (i = 0; i < 3; i++)
f4c956ad 901 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
317c35d1 902
d70bed19
KP		 903 mutex_unlock(&dev->struct_mutex);
904
f899fc64 905 intel_i2c_reset(dev);
f0217c42 906
317c35d1
JB		 907 return 0;
908}
Linux kernel - Deliverables
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