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0136db58 BW |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/device.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/stat.h> | |
31 | #include <linux/sysfs.h> | |
84bc7581 | 32 | #include "intel_drv.h" |
0136db58 BW |
33 | #include "i915_drv.h" |
34 | ||
5bdebb18 | 35 | #define dev_to_drm_minor(d) dev_get_drvdata((d)) |
14c8d110 | 36 | |
5ab3633d | 37 | #ifdef CONFIG_PM |
f0f59a00 VS |
38 | static u32 calc_residency(struct drm_device *dev, |
39 | i915_reg_t reg) | |
0136db58 BW |
40 | { |
41 | struct drm_i915_private *dev_priv = dev->dev_private; | |
42 | u64 raw_time; /* 32b value may overflow during fixed point math */ | |
2cc9fab1 | 43 | u64 units = 128ULL, div = 100000ULL; |
c8c8fb33 | 44 | u32 ret; |
0136db58 | 45 | |
dc97997a | 46 | if (!intel_enable_rc6()) |
0136db58 BW |
47 | return 0; |
48 | ||
c8c8fb33 PZ |
49 | intel_runtime_pm_get(dev_priv); |
50 | ||
542a6b20 | 51 | /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ |
666a4537 | 52 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
2cc9fab1 VS |
53 | units = 1; |
54 | div = dev_priv->czclk_freq; | |
542a6b20 | 55 | |
e454a05d JB |
56 | if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) |
57 | units <<= 8; | |
d8135109 ID |
58 | } else if (IS_BROXTON(dev)) { |
59 | units = 1; | |
60 | div = 1200; /* 833.33ns */ | |
e454a05d JB |
61 | } |
62 | ||
63 | raw_time = I915_READ(reg) * units; | |
c8c8fb33 PZ |
64 | ret = DIV_ROUND_UP_ULL(raw_time, div); |
65 | ||
c8c8fb33 PZ |
66 | intel_runtime_pm_put(dev_priv); |
67 | return ret; | |
0136db58 BW |
68 | } |
69 | ||
70 | static ssize_t | |
dbdfd8e9 | 71 | show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 72 | { |
dc97997a | 73 | return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6()); |
0136db58 BW |
74 | } |
75 | ||
76 | static ssize_t | |
dbdfd8e9 | 77 | show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 78 | { |
5bdebb18 | 79 | struct drm_minor *dminor = dev_get_drvdata(kdev); |
0136db58 | 80 | u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6); |
3e2a1556 | 81 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); |
0136db58 BW |
82 | } |
83 | ||
84 | static ssize_t | |
dbdfd8e9 | 85 | show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 86 | { |
14c8d110 | 87 | struct drm_minor *dminor = dev_to_drm_minor(kdev); |
0136db58 | 88 | u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p); |
3e2a1556 | 89 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency); |
0136db58 BW |
90 | } |
91 | ||
92 | static ssize_t | |
dbdfd8e9 | 93 | show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 94 | { |
14c8d110 | 95 | struct drm_minor *dminor = dev_to_drm_minor(kdev); |
0136db58 | 96 | u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp); |
3e2a1556 | 97 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency); |
0136db58 BW |
98 | } |
99 | ||
626ad6f3 VS |
100 | static ssize_t |
101 | show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) | |
102 | { | |
103 | struct drm_minor *dminor = dev_get_drvdata(kdev); | |
104 | u32 rc6_residency = calc_residency(dminor->dev, VLV_GT_MEDIA_RC6); | |
105 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); | |
106 | } | |
107 | ||
0136db58 BW |
108 | static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL); |
109 | static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL); | |
110 | static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL); | |
111 | static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL); | |
626ad6f3 | 112 | static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL); |
0136db58 BW |
113 | |
114 | static struct attribute *rc6_attrs[] = { | |
115 | &dev_attr_rc6_enable.attr, | |
116 | &dev_attr_rc6_residency_ms.attr, | |
0136db58 BW |
117 | NULL |
118 | }; | |
119 | ||
120 | static struct attribute_group rc6_attr_group = { | |
121 | .name = power_group_name, | |
122 | .attrs = rc6_attrs | |
123 | }; | |
58abf1da RV |
124 | |
125 | static struct attribute *rc6p_attrs[] = { | |
126 | &dev_attr_rc6p_residency_ms.attr, | |
127 | &dev_attr_rc6pp_residency_ms.attr, | |
128 | NULL | |
129 | }; | |
130 | ||
131 | static struct attribute_group rc6p_attr_group = { | |
132 | .name = power_group_name, | |
133 | .attrs = rc6p_attrs | |
134 | }; | |
626ad6f3 VS |
135 | |
136 | static struct attribute *media_rc6_attrs[] = { | |
137 | &dev_attr_media_rc6_residency_ms.attr, | |
138 | NULL | |
139 | }; | |
140 | ||
141 | static struct attribute_group media_rc6_attr_group = { | |
142 | .name = power_group_name, | |
143 | .attrs = media_rc6_attrs | |
144 | }; | |
8c3f929b | 145 | #endif |
0136db58 | 146 | |
84bc7581 BW |
147 | static int l3_access_valid(struct drm_device *dev, loff_t offset) |
148 | { | |
040d2baa | 149 | if (!HAS_L3_DPF(dev)) |
84bc7581 BW |
150 | return -EPERM; |
151 | ||
152 | if (offset % 4 != 0) | |
153 | return -EINVAL; | |
154 | ||
155 | if (offset >= GEN7_L3LOG_SIZE) | |
156 | return -ENXIO; | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | static ssize_t | |
162 | i915_l3_read(struct file *filp, struct kobject *kobj, | |
163 | struct bin_attribute *attr, char *buf, | |
164 | loff_t offset, size_t count) | |
165 | { | |
657fb5fb | 166 | struct device *dev = kobj_to_dev(kobj); |
14c8d110 | 167 | struct drm_minor *dminor = dev_to_drm_minor(dev); |
84bc7581 BW |
168 | struct drm_device *drm_dev = dminor->dev; |
169 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
35a85ac6 | 170 | int slice = (int)(uintptr_t)attr->private; |
3ccfd19d | 171 | int ret; |
84bc7581 | 172 | |
1c3dcd1c BW |
173 | count = round_down(count, 4); |
174 | ||
84bc7581 BW |
175 | ret = l3_access_valid(drm_dev, offset); |
176 | if (ret) | |
177 | return ret; | |
178 | ||
e5ad4026 | 179 | count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count); |
33618ea5 | 180 | |
84bc7581 BW |
181 | ret = i915_mutex_lock_interruptible(drm_dev); |
182 | if (ret) | |
183 | return ret; | |
184 | ||
3ccfd19d BW |
185 | if (dev_priv->l3_parity.remap_info[slice]) |
186 | memcpy(buf, | |
187 | dev_priv->l3_parity.remap_info[slice] + (offset/4), | |
188 | count); | |
189 | else | |
190 | memset(buf, 0, count); | |
84bc7581 | 191 | |
84bc7581 BW |
192 | mutex_unlock(&drm_dev->struct_mutex); |
193 | ||
1c966dd2 | 194 | return count; |
84bc7581 BW |
195 | } |
196 | ||
197 | static ssize_t | |
198 | i915_l3_write(struct file *filp, struct kobject *kobj, | |
199 | struct bin_attribute *attr, char *buf, | |
200 | loff_t offset, size_t count) | |
201 | { | |
657fb5fb | 202 | struct device *dev = kobj_to_dev(kobj); |
14c8d110 | 203 | struct drm_minor *dminor = dev_to_drm_minor(dev); |
84bc7581 BW |
204 | struct drm_device *drm_dev = dminor->dev; |
205 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
e2efd130 | 206 | struct i915_gem_context *ctx; |
84bc7581 | 207 | u32 *temp = NULL; /* Just here to make handling failures easy */ |
35a85ac6 | 208 | int slice = (int)(uintptr_t)attr->private; |
84bc7581 BW |
209 | int ret; |
210 | ||
8245be31 BW |
211 | if (!HAS_HW_CONTEXTS(drm_dev)) |
212 | return -ENXIO; | |
213 | ||
84bc7581 BW |
214 | ret = l3_access_valid(drm_dev, offset); |
215 | if (ret) | |
216 | return ret; | |
217 | ||
218 | ret = i915_mutex_lock_interruptible(drm_dev); | |
219 | if (ret) | |
220 | return ret; | |
221 | ||
35a85ac6 | 222 | if (!dev_priv->l3_parity.remap_info[slice]) { |
84bc7581 BW |
223 | temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL); |
224 | if (!temp) { | |
225 | mutex_unlock(&drm_dev->struct_mutex); | |
226 | return -ENOMEM; | |
227 | } | |
228 | } | |
229 | ||
230 | ret = i915_gpu_idle(drm_dev); | |
231 | if (ret) { | |
232 | kfree(temp); | |
233 | mutex_unlock(&drm_dev->struct_mutex); | |
234 | return ret; | |
235 | } | |
236 | ||
237 | /* TODO: Ideally we really want a GPU reset here to make sure errors | |
238 | * aren't propagated. Since I cannot find a stable way to reset the GPU | |
239 | * at this point it is left as a TODO. | |
240 | */ | |
241 | if (temp) | |
35a85ac6 | 242 | dev_priv->l3_parity.remap_info[slice] = temp; |
84bc7581 | 243 | |
35a85ac6 | 244 | memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count); |
84bc7581 | 245 | |
3ccfd19d BW |
246 | /* NB: We defer the remapping until we switch to the context */ |
247 | list_for_each_entry(ctx, &dev_priv->context_list, link) | |
248 | ctx->remap_slice |= (1<<slice); | |
84bc7581 BW |
249 | |
250 | mutex_unlock(&drm_dev->struct_mutex); | |
251 | ||
252 | return count; | |
253 | } | |
254 | ||
255 | static struct bin_attribute dpf_attrs = { | |
256 | .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, | |
257 | .size = GEN7_L3LOG_SIZE, | |
258 | .read = i915_l3_read, | |
259 | .write = i915_l3_write, | |
35a85ac6 BW |
260 | .mmap = NULL, |
261 | .private = (void *)0 | |
262 | }; | |
263 | ||
264 | static struct bin_attribute dpf_attrs_1 = { | |
265 | .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, | |
266 | .size = GEN7_L3LOG_SIZE, | |
267 | .read = i915_l3_read, | |
268 | .write = i915_l3_write, | |
269 | .mmap = NULL, | |
270 | .private = (void *)1 | |
84bc7581 BW |
271 | }; |
272 | ||
c8c972eb | 273 | static ssize_t gt_act_freq_mhz_show(struct device *kdev, |
df6eedc8 BW |
274 | struct device_attribute *attr, char *buf) |
275 | { | |
14c8d110 | 276 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
df6eedc8 BW |
277 | struct drm_device *dev = minor->dev; |
278 | struct drm_i915_private *dev_priv = dev->dev_private; | |
279 | int ret; | |
280 | ||
5c9669ce TR |
281 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
282 | ||
d46c0517 ID |
283 | intel_runtime_pm_get(dev_priv); |
284 | ||
4fc688ce | 285 | mutex_lock(&dev_priv->rps.hw_lock); |
666a4537 | 286 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
177006a1 | 287 | u32 freq; |
64936258 | 288 | freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
7c59a9c1 | 289 | ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff); |
c8c972eb VS |
290 | } else { |
291 | u32 rpstat = I915_READ(GEN6_RPSTAT1); | |
ed64d66f AG |
292 | if (IS_GEN9(dev_priv)) |
293 | ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; | |
294 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
c8c972eb VS |
295 | ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
296 | else | |
297 | ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 298 | ret = intel_gpu_freq(dev_priv, ret); |
c8c972eb VS |
299 | } |
300 | mutex_unlock(&dev_priv->rps.hw_lock); | |
301 | ||
302 | intel_runtime_pm_put(dev_priv); | |
303 | ||
304 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); | |
305 | } | |
306 | ||
307 | static ssize_t gt_cur_freq_mhz_show(struct device *kdev, | |
308 | struct device_attribute *attr, char *buf) | |
309 | { | |
310 | struct drm_minor *minor = dev_to_drm_minor(kdev); | |
311 | struct drm_device *dev = minor->dev; | |
312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
313 | int ret; | |
314 | ||
315 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
316 | ||
317 | intel_runtime_pm_get(dev_priv); | |
318 | ||
319 | mutex_lock(&dev_priv->rps.hw_lock); | |
7c59a9c1 | 320 | ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq); |
4fc688ce | 321 | mutex_unlock(&dev_priv->rps.hw_lock); |
df6eedc8 | 322 | |
d46c0517 ID |
323 | intel_runtime_pm_put(dev_priv); |
324 | ||
3e2a1556 | 325 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); |
df6eedc8 BW |
326 | } |
327 | ||
97e4eed7 CW |
328 | static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, |
329 | struct device_attribute *attr, char *buf) | |
330 | { | |
14c8d110 | 331 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
97e4eed7 CW |
332 | struct drm_device *dev = minor->dev; |
333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
334 | ||
7c59a9c1 VS |
335 | return snprintf(buf, PAGE_SIZE, |
336 | "%d\n", | |
337 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
97e4eed7 CW |
338 | } |
339 | ||
df6eedc8 BW |
340 | static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) |
341 | { | |
14c8d110 | 342 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
df6eedc8 BW |
343 | struct drm_device *dev = minor->dev; |
344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
345 | int ret; | |
346 | ||
5c9669ce TR |
347 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
348 | ||
4fc688ce | 349 | mutex_lock(&dev_priv->rps.hw_lock); |
7c59a9c1 | 350 | ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
4fc688ce | 351 | mutex_unlock(&dev_priv->rps.hw_lock); |
df6eedc8 | 352 | |
3e2a1556 | 353 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); |
df6eedc8 BW |
354 | } |
355 | ||
46ddf194 BW |
356 | static ssize_t gt_max_freq_mhz_store(struct device *kdev, |
357 | struct device_attribute *attr, | |
358 | const char *buf, size_t count) | |
359 | { | |
14c8d110 | 360 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
46ddf194 BW |
361 | struct drm_device *dev = minor->dev; |
362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2a5913a8 | 363 | u32 val; |
46ddf194 BW |
364 | ssize_t ret; |
365 | ||
366 | ret = kstrtou32(buf, 0, &val); | |
367 | if (ret) | |
368 | return ret; | |
369 | ||
5c9669ce TR |
370 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
371 | ||
933bfb44 SAK |
372 | intel_runtime_pm_get(dev_priv); |
373 | ||
4fc688ce | 374 | mutex_lock(&dev_priv->rps.hw_lock); |
46ddf194 | 375 | |
7c59a9c1 | 376 | val = intel_freq_opcode(dev_priv, val); |
46ddf194 | 377 | |
2a5913a8 BW |
378 | if (val < dev_priv->rps.min_freq || |
379 | val > dev_priv->rps.max_freq || | |
b39fb297 | 380 | val < dev_priv->rps.min_freq_softlimit) { |
4fc688ce | 381 | mutex_unlock(&dev_priv->rps.hw_lock); |
933bfb44 | 382 | intel_runtime_pm_put(dev_priv); |
46ddf194 BW |
383 | return -EINVAL; |
384 | } | |
385 | ||
2a5913a8 | 386 | if (val > dev_priv->rps.rp0_freq) |
31c77388 | 387 | DRM_DEBUG("User requested overclocking to %d\n", |
7c59a9c1 | 388 | intel_gpu_freq(dev_priv, val)); |
31c77388 | 389 | |
b39fb297 | 390 | dev_priv->rps.max_freq_softlimit = val; |
6917c7b9 | 391 | |
f745a80e VS |
392 | val = clamp_t(int, dev_priv->rps.cur_freq, |
393 | dev_priv->rps.min_freq_softlimit, | |
394 | dev_priv->rps.max_freq_softlimit); | |
395 | ||
396 | /* We still need *_set_rps to process the new max_delay and | |
397 | * update the interrupt limits and PMINTRMSK even though | |
398 | * frequency request may be unchanged. */ | |
dc97997a | 399 | intel_set_rps(dev_priv, val); |
46ddf194 | 400 | |
4fc688ce | 401 | mutex_unlock(&dev_priv->rps.hw_lock); |
46ddf194 | 402 | |
933bfb44 SAK |
403 | intel_runtime_pm_put(dev_priv); |
404 | ||
46ddf194 BW |
405 | return count; |
406 | } | |
407 | ||
df6eedc8 BW |
408 | static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) |
409 | { | |
14c8d110 | 410 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
df6eedc8 BW |
411 | struct drm_device *dev = minor->dev; |
412 | struct drm_i915_private *dev_priv = dev->dev_private; | |
413 | int ret; | |
414 | ||
5c9669ce TR |
415 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
416 | ||
4fc688ce | 417 | mutex_lock(&dev_priv->rps.hw_lock); |
7c59a9c1 | 418 | ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
4fc688ce | 419 | mutex_unlock(&dev_priv->rps.hw_lock); |
df6eedc8 | 420 | |
3e2a1556 | 421 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); |
df6eedc8 BW |
422 | } |
423 | ||
46ddf194 BW |
424 | static ssize_t gt_min_freq_mhz_store(struct device *kdev, |
425 | struct device_attribute *attr, | |
426 | const char *buf, size_t count) | |
427 | { | |
14c8d110 | 428 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
46ddf194 BW |
429 | struct drm_device *dev = minor->dev; |
430 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2a5913a8 | 431 | u32 val; |
46ddf194 BW |
432 | ssize_t ret; |
433 | ||
434 | ret = kstrtou32(buf, 0, &val); | |
435 | if (ret) | |
436 | return ret; | |
437 | ||
5c9669ce TR |
438 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
439 | ||
933bfb44 SAK |
440 | intel_runtime_pm_get(dev_priv); |
441 | ||
4fc688ce | 442 | mutex_lock(&dev_priv->rps.hw_lock); |
46ddf194 | 443 | |
7c59a9c1 | 444 | val = intel_freq_opcode(dev_priv, val); |
0a073b84 | 445 | |
2a5913a8 BW |
446 | if (val < dev_priv->rps.min_freq || |
447 | val > dev_priv->rps.max_freq || | |
448 | val > dev_priv->rps.max_freq_softlimit) { | |
4fc688ce | 449 | mutex_unlock(&dev_priv->rps.hw_lock); |
933bfb44 | 450 | intel_runtime_pm_put(dev_priv); |
46ddf194 BW |
451 | return -EINVAL; |
452 | } | |
453 | ||
b39fb297 | 454 | dev_priv->rps.min_freq_softlimit = val; |
6917c7b9 | 455 | |
f745a80e VS |
456 | val = clamp_t(int, dev_priv->rps.cur_freq, |
457 | dev_priv->rps.min_freq_softlimit, | |
458 | dev_priv->rps.max_freq_softlimit); | |
459 | ||
460 | /* We still need *_set_rps to process the new min_delay and | |
461 | * update the interrupt limits and PMINTRMSK even though | |
462 | * frequency request may be unchanged. */ | |
dc97997a | 463 | intel_set_rps(dev_priv, val); |
46ddf194 | 464 | |
4fc688ce | 465 | mutex_unlock(&dev_priv->rps.hw_lock); |
46ddf194 | 466 | |
933bfb44 SAK |
467 | intel_runtime_pm_put(dev_priv); |
468 | ||
46ddf194 BW |
469 | return count; |
470 | ||
471 | } | |
472 | ||
c8c972eb | 473 | static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL); |
df6eedc8 | 474 | static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL); |
46ddf194 BW |
475 | static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store); |
476 | static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store); | |
df6eedc8 | 477 | |
97e4eed7 | 478 | static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL); |
ac6ae347 BW |
479 | |
480 | static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf); | |
481 | static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); | |
482 | static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); | |
483 | static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); | |
484 | ||
485 | /* For now we have a static number of RP states */ | |
486 | static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) | |
487 | { | |
14c8d110 | 488 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
ac6ae347 BW |
489 | struct drm_device *dev = minor->dev; |
490 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bc4d91f6 | 491 | u32 val; |
ac6ae347 | 492 | |
bc4d91f6 AG |
493 | if (attr == &dev_attr_gt_RP0_freq_mhz) |
494 | val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq); | |
495 | else if (attr == &dev_attr_gt_RP1_freq_mhz) | |
496 | val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq); | |
497 | else if (attr == &dev_attr_gt_RPn_freq_mhz) | |
498 | val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq); | |
499 | else | |
ac6ae347 | 500 | BUG(); |
bc4d91f6 | 501 | |
3e2a1556 | 502 | return snprintf(buf, PAGE_SIZE, "%d\n", val); |
ac6ae347 BW |
503 | } |
504 | ||
df6eedc8 | 505 | static const struct attribute *gen6_attrs[] = { |
c8c972eb | 506 | &dev_attr_gt_act_freq_mhz.attr, |
df6eedc8 BW |
507 | &dev_attr_gt_cur_freq_mhz.attr, |
508 | &dev_attr_gt_max_freq_mhz.attr, | |
509 | &dev_attr_gt_min_freq_mhz.attr, | |
ac6ae347 BW |
510 | &dev_attr_gt_RP0_freq_mhz.attr, |
511 | &dev_attr_gt_RP1_freq_mhz.attr, | |
512 | &dev_attr_gt_RPn_freq_mhz.attr, | |
df6eedc8 BW |
513 | NULL, |
514 | }; | |
515 | ||
97e4eed7 | 516 | static const struct attribute *vlv_attrs[] = { |
c8c972eb | 517 | &dev_attr_gt_act_freq_mhz.attr, |
97e4eed7 CW |
518 | &dev_attr_gt_cur_freq_mhz.attr, |
519 | &dev_attr_gt_max_freq_mhz.attr, | |
520 | &dev_attr_gt_min_freq_mhz.attr, | |
74c4f62b D |
521 | &dev_attr_gt_RP0_freq_mhz.attr, |
522 | &dev_attr_gt_RP1_freq_mhz.attr, | |
523 | &dev_attr_gt_RPn_freq_mhz.attr, | |
97e4eed7 CW |
524 | &dev_attr_vlv_rpe_freq_mhz.attr, |
525 | NULL, | |
526 | }; | |
527 | ||
ef86ddce MK |
528 | static ssize_t error_state_read(struct file *filp, struct kobject *kobj, |
529 | struct bin_attribute *attr, char *buf, | |
530 | loff_t off, size_t count) | |
531 | { | |
532 | ||
657fb5fb | 533 | struct device *kdev = kobj_to_dev(kobj); |
14c8d110 | 534 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
ef86ddce MK |
535 | struct drm_device *dev = minor->dev; |
536 | struct i915_error_state_file_priv error_priv; | |
537 | struct drm_i915_error_state_buf error_str; | |
538 | ssize_t ret_count = 0; | |
539 | int ret; | |
540 | ||
541 | memset(&error_priv, 0, sizeof(error_priv)); | |
542 | ||
0a4cd7c8 | 543 | ret = i915_error_state_buf_init(&error_str, to_i915(dev), count, off); |
ef86ddce MK |
544 | if (ret) |
545 | return ret; | |
546 | ||
547 | error_priv.dev = dev; | |
548 | i915_error_state_get(dev, &error_priv); | |
549 | ||
550 | ret = i915_error_state_to_str(&error_str, &error_priv); | |
551 | if (ret) | |
552 | goto out; | |
553 | ||
554 | ret_count = count < error_str.bytes ? count : error_str.bytes; | |
555 | ||
556 | memcpy(buf, error_str.buf, ret_count); | |
557 | out: | |
558 | i915_error_state_put(&error_priv); | |
559 | i915_error_state_buf_release(&error_str); | |
560 | ||
561 | return ret ?: ret_count; | |
562 | } | |
563 | ||
564 | static ssize_t error_state_write(struct file *file, struct kobject *kobj, | |
565 | struct bin_attribute *attr, char *buf, | |
566 | loff_t off, size_t count) | |
567 | { | |
657fb5fb | 568 | struct device *kdev = kobj_to_dev(kobj); |
14c8d110 | 569 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
ef86ddce MK |
570 | struct drm_device *dev = minor->dev; |
571 | int ret; | |
572 | ||
573 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
574 | ||
575 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
576 | if (ret) | |
577 | return ret; | |
578 | ||
579 | i915_destroy_error_state(dev); | |
580 | mutex_unlock(&dev->struct_mutex); | |
581 | ||
582 | return count; | |
583 | } | |
584 | ||
585 | static struct bin_attribute error_state_attr = { | |
586 | .attr.name = "error", | |
587 | .attr.mode = S_IRUSR | S_IWUSR, | |
588 | .size = 0, | |
589 | .read = error_state_read, | |
590 | .write = error_state_write, | |
591 | }; | |
592 | ||
0136db58 BW |
593 | void i915_setup_sysfs(struct drm_device *dev) |
594 | { | |
595 | int ret; | |
596 | ||
8c3f929b | 597 | #ifdef CONFIG_PM |
58abf1da | 598 | if (HAS_RC6(dev)) { |
5bdebb18 | 599 | ret = sysfs_merge_group(&dev->primary->kdev->kobj, |
112abd29 DV |
600 | &rc6_attr_group); |
601 | if (ret) | |
602 | DRM_ERROR("RC6 residency sysfs setup failed\n"); | |
603 | } | |
58abf1da RV |
604 | if (HAS_RC6p(dev)) { |
605 | ret = sysfs_merge_group(&dev->primary->kdev->kobj, | |
606 | &rc6p_attr_group); | |
607 | if (ret) | |
608 | DRM_ERROR("RC6p residency sysfs setup failed\n"); | |
609 | } | |
666a4537 | 610 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
626ad6f3 VS |
611 | ret = sysfs_merge_group(&dev->primary->kdev->kobj, |
612 | &media_rc6_attr_group); | |
613 | if (ret) | |
614 | DRM_ERROR("Media RC6 residency sysfs setup failed\n"); | |
615 | } | |
8c3f929b | 616 | #endif |
040d2baa | 617 | if (HAS_L3_DPF(dev)) { |
5bdebb18 | 618 | ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs); |
112abd29 DV |
619 | if (ret) |
620 | DRM_ERROR("l3 parity sysfs setup failed\n"); | |
35a85ac6 BW |
621 | |
622 | if (NUM_L3_SLICES(dev) > 1) { | |
5bdebb18 | 623 | ret = device_create_bin_file(dev->primary->kdev, |
35a85ac6 BW |
624 | &dpf_attrs_1); |
625 | if (ret) | |
626 | DRM_ERROR("l3 parity slice 1 setup failed\n"); | |
627 | } | |
112abd29 | 628 | } |
df6eedc8 | 629 | |
97e4eed7 | 630 | ret = 0; |
666a4537 | 631 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5bdebb18 | 632 | ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs); |
97e4eed7 | 633 | else if (INTEL_INFO(dev)->gen >= 6) |
5bdebb18 | 634 | ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs); |
97e4eed7 CW |
635 | if (ret) |
636 | DRM_ERROR("RPS sysfs setup failed\n"); | |
ef86ddce | 637 | |
5bdebb18 | 638 | ret = sysfs_create_bin_file(&dev->primary->kdev->kobj, |
ef86ddce MK |
639 | &error_state_attr); |
640 | if (ret) | |
641 | DRM_ERROR("error_state sysfs setup failed\n"); | |
0136db58 BW |
642 | } |
643 | ||
644 | void i915_teardown_sysfs(struct drm_device *dev) | |
645 | { | |
5bdebb18 | 646 | sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr); |
666a4537 | 647 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5bdebb18 | 648 | sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs); |
97e4eed7 | 649 | else |
5bdebb18 DA |
650 | sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs); |
651 | device_remove_bin_file(dev->primary->kdev, &dpf_attrs_1); | |
652 | device_remove_bin_file(dev->primary->kdev, &dpf_attrs); | |
853c70e8 | 653 | #ifdef CONFIG_PM |
5bdebb18 | 654 | sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group); |
58abf1da | 655 | sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6p_attr_group); |
853c70e8 | 656 | #endif |
0136db58 | 657 | } |