[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_sysfs.c

/*
 * Copyright © 2012 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Ben Widawsky <ben@bwidawsk.net>
 *
 */

#include <linux/device.h>
#include <linux/module.h>
#include <linux/stat.h>
#include <linux/sysfs.h>
#include "intel_drv.h"
#include "i915_drv.h"

#define dev_to_drm_minor(d) dev_get_drvdata((d))

#ifdef CONFIG_PM
static u32 calc_residency(struct drm_device *dev, const u32 reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u64 raw_time; /* 32b value may overflow during fixed point math */
	u64 units = 128ULL, div = 100000ULL, bias = 100ULL;

	if (!intel_enable_rc6(dev))
		return 0;

	/* On VLV, residency time is in CZ units rather than 1.28us */
	if (IS_VALLEYVIEW(dev)) {
		u32 clkctl2;

		clkctl2 = I915_READ(VLV_CLK_CTL2) >>
			CLK_CTL2_CZCOUNT_30NS_SHIFT;
		if (!clkctl2) {
			WARN(!clkctl2, "bogus CZ count value");
			return 0;
		}
		units = DIV_ROUND_UP_ULL(30ULL * bias, (u64)clkctl2);
		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
			units <<= 8;

		div = 1000000ULL * bias;
	}

	raw_time = I915_READ(reg) * units;
	return DIV_ROUND_UP_ULL(raw_time, div);
}

static ssize_t
show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = dev_to_drm_minor(kdev);
	return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
}

static ssize_t
show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = dev_get_drvdata(kdev);
	u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
	return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
}

static ssize_t
show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = dev_to_drm_minor(kdev);
	u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
	if (IS_VALLEYVIEW(dminor->dev))
		rc6p_residency = 0;
	return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
}

static ssize_t
show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = dev_to_drm_minor(kdev);
	u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
	if (IS_VALLEYVIEW(dminor->dev))
		rc6pp_residency = 0;
	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
}

static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);

static struct attribute *rc6_attrs[] = {
	&dev_attr_rc6_enable.attr,
	&dev_attr_rc6_residency_ms.attr,
	&dev_attr_rc6p_residency_ms.attr,
	&dev_attr_rc6pp_residency_ms.attr,
	NULL
};

static struct attribute_group rc6_attr_group = {
	.name = power_group_name,
	.attrs =  rc6_attrs
};
#endif

static int l3_access_valid(struct drm_device *dev, loff_t offset)
{
	if (!HAS_L3_DPF(dev))
		return -EPERM;

	if (offset % 4 != 0)
		return -EINVAL;

	if (offset >= GEN7_L3LOG_SIZE)
		return -ENXIO;

	return 0;
}

static ssize_t
i915_l3_read(struct file *filp, struct kobject *kobj,
	     struct bin_attribute *attr, char *buf,
	     loff_t offset, size_t count)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct drm_minor *dminor = dev_to_drm_minor(dev);
	struct drm_device *drm_dev = dminor->dev;
	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	int slice = (int)(uintptr_t)attr->private;
	int ret;

	count = round_down(count, 4);

	ret = l3_access_valid(drm_dev, offset);
	if (ret)
		return ret;

	count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);

	ret = i915_mutex_lock_interruptible(drm_dev);
	if (ret)
		return ret;

	if (dev_priv->l3_parity.remap_info[slice])
		memcpy(buf,
		       dev_priv->l3_parity.remap_info[slice] + (offset/4),
		       count);
	else
		memset(buf, 0, count);

	mutex_unlock(&drm_dev->struct_mutex);

	return count;
}

static ssize_t
i915_l3_write(struct file *filp, struct kobject *kobj,
	      struct bin_attribute *attr, char *buf,
	      loff_t offset, size_t count)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct drm_minor *dminor = dev_to_drm_minor(dev);
	struct drm_device *drm_dev = dminor->dev;
	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	struct i915_hw_context *ctx;
	u32 *temp = NULL; /* Just here to make handling failures easy */
	int slice = (int)(uintptr_t)attr->private;
	int ret;

	if (!HAS_HW_CONTEXTS(drm_dev))
		return -ENXIO;

	ret = l3_access_valid(drm_dev, offset);
	if (ret)
		return ret;

	ret = i915_mutex_lock_interruptible(drm_dev);
	if (ret)
		return ret;

	if (!dev_priv->l3_parity.remap_info[slice]) {
		temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
		if (!temp) {
			mutex_unlock(&drm_dev->struct_mutex);
			return -ENOMEM;
		}
	}

	ret = i915_gpu_idle(drm_dev);
	if (ret) {
		kfree(temp);
		mutex_unlock(&drm_dev->struct_mutex);
		return ret;
	}

	/* TODO: Ideally we really want a GPU reset here to make sure errors
	 * aren't propagated. Since I cannot find a stable way to reset the GPU
	 * at this point it is left as a TODO.
	*/
	if (temp)
		dev_priv->l3_parity.remap_info[slice] = temp;

	memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);

	/* NB: We defer the remapping until we switch to the context */
	list_for_each_entry(ctx, &dev_priv->context_list, link)
		ctx->remap_slice |= (1<<slice);

	mutex_unlock(&drm_dev->struct_mutex);

	return count;
}

static struct bin_attribute dpf_attrs = {
	.attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
	.size = GEN7_L3LOG_SIZE,
	.read = i915_l3_read,
	.write = i915_l3_write,
	.mmap = NULL,
	.private = (void *)0
};

static struct bin_attribute dpf_attrs_1 = {
	.attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
	.size = GEN7_L3LOG_SIZE,
	.read = i915_l3_read,
	.write = i915_l3_write,
	.mmap = NULL,
	.private = (void *)1
};

static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
				    struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = dev_to_drm_minor(kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

	mutex_lock(&dev_priv->rps.hw_lock);
	if (IS_VALLEYVIEW(dev_priv->dev)) {
		u32 freq;
		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
		ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff);
	} else {
		ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
	}
	mutex_unlock(&dev_priv->rps.hw_lock);

	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
}

static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
				     struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = dev_to_drm_minor(kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	return snprintf(buf, PAGE_SIZE, "%d\n",
			vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay));
}

static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = dev_to_drm_minor(kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

	mutex_lock(&dev_priv->rps.hw_lock);
	if (IS_VALLEYVIEW(dev_priv->dev))
		ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
	else
		ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
	mutex_unlock(&dev_priv->rps.hw_lock);

	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
}

static ssize_t gt_max_freq_mhz_store(struct device *kdev,
				     struct device_attribute *attr,
				     const char *buf, size_t count)
{
	struct drm_minor *minor = dev_to_drm_minor(kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val, rp_state_cap, hw_max, hw_min, non_oc_max;
	ssize_t ret;

	ret = kstrtou32(buf, 0, &val);
	if (ret)
		return ret;

	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

	mutex_lock(&dev_priv->rps.hw_lock);

	if (IS_VALLEYVIEW(dev_priv->dev)) {
		val = vlv_freq_opcode(dev_priv, val);

		hw_max = valleyview_rps_max_freq(dev_priv);
		hw_min = valleyview_rps_min_freq(dev_priv);
		non_oc_max = hw_max;
	} else {
		val /= GT_FREQUENCY_MULTIPLIER;

		rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
		hw_max = dev_priv->rps.hw_max;
		non_oc_max = (rp_state_cap & 0xff);
		hw_min = ((rp_state_cap & 0xff0000) >> 16);
	}

	if (val < hw_min || val > hw_max ||
	    val < dev_priv->rps.min_delay) {
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
	}

	if (val > non_oc_max)
		DRM_DEBUG("User requested overclocking to %d\n",
			  val * GT_FREQUENCY_MULTIPLIER);

	dev_priv->rps.max_delay = val;

	if (dev_priv->rps.cur_delay > val) {
		if (IS_VALLEYVIEW(dev))
			valleyview_set_rps(dev, val);
		else
			gen6_set_rps(dev, val);
	}

	mutex_unlock(&dev_priv->rps.hw_lock);

	return count;
}

static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = dev_to_drm_minor(kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

	mutex_lock(&dev_priv->rps.hw_lock);
	if (IS_VALLEYVIEW(dev_priv->dev))
		ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
	else
		ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
	mutex_unlock(&dev_priv->rps.hw_lock);

	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
}

static ssize_t gt_min_freq_mhz_store(struct device *kdev,
				     struct device_attribute *attr,
				     const char *buf, size_t count)
{
	struct drm_minor *minor = dev_to_drm_minor(kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val, rp_state_cap, hw_max, hw_min;
	ssize_t ret;

	ret = kstrtou32(buf, 0, &val);
	if (ret)
		return ret;

	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

	mutex_lock(&dev_priv->rps.hw_lock);

	if (IS_VALLEYVIEW(dev)) {
		val = vlv_freq_opcode(dev_priv, val);

		hw_max = valleyview_rps_max_freq(dev_priv);
		hw_min = valleyview_rps_min_freq(dev_priv);
	} else {
		val /= GT_FREQUENCY_MULTIPLIER;

		rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
		hw_max = dev_priv->rps.hw_max;
		hw_min = ((rp_state_cap & 0xff0000) >> 16);
	}

	if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
	}

	dev_priv->rps.min_delay = val;

	if (dev_priv->rps.cur_delay < val) {
		if (IS_VALLEYVIEW(dev))
			valleyview_set_rps(dev, val);
		else
			gen6_set_rps(dev, val);
	}

	mutex_unlock(&dev_priv->rps.hw_lock);

	return count;

}

static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);

static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);

static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);

/* For now we have a static number of RP states */
static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = dev_to_drm_minor(kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val, rp_state_cap;
	ssize_t ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	mutex_unlock(&dev->struct_mutex);

	if (attr == &dev_attr_gt_RP0_freq_mhz) {
		val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
		val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
		val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
	} else {
		BUG();
	}
	return snprintf(buf, PAGE_SIZE, "%d\n", val);
}

static const struct attribute *gen6_attrs[] = {
	&dev_attr_gt_cur_freq_mhz.attr,
	&dev_attr_gt_max_freq_mhz.attr,
	&dev_attr_gt_min_freq_mhz.attr,
	&dev_attr_gt_RP0_freq_mhz.attr,
	&dev_attr_gt_RP1_freq_mhz.attr,
	&dev_attr_gt_RPn_freq_mhz.attr,
	NULL,
};

static const struct attribute *vlv_attrs[] = {
	&dev_attr_gt_cur_freq_mhz.attr,
	&dev_attr_gt_max_freq_mhz.attr,
	&dev_attr_gt_min_freq_mhz.attr,
	&dev_attr_vlv_rpe_freq_mhz.attr,
	NULL,
};

static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
				struct bin_attribute *attr, char *buf,
				loff_t off, size_t count)
{

	struct device *kdev = container_of(kobj, struct device, kobj);
	struct drm_minor *minor = dev_to_drm_minor(kdev);
	struct drm_device *dev = minor->dev;
	struct i915_error_state_file_priv error_priv;
	struct drm_i915_error_state_buf error_str;
	ssize_t ret_count = 0;
	int ret;

	memset(&error_priv, 0, sizeof(error_priv));

	ret = i915_error_state_buf_init(&error_str, count, off);
	if (ret)
		return ret;

	error_priv.dev = dev;
	i915_error_state_get(dev, &error_priv);

	ret = i915_error_state_to_str(&error_str, &error_priv);
	if (ret)
		goto out;

	ret_count = count < error_str.bytes ? count : error_str.bytes;

	memcpy(buf, error_str.buf, ret_count);
out:
	i915_error_state_put(&error_priv);
	i915_error_state_buf_release(&error_str);

	return ret ?: ret_count;
}

static ssize_t error_state_write(struct file *file, struct kobject *kobj,
				 struct bin_attribute *attr, char *buf,
				 loff_t off, size_t count)
{
	struct device *kdev = container_of(kobj, struct device, kobj);
	struct drm_minor *minor = dev_to_drm_minor(kdev);
	struct drm_device *dev = minor->dev;
	int ret;

	DRM_DEBUG_DRIVER("Resetting error state\n");

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	i915_destroy_error_state(dev);
	mutex_unlock(&dev->struct_mutex);

	return count;
}

static struct bin_attribute error_state_attr = {
	.attr.name = "error",
	.attr.mode = S_IRUSR | S_IWUSR,
	.size = 0,
	.read = error_state_read,
	.write = error_state_write,
};

void i915_setup_sysfs(struct drm_device *dev)
{
	int ret;

#ifdef CONFIG_PM
	if (INTEL_INFO(dev)->gen >= 6) {
		ret = sysfs_merge_group(&dev->primary->kdev->kobj,
					&rc6_attr_group);
		if (ret)
			DRM_ERROR("RC6 residency sysfs setup failed\n");
	}
#endif
	if (HAS_L3_DPF(dev)) {
		ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs);
		if (ret)
			DRM_ERROR("l3 parity sysfs setup failed\n");

		if (NUM_L3_SLICES(dev) > 1) {
			ret = device_create_bin_file(dev->primary->kdev,
						     &dpf_attrs_1);
			if (ret)
				DRM_ERROR("l3 parity slice 1 setup failed\n");
		}
	}

	ret = 0;
	if (IS_VALLEYVIEW(dev))
		ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
	else if (INTEL_INFO(dev)->gen >= 6)
		ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
	if (ret)
		DRM_ERROR("RPS sysfs setup failed\n");

	ret = sysfs_create_bin_file(&dev->primary->kdev->kobj,
				    &error_state_attr);
	if (ret)
		DRM_ERROR("error_state sysfs setup failed\n");
}

void i915_teardown_sysfs(struct drm_device *dev)
{
	sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
	if (IS_VALLEYVIEW(dev))
		sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
	else
		sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
	device_remove_bin_file(dev->primary->kdev,  &dpf_attrs_1);
	device_remove_bin_file(dev->primary->kdev,  &dpf_attrs);
#ifdef CONFIG_PM
	sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group);
#endif
}
Commit	Line	Data
0136db58 BW	1	/*
	2	* Copyright © 2012 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Ben Widawsky <ben@bwidawsk.net>
	25	*
	26	*/
	27
	28	#include <linux/device.h>
	29	#include <linux/module.h>
	30	#include <linux/stat.h>
	31	#include <linux/sysfs.h>
84bc7581	32	#include "intel_drv.h"
0136db58 BW	33	#include "i915_drv.h"
0136db58 BW	34
5bdebb18	35	#define dev_to_drm_minor(d) dev_get_drvdata((d))
14c8d110	36
5ab3633d	37	#ifdef CONFIG_PM
0136db58 BW	38	static u32 calc_residency(struct drm_device *dev, const u32 reg)
	39	{
	40	struct drm_i915_private *dev_priv = dev->dev_private;
	41	u64 raw_time; /* 32b value may overflow during fixed point math */
e454a05d	42	u64 units = 128ULL, div = 100000ULL, bias = 100ULL;
0136db58 BW	43
	44	if (!intel_enable_rc6(dev))
	45	return 0;
	46
e454a05d JB	47	/* On VLV, residency time is in CZ units rather than 1.28us */
	48	if (IS_VALLEYVIEW(dev)) {
	49	u32 clkctl2;
	50
	51	clkctl2 = I915_READ(VLV_CLK_CTL2) >>
	52	CLK_CTL2_CZCOUNT_30NS_SHIFT;
	53	if (!clkctl2) {
	54	WARN(!clkctl2, "bogus CZ count value");
	55	return 0;
	56	}
	57	units = DIV_ROUND_UP_ULL(30ULL * bias, (u64)clkctl2);
	58	if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
	59	units <<= 8;
	60
	61	div = 1000000ULL * bias;
	62	}
	63
	64	raw_time = I915_READ(reg) * units;
	65	return DIV_ROUND_UP_ULL(raw_time, div);
0136db58 BW	66	}
	67
	68	static ssize_t
dbdfd8e9	69	show_rc6_mask(struct device kdev, struct device_attribute attr, char *buf)
0136db58	70	{
14c8d110	71	struct drm_minor *dminor = dev_to_drm_minor(kdev);
3e2a1556	72	return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
0136db58 BW	73	}
	74
	75	static ssize_t
dbdfd8e9	76	show_rc6_ms(struct device kdev, struct device_attribute attr, char *buf)
0136db58	77	{
5bdebb18	78	struct drm_minor *dminor = dev_get_drvdata(kdev);
0136db58	79	u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
3e2a1556	80	return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
0136db58 BW	81	}
	82
	83	static ssize_t
dbdfd8e9	84	show_rc6p_ms(struct device kdev, struct device_attribute attr, char *buf)
0136db58	85	{
14c8d110	86	struct drm_minor *dminor = dev_to_drm_minor(kdev);
0136db58	87	u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
5ffd494b JB	88	if (IS_VALLEYVIEW(dminor->dev))
5ffd494b JB	89	rc6p_residency = 0;
3e2a1556	90	return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
0136db58 BW	91	}
	92
	93	static ssize_t
dbdfd8e9	94	show_rc6pp_ms(struct device kdev, struct device_attribute attr, char *buf)
0136db58	95	{
14c8d110	96	struct drm_minor *dminor = dev_to_drm_minor(kdev);
0136db58	97	u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
5ffd494b JB	98	if (IS_VALLEYVIEW(dminor->dev))
5ffd494b JB	99	rc6pp_residency = 0;
3e2a1556	100	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
0136db58 BW	101	}
	102
	103	static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
	104	static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
	105	static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
	106	static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
	107
	108	static struct attribute *rc6_attrs[] = {
	109	&dev_attr_rc6_enable.attr,
	110	&dev_attr_rc6_residency_ms.attr,
	111	&dev_attr_rc6p_residency_ms.attr,
	112	&dev_attr_rc6pp_residency_ms.attr,
	113	NULL
	114	};
	115
	116	static struct attribute_group rc6_attr_group = {
	117	.name = power_group_name,
	118	.attrs = rc6_attrs
	119	};
8c3f929b	120	#endif
0136db58	121
84bc7581 BW	122	static int l3_access_valid(struct drm_device *dev, loff_t offset)
84bc7581 BW	123	{
040d2baa	124	if (!HAS_L3_DPF(dev))
84bc7581 BW	125	return -EPERM;
	126
	127	if (offset % 4 != 0)
	128	return -EINVAL;
	129
	130	if (offset >= GEN7_L3LOG_SIZE)
	131	return -ENXIO;
	132
	133	return 0;
	134	}
	135
	136	static ssize_t
	137	i915_l3_read(struct file filp, struct kobject kobj,
	138	struct bin_attribute attr, char buf,
	139	loff_t offset, size_t count)
	140	{
	141	struct device *dev = container_of(kobj, struct device, kobj);
14c8d110	142	struct drm_minor *dminor = dev_to_drm_minor(dev);
84bc7581 BW	143	struct drm_device *drm_dev = dminor->dev;
84bc7581 BW	144	struct drm_i915_private *dev_priv = drm_dev->dev_private;
35a85ac6	145	int slice = (int)(uintptr_t)attr->private;
3ccfd19d	146	int ret;
84bc7581	147
1c3dcd1c BW	148	count = round_down(count, 4);
1c3dcd1c BW	149
84bc7581 BW	150	ret = l3_access_valid(drm_dev, offset);
	151	if (ret)
	152	return ret;
	153
e5ad4026	154	count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
33618ea5	155
84bc7581 BW	156	ret = i915_mutex_lock_interruptible(drm_dev);
	157	if (ret)
	158	return ret;
	159
3ccfd19d BW	160	if (dev_priv->l3_parity.remap_info[slice])
	161	memcpy(buf,
	162	dev_priv->l3_parity.remap_info[slice] + (offset/4),
	163	count);
	164	else
	165	memset(buf, 0, count);
84bc7581	166
84bc7581 BW	167	mutex_unlock(&drm_dev->struct_mutex);
84bc7581 BW	168
1c966dd2	169	return count;
84bc7581 BW	170	}
	171
	172	static ssize_t
	173	i915_l3_write(struct file filp, struct kobject kobj,
	174	struct bin_attribute attr, char buf,
	175	loff_t offset, size_t count)
	176	{
	177	struct device *dev = container_of(kobj, struct device, kobj);
14c8d110	178	struct drm_minor *dminor = dev_to_drm_minor(dev);
84bc7581 BW	179	struct drm_device *drm_dev = dminor->dev;
84bc7581 BW	180	struct drm_i915_private *dev_priv = drm_dev->dev_private;
3ccfd19d	181	struct i915_hw_context *ctx;
84bc7581	182	u32 temp = NULL; / Just here to make handling failures easy */
35a85ac6	183	int slice = (int)(uintptr_t)attr->private;
84bc7581 BW	184	int ret;
84bc7581 BW	185
8245be31 BW	186	if (!HAS_HW_CONTEXTS(drm_dev))
	187	return -ENXIO;
	188
84bc7581 BW	189	ret = l3_access_valid(drm_dev, offset);
	190	if (ret)
	191	return ret;
	192
	193	ret = i915_mutex_lock_interruptible(drm_dev);
	194	if (ret)
	195	return ret;
	196
35a85ac6	197	if (!dev_priv->l3_parity.remap_info[slice]) {
84bc7581 BW	198	temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
	199	if (!temp) {
	200	mutex_unlock(&drm_dev->struct_mutex);
	201	return -ENOMEM;
	202	}
	203	}
	204
	205	ret = i915_gpu_idle(drm_dev);
	206	if (ret) {
	207	kfree(temp);
	208	mutex_unlock(&drm_dev->struct_mutex);
	209	return ret;
	210	}
	211
	212	/* TODO: Ideally we really want a GPU reset here to make sure errors
	213	* aren't propagated. Since I cannot find a stable way to reset the GPU
	214	* at this point it is left as a TODO.
	215	*/
	216	if (temp)
35a85ac6	217	dev_priv->l3_parity.remap_info[slice] = temp;
84bc7581	218
35a85ac6	219	memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);
84bc7581	220
3ccfd19d BW	221	/* NB: We defer the remapping until we switch to the context */
	222	list_for_each_entry(ctx, &dev_priv->context_list, link)
	223	ctx->remap_slice \|= (1<<slice);
84bc7581 BW	224
	225	mutex_unlock(&drm_dev->struct_mutex);
	226
	227	return count;
	228	}
	229
	230	static struct bin_attribute dpf_attrs = {
	231	.attr = {.name = "l3_parity", .mode = (S_IRUSR \| S_IWUSR)},
	232	.size = GEN7_L3LOG_SIZE,
	233	.read = i915_l3_read,
	234	.write = i915_l3_write,
35a85ac6 BW	235	.mmap = NULL,
	236	.private = (void *)0
	237	};
	238
	239	static struct bin_attribute dpf_attrs_1 = {
	240	.attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR \| S_IWUSR)},
	241	.size = GEN7_L3LOG_SIZE,
	242	.read = i915_l3_read,
	243	.write = i915_l3_write,
	244	.mmap = NULL,
	245	.private = (void *)1
84bc7581 BW	246	};
84bc7581 BW	247
df6eedc8 BW	248	static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
	249	struct device_attribute attr, char buf)
	250	{
14c8d110	251	struct drm_minor *minor = dev_to_drm_minor(kdev);
df6eedc8 BW	252	struct drm_device *dev = minor->dev;
	253	struct drm_i915_private *dev_priv = dev->dev_private;
	254	int ret;
	255
5c9669ce TR	256	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5c9669ce TR	257
4fc688ce	258	mutex_lock(&dev_priv->rps.hw_lock);
177006a1 JB	259	if (IS_VALLEYVIEW(dev_priv->dev)) {
177006a1 JB	260	u32 freq;
64936258	261	freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2ec3815f	262	ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff);
177006a1	263	} else {
0a073b84	264	ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
177006a1	265	}
4fc688ce	266	mutex_unlock(&dev_priv->rps.hw_lock);
df6eedc8	267
3e2a1556	268	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
df6eedc8 BW	269	}
df6eedc8 BW	270
97e4eed7 CW	271	static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
	272	struct device_attribute attr, char buf)
	273	{
14c8d110	274	struct drm_minor *minor = dev_to_drm_minor(kdev);
97e4eed7 CW	275	struct drm_device *dev = minor->dev;
	276	struct drm_i915_private *dev_priv = dev->dev_private;
	277
	278	return snprintf(buf, PAGE_SIZE, "%d\n",
2ec3815f	279	vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay));
97e4eed7 CW	280	}
97e4eed7 CW	281
df6eedc8 BW	282	static ssize_t gt_max_freq_mhz_show(struct device kdev, struct device_attribute attr, char *buf)
df6eedc8 BW	283	{
14c8d110	284	struct drm_minor *minor = dev_to_drm_minor(kdev);
df6eedc8 BW	285	struct drm_device *dev = minor->dev;
	286	struct drm_i915_private *dev_priv = dev->dev_private;
	287	int ret;
	288
5c9669ce TR	289	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5c9669ce TR	290
4fc688ce	291	mutex_lock(&dev_priv->rps.hw_lock);
0a073b84	292	if (IS_VALLEYVIEW(dev_priv->dev))
2ec3815f	293	ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
0a073b84 JB	294	else
0a073b84 JB	295	ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce	296	mutex_unlock(&dev_priv->rps.hw_lock);
df6eedc8	297
3e2a1556	298	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
df6eedc8 BW	299	}
df6eedc8 BW	300
46ddf194 BW	301	static ssize_t gt_max_freq_mhz_store(struct device *kdev,
	302	struct device_attribute *attr,
	303	const char *buf, size_t count)
	304	{
14c8d110	305	struct drm_minor *minor = dev_to_drm_minor(kdev);
46ddf194 BW	306	struct drm_device *dev = minor->dev;
46ddf194 BW	307	struct drm_i915_private *dev_priv = dev->dev_private;
31c77388	308	u32 val, rp_state_cap, hw_max, hw_min, non_oc_max;
46ddf194 BW	309	ssize_t ret;
	310
	311	ret = kstrtou32(buf, 0, &val);
	312	if (ret)
	313	return ret;
	314
5c9669ce TR	315	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5c9669ce TR	316
4fc688ce	317	mutex_lock(&dev_priv->rps.hw_lock);
46ddf194	318
0a073b84	319	if (IS_VALLEYVIEW(dev_priv->dev)) {
2ec3815f	320	val = vlv_freq_opcode(dev_priv, val);
0a073b84 JB	321
	322	hw_max = valleyview_rps_max_freq(dev_priv);
	323	hw_min = valleyview_rps_min_freq(dev_priv);
	324	non_oc_max = hw_max;
	325	} else {
	326	val /= GT_FREQUENCY_MULTIPLIER;
46ddf194	327
0a073b84 JB	328	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	329	hw_max = dev_priv->rps.hw_max;
	330	non_oc_max = (rp_state_cap & 0xff);
	331	hw_min = ((rp_state_cap & 0xff0000) >> 16);
	332	}
	333
	334	if (val < hw_min \|\| val > hw_max \|\|
	335	val < dev_priv->rps.min_delay) {
4fc688ce	336	mutex_unlock(&dev_priv->rps.hw_lock);
46ddf194 BW	337	return -EINVAL;
	338	}
	339
31c77388 BW	340	if (val > non_oc_max)
	341	DRM_DEBUG("User requested overclocking to %d\n",
	342	val * GT_FREQUENCY_MULTIPLIER);
	343
6917c7b9 CW	344	dev_priv->rps.max_delay = val;
6917c7b9 CW	345
0a073b84	346	if (dev_priv->rps.cur_delay > val) {
6917c7b9 CW	347	if (IS_VALLEYVIEW(dev))
6917c7b9 CW	348	valleyview_set_rps(dev, val);
0a073b84	349	else
6917c7b9	350	gen6_set_rps(dev, val);
0a073b84	351	}
46ddf194	352
4fc688ce	353	mutex_unlock(&dev_priv->rps.hw_lock);
46ddf194 BW	354
	355	return count;
	356	}
	357
df6eedc8 BW	358	static ssize_t gt_min_freq_mhz_show(struct device kdev, struct device_attribute attr, char *buf)
df6eedc8 BW	359	{
14c8d110	360	struct drm_minor *minor = dev_to_drm_minor(kdev);
df6eedc8 BW	361	struct drm_device *dev = minor->dev;
	362	struct drm_i915_private *dev_priv = dev->dev_private;
	363	int ret;
	364
5c9669ce TR	365	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5c9669ce TR	366
4fc688ce	367	mutex_lock(&dev_priv->rps.hw_lock);
0a073b84	368	if (IS_VALLEYVIEW(dev_priv->dev))
2ec3815f	369	ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
0a073b84 JB	370	else
0a073b84 JB	371	ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce	372	mutex_unlock(&dev_priv->rps.hw_lock);
df6eedc8	373
3e2a1556	374	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
df6eedc8 BW	375	}
df6eedc8 BW	376
46ddf194 BW	377	static ssize_t gt_min_freq_mhz_store(struct device *kdev,
	378	struct device_attribute *attr,
	379	const char *buf, size_t count)
	380	{
14c8d110	381	struct drm_minor *minor = dev_to_drm_minor(kdev);
46ddf194 BW	382	struct drm_device *dev = minor->dev;
	383	struct drm_i915_private *dev_priv = dev->dev_private;
	384	u32 val, rp_state_cap, hw_max, hw_min;
	385	ssize_t ret;
	386
	387	ret = kstrtou32(buf, 0, &val);
	388	if (ret)
	389	return ret;
	390
5c9669ce TR	391	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5c9669ce TR	392
4fc688ce	393	mutex_lock(&dev_priv->rps.hw_lock);
46ddf194	394
0a073b84	395	if (IS_VALLEYVIEW(dev)) {
2ec3815f	396	val = vlv_freq_opcode(dev_priv, val);
0a073b84 JB	397
	398	hw_max = valleyview_rps_max_freq(dev_priv);
	399	hw_min = valleyview_rps_min_freq(dev_priv);
	400	} else {
	401	val /= GT_FREQUENCY_MULTIPLIER;
	402
	403	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	404	hw_max = dev_priv->rps.hw_max;
	405	hw_min = ((rp_state_cap & 0xff0000) >> 16);
	406	}
46ddf194 BW	407
46ddf194 BW	408	if (val < hw_min \|\| val > hw_max \|\| val > dev_priv->rps.max_delay) {
4fc688ce	409	mutex_unlock(&dev_priv->rps.hw_lock);
46ddf194 BW	410	return -EINVAL;
	411	}
	412
6917c7b9 CW	413	dev_priv->rps.min_delay = val;
6917c7b9 CW	414
0a073b84 JB	415	if (dev_priv->rps.cur_delay < val) {
	416	if (IS_VALLEYVIEW(dev))
	417	valleyview_set_rps(dev, val);
	418	else
6917c7b9	419	gen6_set_rps(dev, val);
0a073b84	420	}
46ddf194	421
4fc688ce	422	mutex_unlock(&dev_priv->rps.hw_lock);
46ddf194 BW	423
	424	return count;
	425
	426	}
	427
df6eedc8	428	static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
46ddf194 BW	429	static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO \| S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
46ddf194 BW	430	static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO \| S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
df6eedc8	431
97e4eed7	432	static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
ac6ae347 BW	433
	434	static ssize_t gt_rp_mhz_show(struct device kdev, struct device_attribute attr, char *buf);
	435	static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
	436	static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
	437	static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
	438
	439	/* For now we have a static number of RP states */
	440	static ssize_t gt_rp_mhz_show(struct device kdev, struct device_attribute attr, char *buf)
	441	{
14c8d110	442	struct drm_minor *minor = dev_to_drm_minor(kdev);
ac6ae347 BW	443	struct drm_device *dev = minor->dev;
	444	struct drm_i915_private *dev_priv = dev->dev_private;
	445	u32 val, rp_state_cap;
	446	ssize_t ret;
	447
	448	ret = mutex_lock_interruptible(&dev->struct_mutex);
	449	if (ret)
	450	return ret;
	451	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	452	mutex_unlock(&dev->struct_mutex);
	453
	454	if (attr == &dev_attr_gt_RP0_freq_mhz) {
	455	val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
	456	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
	457	val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
	458	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
	459	val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
	460	} else {
	461	BUG();
	462	}
3e2a1556	463	return snprintf(buf, PAGE_SIZE, "%d\n", val);
ac6ae347 BW	464	}
ac6ae347 BW	465
df6eedc8 BW	466	static const struct attribute *gen6_attrs[] = {
	467	&dev_attr_gt_cur_freq_mhz.attr,
	468	&dev_attr_gt_max_freq_mhz.attr,
	469	&dev_attr_gt_min_freq_mhz.attr,
ac6ae347 BW	470	&dev_attr_gt_RP0_freq_mhz.attr,
	471	&dev_attr_gt_RP1_freq_mhz.attr,
	472	&dev_attr_gt_RPn_freq_mhz.attr,
df6eedc8 BW	473	NULL,
	474	};
	475
97e4eed7 CW	476	static const struct attribute *vlv_attrs[] = {
	477	&dev_attr_gt_cur_freq_mhz.attr,
	478	&dev_attr_gt_max_freq_mhz.attr,
	479	&dev_attr_gt_min_freq_mhz.attr,
	480	&dev_attr_vlv_rpe_freq_mhz.attr,
	481	NULL,
	482	};
	483
ef86ddce MK	484	static ssize_t error_state_read(struct file filp, struct kobject kobj,
	485	struct bin_attribute attr, char buf,
	486	loff_t off, size_t count)
	487	{
	488
	489	struct device *kdev = container_of(kobj, struct device, kobj);
14c8d110	490	struct drm_minor *minor = dev_to_drm_minor(kdev);
ef86ddce MK	491	struct drm_device *dev = minor->dev;
	492	struct i915_error_state_file_priv error_priv;
	493	struct drm_i915_error_state_buf error_str;
	494	ssize_t ret_count = 0;
	495	int ret;
	496
	497	memset(&error_priv, 0, sizeof(error_priv));
	498
	499	ret = i915_error_state_buf_init(&error_str, count, off);
	500	if (ret)
	501	return ret;
	502
	503	error_priv.dev = dev;
	504	i915_error_state_get(dev, &error_priv);
	505
	506	ret = i915_error_state_to_str(&error_str, &error_priv);
	507	if (ret)
	508	goto out;
	509
	510	ret_count = count < error_str.bytes ? count : error_str.bytes;
	511
	512	memcpy(buf, error_str.buf, ret_count);
	513	out:
	514	i915_error_state_put(&error_priv);
	515	i915_error_state_buf_release(&error_str);
	516
	517	return ret ?: ret_count;
	518	}
	519
	520	static ssize_t error_state_write(struct file file, struct kobject kobj,
	521	struct bin_attribute attr, char buf,
	522	loff_t off, size_t count)
	523	{
	524	struct device *kdev = container_of(kobj, struct device, kobj);
14c8d110	525	struct drm_minor *minor = dev_to_drm_minor(kdev);
ef86ddce MK	526	struct drm_device *dev = minor->dev;
	527	int ret;
	528
	529	DRM_DEBUG_DRIVER("Resetting error state\n");
	530
	531	ret = mutex_lock_interruptible(&dev->struct_mutex);
	532	if (ret)
	533	return ret;
	534
	535	i915_destroy_error_state(dev);
	536	mutex_unlock(&dev->struct_mutex);
	537
	538	return count;
	539	}
	540
	541	static struct bin_attribute error_state_attr = {
	542	.attr.name = "error",
	543	.attr.mode = S_IRUSR \| S_IWUSR,
	544	.size = 0,
	545	.read = error_state_read,
	546	.write = error_state_write,
	547	};
	548
0136db58 BW	549	void i915_setup_sysfs(struct drm_device *dev)
	550	{
	551	int ret;
	552
8c3f929b	553	#ifdef CONFIG_PM
112abd29	554	if (INTEL_INFO(dev)->gen >= 6) {
5bdebb18	555	ret = sysfs_merge_group(&dev->primary->kdev->kobj,
112abd29 DV	556	&rc6_attr_group);
	557	if (ret)
	558	DRM_ERROR("RC6 residency sysfs setup failed\n");
	559	}
8c3f929b	560	#endif
040d2baa	561	if (HAS_L3_DPF(dev)) {
5bdebb18	562	ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs);
112abd29 DV	563	if (ret)
112abd29 DV	564	DRM_ERROR("l3 parity sysfs setup failed\n");
35a85ac6 BW	565
35a85ac6 BW	566	if (NUM_L3_SLICES(dev) > 1) {
5bdebb18	567	ret = device_create_bin_file(dev->primary->kdev,
35a85ac6 BW	568	&dpf_attrs_1);
	569	if (ret)
	570	DRM_ERROR("l3 parity slice 1 setup failed\n");
	571	}
112abd29	572	}
df6eedc8	573
97e4eed7 CW	574	ret = 0;
97e4eed7 CW	575	if (IS_VALLEYVIEW(dev))
5bdebb18	576	ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
97e4eed7	577	else if (INTEL_INFO(dev)->gen >= 6)
5bdebb18	578	ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
97e4eed7 CW	579	if (ret)
97e4eed7 CW	580	DRM_ERROR("RPS sysfs setup failed\n");
ef86ddce	581
5bdebb18	582	ret = sysfs_create_bin_file(&dev->primary->kdev->kobj,
ef86ddce MK	583	&error_state_attr);
	584	if (ret)
	585	DRM_ERROR("error_state sysfs setup failed\n");
0136db58 BW	586	}
	587
	588	void i915_teardown_sysfs(struct drm_device *dev)
	589	{
5bdebb18	590	sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
97e4eed7	591	if (IS_VALLEYVIEW(dev))
5bdebb18	592	sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
97e4eed7	593	else
5bdebb18 DA	594	sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
	595	device_remove_bin_file(dev->primary->kdev, &dpf_attrs_1);
	596	device_remove_bin_file(dev->primary->kdev, &dpf_attrs);
853c70e8	597	#ifdef CONFIG_PM
5bdebb18	598	sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group);
853c70e8	599	#endif
0136db58	600	}