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0136db58 BW |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/device.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/stat.h> | |
31 | #include <linux/sysfs.h> | |
84bc7581 | 32 | #include "intel_drv.h" |
0136db58 BW |
33 | #include "i915_drv.h" |
34 | ||
5bdebb18 | 35 | #define dev_to_drm_minor(d) dev_get_drvdata((d)) |
14c8d110 | 36 | |
5ab3633d | 37 | #ifdef CONFIG_PM |
0136db58 BW |
38 | static u32 calc_residency(struct drm_device *dev, const u32 reg) |
39 | { | |
40 | struct drm_i915_private *dev_priv = dev->dev_private; | |
41 | u64 raw_time; /* 32b value may overflow during fixed point math */ | |
e454a05d | 42 | u64 units = 128ULL, div = 100000ULL, bias = 100ULL; |
c8c8fb33 | 43 | u32 ret; |
0136db58 BW |
44 | |
45 | if (!intel_enable_rc6(dev)) | |
46 | return 0; | |
47 | ||
c8c8fb33 PZ |
48 | intel_runtime_pm_get(dev_priv); |
49 | ||
e454a05d JB |
50 | /* On VLV, residency time is in CZ units rather than 1.28us */ |
51 | if (IS_VALLEYVIEW(dev)) { | |
52 | u32 clkctl2; | |
53 | ||
54 | clkctl2 = I915_READ(VLV_CLK_CTL2) >> | |
55 | CLK_CTL2_CZCOUNT_30NS_SHIFT; | |
56 | if (!clkctl2) { | |
57 | WARN(!clkctl2, "bogus CZ count value"); | |
c8c8fb33 PZ |
58 | ret = 0; |
59 | goto out; | |
e454a05d JB |
60 | } |
61 | units = DIV_ROUND_UP_ULL(30ULL * bias, (u64)clkctl2); | |
62 | if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) | |
63 | units <<= 8; | |
64 | ||
65 | div = 1000000ULL * bias; | |
66 | } | |
67 | ||
68 | raw_time = I915_READ(reg) * units; | |
c8c8fb33 PZ |
69 | ret = DIV_ROUND_UP_ULL(raw_time, div); |
70 | ||
71 | out: | |
72 | intel_runtime_pm_put(dev_priv); | |
73 | return ret; | |
0136db58 BW |
74 | } |
75 | ||
76 | static ssize_t | |
dbdfd8e9 | 77 | show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 78 | { |
14c8d110 | 79 | struct drm_minor *dminor = dev_to_drm_minor(kdev); |
3e2a1556 | 80 | return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev)); |
0136db58 BW |
81 | } |
82 | ||
83 | static ssize_t | |
dbdfd8e9 | 84 | show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 85 | { |
5bdebb18 | 86 | struct drm_minor *dminor = dev_get_drvdata(kdev); |
0136db58 | 87 | u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6); |
3e2a1556 | 88 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); |
0136db58 BW |
89 | } |
90 | ||
91 | static ssize_t | |
dbdfd8e9 | 92 | show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 93 | { |
14c8d110 | 94 | struct drm_minor *dminor = dev_to_drm_minor(kdev); |
0136db58 | 95 | u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p); |
5ffd494b JB |
96 | if (IS_VALLEYVIEW(dminor->dev)) |
97 | rc6p_residency = 0; | |
3e2a1556 | 98 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency); |
0136db58 BW |
99 | } |
100 | ||
101 | static ssize_t | |
dbdfd8e9 | 102 | show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 103 | { |
14c8d110 | 104 | struct drm_minor *dminor = dev_to_drm_minor(kdev); |
0136db58 | 105 | u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp); |
5ffd494b JB |
106 | if (IS_VALLEYVIEW(dminor->dev)) |
107 | rc6pp_residency = 0; | |
3e2a1556 | 108 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency); |
0136db58 BW |
109 | } |
110 | ||
111 | static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL); | |
112 | static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL); | |
113 | static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL); | |
114 | static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL); | |
115 | ||
116 | static struct attribute *rc6_attrs[] = { | |
117 | &dev_attr_rc6_enable.attr, | |
118 | &dev_attr_rc6_residency_ms.attr, | |
119 | &dev_attr_rc6p_residency_ms.attr, | |
120 | &dev_attr_rc6pp_residency_ms.attr, | |
121 | NULL | |
122 | }; | |
123 | ||
124 | static struct attribute_group rc6_attr_group = { | |
125 | .name = power_group_name, | |
126 | .attrs = rc6_attrs | |
127 | }; | |
8c3f929b | 128 | #endif |
0136db58 | 129 | |
84bc7581 BW |
130 | static int l3_access_valid(struct drm_device *dev, loff_t offset) |
131 | { | |
040d2baa | 132 | if (!HAS_L3_DPF(dev)) |
84bc7581 BW |
133 | return -EPERM; |
134 | ||
135 | if (offset % 4 != 0) | |
136 | return -EINVAL; | |
137 | ||
138 | if (offset >= GEN7_L3LOG_SIZE) | |
139 | return -ENXIO; | |
140 | ||
141 | return 0; | |
142 | } | |
143 | ||
144 | static ssize_t | |
145 | i915_l3_read(struct file *filp, struct kobject *kobj, | |
146 | struct bin_attribute *attr, char *buf, | |
147 | loff_t offset, size_t count) | |
148 | { | |
149 | struct device *dev = container_of(kobj, struct device, kobj); | |
14c8d110 | 150 | struct drm_minor *dminor = dev_to_drm_minor(dev); |
84bc7581 BW |
151 | struct drm_device *drm_dev = dminor->dev; |
152 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
35a85ac6 | 153 | int slice = (int)(uintptr_t)attr->private; |
3ccfd19d | 154 | int ret; |
84bc7581 | 155 | |
1c3dcd1c BW |
156 | count = round_down(count, 4); |
157 | ||
84bc7581 BW |
158 | ret = l3_access_valid(drm_dev, offset); |
159 | if (ret) | |
160 | return ret; | |
161 | ||
e5ad4026 | 162 | count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count); |
33618ea5 | 163 | |
84bc7581 BW |
164 | ret = i915_mutex_lock_interruptible(drm_dev); |
165 | if (ret) | |
166 | return ret; | |
167 | ||
3ccfd19d BW |
168 | if (dev_priv->l3_parity.remap_info[slice]) |
169 | memcpy(buf, | |
170 | dev_priv->l3_parity.remap_info[slice] + (offset/4), | |
171 | count); | |
172 | else | |
173 | memset(buf, 0, count); | |
84bc7581 | 174 | |
84bc7581 BW |
175 | mutex_unlock(&drm_dev->struct_mutex); |
176 | ||
1c966dd2 | 177 | return count; |
84bc7581 BW |
178 | } |
179 | ||
180 | static ssize_t | |
181 | i915_l3_write(struct file *filp, struct kobject *kobj, | |
182 | struct bin_attribute *attr, char *buf, | |
183 | loff_t offset, size_t count) | |
184 | { | |
185 | struct device *dev = container_of(kobj, struct device, kobj); | |
14c8d110 | 186 | struct drm_minor *dminor = dev_to_drm_minor(dev); |
84bc7581 BW |
187 | struct drm_device *drm_dev = dminor->dev; |
188 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
273497e5 | 189 | struct intel_context *ctx; |
84bc7581 | 190 | u32 *temp = NULL; /* Just here to make handling failures easy */ |
35a85ac6 | 191 | int slice = (int)(uintptr_t)attr->private; |
84bc7581 BW |
192 | int ret; |
193 | ||
8245be31 BW |
194 | if (!HAS_HW_CONTEXTS(drm_dev)) |
195 | return -ENXIO; | |
196 | ||
84bc7581 BW |
197 | ret = l3_access_valid(drm_dev, offset); |
198 | if (ret) | |
199 | return ret; | |
200 | ||
201 | ret = i915_mutex_lock_interruptible(drm_dev); | |
202 | if (ret) | |
203 | return ret; | |
204 | ||
35a85ac6 | 205 | if (!dev_priv->l3_parity.remap_info[slice]) { |
84bc7581 BW |
206 | temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL); |
207 | if (!temp) { | |
208 | mutex_unlock(&drm_dev->struct_mutex); | |
209 | return -ENOMEM; | |
210 | } | |
211 | } | |
212 | ||
213 | ret = i915_gpu_idle(drm_dev); | |
214 | if (ret) { | |
215 | kfree(temp); | |
216 | mutex_unlock(&drm_dev->struct_mutex); | |
217 | return ret; | |
218 | } | |
219 | ||
220 | /* TODO: Ideally we really want a GPU reset here to make sure errors | |
221 | * aren't propagated. Since I cannot find a stable way to reset the GPU | |
222 | * at this point it is left as a TODO. | |
223 | */ | |
224 | if (temp) | |
35a85ac6 | 225 | dev_priv->l3_parity.remap_info[slice] = temp; |
84bc7581 | 226 | |
35a85ac6 | 227 | memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count); |
84bc7581 | 228 | |
3ccfd19d BW |
229 | /* NB: We defer the remapping until we switch to the context */ |
230 | list_for_each_entry(ctx, &dev_priv->context_list, link) | |
231 | ctx->remap_slice |= (1<<slice); | |
84bc7581 BW |
232 | |
233 | mutex_unlock(&drm_dev->struct_mutex); | |
234 | ||
235 | return count; | |
236 | } | |
237 | ||
238 | static struct bin_attribute dpf_attrs = { | |
239 | .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, | |
240 | .size = GEN7_L3LOG_SIZE, | |
241 | .read = i915_l3_read, | |
242 | .write = i915_l3_write, | |
35a85ac6 BW |
243 | .mmap = NULL, |
244 | .private = (void *)0 | |
245 | }; | |
246 | ||
247 | static struct bin_attribute dpf_attrs_1 = { | |
248 | .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, | |
249 | .size = GEN7_L3LOG_SIZE, | |
250 | .read = i915_l3_read, | |
251 | .write = i915_l3_write, | |
252 | .mmap = NULL, | |
253 | .private = (void *)1 | |
84bc7581 BW |
254 | }; |
255 | ||
df6eedc8 BW |
256 | static ssize_t gt_cur_freq_mhz_show(struct device *kdev, |
257 | struct device_attribute *attr, char *buf) | |
258 | { | |
14c8d110 | 259 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
df6eedc8 BW |
260 | struct drm_device *dev = minor->dev; |
261 | struct drm_i915_private *dev_priv = dev->dev_private; | |
262 | int ret; | |
263 | ||
5c9669ce TR |
264 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
265 | ||
d46c0517 ID |
266 | intel_runtime_pm_get(dev_priv); |
267 | ||
4fc688ce | 268 | mutex_lock(&dev_priv->rps.hw_lock); |
177006a1 JB |
269 | if (IS_VALLEYVIEW(dev_priv->dev)) { |
270 | u32 freq; | |
64936258 | 271 | freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
2ec3815f | 272 | ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff); |
177006a1 | 273 | } else { |
b39fb297 | 274 | ret = dev_priv->rps.cur_freq * GT_FREQUENCY_MULTIPLIER; |
177006a1 | 275 | } |
4fc688ce | 276 | mutex_unlock(&dev_priv->rps.hw_lock); |
df6eedc8 | 277 | |
d46c0517 ID |
278 | intel_runtime_pm_put(dev_priv); |
279 | ||
3e2a1556 | 280 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); |
df6eedc8 BW |
281 | } |
282 | ||
97e4eed7 CW |
283 | static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, |
284 | struct device_attribute *attr, char *buf) | |
285 | { | |
14c8d110 | 286 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
97e4eed7 CW |
287 | struct drm_device *dev = minor->dev; |
288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
289 | ||
290 | return snprintf(buf, PAGE_SIZE, "%d\n", | |
b39fb297 | 291 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); |
97e4eed7 CW |
292 | } |
293 | ||
df6eedc8 BW |
294 | static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) |
295 | { | |
14c8d110 | 296 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
df6eedc8 BW |
297 | struct drm_device *dev = minor->dev; |
298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
299 | int ret; | |
300 | ||
5c9669ce TR |
301 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
302 | ||
4fc688ce | 303 | mutex_lock(&dev_priv->rps.hw_lock); |
0a073b84 | 304 | if (IS_VALLEYVIEW(dev_priv->dev)) |
b39fb297 | 305 | ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
0a073b84 | 306 | else |
b39fb297 | 307 | ret = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
4fc688ce | 308 | mutex_unlock(&dev_priv->rps.hw_lock); |
df6eedc8 | 309 | |
3e2a1556 | 310 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); |
df6eedc8 BW |
311 | } |
312 | ||
46ddf194 BW |
313 | static ssize_t gt_max_freq_mhz_store(struct device *kdev, |
314 | struct device_attribute *attr, | |
315 | const char *buf, size_t count) | |
316 | { | |
14c8d110 | 317 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
46ddf194 BW |
318 | struct drm_device *dev = minor->dev; |
319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2a5913a8 | 320 | u32 val; |
46ddf194 BW |
321 | ssize_t ret; |
322 | ||
323 | ret = kstrtou32(buf, 0, &val); | |
324 | if (ret) | |
325 | return ret; | |
326 | ||
5c9669ce TR |
327 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
328 | ||
4fc688ce | 329 | mutex_lock(&dev_priv->rps.hw_lock); |
46ddf194 | 330 | |
2a5913a8 | 331 | if (IS_VALLEYVIEW(dev_priv->dev)) |
2ec3815f | 332 | val = vlv_freq_opcode(dev_priv, val); |
2a5913a8 | 333 | else |
0a073b84 | 334 | val /= GT_FREQUENCY_MULTIPLIER; |
46ddf194 | 335 | |
2a5913a8 BW |
336 | if (val < dev_priv->rps.min_freq || |
337 | val > dev_priv->rps.max_freq || | |
b39fb297 | 338 | val < dev_priv->rps.min_freq_softlimit) { |
4fc688ce | 339 | mutex_unlock(&dev_priv->rps.hw_lock); |
46ddf194 BW |
340 | return -EINVAL; |
341 | } | |
342 | ||
2a5913a8 | 343 | if (val > dev_priv->rps.rp0_freq) |
31c77388 BW |
344 | DRM_DEBUG("User requested overclocking to %d\n", |
345 | val * GT_FREQUENCY_MULTIPLIER); | |
346 | ||
b39fb297 | 347 | dev_priv->rps.max_freq_softlimit = val; |
6917c7b9 | 348 | |
b39fb297 | 349 | if (dev_priv->rps.cur_freq > val) { |
6917c7b9 CW |
350 | if (IS_VALLEYVIEW(dev)) |
351 | valleyview_set_rps(dev, val); | |
0a073b84 | 352 | else |
6917c7b9 | 353 | gen6_set_rps(dev, val); |
5a953add BW |
354 | } else if (!IS_VALLEYVIEW(dev)) { |
355 | /* We still need gen6_set_rps to process the new max_delay and | |
356 | * update the interrupt limits even though frequency request is | |
357 | * unchanged. */ | |
b39fb297 | 358 | gen6_set_rps(dev, dev_priv->rps.cur_freq); |
5a953add | 359 | } |
46ddf194 | 360 | |
4fc688ce | 361 | mutex_unlock(&dev_priv->rps.hw_lock); |
46ddf194 BW |
362 | |
363 | return count; | |
364 | } | |
365 | ||
df6eedc8 BW |
366 | static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) |
367 | { | |
14c8d110 | 368 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
df6eedc8 BW |
369 | struct drm_device *dev = minor->dev; |
370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
371 | int ret; | |
372 | ||
5c9669ce TR |
373 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
374 | ||
4fc688ce | 375 | mutex_lock(&dev_priv->rps.hw_lock); |
0a073b84 | 376 | if (IS_VALLEYVIEW(dev_priv->dev)) |
b39fb297 | 377 | ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
0a073b84 | 378 | else |
b39fb297 | 379 | ret = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
4fc688ce | 380 | mutex_unlock(&dev_priv->rps.hw_lock); |
df6eedc8 | 381 | |
3e2a1556 | 382 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); |
df6eedc8 BW |
383 | } |
384 | ||
46ddf194 BW |
385 | static ssize_t gt_min_freq_mhz_store(struct device *kdev, |
386 | struct device_attribute *attr, | |
387 | const char *buf, size_t count) | |
388 | { | |
14c8d110 | 389 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
46ddf194 BW |
390 | struct drm_device *dev = minor->dev; |
391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2a5913a8 | 392 | u32 val; |
46ddf194 BW |
393 | ssize_t ret; |
394 | ||
395 | ret = kstrtou32(buf, 0, &val); | |
396 | if (ret) | |
397 | return ret; | |
398 | ||
5c9669ce TR |
399 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
400 | ||
4fc688ce | 401 | mutex_lock(&dev_priv->rps.hw_lock); |
46ddf194 | 402 | |
2a5913a8 | 403 | if (IS_VALLEYVIEW(dev)) |
2ec3815f | 404 | val = vlv_freq_opcode(dev_priv, val); |
2a5913a8 | 405 | else |
0a073b84 JB |
406 | val /= GT_FREQUENCY_MULTIPLIER; |
407 | ||
2a5913a8 BW |
408 | if (val < dev_priv->rps.min_freq || |
409 | val > dev_priv->rps.max_freq || | |
410 | val > dev_priv->rps.max_freq_softlimit) { | |
4fc688ce | 411 | mutex_unlock(&dev_priv->rps.hw_lock); |
46ddf194 BW |
412 | return -EINVAL; |
413 | } | |
414 | ||
b39fb297 | 415 | dev_priv->rps.min_freq_softlimit = val; |
6917c7b9 | 416 | |
b39fb297 | 417 | if (dev_priv->rps.cur_freq < val) { |
0a073b84 JB |
418 | if (IS_VALLEYVIEW(dev)) |
419 | valleyview_set_rps(dev, val); | |
420 | else | |
6917c7b9 | 421 | gen6_set_rps(dev, val); |
5a953add BW |
422 | } else if (!IS_VALLEYVIEW(dev)) { |
423 | /* We still need gen6_set_rps to process the new min_delay and | |
424 | * update the interrupt limits even though frequency request is | |
425 | * unchanged. */ | |
b39fb297 | 426 | gen6_set_rps(dev, dev_priv->rps.cur_freq); |
5a953add | 427 | } |
46ddf194 | 428 | |
4fc688ce | 429 | mutex_unlock(&dev_priv->rps.hw_lock); |
46ddf194 BW |
430 | |
431 | return count; | |
432 | ||
433 | } | |
434 | ||
df6eedc8 | 435 | static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL); |
46ddf194 BW |
436 | static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store); |
437 | static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store); | |
df6eedc8 | 438 | |
97e4eed7 | 439 | static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL); |
ac6ae347 BW |
440 | |
441 | static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf); | |
442 | static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); | |
443 | static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); | |
444 | static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); | |
445 | ||
446 | /* For now we have a static number of RP states */ | |
447 | static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) | |
448 | { | |
14c8d110 | 449 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
ac6ae347 BW |
450 | struct drm_device *dev = minor->dev; |
451 | struct drm_i915_private *dev_priv = dev->dev_private; | |
452 | u32 val, rp_state_cap; | |
453 | ssize_t ret; | |
454 | ||
455 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
456 | if (ret) | |
457 | return ret; | |
c8c8fb33 | 458 | intel_runtime_pm_get(dev_priv); |
ac6ae347 | 459 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
c8c8fb33 | 460 | intel_runtime_pm_put(dev_priv); |
ac6ae347 BW |
461 | mutex_unlock(&dev->struct_mutex); |
462 | ||
463 | if (attr == &dev_attr_gt_RP0_freq_mhz) { | |
464 | val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER; | |
465 | } else if (attr == &dev_attr_gt_RP1_freq_mhz) { | |
466 | val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER; | |
467 | } else if (attr == &dev_attr_gt_RPn_freq_mhz) { | |
468 | val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER; | |
469 | } else { | |
470 | BUG(); | |
471 | } | |
3e2a1556 | 472 | return snprintf(buf, PAGE_SIZE, "%d\n", val); |
ac6ae347 BW |
473 | } |
474 | ||
df6eedc8 BW |
475 | static const struct attribute *gen6_attrs[] = { |
476 | &dev_attr_gt_cur_freq_mhz.attr, | |
477 | &dev_attr_gt_max_freq_mhz.attr, | |
478 | &dev_attr_gt_min_freq_mhz.attr, | |
ac6ae347 BW |
479 | &dev_attr_gt_RP0_freq_mhz.attr, |
480 | &dev_attr_gt_RP1_freq_mhz.attr, | |
481 | &dev_attr_gt_RPn_freq_mhz.attr, | |
df6eedc8 BW |
482 | NULL, |
483 | }; | |
484 | ||
97e4eed7 CW |
485 | static const struct attribute *vlv_attrs[] = { |
486 | &dev_attr_gt_cur_freq_mhz.attr, | |
487 | &dev_attr_gt_max_freq_mhz.attr, | |
488 | &dev_attr_gt_min_freq_mhz.attr, | |
489 | &dev_attr_vlv_rpe_freq_mhz.attr, | |
490 | NULL, | |
491 | }; | |
492 | ||
ef86ddce MK |
493 | static ssize_t error_state_read(struct file *filp, struct kobject *kobj, |
494 | struct bin_attribute *attr, char *buf, | |
495 | loff_t off, size_t count) | |
496 | { | |
497 | ||
498 | struct device *kdev = container_of(kobj, struct device, kobj); | |
14c8d110 | 499 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
ef86ddce MK |
500 | struct drm_device *dev = minor->dev; |
501 | struct i915_error_state_file_priv error_priv; | |
502 | struct drm_i915_error_state_buf error_str; | |
503 | ssize_t ret_count = 0; | |
504 | int ret; | |
505 | ||
506 | memset(&error_priv, 0, sizeof(error_priv)); | |
507 | ||
508 | ret = i915_error_state_buf_init(&error_str, count, off); | |
509 | if (ret) | |
510 | return ret; | |
511 | ||
512 | error_priv.dev = dev; | |
513 | i915_error_state_get(dev, &error_priv); | |
514 | ||
515 | ret = i915_error_state_to_str(&error_str, &error_priv); | |
516 | if (ret) | |
517 | goto out; | |
518 | ||
519 | ret_count = count < error_str.bytes ? count : error_str.bytes; | |
520 | ||
521 | memcpy(buf, error_str.buf, ret_count); | |
522 | out: | |
523 | i915_error_state_put(&error_priv); | |
524 | i915_error_state_buf_release(&error_str); | |
525 | ||
526 | return ret ?: ret_count; | |
527 | } | |
528 | ||
529 | static ssize_t error_state_write(struct file *file, struct kobject *kobj, | |
530 | struct bin_attribute *attr, char *buf, | |
531 | loff_t off, size_t count) | |
532 | { | |
533 | struct device *kdev = container_of(kobj, struct device, kobj); | |
14c8d110 | 534 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
ef86ddce MK |
535 | struct drm_device *dev = minor->dev; |
536 | int ret; | |
537 | ||
538 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
539 | ||
540 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
541 | if (ret) | |
542 | return ret; | |
543 | ||
544 | i915_destroy_error_state(dev); | |
545 | mutex_unlock(&dev->struct_mutex); | |
546 | ||
547 | return count; | |
548 | } | |
549 | ||
550 | static struct bin_attribute error_state_attr = { | |
551 | .attr.name = "error", | |
552 | .attr.mode = S_IRUSR | S_IWUSR, | |
553 | .size = 0, | |
554 | .read = error_state_read, | |
555 | .write = error_state_write, | |
556 | }; | |
557 | ||
0136db58 BW |
558 | void i915_setup_sysfs(struct drm_device *dev) |
559 | { | |
560 | int ret; | |
561 | ||
8c3f929b | 562 | #ifdef CONFIG_PM |
112abd29 | 563 | if (INTEL_INFO(dev)->gen >= 6) { |
5bdebb18 | 564 | ret = sysfs_merge_group(&dev->primary->kdev->kobj, |
112abd29 DV |
565 | &rc6_attr_group); |
566 | if (ret) | |
567 | DRM_ERROR("RC6 residency sysfs setup failed\n"); | |
568 | } | |
8c3f929b | 569 | #endif |
040d2baa | 570 | if (HAS_L3_DPF(dev)) { |
5bdebb18 | 571 | ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs); |
112abd29 DV |
572 | if (ret) |
573 | DRM_ERROR("l3 parity sysfs setup failed\n"); | |
35a85ac6 BW |
574 | |
575 | if (NUM_L3_SLICES(dev) > 1) { | |
5bdebb18 | 576 | ret = device_create_bin_file(dev->primary->kdev, |
35a85ac6 BW |
577 | &dpf_attrs_1); |
578 | if (ret) | |
579 | DRM_ERROR("l3 parity slice 1 setup failed\n"); | |
580 | } | |
112abd29 | 581 | } |
df6eedc8 | 582 | |
97e4eed7 CW |
583 | ret = 0; |
584 | if (IS_VALLEYVIEW(dev)) | |
5bdebb18 | 585 | ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs); |
97e4eed7 | 586 | else if (INTEL_INFO(dev)->gen >= 6) |
5bdebb18 | 587 | ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs); |
97e4eed7 CW |
588 | if (ret) |
589 | DRM_ERROR("RPS sysfs setup failed\n"); | |
ef86ddce | 590 | |
5bdebb18 | 591 | ret = sysfs_create_bin_file(&dev->primary->kdev->kobj, |
ef86ddce MK |
592 | &error_state_attr); |
593 | if (ret) | |
594 | DRM_ERROR("error_state sysfs setup failed\n"); | |
0136db58 BW |
595 | } |
596 | ||
597 | void i915_teardown_sysfs(struct drm_device *dev) | |
598 | { | |
5bdebb18 | 599 | sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr); |
97e4eed7 | 600 | if (IS_VALLEYVIEW(dev)) |
5bdebb18 | 601 | sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs); |
97e4eed7 | 602 | else |
5bdebb18 DA |
603 | sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs); |
604 | device_remove_bin_file(dev->primary->kdev, &dpf_attrs_1); | |
605 | device_remove_bin_file(dev->primary->kdev, &dpf_attrs); | |
853c70e8 | 606 | #ifdef CONFIG_PM |
5bdebb18 | 607 | sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group); |
853c70e8 | 608 | #endif |
0136db58 | 609 | } |