[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_sysfs.c

/*
 * Copyright © 2012 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Ben Widawsky <ben@bwidawsk.net>
 *
 */

#include <linux/device.h>
#include <linux/module.h>
#include <linux/stat.h>
#include <linux/sysfs.h>
#include "intel_drv.h"
#include "i915_drv.h"

#ifdef CONFIG_PM
static u32 calc_residency(struct drm_device *dev, const u32 reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u64 raw_time; /* 32b value may overflow during fixed point math */

	if (!intel_enable_rc6(dev))
		return 0;

	raw_time = I915_READ(reg) * 128ULL;
	return DIV_ROUND_UP_ULL(raw_time, 100000);
}

static ssize_t
show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
	return snprintf(buf, PAGE_SIZE, "%x", intel_enable_rc6(dminor->dev));
}

static ssize_t
show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
	u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
	return snprintf(buf, PAGE_SIZE, "%u", rc6_residency);
}

static ssize_t
show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
	u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
	return snprintf(buf, PAGE_SIZE, "%u", rc6p_residency);
}

static ssize_t
show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
	u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
	return snprintf(buf, PAGE_SIZE, "%u", rc6pp_residency);
}

static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);

static struct attribute *rc6_attrs[] = {
	&dev_attr_rc6_enable.attr,
	&dev_attr_rc6_residency_ms.attr,
	&dev_attr_rc6p_residency_ms.attr,
	&dev_attr_rc6pp_residency_ms.attr,
	NULL
};

static struct attribute_group rc6_attr_group = {
	.name = power_group_name,
	.attrs =  rc6_attrs
};
#endif

static int l3_access_valid(struct drm_device *dev, loff_t offset)
{
	if (!IS_IVYBRIDGE(dev))
		return -EPERM;

	if (offset % 4 != 0)
		return -EINVAL;

	if (offset >= GEN7_L3LOG_SIZE)
		return -ENXIO;

	return 0;
}

static ssize_t
i915_l3_read(struct file *filp, struct kobject *kobj,
	     struct bin_attribute *attr, char *buf,
	     loff_t offset, size_t count)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
	struct drm_device *drm_dev = dminor->dev;
	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	uint32_t misccpctl;
	int i, ret;

	ret = l3_access_valid(drm_dev, offset);
	if (ret)
		return ret;

	ret = i915_mutex_lock_interruptible(drm_dev);
	if (ret)
		return ret;

	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);

	for (i = offset; count >= 4 && i < GEN7_L3LOG_SIZE; i += 4, count -= 4)
		*((uint32_t *)(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + i);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl);

	mutex_unlock(&drm_dev->struct_mutex);

	return i - offset;
}

static ssize_t
i915_l3_write(struct file *filp, struct kobject *kobj,
	      struct bin_attribute *attr, char *buf,
	      loff_t offset, size_t count)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
	struct drm_device *drm_dev = dminor->dev;
	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	u32 *temp = NULL; /* Just here to make handling failures easy */
	int ret;

	ret = l3_access_valid(drm_dev, offset);
	if (ret)
		return ret;

	ret = i915_mutex_lock_interruptible(drm_dev);
	if (ret)
		return ret;

	if (!dev_priv->mm.l3_remap_info) {
		temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
		if (!temp) {
			mutex_unlock(&drm_dev->struct_mutex);
			return -ENOMEM;
		}
	}

	ret = i915_gpu_idle(drm_dev);
	if (ret) {
		kfree(temp);
		mutex_unlock(&drm_dev->struct_mutex);
		return ret;
	}

	/* TODO: Ideally we really want a GPU reset here to make sure errors
	 * aren't propagated. Since I cannot find a stable way to reset the GPU
	 * at this point it is left as a TODO.
	*/
	if (temp)
		dev_priv->mm.l3_remap_info = temp;

	memcpy(dev_priv->mm.l3_remap_info + (offset/4),
	       buf + (offset/4),
	       count);

	i915_gem_l3_remap(drm_dev);

	mutex_unlock(&drm_dev->struct_mutex);

	return count;
}

static struct bin_attribute dpf_attrs = {
	.attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
	.size = GEN7_L3LOG_SIZE,
	.read = i915_l3_read,
	.write = i915_l3_write,
	.mmap = NULL
};

static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
				    struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

	ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
	mutex_unlock(&dev->struct_mutex);

	return snprintf(buf, PAGE_SIZE, "%d", ret);
}

static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

	ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
	mutex_unlock(&dev->struct_mutex);

	return snprintf(buf, PAGE_SIZE, "%d", ret);
}

static ssize_t gt_max_freq_mhz_store(struct device *kdev,
				     struct device_attribute *attr,
				     const char *buf, size_t count)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val, rp_state_cap, hw_max, hw_min;
	ssize_t ret;

	ret = kstrtou32(buf, 0, &val);
	if (ret)
		return ret;

	val /= GT_FREQUENCY_MULTIPLIER;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	hw_max = (rp_state_cap & 0xff);
	hw_min = ((rp_state_cap & 0xff0000) >> 16);

	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) {
		mutex_unlock(&dev->struct_mutex);
		return -EINVAL;
	}

	if (dev_priv->rps.cur_delay > val)
		gen6_set_rps(dev_priv->dev, val);

	dev_priv->rps.max_delay = val;

	mutex_unlock(&dev->struct_mutex);

	return count;
}

static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

	ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
	mutex_unlock(&dev->struct_mutex);

	return snprintf(buf, PAGE_SIZE, "%d", ret);
}

static ssize_t gt_min_freq_mhz_store(struct device *kdev,
				     struct device_attribute *attr,
				     const char *buf, size_t count)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val, rp_state_cap, hw_max, hw_min;
	ssize_t ret;

	ret = kstrtou32(buf, 0, &val);
	if (ret)
		return ret;

	val /= GT_FREQUENCY_MULTIPLIER;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	hw_max = (rp_state_cap & 0xff);
	hw_min = ((rp_state_cap & 0xff0000) >> 16);

	if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
		mutex_unlock(&dev->struct_mutex);
		return -EINVAL;
	}

	if (dev_priv->rps.cur_delay < val)
		gen6_set_rps(dev_priv->dev, val);

	dev_priv->rps.min_delay = val;

	mutex_unlock(&dev->struct_mutex);

	return count;

}

static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);


static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);

/* For now we have a static number of RP states */
static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val, rp_state_cap;
	ssize_t ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	mutex_unlock(&dev->struct_mutex);

	if (attr == &dev_attr_gt_RP0_freq_mhz) {
		val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
		val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
		val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
	} else {
		BUG();
	}
	return snprintf(buf, PAGE_SIZE, "%d", val);
}

static const struct attribute *gen6_attrs[] = {
	&dev_attr_gt_cur_freq_mhz.attr,
	&dev_attr_gt_max_freq_mhz.attr,
	&dev_attr_gt_min_freq_mhz.attr,
	&dev_attr_gt_RP0_freq_mhz.attr,
	&dev_attr_gt_RP1_freq_mhz.attr,
	&dev_attr_gt_RPn_freq_mhz.attr,
	NULL,
};

void i915_setup_sysfs(struct drm_device *dev)
{
	int ret;

#ifdef CONFIG_PM
	if (INTEL_INFO(dev)->gen >= 6) {
		ret = sysfs_merge_group(&dev->primary->kdev.kobj,
					&rc6_attr_group);
		if (ret)
			DRM_ERROR("RC6 residency sysfs setup failed\n");
	}
#endif
	if (HAS_L3_GPU_CACHE(dev)) {
		ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
		if (ret)
			DRM_ERROR("l3 parity sysfs setup failed\n");
	}

	if (INTEL_INFO(dev)->gen >= 6) {
		ret = sysfs_create_files(&dev->primary->kdev.kobj, gen6_attrs);
		if (ret)
			DRM_ERROR("gen6 sysfs setup failed\n");
	}
}

void i915_teardown_sysfs(struct drm_device *dev)
{
	sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
	device_remove_bin_file(&dev->primary->kdev,  &dpf_attrs);
#ifdef CONFIG_PM
	sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
#endif
}
Commit	Line	Data
0136db58 BW	1	/*
	2	* Copyright © 2012 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Ben Widawsky <ben@bwidawsk.net>
	25	*
	26	*/
	27
	28	#include <linux/device.h>
	29	#include <linux/module.h>
	30	#include <linux/stat.h>
	31	#include <linux/sysfs.h>
84bc7581	32	#include "intel_drv.h"
0136db58 BW	33	#include "i915_drv.h"
0136db58 BW	34
5ab3633d	35	#ifdef CONFIG_PM
0136db58 BW	36	static u32 calc_residency(struct drm_device *dev, const u32 reg)
	37	{
	38	struct drm_i915_private *dev_priv = dev->dev_private;
	39	u64 raw_time; /* 32b value may overflow during fixed point math */
	40
	41	if (!intel_enable_rc6(dev))
	42	return 0;
	43
a85d4bcb BW	44	raw_time = I915_READ(reg) * 128ULL;
a85d4bcb BW	45	return DIV_ROUND_UP_ULL(raw_time, 100000);
0136db58 BW	46	}
	47
	48	static ssize_t
dbdfd8e9	49	show_rc6_mask(struct device kdev, struct device_attribute attr, char *buf)
0136db58	50	{
dbdfd8e9	51	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
0136db58 BW	52	return snprintf(buf, PAGE_SIZE, "%x", intel_enable_rc6(dminor->dev));
	53	}
	54
	55	static ssize_t
dbdfd8e9	56	show_rc6_ms(struct device kdev, struct device_attribute attr, char *buf)
0136db58	57	{
dbdfd8e9	58	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
0136db58 BW	59	u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
	60	return snprintf(buf, PAGE_SIZE, "%u", rc6_residency);
	61	}
	62
	63	static ssize_t
dbdfd8e9	64	show_rc6p_ms(struct device kdev, struct device_attribute attr, char *buf)
0136db58	65	{
dbdfd8e9	66	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
0136db58 BW	67	u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
	68	return snprintf(buf, PAGE_SIZE, "%u", rc6p_residency);
	69	}
	70
	71	static ssize_t
dbdfd8e9	72	show_rc6pp_ms(struct device kdev, struct device_attribute attr, char *buf)
0136db58	73	{
dbdfd8e9	74	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
0136db58 BW	75	u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
	76	return snprintf(buf, PAGE_SIZE, "%u", rc6pp_residency);
	77	}
	78
	79	static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
	80	static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
	81	static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
	82	static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
	83
	84	static struct attribute *rc6_attrs[] = {
	85	&dev_attr_rc6_enable.attr,
	86	&dev_attr_rc6_residency_ms.attr,
	87	&dev_attr_rc6p_residency_ms.attr,
	88	&dev_attr_rc6pp_residency_ms.attr,
	89	NULL
	90	};
	91
	92	static struct attribute_group rc6_attr_group = {
	93	.name = power_group_name,
	94	.attrs = rc6_attrs
	95	};
8c3f929b	96	#endif
0136db58	97
84bc7581 BW	98	static int l3_access_valid(struct drm_device *dev, loff_t offset)
	99	{
	100	if (!IS_IVYBRIDGE(dev))
	101	return -EPERM;
	102
	103	if (offset % 4 != 0)
	104	return -EINVAL;
	105
	106	if (offset >= GEN7_L3LOG_SIZE)
	107	return -ENXIO;
	108
	109	return 0;
	110	}
	111
	112	static ssize_t
	113	i915_l3_read(struct file filp, struct kobject kobj,
	114	struct bin_attribute attr, char buf,
	115	loff_t offset, size_t count)
	116	{
	117	struct device *dev = container_of(kobj, struct device, kobj);
	118	struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
	119	struct drm_device *drm_dev = dminor->dev;
	120	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	121	uint32_t misccpctl;
	122	int i, ret;
	123
	124	ret = l3_access_valid(drm_dev, offset);
	125	if (ret)
	126	return ret;
	127
	128	ret = i915_mutex_lock_interruptible(drm_dev);
	129	if (ret)
	130	return ret;
	131
	132	misccpctl = I915_READ(GEN7_MISCCPCTL);
	133	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	134
	135	for (i = offset; count >= 4 && i < GEN7_L3LOG_SIZE; i += 4, count -= 4)
	136	((uint32_t )(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + i);
	137
	138	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
	139
	140	mutex_unlock(&drm_dev->struct_mutex);
	141
	142	return i - offset;
	143	}
	144
	145	static ssize_t
	146	i915_l3_write(struct file filp, struct kobject kobj,
	147	struct bin_attribute attr, char buf,
	148	loff_t offset, size_t count)
	149	{
	150	struct device *dev = container_of(kobj, struct device, kobj);
	151	struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
	152	struct drm_device *drm_dev = dminor->dev;
	153	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	154	u32 temp = NULL; / Just here to make handling failures easy */
	155	int ret;
	156
	157	ret = l3_access_valid(drm_dev, offset);
	158	if (ret)
	159	return ret;
	160
	161	ret = i915_mutex_lock_interruptible(drm_dev);
162	if (ret)
163	return ret;
164
165	if (!dev_priv->mm.l3_remap_info) {
166	temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
167	if (!temp) {
168	mutex_unlock(&drm_dev->struct_mutex);
169	return -ENOMEM;
170	}
171	}
172
173	ret = i915_gpu_idle(drm_dev);
174	if (ret) {
175	kfree(temp);
176	mutex_unlock(&drm_dev->struct_mutex);
177	return ret;
178	}
179
180	/* TODO: Ideally we really want a GPU reset here to make sure errors
181	* aren't propagated. Since I cannot find a stable way to reset the GPU
182	* at this point it is left as a TODO.
183	*/
184	if (temp)
185	dev_priv->mm.l3_remap_info = temp;
186
187	memcpy(dev_priv->mm.l3_remap_info + (offset/4),
188	buf + (offset/4),
189	count);
190
191	i915_gem_l3_remap(drm_dev);
192
193	mutex_unlock(&drm_dev->struct_mutex);
194
195	return count;
196	}
197
198	static struct bin_attribute dpf_attrs = {
199	.attr = {.name = "l3_parity", .mode = (S_IRUSR \| S_IWUSR)},
200	.size = GEN7_L3LOG_SIZE,
201	.read = i915_l3_read,
202	.write = i915_l3_write,
203	.mmap = NULL
204	};
205
df6eedc8 BW	206	static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
	207	struct device_attribute attr, char buf)
	208	{
	209	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	210	struct drm_device *dev = minor->dev;
	211	struct drm_i915_private *dev_priv = dev->dev_private;
	212	int ret;
	213
	214	ret = i915_mutex_lock_interruptible(dev);
	215	if (ret)
	216	return ret;
	217
	218	ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
	219	mutex_unlock(&dev->struct_mutex);
	220
	221	return snprintf(buf, PAGE_SIZE, "%d", ret);
	222	}
	223
	224	static ssize_t gt_max_freq_mhz_show(struct device kdev, struct device_attribute attr, char *buf)
	225	{
	226	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	227	struct drm_device *dev = minor->dev;
	228	struct drm_i915_private *dev_priv = dev->dev_private;
	229	int ret;
	230
	231	ret = i915_mutex_lock_interruptible(dev);
	232	if (ret)
	233	return ret;
	234
	235	ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
	236	mutex_unlock(&dev->struct_mutex);
	237
	238	return snprintf(buf, PAGE_SIZE, "%d", ret);
	239	}
	240
46ddf194 BW	241	static ssize_t gt_max_freq_mhz_store(struct device *kdev,
	242	struct device_attribute *attr,
	243	const char *buf, size_t count)
	244	{
	245	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	246	struct drm_device *dev = minor->dev;
	247	struct drm_i915_private *dev_priv = dev->dev_private;
	248	u32 val, rp_state_cap, hw_max, hw_min;
	249	ssize_t ret;
	250
	251	ret = kstrtou32(buf, 0, &val);
	252	if (ret)
	253	return ret;
	254
	255	val /= GT_FREQUENCY_MULTIPLIER;
	256
	257	ret = mutex_lock_interruptible(&dev->struct_mutex);
	258	if (ret)
	259	return ret;
	260
	261	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	262	hw_max = (rp_state_cap & 0xff);
	263	hw_min = ((rp_state_cap & 0xff0000) >> 16);
	264
	265	if (val < hw_min \|\| val > hw_max \|\| val < dev_priv->rps.min_delay) {
	266	mutex_unlock(&dev->struct_mutex);
	267	return -EINVAL;
	268	}
	269
	270	if (dev_priv->rps.cur_delay > val)
	271	gen6_set_rps(dev_priv->dev, val);
	272
	273	dev_priv->rps.max_delay = val;
	274
	275	mutex_unlock(&dev->struct_mutex);
	276
	277	return count;
	278	}
	279
df6eedc8 BW	280	static ssize_t gt_min_freq_mhz_show(struct device kdev, struct device_attribute attr, char *buf)
	281	{
	282	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	283	struct drm_device *dev = minor->dev;
	284	struct drm_i915_private *dev_priv = dev->dev_private;
	285	int ret;
	286
	287	ret = i915_mutex_lock_interruptible(dev);
	288	if (ret)
	289	return ret;
	290
	291	ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
	292	mutex_unlock(&dev->struct_mutex);
	293
	294	return snprintf(buf, PAGE_SIZE, "%d", ret);
	295	}
	296
46ddf194 BW	297	static ssize_t gt_min_freq_mhz_store(struct device *kdev,
	298	struct device_attribute *attr,
	299	const char *buf, size_t count)
	300	{
	301	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	302	struct drm_device *dev = minor->dev;
	303	struct drm_i915_private *dev_priv = dev->dev_private;
	304	u32 val, rp_state_cap, hw_max, hw_min;
	305	ssize_t ret;
	306
	307	ret = kstrtou32(buf, 0, &val);
	308	if (ret)
	309	return ret;
	310
	311	val /= GT_FREQUENCY_MULTIPLIER;
	312
	313	ret = mutex_lock_interruptible(&dev->struct_mutex);
	314	if (ret)
	315	return ret;
	316
	317	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	318	hw_max = (rp_state_cap & 0xff);
	319	hw_min = ((rp_state_cap & 0xff0000) >> 16);
	320
	321	if (val < hw_min \|\| val > hw_max \|\| val > dev_priv->rps.max_delay) {
	322	mutex_unlock(&dev->struct_mutex);
	323	return -EINVAL;
	324	}
	325
	326	if (dev_priv->rps.cur_delay < val)
	327	gen6_set_rps(dev_priv->dev, val);
	328
	329	dev_priv->rps.min_delay = val;
	330
	331	mutex_unlock(&dev->struct_mutex);
	332
	333	return count;
	334
	335	}
	336
df6eedc8	337	static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
46ddf194 BW	338	static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO \| S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
46ddf194 BW	339	static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO \| S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
df6eedc8	340
ac6ae347 BW	341
	342	static ssize_t gt_rp_mhz_show(struct device kdev, struct device_attribute attr, char *buf);
	343	static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
	344	static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
	345	static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
	346
	347	/* For now we have a static number of RP states */
	348	static ssize_t gt_rp_mhz_show(struct device kdev, struct device_attribute attr, char *buf)
	349	{
	350	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	351	struct drm_device *dev = minor->dev;
	352	struct drm_i915_private *dev_priv = dev->dev_private;
	353	u32 val, rp_state_cap;
	354	ssize_t ret;
	355
	356	ret = mutex_lock_interruptible(&dev->struct_mutex);
	357	if (ret)
	358	return ret;
	359	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	360	mutex_unlock(&dev->struct_mutex);
	361
	362	if (attr == &dev_attr_gt_RP0_freq_mhz) {
	363	val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
	364	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
	365	val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
	366	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
	367	val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
	368	} else {
	369	BUG();
	370	}
	371	return snprintf(buf, PAGE_SIZE, "%d", val);
	372	}
	373
df6eedc8 BW	374	static const struct attribute *gen6_attrs[] = {
	375	&dev_attr_gt_cur_freq_mhz.attr,
	376	&dev_attr_gt_max_freq_mhz.attr,
	377	&dev_attr_gt_min_freq_mhz.attr,
ac6ae347 BW	378	&dev_attr_gt_RP0_freq_mhz.attr,
	379	&dev_attr_gt_RP1_freq_mhz.attr,
	380	&dev_attr_gt_RPn_freq_mhz.attr,
df6eedc8 BW	381	NULL,
	382	};
	383
0136db58 BW	384	void i915_setup_sysfs(struct drm_device *dev)
	385	{
	386	int ret;
	387
8c3f929b	388	#ifdef CONFIG_PM
112abd29 DV	389	if (INTEL_INFO(dev)->gen >= 6) {
	390	ret = sysfs_merge_group(&dev->primary->kdev.kobj,
	391	&rc6_attr_group);
	392	if (ret)
	393	DRM_ERROR("RC6 residency sysfs setup failed\n");
	394	}
8c3f929b	395	#endif
e1ef7cc2	396	if (HAS_L3_GPU_CACHE(dev)) {
112abd29 DV	397	ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
	398	if (ret)
	399	DRM_ERROR("l3 parity sysfs setup failed\n");
	400	}
df6eedc8 BW	401
	402	if (INTEL_INFO(dev)->gen >= 6) {
	403	ret = sysfs_create_files(&dev->primary->kdev.kobj, gen6_attrs);
	404	if (ret)
	405	DRM_ERROR("gen6 sysfs setup failed\n");
	406	}
0136db58 BW	407	}
	408
	409	void i915_teardown_sysfs(struct drm_device *dev)
	410	{
df6eedc8	411	sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
84bc7581	412	device_remove_bin_file(&dev->primary->kdev, &dpf_attrs);
853c70e8	413	#ifdef CONFIG_PM
0136db58	414	sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
853c70e8	415	#endif
0136db58	416	}