[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_sysfs.c

/*
 * Copyright © 2012 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Ben Widawsky <ben@bwidawsk.net>
 *
 */

#include <linux/device.h>
#include <linux/module.h>
#include <linux/stat.h>
#include <linux/sysfs.h>
#include "intel_drv.h"
#include "i915_drv.h"

#ifdef CONFIG_PM
static u32 calc_residency(struct drm_device *dev, const u32 reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u64 raw_time; /* 32b value may overflow during fixed point math */

	if (!intel_enable_rc6(dev))
		return 0;

	raw_time = I915_READ(reg) * 128ULL;
	return DIV_ROUND_UP_ULL(raw_time, 100000);
}

static ssize_t
show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
	return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
}

static ssize_t
show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
	u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
	return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
}

static ssize_t
show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
	u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
	return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
}

static ssize_t
show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
	u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
}

static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);

static struct attribute *rc6_attrs[] = {
	&dev_attr_rc6_enable.attr,
	&dev_attr_rc6_residency_ms.attr,
	&dev_attr_rc6p_residency_ms.attr,
	&dev_attr_rc6pp_residency_ms.attr,
	NULL
};

static struct attribute_group rc6_attr_group = {
	.name = power_group_name,
	.attrs =  rc6_attrs
};
#endif

static int l3_access_valid(struct drm_device *dev, loff_t offset)
{
	if (!HAS_L3_GPU_CACHE(dev))
		return -EPERM;

	if (offset % 4 != 0)
		return -EINVAL;

	if (offset >= GEN7_L3LOG_SIZE)
		return -ENXIO;

	return 0;
}

static ssize_t
i915_l3_read(struct file *filp, struct kobject *kobj,
	     struct bin_attribute *attr, char *buf,
	     loff_t offset, size_t count)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
	struct drm_device *drm_dev = dminor->dev;
	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	uint32_t misccpctl;
	int i, ret;

	ret = l3_access_valid(drm_dev, offset);
	if (ret)
		return ret;

	ret = i915_mutex_lock_interruptible(drm_dev);
	if (ret)
		return ret;

	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);

	for (i = offset; count >= 4 && i < GEN7_L3LOG_SIZE; i += 4, count -= 4)
		*((uint32_t *)(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + i);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl);

	mutex_unlock(&drm_dev->struct_mutex);

	return i - offset;
}

static ssize_t
i915_l3_write(struct file *filp, struct kobject *kobj,
	      struct bin_attribute *attr, char *buf,
	      loff_t offset, size_t count)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
	struct drm_device *drm_dev = dminor->dev;
	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	u32 *temp = NULL; /* Just here to make handling failures easy */
	int ret;

	ret = l3_access_valid(drm_dev, offset);
	if (ret)
		return ret;

	ret = i915_mutex_lock_interruptible(drm_dev);
	if (ret)
		return ret;

	if (!dev_priv->l3_parity.remap_info) {
		temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
		if (!temp) {
			mutex_unlock(&drm_dev->struct_mutex);
			return -ENOMEM;
		}
	}

	ret = i915_gpu_idle(drm_dev);
	if (ret) {
		kfree(temp);
		mutex_unlock(&drm_dev->struct_mutex);
		return ret;
	}

	/* TODO: Ideally we really want a GPU reset here to make sure errors
	 * aren't propagated. Since I cannot find a stable way to reset the GPU
	 * at this point it is left as a TODO.
	*/
	if (temp)
		dev_priv->l3_parity.remap_info = temp;

	memcpy(dev_priv->l3_parity.remap_info + (offset/4),
	       buf + (offset/4),
	       count);

	i915_gem_l3_remap(drm_dev);

	mutex_unlock(&drm_dev->struct_mutex);

	return count;
}

static struct bin_attribute dpf_attrs = {
	.attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
	.size = GEN7_L3LOG_SIZE,
	.read = i915_l3_read,
	.write = i915_l3_write,
	.mmap = NULL
};

static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
				    struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	mutex_lock(&dev_priv->rps.hw_lock);
	if (IS_VALLEYVIEW(dev_priv->dev)) {
		u32 freq;
		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
		ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
	} else {
		ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
	}
	mutex_unlock(&dev_priv->rps.hw_lock);

	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
}

static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
				     struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	return snprintf(buf, PAGE_SIZE, "%d\n",
			vlv_gpu_freq(dev_priv->mem_freq,
				     dev_priv->rps.rpe_delay));
}

static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	mutex_lock(&dev_priv->rps.hw_lock);
	if (IS_VALLEYVIEW(dev_priv->dev))
		ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);
	else
		ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
	mutex_unlock(&dev_priv->rps.hw_lock);

	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
}

static ssize_t gt_max_freq_mhz_store(struct device *kdev,
				     struct device_attribute *attr,
				     const char *buf, size_t count)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val, rp_state_cap, hw_max, hw_min, non_oc_max;
	ssize_t ret;

	ret = kstrtou32(buf, 0, &val);
	if (ret)
		return ret;

	mutex_lock(&dev_priv->rps.hw_lock);

	if (IS_VALLEYVIEW(dev_priv->dev)) {
		val = vlv_freq_opcode(dev_priv->mem_freq, val);

		hw_max = valleyview_rps_max_freq(dev_priv);
		hw_min = valleyview_rps_min_freq(dev_priv);
		non_oc_max = hw_max;
	} else {
		val /= GT_FREQUENCY_MULTIPLIER;

		rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
		hw_max = dev_priv->rps.hw_max;
		non_oc_max = (rp_state_cap & 0xff);
		hw_min = ((rp_state_cap & 0xff0000) >> 16);
	}

	if (val < hw_min || val > hw_max ||
	    val < dev_priv->rps.min_delay) {
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
	}

	if (val > non_oc_max)
		DRM_DEBUG("User requested overclocking to %d\n",
			  val * GT_FREQUENCY_MULTIPLIER);

	if (dev_priv->rps.cur_delay > val) {
		if (IS_VALLEYVIEW(dev_priv->dev))
			valleyview_set_rps(dev_priv->dev, val);
		else
			gen6_set_rps(dev_priv->dev, val);
	}

	dev_priv->rps.max_delay = val;

	mutex_unlock(&dev_priv->rps.hw_lock);

	return count;
}

static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	mutex_lock(&dev_priv->rps.hw_lock);
	if (IS_VALLEYVIEW(dev_priv->dev))
		ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);
	else
		ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
	mutex_unlock(&dev_priv->rps.hw_lock);

	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
}

static ssize_t gt_min_freq_mhz_store(struct device *kdev,
				     struct device_attribute *attr,
				     const char *buf, size_t count)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val, rp_state_cap, hw_max, hw_min;
	ssize_t ret;

	ret = kstrtou32(buf, 0, &val);
	if (ret)
		return ret;

	mutex_lock(&dev_priv->rps.hw_lock);

	if (IS_VALLEYVIEW(dev)) {
		val = vlv_freq_opcode(dev_priv->mem_freq, val);

		hw_max = valleyview_rps_max_freq(dev_priv);
		hw_min = valleyview_rps_min_freq(dev_priv);
	} else {
		val /= GT_FREQUENCY_MULTIPLIER;

		rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
		hw_max = dev_priv->rps.hw_max;
		hw_min = ((rp_state_cap & 0xff0000) >> 16);
	}

	if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
	}

	if (dev_priv->rps.cur_delay < val) {
		if (IS_VALLEYVIEW(dev))
			valleyview_set_rps(dev, val);
		else
			gen6_set_rps(dev_priv->dev, val);
	}

	dev_priv->rps.min_delay = val;

	mutex_unlock(&dev_priv->rps.hw_lock);

	return count;

}

static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);

static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);

static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);

/* For now we have a static number of RP states */
static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
{
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val, rp_state_cap;
	ssize_t ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	mutex_unlock(&dev->struct_mutex);

	if (attr == &dev_attr_gt_RP0_freq_mhz) {
		val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
		val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
		val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
	} else {
		BUG();
	}
	return snprintf(buf, PAGE_SIZE, "%d\n", val);
}

static const struct attribute *gen6_attrs[] = {
	&dev_attr_gt_cur_freq_mhz.attr,
	&dev_attr_gt_max_freq_mhz.attr,
	&dev_attr_gt_min_freq_mhz.attr,
	&dev_attr_gt_RP0_freq_mhz.attr,
	&dev_attr_gt_RP1_freq_mhz.attr,
	&dev_attr_gt_RPn_freq_mhz.attr,
	NULL,
};

static const struct attribute *vlv_attrs[] = {
	&dev_attr_gt_cur_freq_mhz.attr,
	&dev_attr_gt_max_freq_mhz.attr,
	&dev_attr_gt_min_freq_mhz.attr,
	&dev_attr_vlv_rpe_freq_mhz.attr,
	NULL,
};

static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
				struct bin_attribute *attr, char *buf,
				loff_t off, size_t count)
{

	struct device *kdev = container_of(kobj, struct device, kobj);
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	struct i915_error_state_file_priv error_priv;
	struct drm_i915_error_state_buf error_str;
	ssize_t ret_count = 0;
	int ret;

	memset(&error_priv, 0, sizeof(error_priv));

	ret = i915_error_state_buf_init(&error_str, count, off);
	if (ret)
		return ret;

	error_priv.dev = dev;
	i915_error_state_get(dev, &error_priv);

	ret = i915_error_state_to_str(&error_str, &error_priv);
	if (ret)
		goto out;

	ret_count = count < error_str.bytes ? count : error_str.bytes;

	memcpy(buf, error_str.buf, ret_count);
out:
	i915_error_state_put(&error_priv);
	i915_error_state_buf_release(&error_str);

	return ret ?: ret_count;
}

static ssize_t error_state_write(struct file *file, struct kobject *kobj,
				 struct bin_attribute *attr, char *buf,
				 loff_t off, size_t count)
{
	struct device *kdev = container_of(kobj, struct device, kobj);
	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	struct drm_device *dev = minor->dev;
	int ret;

	DRM_DEBUG_DRIVER("Resetting error state\n");

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	i915_destroy_error_state(dev);
	mutex_unlock(&dev->struct_mutex);

	return count;
}

static struct bin_attribute error_state_attr = {
	.attr.name = "error",
	.attr.mode = S_IRUSR | S_IWUSR,
	.size = 0,
	.read = error_state_read,
	.write = error_state_write,
};

void i915_setup_sysfs(struct drm_device *dev)
{
	int ret;

#ifdef CONFIG_PM
	if (INTEL_INFO(dev)->gen >= 6) {
		ret = sysfs_merge_group(&dev->primary->kdev.kobj,
					&rc6_attr_group);
		if (ret)
			DRM_ERROR("RC6 residency sysfs setup failed\n");
	}
#endif
	if (HAS_L3_GPU_CACHE(dev)) {
		ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
		if (ret)
			DRM_ERROR("l3 parity sysfs setup failed\n");
	}

	ret = 0;
	if (IS_VALLEYVIEW(dev))
		ret = sysfs_create_files(&dev->primary->kdev.kobj, vlv_attrs);
	else if (INTEL_INFO(dev)->gen >= 6)
		ret = sysfs_create_files(&dev->primary->kdev.kobj, gen6_attrs);
	if (ret)
		DRM_ERROR("RPS sysfs setup failed\n");

	ret = sysfs_create_bin_file(&dev->primary->kdev.kobj,
				    &error_state_attr);
	if (ret)
		DRM_ERROR("error_state sysfs setup failed\n");
}

void i915_teardown_sysfs(struct drm_device *dev)
{
	sysfs_remove_bin_file(&dev->primary->kdev.kobj, &error_state_attr);
	if (IS_VALLEYVIEW(dev))
		sysfs_remove_files(&dev->primary->kdev.kobj, vlv_attrs);
	else
		sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
	device_remove_bin_file(&dev->primary->kdev,  &dpf_attrs);
#ifdef CONFIG_PM
	sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
#endif
}
Commit	Line	Data
0136db58 BW	1	/*
	2	* Copyright © 2012 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Ben Widawsky <ben@bwidawsk.net>
	25	*
	26	*/
	27
	28	#include <linux/device.h>
	29	#include <linux/module.h>
	30	#include <linux/stat.h>
	31	#include <linux/sysfs.h>
84bc7581	32	#include "intel_drv.h"
0136db58 BW	33	#include "i915_drv.h"
0136db58 BW	34
5ab3633d	35	#ifdef CONFIG_PM
0136db58 BW	36	static u32 calc_residency(struct drm_device *dev, const u32 reg)
	37	{
	38	struct drm_i915_private *dev_priv = dev->dev_private;
	39	u64 raw_time; /* 32b value may overflow during fixed point math */
	40
	41	if (!intel_enable_rc6(dev))
	42	return 0;
	43
a85d4bcb BW	44	raw_time = I915_READ(reg) * 128ULL;
a85d4bcb BW	45	return DIV_ROUND_UP_ULL(raw_time, 100000);
0136db58 BW	46	}
	47
	48	static ssize_t
dbdfd8e9	49	show_rc6_mask(struct device kdev, struct device_attribute attr, char *buf)
0136db58	50	{
dbdfd8e9	51	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
3e2a1556	52	return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
0136db58 BW	53	}
	54
	55	static ssize_t
dbdfd8e9	56	show_rc6_ms(struct device kdev, struct device_attribute attr, char *buf)
0136db58	57	{
dbdfd8e9	58	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
0136db58	59	u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
3e2a1556	60	return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
0136db58 BW	61	}
	62
	63	static ssize_t
dbdfd8e9	64	show_rc6p_ms(struct device kdev, struct device_attribute attr, char *buf)
0136db58	65	{
dbdfd8e9	66	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
0136db58	67	u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
3e2a1556	68	return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
0136db58 BW	69	}
	70
	71	static ssize_t
dbdfd8e9	72	show_rc6pp_ms(struct device kdev, struct device_attribute attr, char *buf)
0136db58	73	{
dbdfd8e9	74	struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
0136db58	75	u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
3e2a1556	76	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
0136db58 BW	77	}
	78
	79	static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
	80	static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
	81	static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
	82	static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
	83
	84	static struct attribute *rc6_attrs[] = {
	85	&dev_attr_rc6_enable.attr,
	86	&dev_attr_rc6_residency_ms.attr,
	87	&dev_attr_rc6p_residency_ms.attr,
	88	&dev_attr_rc6pp_residency_ms.attr,
	89	NULL
	90	};
	91
	92	static struct attribute_group rc6_attr_group = {
	93	.name = power_group_name,
	94	.attrs = rc6_attrs
	95	};
8c3f929b	96	#endif
0136db58	97
84bc7581 BW	98	static int l3_access_valid(struct drm_device *dev, loff_t offset)
84bc7581 BW	99	{
ebf69cb8	100	if (!HAS_L3_GPU_CACHE(dev))
84bc7581 BW	101	return -EPERM;
	102
	103	if (offset % 4 != 0)
	104	return -EINVAL;
	105
	106	if (offset >= GEN7_L3LOG_SIZE)
	107	return -ENXIO;
	108
	109	return 0;
	110	}
	111
	112	static ssize_t
	113	i915_l3_read(struct file filp, struct kobject kobj,
	114	struct bin_attribute attr, char buf,
	115	loff_t offset, size_t count)
	116	{
	117	struct device *dev = container_of(kobj, struct device, kobj);
	118	struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
	119	struct drm_device *drm_dev = dminor->dev;
	120	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	121	uint32_t misccpctl;
	122	int i, ret;
	123
	124	ret = l3_access_valid(drm_dev, offset);
	125	if (ret)
	126	return ret;
	127
	128	ret = i915_mutex_lock_interruptible(drm_dev);
	129	if (ret)
	130	return ret;
	131
	132	misccpctl = I915_READ(GEN7_MISCCPCTL);
	133	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	134
	135	for (i = offset; count >= 4 && i < GEN7_L3LOG_SIZE; i += 4, count -= 4)
	136	((uint32_t )(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + i);
	137
	138	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
	139
	140	mutex_unlock(&drm_dev->struct_mutex);
	141
	142	return i - offset;
	143	}
	144
	145	static ssize_t
	146	i915_l3_write(struct file filp, struct kobject kobj,
	147	struct bin_attribute attr, char buf,
	148	loff_t offset, size_t count)
	149	{
	150	struct device *dev = container_of(kobj, struct device, kobj);
	151	struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
	152	struct drm_device *drm_dev = dminor->dev;
	153	struct drm_i915_private *dev_priv = drm_dev->dev_private;
	154	u32 temp = NULL; / Just here to make handling failures easy */
	155	int ret;
	156
	157	ret = l3_access_valid(drm_dev, offset);
	158	if (ret)
	159	return ret;
	160
	161	ret = i915_mutex_lock_interruptible(drm_dev);
	162	if (ret)
	163	return ret;
	164
a4da4fa4	165	if (!dev_priv->l3_parity.remap_info) {
84bc7581 BW	166	temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
	167	if (!temp) {
	168	mutex_unlock(&drm_dev->struct_mutex);
	169	return -ENOMEM;
	170	}
	171	}
	172
	173	ret = i915_gpu_idle(drm_dev);
	174	if (ret) {
	175	kfree(temp);
	176	mutex_unlock(&drm_dev->struct_mutex);
	177	return ret;
	178	}
	179
	180	/* TODO: Ideally we really want a GPU reset here to make sure errors
	181	* aren't propagated. Since I cannot find a stable way to reset the GPU
	182	* at this point it is left as a TODO.
	183	*/
	184	if (temp)
a4da4fa4	185	dev_priv->l3_parity.remap_info = temp;
84bc7581	186
a4da4fa4	187	memcpy(dev_priv->l3_parity.remap_info + (offset/4),
84bc7581 BW	188	buf + (offset/4),
	189	count);
	190
	191	i915_gem_l3_remap(drm_dev);
	192
	193	mutex_unlock(&drm_dev->struct_mutex);
	194
	195	return count;
	196	}
	197
	198	static struct bin_attribute dpf_attrs = {
	199	.attr = {.name = "l3_parity", .mode = (S_IRUSR \| S_IWUSR)},
	200	.size = GEN7_L3LOG_SIZE,
	201	.read = i915_l3_read,
	202	.write = i915_l3_write,
	203	.mmap = NULL
	204	};
	205
df6eedc8 BW	206	static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
	207	struct device_attribute attr, char buf)
	208	{
	209	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	210	struct drm_device *dev = minor->dev;
	211	struct drm_i915_private *dev_priv = dev->dev_private;
	212	int ret;
	213
4fc688ce	214	mutex_lock(&dev_priv->rps.hw_lock);
177006a1 JB	215	if (IS_VALLEYVIEW(dev_priv->dev)) {
177006a1 JB	216	u32 freq;
64936258	217	freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
177006a1 JB	218	ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
177006a1 JB	219	} else {
0a073b84	220	ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
177006a1	221	}
4fc688ce	222	mutex_unlock(&dev_priv->rps.hw_lock);
df6eedc8	223
3e2a1556	224	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
df6eedc8 BW	225	}
df6eedc8 BW	226
97e4eed7 CW	227	static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
	228	struct device_attribute attr, char buf)
	229	{
	230	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	231	struct drm_device *dev = minor->dev;
	232	struct drm_i915_private *dev_priv = dev->dev_private;
	233
	234	return snprintf(buf, PAGE_SIZE, "%d\n",
	235	vlv_gpu_freq(dev_priv->mem_freq,
	236	dev_priv->rps.rpe_delay));
	237	}
	238
df6eedc8 BW	239	static ssize_t gt_max_freq_mhz_show(struct device kdev, struct device_attribute attr, char *buf)
	240	{
	241	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	242	struct drm_device *dev = minor->dev;
	243	struct drm_i915_private *dev_priv = dev->dev_private;
	244	int ret;
	245
4fc688ce	246	mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 JB	247	if (IS_VALLEYVIEW(dev_priv->dev))
	248	ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);
	249	else
	250	ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce	251	mutex_unlock(&dev_priv->rps.hw_lock);
df6eedc8	252
3e2a1556	253	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
df6eedc8 BW	254	}
df6eedc8 BW	255
46ddf194 BW	256	static ssize_t gt_max_freq_mhz_store(struct device *kdev,
	257	struct device_attribute *attr,
	258	const char *buf, size_t count)
	259	{
	260	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	261	struct drm_device *dev = minor->dev;
	262	struct drm_i915_private *dev_priv = dev->dev_private;
31c77388	263	u32 val, rp_state_cap, hw_max, hw_min, non_oc_max;
46ddf194 BW	264	ssize_t ret;
	265
	266	ret = kstrtou32(buf, 0, &val);
	267	if (ret)
	268	return ret;
	269
4fc688ce	270	mutex_lock(&dev_priv->rps.hw_lock);
46ddf194	271
0a073b84 JB	272	if (IS_VALLEYVIEW(dev_priv->dev)) {
	273	val = vlv_freq_opcode(dev_priv->mem_freq, val);
	274
	275	hw_max = valleyview_rps_max_freq(dev_priv);
	276	hw_min = valleyview_rps_min_freq(dev_priv);
	277	non_oc_max = hw_max;
	278	} else {
	279	val /= GT_FREQUENCY_MULTIPLIER;
46ddf194	280
0a073b84 JB	281	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	282	hw_max = dev_priv->rps.hw_max;
	283	non_oc_max = (rp_state_cap & 0xff);
	284	hw_min = ((rp_state_cap & 0xff0000) >> 16);
	285	}
	286
	287	if (val < hw_min \|\| val > hw_max \|\|
	288	val < dev_priv->rps.min_delay) {
4fc688ce	289	mutex_unlock(&dev_priv->rps.hw_lock);
46ddf194 BW	290	return -EINVAL;
	291	}
	292
31c77388 BW	293	if (val > non_oc_max)
	294	DRM_DEBUG("User requested overclocking to %d\n",
	295	val * GT_FREQUENCY_MULTIPLIER);
	296
0a073b84 JB	297	if (dev_priv->rps.cur_delay > val) {
	298	if (IS_VALLEYVIEW(dev_priv->dev))
	299	valleyview_set_rps(dev_priv->dev, val);
	300	else
	301	gen6_set_rps(dev_priv->dev, val);
	302	}
46ddf194 BW	303
	304	dev_priv->rps.max_delay = val;
	305
4fc688ce	306	mutex_unlock(&dev_priv->rps.hw_lock);
46ddf194 BW	307
	308	return count;
	309	}
	310
df6eedc8 BW	311	static ssize_t gt_min_freq_mhz_show(struct device kdev, struct device_attribute attr, char *buf)
	312	{
	313	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	314	struct drm_device *dev = minor->dev;
	315	struct drm_i915_private *dev_priv = dev->dev_private;
	316	int ret;
	317
4fc688ce	318	mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 JB	319	if (IS_VALLEYVIEW(dev_priv->dev))
	320	ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);
	321	else
	322	ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce	323	mutex_unlock(&dev_priv->rps.hw_lock);
df6eedc8	324
3e2a1556	325	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
df6eedc8 BW	326	}
df6eedc8 BW	327
46ddf194 BW	328	static ssize_t gt_min_freq_mhz_store(struct device *kdev,
	329	struct device_attribute *attr,
	330	const char *buf, size_t count)
	331	{
	332	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	333	struct drm_device *dev = minor->dev;
	334	struct drm_i915_private *dev_priv = dev->dev_private;
	335	u32 val, rp_state_cap, hw_max, hw_min;
	336	ssize_t ret;
	337
	338	ret = kstrtou32(buf, 0, &val);
	339	if (ret)
	340	return ret;
	341
4fc688ce	342	mutex_lock(&dev_priv->rps.hw_lock);
46ddf194	343
0a073b84 JB	344	if (IS_VALLEYVIEW(dev)) {
	345	val = vlv_freq_opcode(dev_priv->mem_freq, val);
	346
	347	hw_max = valleyview_rps_max_freq(dev_priv);
	348	hw_min = valleyview_rps_min_freq(dev_priv);
	349	} else {
	350	val /= GT_FREQUENCY_MULTIPLIER;
	351
	352	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	353	hw_max = dev_priv->rps.hw_max;
	354	hw_min = ((rp_state_cap & 0xff0000) >> 16);
	355	}
46ddf194 BW	356
46ddf194 BW	357	if (val < hw_min \|\| val > hw_max \|\| val > dev_priv->rps.max_delay) {
4fc688ce	358	mutex_unlock(&dev_priv->rps.hw_lock);
46ddf194 BW	359	return -EINVAL;
	360	}
	361
0a073b84 JB	362	if (dev_priv->rps.cur_delay < val) {
	363	if (IS_VALLEYVIEW(dev))
	364	valleyview_set_rps(dev, val);
	365	else
	366	gen6_set_rps(dev_priv->dev, val);
	367	}
46ddf194 BW	368
	369	dev_priv->rps.min_delay = val;
	370
4fc688ce	371	mutex_unlock(&dev_priv->rps.hw_lock);
46ddf194 BW	372
	373	return count;
	374
	375	}
	376
df6eedc8	377	static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
46ddf194 BW	378	static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO \| S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
46ddf194 BW	379	static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO \| S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
df6eedc8	380
97e4eed7	381	static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
ac6ae347 BW	382
	383	static ssize_t gt_rp_mhz_show(struct device kdev, struct device_attribute attr, char *buf);
	384	static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
	385	static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
	386	static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
	387
	388	/* For now we have a static number of RP states */
	389	static ssize_t gt_rp_mhz_show(struct device kdev, struct device_attribute attr, char *buf)
	390	{
	391	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	392	struct drm_device *dev = minor->dev;
	393	struct drm_i915_private *dev_priv = dev->dev_private;
	394	u32 val, rp_state_cap;
	395	ssize_t ret;
	396
	397	ret = mutex_lock_interruptible(&dev->struct_mutex);
	398	if (ret)
	399	return ret;
	400	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	401	mutex_unlock(&dev->struct_mutex);
	402
	403	if (attr == &dev_attr_gt_RP0_freq_mhz) {
	404	val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
	405	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
	406	val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
	407	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
	408	val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
	409	} else {
	410	BUG();
	411	}
3e2a1556	412	return snprintf(buf, PAGE_SIZE, "%d\n", val);
ac6ae347 BW	413	}
ac6ae347 BW	414
df6eedc8 BW	415	static const struct attribute *gen6_attrs[] = {
	416	&dev_attr_gt_cur_freq_mhz.attr,
	417	&dev_attr_gt_max_freq_mhz.attr,
	418	&dev_attr_gt_min_freq_mhz.attr,
ac6ae347 BW	419	&dev_attr_gt_RP0_freq_mhz.attr,
	420	&dev_attr_gt_RP1_freq_mhz.attr,
	421	&dev_attr_gt_RPn_freq_mhz.attr,
df6eedc8 BW	422	NULL,
	423	};
	424
97e4eed7 CW	425	static const struct attribute *vlv_attrs[] = {
	426	&dev_attr_gt_cur_freq_mhz.attr,
	427	&dev_attr_gt_max_freq_mhz.attr,
	428	&dev_attr_gt_min_freq_mhz.attr,
	429	&dev_attr_vlv_rpe_freq_mhz.attr,
	430	NULL,
	431	};
	432
ef86ddce MK	433	static ssize_t error_state_read(struct file filp, struct kobject kobj,
	434	struct bin_attribute attr, char buf,
	435	loff_t off, size_t count)
	436	{
	437
	438	struct device *kdev = container_of(kobj, struct device, kobj);
	439	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	440	struct drm_device *dev = minor->dev;
	441	struct i915_error_state_file_priv error_priv;
	442	struct drm_i915_error_state_buf error_str;
	443	ssize_t ret_count = 0;
	444	int ret;
	445
	446	memset(&error_priv, 0, sizeof(error_priv));
	447
	448	ret = i915_error_state_buf_init(&error_str, count, off);
	449	if (ret)
	450	return ret;
	451
	452	error_priv.dev = dev;
	453	i915_error_state_get(dev, &error_priv);
	454
	455	ret = i915_error_state_to_str(&error_str, &error_priv);
	456	if (ret)
	457	goto out;
	458
	459	ret_count = count < error_str.bytes ? count : error_str.bytes;
	460
	461	memcpy(buf, error_str.buf, ret_count);
	462	out:
	463	i915_error_state_put(&error_priv);
	464	i915_error_state_buf_release(&error_str);
	465
	466	return ret ?: ret_count;
	467	}
	468
	469	static ssize_t error_state_write(struct file file, struct kobject kobj,
	470	struct bin_attribute attr, char buf,
	471	loff_t off, size_t count)
	472	{
	473	struct device *kdev = container_of(kobj, struct device, kobj);
	474	struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
	475	struct drm_device *dev = minor->dev;
	476	int ret;
	477
	478	DRM_DEBUG_DRIVER("Resetting error state\n");
	479
	480	ret = mutex_lock_interruptible(&dev->struct_mutex);
	481	if (ret)
	482	return ret;
	483
	484	i915_destroy_error_state(dev);
	485	mutex_unlock(&dev->struct_mutex);
	486
	487	return count;
	488	}
	489
	490	static struct bin_attribute error_state_attr = {
	491	.attr.name = "error",
	492	.attr.mode = S_IRUSR \| S_IWUSR,
	493	.size = 0,
	494	.read = error_state_read,
	495	.write = error_state_write,
	496	};
497
0136db58 BW	498	void i915_setup_sysfs(struct drm_device *dev)
	499	{
	500	int ret;
	501
8c3f929b	502	#ifdef CONFIG_PM
112abd29 DV	503	if (INTEL_INFO(dev)->gen >= 6) {
	504	ret = sysfs_merge_group(&dev->primary->kdev.kobj,
	505	&rc6_attr_group);
	506	if (ret)
	507	DRM_ERROR("RC6 residency sysfs setup failed\n");
	508	}
8c3f929b	509	#endif
e1ef7cc2	510	if (HAS_L3_GPU_CACHE(dev)) {
112abd29 DV	511	ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
	512	if (ret)
	513	DRM_ERROR("l3 parity sysfs setup failed\n");
	514	}
df6eedc8	515
97e4eed7 CW	516	ret = 0;
	517	if (IS_VALLEYVIEW(dev))
	518	ret = sysfs_create_files(&dev->primary->kdev.kobj, vlv_attrs);
	519	else if (INTEL_INFO(dev)->gen >= 6)
df6eedc8	520	ret = sysfs_create_files(&dev->primary->kdev.kobj, gen6_attrs);
97e4eed7 CW	521	if (ret)
97e4eed7 CW	522	DRM_ERROR("RPS sysfs setup failed\n");
ef86ddce MK	523
	524	ret = sysfs_create_bin_file(&dev->primary->kdev.kobj,
	525	&error_state_attr);
	526	if (ret)
	527	DRM_ERROR("error_state sysfs setup failed\n");
0136db58 BW	528	}
	529
	530	void i915_teardown_sysfs(struct drm_device *dev)
	531	{
ef86ddce	532	sysfs_remove_bin_file(&dev->primary->kdev.kobj, &error_state_attr);
97e4eed7 CW	533	if (IS_VALLEYVIEW(dev))
	534	sysfs_remove_files(&dev->primary->kdev.kobj, vlv_attrs);
	535	else
	536	sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
84bc7581	537	device_remove_bin_file(&dev->primary->kdev, &dpf_attrs);
853c70e8	538	#ifdef CONFIG_PM
0136db58	539	sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
853c70e8	540	#endif
0136db58	541	}