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0136db58 BW |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/device.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/stat.h> | |
31 | #include <linux/sysfs.h> | |
84bc7581 | 32 | #include "intel_drv.h" |
0136db58 BW |
33 | #include "i915_drv.h" |
34 | ||
5bdebb18 | 35 | #define dev_to_drm_minor(d) dev_get_drvdata((d)) |
14c8d110 | 36 | |
5ab3633d | 37 | #ifdef CONFIG_PM |
f0f59a00 VS |
38 | static u32 calc_residency(struct drm_device *dev, |
39 | i915_reg_t reg) | |
0136db58 | 40 | { |
fac5e23e | 41 | struct drm_i915_private *dev_priv = to_i915(dev); |
0136db58 | 42 | u64 raw_time; /* 32b value may overflow during fixed point math */ |
2cc9fab1 | 43 | u64 units = 128ULL, div = 100000ULL; |
c8c8fb33 | 44 | u32 ret; |
0136db58 | 45 | |
dc97997a | 46 | if (!intel_enable_rc6()) |
0136db58 BW |
47 | return 0; |
48 | ||
c8c8fb33 PZ |
49 | intel_runtime_pm_get(dev_priv); |
50 | ||
542a6b20 | 51 | /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ |
666a4537 | 52 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
2cc9fab1 VS |
53 | units = 1; |
54 | div = dev_priv->czclk_freq; | |
542a6b20 | 55 | |
e454a05d JB |
56 | if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) |
57 | units <<= 8; | |
d8135109 ID |
58 | } else if (IS_BROXTON(dev)) { |
59 | units = 1; | |
60 | div = 1200; /* 833.33ns */ | |
e454a05d JB |
61 | } |
62 | ||
63 | raw_time = I915_READ(reg) * units; | |
c8c8fb33 PZ |
64 | ret = DIV_ROUND_UP_ULL(raw_time, div); |
65 | ||
c8c8fb33 PZ |
66 | intel_runtime_pm_put(dev_priv); |
67 | return ret; | |
0136db58 BW |
68 | } |
69 | ||
70 | static ssize_t | |
dbdfd8e9 | 71 | show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 72 | { |
dc97997a | 73 | return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6()); |
0136db58 BW |
74 | } |
75 | ||
76 | static ssize_t | |
dbdfd8e9 | 77 | show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 78 | { |
5bdebb18 | 79 | struct drm_minor *dminor = dev_get_drvdata(kdev); |
0136db58 | 80 | u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6); |
3e2a1556 | 81 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); |
0136db58 BW |
82 | } |
83 | ||
84 | static ssize_t | |
dbdfd8e9 | 85 | show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 86 | { |
14c8d110 | 87 | struct drm_minor *dminor = dev_to_drm_minor(kdev); |
0136db58 | 88 | u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p); |
3e2a1556 | 89 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency); |
0136db58 BW |
90 | } |
91 | ||
92 | static ssize_t | |
dbdfd8e9 | 93 | show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 94 | { |
14c8d110 | 95 | struct drm_minor *dminor = dev_to_drm_minor(kdev); |
0136db58 | 96 | u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp); |
3e2a1556 | 97 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency); |
0136db58 BW |
98 | } |
99 | ||
626ad6f3 VS |
100 | static ssize_t |
101 | show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) | |
102 | { | |
103 | struct drm_minor *dminor = dev_get_drvdata(kdev); | |
104 | u32 rc6_residency = calc_residency(dminor->dev, VLV_GT_MEDIA_RC6); | |
105 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); | |
106 | } | |
107 | ||
0136db58 BW |
108 | static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL); |
109 | static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL); | |
110 | static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL); | |
111 | static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL); | |
626ad6f3 | 112 | static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL); |
0136db58 BW |
113 | |
114 | static struct attribute *rc6_attrs[] = { | |
115 | &dev_attr_rc6_enable.attr, | |
116 | &dev_attr_rc6_residency_ms.attr, | |
0136db58 BW |
117 | NULL |
118 | }; | |
119 | ||
120 | static struct attribute_group rc6_attr_group = { | |
121 | .name = power_group_name, | |
122 | .attrs = rc6_attrs | |
123 | }; | |
58abf1da RV |
124 | |
125 | static struct attribute *rc6p_attrs[] = { | |
126 | &dev_attr_rc6p_residency_ms.attr, | |
127 | &dev_attr_rc6pp_residency_ms.attr, | |
128 | NULL | |
129 | }; | |
130 | ||
131 | static struct attribute_group rc6p_attr_group = { | |
132 | .name = power_group_name, | |
133 | .attrs = rc6p_attrs | |
134 | }; | |
626ad6f3 VS |
135 | |
136 | static struct attribute *media_rc6_attrs[] = { | |
137 | &dev_attr_media_rc6_residency_ms.attr, | |
138 | NULL | |
139 | }; | |
140 | ||
141 | static struct attribute_group media_rc6_attr_group = { | |
142 | .name = power_group_name, | |
143 | .attrs = media_rc6_attrs | |
144 | }; | |
8c3f929b | 145 | #endif |
0136db58 | 146 | |
84bc7581 BW |
147 | static int l3_access_valid(struct drm_device *dev, loff_t offset) |
148 | { | |
040d2baa | 149 | if (!HAS_L3_DPF(dev)) |
84bc7581 BW |
150 | return -EPERM; |
151 | ||
152 | if (offset % 4 != 0) | |
153 | return -EINVAL; | |
154 | ||
155 | if (offset >= GEN7_L3LOG_SIZE) | |
156 | return -ENXIO; | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | static ssize_t | |
162 | i915_l3_read(struct file *filp, struct kobject *kobj, | |
163 | struct bin_attribute *attr, char *buf, | |
164 | loff_t offset, size_t count) | |
165 | { | |
657fb5fb | 166 | struct device *dev = kobj_to_dev(kobj); |
14c8d110 | 167 | struct drm_minor *dminor = dev_to_drm_minor(dev); |
84bc7581 | 168 | struct drm_device *drm_dev = dminor->dev; |
fac5e23e | 169 | struct drm_i915_private *dev_priv = to_i915(drm_dev); |
35a85ac6 | 170 | int slice = (int)(uintptr_t)attr->private; |
3ccfd19d | 171 | int ret; |
84bc7581 | 172 | |
1c3dcd1c BW |
173 | count = round_down(count, 4); |
174 | ||
84bc7581 BW |
175 | ret = l3_access_valid(drm_dev, offset); |
176 | if (ret) | |
177 | return ret; | |
178 | ||
e5ad4026 | 179 | count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count); |
33618ea5 | 180 | |
84bc7581 BW |
181 | ret = i915_mutex_lock_interruptible(drm_dev); |
182 | if (ret) | |
183 | return ret; | |
184 | ||
3ccfd19d BW |
185 | if (dev_priv->l3_parity.remap_info[slice]) |
186 | memcpy(buf, | |
187 | dev_priv->l3_parity.remap_info[slice] + (offset/4), | |
188 | count); | |
189 | else | |
190 | memset(buf, 0, count); | |
84bc7581 | 191 | |
84bc7581 BW |
192 | mutex_unlock(&drm_dev->struct_mutex); |
193 | ||
1c966dd2 | 194 | return count; |
84bc7581 BW |
195 | } |
196 | ||
197 | static ssize_t | |
198 | i915_l3_write(struct file *filp, struct kobject *kobj, | |
199 | struct bin_attribute *attr, char *buf, | |
200 | loff_t offset, size_t count) | |
201 | { | |
657fb5fb | 202 | struct device *dev = kobj_to_dev(kobj); |
14c8d110 | 203 | struct drm_minor *dminor = dev_to_drm_minor(dev); |
84bc7581 | 204 | struct drm_device *drm_dev = dminor->dev; |
fac5e23e | 205 | struct drm_i915_private *dev_priv = to_i915(drm_dev); |
e2efd130 | 206 | struct i915_gem_context *ctx; |
84bc7581 | 207 | u32 *temp = NULL; /* Just here to make handling failures easy */ |
35a85ac6 | 208 | int slice = (int)(uintptr_t)attr->private; |
84bc7581 BW |
209 | int ret; |
210 | ||
8245be31 BW |
211 | if (!HAS_HW_CONTEXTS(drm_dev)) |
212 | return -ENXIO; | |
213 | ||
84bc7581 BW |
214 | ret = l3_access_valid(drm_dev, offset); |
215 | if (ret) | |
216 | return ret; | |
217 | ||
218 | ret = i915_mutex_lock_interruptible(drm_dev); | |
219 | if (ret) | |
220 | return ret; | |
221 | ||
35a85ac6 | 222 | if (!dev_priv->l3_parity.remap_info[slice]) { |
84bc7581 BW |
223 | temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL); |
224 | if (!temp) { | |
225 | mutex_unlock(&drm_dev->struct_mutex); | |
226 | return -ENOMEM; | |
227 | } | |
228 | } | |
229 | ||
84bc7581 BW |
230 | /* TODO: Ideally we really want a GPU reset here to make sure errors |
231 | * aren't propagated. Since I cannot find a stable way to reset the GPU | |
232 | * at this point it is left as a TODO. | |
233 | */ | |
234 | if (temp) | |
35a85ac6 | 235 | dev_priv->l3_parity.remap_info[slice] = temp; |
84bc7581 | 236 | |
35a85ac6 | 237 | memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count); |
84bc7581 | 238 | |
3ccfd19d BW |
239 | /* NB: We defer the remapping until we switch to the context */ |
240 | list_for_each_entry(ctx, &dev_priv->context_list, link) | |
241 | ctx->remap_slice |= (1<<slice); | |
84bc7581 BW |
242 | |
243 | mutex_unlock(&drm_dev->struct_mutex); | |
244 | ||
245 | return count; | |
246 | } | |
247 | ||
248 | static struct bin_attribute dpf_attrs = { | |
249 | .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, | |
250 | .size = GEN7_L3LOG_SIZE, | |
251 | .read = i915_l3_read, | |
252 | .write = i915_l3_write, | |
35a85ac6 BW |
253 | .mmap = NULL, |
254 | .private = (void *)0 | |
255 | }; | |
256 | ||
257 | static struct bin_attribute dpf_attrs_1 = { | |
258 | .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, | |
259 | .size = GEN7_L3LOG_SIZE, | |
260 | .read = i915_l3_read, | |
261 | .write = i915_l3_write, | |
262 | .mmap = NULL, | |
263 | .private = (void *)1 | |
84bc7581 BW |
264 | }; |
265 | ||
c8c972eb | 266 | static ssize_t gt_act_freq_mhz_show(struct device *kdev, |
df6eedc8 BW |
267 | struct device_attribute *attr, char *buf) |
268 | { | |
14c8d110 | 269 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
df6eedc8 | 270 | struct drm_device *dev = minor->dev; |
fac5e23e | 271 | struct drm_i915_private *dev_priv = to_i915(dev); |
df6eedc8 BW |
272 | int ret; |
273 | ||
5c9669ce TR |
274 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
275 | ||
d46c0517 ID |
276 | intel_runtime_pm_get(dev_priv); |
277 | ||
4fc688ce | 278 | mutex_lock(&dev_priv->rps.hw_lock); |
666a4537 | 279 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
177006a1 | 280 | u32 freq; |
64936258 | 281 | freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
7c59a9c1 | 282 | ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff); |
c8c972eb VS |
283 | } else { |
284 | u32 rpstat = I915_READ(GEN6_RPSTAT1); | |
ed64d66f AG |
285 | if (IS_GEN9(dev_priv)) |
286 | ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; | |
287 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
c8c972eb VS |
288 | ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
289 | else | |
290 | ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 291 | ret = intel_gpu_freq(dev_priv, ret); |
c8c972eb VS |
292 | } |
293 | mutex_unlock(&dev_priv->rps.hw_lock); | |
294 | ||
295 | intel_runtime_pm_put(dev_priv); | |
296 | ||
297 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); | |
298 | } | |
299 | ||
300 | static ssize_t gt_cur_freq_mhz_show(struct device *kdev, | |
301 | struct device_attribute *attr, char *buf) | |
302 | { | |
303 | struct drm_minor *minor = dev_to_drm_minor(kdev); | |
304 | struct drm_device *dev = minor->dev; | |
fac5e23e | 305 | struct drm_i915_private *dev_priv = to_i915(dev); |
c8c972eb VS |
306 | int ret; |
307 | ||
308 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
309 | ||
310 | intel_runtime_pm_get(dev_priv); | |
311 | ||
312 | mutex_lock(&dev_priv->rps.hw_lock); | |
7c59a9c1 | 313 | ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq); |
4fc688ce | 314 | mutex_unlock(&dev_priv->rps.hw_lock); |
df6eedc8 | 315 | |
d46c0517 ID |
316 | intel_runtime_pm_put(dev_priv); |
317 | ||
3e2a1556 | 318 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); |
df6eedc8 BW |
319 | } |
320 | ||
97e4eed7 CW |
321 | static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, |
322 | struct device_attribute *attr, char *buf) | |
323 | { | |
14c8d110 | 324 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
97e4eed7 | 325 | struct drm_device *dev = minor->dev; |
fac5e23e | 326 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e4eed7 | 327 | |
7c59a9c1 VS |
328 | return snprintf(buf, PAGE_SIZE, |
329 | "%d\n", | |
330 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
97e4eed7 CW |
331 | } |
332 | ||
df6eedc8 BW |
333 | static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) |
334 | { | |
14c8d110 | 335 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
df6eedc8 | 336 | struct drm_device *dev = minor->dev; |
fac5e23e | 337 | struct drm_i915_private *dev_priv = to_i915(dev); |
df6eedc8 BW |
338 | int ret; |
339 | ||
5c9669ce TR |
340 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
341 | ||
4fc688ce | 342 | mutex_lock(&dev_priv->rps.hw_lock); |
7c59a9c1 | 343 | ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
4fc688ce | 344 | mutex_unlock(&dev_priv->rps.hw_lock); |
df6eedc8 | 345 | |
3e2a1556 | 346 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); |
df6eedc8 BW |
347 | } |
348 | ||
46ddf194 BW |
349 | static ssize_t gt_max_freq_mhz_store(struct device *kdev, |
350 | struct device_attribute *attr, | |
351 | const char *buf, size_t count) | |
352 | { | |
14c8d110 | 353 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
46ddf194 | 354 | struct drm_device *dev = minor->dev; |
fac5e23e | 355 | struct drm_i915_private *dev_priv = to_i915(dev); |
2a5913a8 | 356 | u32 val; |
46ddf194 BW |
357 | ssize_t ret; |
358 | ||
359 | ret = kstrtou32(buf, 0, &val); | |
360 | if (ret) | |
361 | return ret; | |
362 | ||
5c9669ce TR |
363 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
364 | ||
933bfb44 SAK |
365 | intel_runtime_pm_get(dev_priv); |
366 | ||
4fc688ce | 367 | mutex_lock(&dev_priv->rps.hw_lock); |
46ddf194 | 368 | |
7c59a9c1 | 369 | val = intel_freq_opcode(dev_priv, val); |
46ddf194 | 370 | |
2a5913a8 BW |
371 | if (val < dev_priv->rps.min_freq || |
372 | val > dev_priv->rps.max_freq || | |
b39fb297 | 373 | val < dev_priv->rps.min_freq_softlimit) { |
4fc688ce | 374 | mutex_unlock(&dev_priv->rps.hw_lock); |
933bfb44 | 375 | intel_runtime_pm_put(dev_priv); |
46ddf194 BW |
376 | return -EINVAL; |
377 | } | |
378 | ||
2a5913a8 | 379 | if (val > dev_priv->rps.rp0_freq) |
31c77388 | 380 | DRM_DEBUG("User requested overclocking to %d\n", |
7c59a9c1 | 381 | intel_gpu_freq(dev_priv, val)); |
31c77388 | 382 | |
b39fb297 | 383 | dev_priv->rps.max_freq_softlimit = val; |
6917c7b9 | 384 | |
f745a80e VS |
385 | val = clamp_t(int, dev_priv->rps.cur_freq, |
386 | dev_priv->rps.min_freq_softlimit, | |
387 | dev_priv->rps.max_freq_softlimit); | |
388 | ||
389 | /* We still need *_set_rps to process the new max_delay and | |
390 | * update the interrupt limits and PMINTRMSK even though | |
391 | * frequency request may be unchanged. */ | |
dc97997a | 392 | intel_set_rps(dev_priv, val); |
46ddf194 | 393 | |
4fc688ce | 394 | mutex_unlock(&dev_priv->rps.hw_lock); |
46ddf194 | 395 | |
933bfb44 SAK |
396 | intel_runtime_pm_put(dev_priv); |
397 | ||
46ddf194 BW |
398 | return count; |
399 | } | |
400 | ||
df6eedc8 BW |
401 | static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) |
402 | { | |
14c8d110 | 403 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
df6eedc8 | 404 | struct drm_device *dev = minor->dev; |
fac5e23e | 405 | struct drm_i915_private *dev_priv = to_i915(dev); |
df6eedc8 BW |
406 | int ret; |
407 | ||
5c9669ce TR |
408 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
409 | ||
4fc688ce | 410 | mutex_lock(&dev_priv->rps.hw_lock); |
7c59a9c1 | 411 | ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
4fc688ce | 412 | mutex_unlock(&dev_priv->rps.hw_lock); |
df6eedc8 | 413 | |
3e2a1556 | 414 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); |
df6eedc8 BW |
415 | } |
416 | ||
46ddf194 BW |
417 | static ssize_t gt_min_freq_mhz_store(struct device *kdev, |
418 | struct device_attribute *attr, | |
419 | const char *buf, size_t count) | |
420 | { | |
14c8d110 | 421 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
46ddf194 | 422 | struct drm_device *dev = minor->dev; |
fac5e23e | 423 | struct drm_i915_private *dev_priv = to_i915(dev); |
2a5913a8 | 424 | u32 val; |
46ddf194 BW |
425 | ssize_t ret; |
426 | ||
427 | ret = kstrtou32(buf, 0, &val); | |
428 | if (ret) | |
429 | return ret; | |
430 | ||
5c9669ce TR |
431 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
432 | ||
933bfb44 SAK |
433 | intel_runtime_pm_get(dev_priv); |
434 | ||
4fc688ce | 435 | mutex_lock(&dev_priv->rps.hw_lock); |
46ddf194 | 436 | |
7c59a9c1 | 437 | val = intel_freq_opcode(dev_priv, val); |
0a073b84 | 438 | |
2a5913a8 BW |
439 | if (val < dev_priv->rps.min_freq || |
440 | val > dev_priv->rps.max_freq || | |
441 | val > dev_priv->rps.max_freq_softlimit) { | |
4fc688ce | 442 | mutex_unlock(&dev_priv->rps.hw_lock); |
933bfb44 | 443 | intel_runtime_pm_put(dev_priv); |
46ddf194 BW |
444 | return -EINVAL; |
445 | } | |
446 | ||
b39fb297 | 447 | dev_priv->rps.min_freq_softlimit = val; |
6917c7b9 | 448 | |
f745a80e VS |
449 | val = clamp_t(int, dev_priv->rps.cur_freq, |
450 | dev_priv->rps.min_freq_softlimit, | |
451 | dev_priv->rps.max_freq_softlimit); | |
452 | ||
453 | /* We still need *_set_rps to process the new min_delay and | |
454 | * update the interrupt limits and PMINTRMSK even though | |
455 | * frequency request may be unchanged. */ | |
dc97997a | 456 | intel_set_rps(dev_priv, val); |
46ddf194 | 457 | |
4fc688ce | 458 | mutex_unlock(&dev_priv->rps.hw_lock); |
46ddf194 | 459 | |
933bfb44 SAK |
460 | intel_runtime_pm_put(dev_priv); |
461 | ||
46ddf194 BW |
462 | return count; |
463 | ||
464 | } | |
465 | ||
c8c972eb | 466 | static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL); |
df6eedc8 | 467 | static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL); |
46ddf194 BW |
468 | static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store); |
469 | static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store); | |
df6eedc8 | 470 | |
97e4eed7 | 471 | static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL); |
ac6ae347 BW |
472 | |
473 | static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf); | |
474 | static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); | |
475 | static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); | |
476 | static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); | |
477 | ||
478 | /* For now we have a static number of RP states */ | |
479 | static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) | |
480 | { | |
14c8d110 | 481 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
ac6ae347 | 482 | struct drm_device *dev = minor->dev; |
fac5e23e | 483 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc4d91f6 | 484 | u32 val; |
ac6ae347 | 485 | |
bc4d91f6 AG |
486 | if (attr == &dev_attr_gt_RP0_freq_mhz) |
487 | val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq); | |
488 | else if (attr == &dev_attr_gt_RP1_freq_mhz) | |
489 | val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq); | |
490 | else if (attr == &dev_attr_gt_RPn_freq_mhz) | |
491 | val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq); | |
492 | else | |
ac6ae347 | 493 | BUG(); |
bc4d91f6 | 494 | |
3e2a1556 | 495 | return snprintf(buf, PAGE_SIZE, "%d\n", val); |
ac6ae347 BW |
496 | } |
497 | ||
df6eedc8 | 498 | static const struct attribute *gen6_attrs[] = { |
c8c972eb | 499 | &dev_attr_gt_act_freq_mhz.attr, |
df6eedc8 BW |
500 | &dev_attr_gt_cur_freq_mhz.attr, |
501 | &dev_attr_gt_max_freq_mhz.attr, | |
502 | &dev_attr_gt_min_freq_mhz.attr, | |
ac6ae347 BW |
503 | &dev_attr_gt_RP0_freq_mhz.attr, |
504 | &dev_attr_gt_RP1_freq_mhz.attr, | |
505 | &dev_attr_gt_RPn_freq_mhz.attr, | |
df6eedc8 BW |
506 | NULL, |
507 | }; | |
508 | ||
97e4eed7 | 509 | static const struct attribute *vlv_attrs[] = { |
c8c972eb | 510 | &dev_attr_gt_act_freq_mhz.attr, |
97e4eed7 CW |
511 | &dev_attr_gt_cur_freq_mhz.attr, |
512 | &dev_attr_gt_max_freq_mhz.attr, | |
513 | &dev_attr_gt_min_freq_mhz.attr, | |
74c4f62b D |
514 | &dev_attr_gt_RP0_freq_mhz.attr, |
515 | &dev_attr_gt_RP1_freq_mhz.attr, | |
516 | &dev_attr_gt_RPn_freq_mhz.attr, | |
97e4eed7 CW |
517 | &dev_attr_vlv_rpe_freq_mhz.attr, |
518 | NULL, | |
519 | }; | |
520 | ||
ef86ddce MK |
521 | static ssize_t error_state_read(struct file *filp, struct kobject *kobj, |
522 | struct bin_attribute *attr, char *buf, | |
523 | loff_t off, size_t count) | |
524 | { | |
525 | ||
657fb5fb | 526 | struct device *kdev = kobj_to_dev(kobj); |
14c8d110 | 527 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
ef86ddce MK |
528 | struct drm_device *dev = minor->dev; |
529 | struct i915_error_state_file_priv error_priv; | |
530 | struct drm_i915_error_state_buf error_str; | |
531 | ssize_t ret_count = 0; | |
532 | int ret; | |
533 | ||
534 | memset(&error_priv, 0, sizeof(error_priv)); | |
535 | ||
0a4cd7c8 | 536 | ret = i915_error_state_buf_init(&error_str, to_i915(dev), count, off); |
ef86ddce MK |
537 | if (ret) |
538 | return ret; | |
539 | ||
540 | error_priv.dev = dev; | |
541 | i915_error_state_get(dev, &error_priv); | |
542 | ||
543 | ret = i915_error_state_to_str(&error_str, &error_priv); | |
544 | if (ret) | |
545 | goto out; | |
546 | ||
547 | ret_count = count < error_str.bytes ? count : error_str.bytes; | |
548 | ||
549 | memcpy(buf, error_str.buf, ret_count); | |
550 | out: | |
551 | i915_error_state_put(&error_priv); | |
552 | i915_error_state_buf_release(&error_str); | |
553 | ||
554 | return ret ?: ret_count; | |
555 | } | |
556 | ||
557 | static ssize_t error_state_write(struct file *file, struct kobject *kobj, | |
558 | struct bin_attribute *attr, char *buf, | |
559 | loff_t off, size_t count) | |
560 | { | |
657fb5fb | 561 | struct device *kdev = kobj_to_dev(kobj); |
14c8d110 | 562 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
ef86ddce MK |
563 | struct drm_device *dev = minor->dev; |
564 | int ret; | |
565 | ||
566 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
567 | ||
568 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
569 | if (ret) | |
570 | return ret; | |
571 | ||
572 | i915_destroy_error_state(dev); | |
573 | mutex_unlock(&dev->struct_mutex); | |
574 | ||
575 | return count; | |
576 | } | |
577 | ||
578 | static struct bin_attribute error_state_attr = { | |
579 | .attr.name = "error", | |
580 | .attr.mode = S_IRUSR | S_IWUSR, | |
581 | .size = 0, | |
582 | .read = error_state_read, | |
583 | .write = error_state_write, | |
584 | }; | |
585 | ||
0136db58 BW |
586 | void i915_setup_sysfs(struct drm_device *dev) |
587 | { | |
588 | int ret; | |
589 | ||
8c3f929b | 590 | #ifdef CONFIG_PM |
58abf1da | 591 | if (HAS_RC6(dev)) { |
5bdebb18 | 592 | ret = sysfs_merge_group(&dev->primary->kdev->kobj, |
112abd29 DV |
593 | &rc6_attr_group); |
594 | if (ret) | |
595 | DRM_ERROR("RC6 residency sysfs setup failed\n"); | |
596 | } | |
58abf1da RV |
597 | if (HAS_RC6p(dev)) { |
598 | ret = sysfs_merge_group(&dev->primary->kdev->kobj, | |
599 | &rc6p_attr_group); | |
600 | if (ret) | |
601 | DRM_ERROR("RC6p residency sysfs setup failed\n"); | |
602 | } | |
666a4537 | 603 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
626ad6f3 VS |
604 | ret = sysfs_merge_group(&dev->primary->kdev->kobj, |
605 | &media_rc6_attr_group); | |
606 | if (ret) | |
607 | DRM_ERROR("Media RC6 residency sysfs setup failed\n"); | |
608 | } | |
8c3f929b | 609 | #endif |
040d2baa | 610 | if (HAS_L3_DPF(dev)) { |
5bdebb18 | 611 | ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs); |
112abd29 DV |
612 | if (ret) |
613 | DRM_ERROR("l3 parity sysfs setup failed\n"); | |
35a85ac6 BW |
614 | |
615 | if (NUM_L3_SLICES(dev) > 1) { | |
5bdebb18 | 616 | ret = device_create_bin_file(dev->primary->kdev, |
35a85ac6 BW |
617 | &dpf_attrs_1); |
618 | if (ret) | |
619 | DRM_ERROR("l3 parity slice 1 setup failed\n"); | |
620 | } | |
112abd29 | 621 | } |
df6eedc8 | 622 | |
97e4eed7 | 623 | ret = 0; |
666a4537 | 624 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5bdebb18 | 625 | ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs); |
97e4eed7 | 626 | else if (INTEL_INFO(dev)->gen >= 6) |
5bdebb18 | 627 | ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs); |
97e4eed7 CW |
628 | if (ret) |
629 | DRM_ERROR("RPS sysfs setup failed\n"); | |
ef86ddce | 630 | |
5bdebb18 | 631 | ret = sysfs_create_bin_file(&dev->primary->kdev->kobj, |
ef86ddce MK |
632 | &error_state_attr); |
633 | if (ret) | |
634 | DRM_ERROR("error_state sysfs setup failed\n"); | |
0136db58 BW |
635 | } |
636 | ||
637 | void i915_teardown_sysfs(struct drm_device *dev) | |
638 | { | |
5bdebb18 | 639 | sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr); |
666a4537 | 640 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5bdebb18 | 641 | sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs); |
97e4eed7 | 642 | else |
5bdebb18 DA |
643 | sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs); |
644 | device_remove_bin_file(dev->primary->kdev, &dpf_attrs_1); | |
645 | device_remove_bin_file(dev->primary->kdev, &dpf_attrs); | |
853c70e8 | 646 | #ifdef CONFIG_PM |
5bdebb18 | 647 | sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group); |
58abf1da | 648 | sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6p_attr_group); |
853c70e8 | 649 | #endif |
0136db58 | 650 | } |