projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: move dev_priv->suspend around
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_ums.c
CommitLineData
d8157a36
DV		 1/*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 * Copyright 2013 (c) Intel Corporation
6 * Daniel Vetter <daniel.vetter@ffwll.ch>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29#include <drm/drmP.h>
30#include <drm/i915_drm.h>
31#include "intel_drv.h"
32#include "i915_reg.h"
33
34static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
35{
36 struct drm_i915_private *dev_priv = dev->dev_private;
37 u32 dpll_reg;
38
39 /* On IVB, 3rd pipe shares PLL with another one */
40 if (pipe > 1)
41 return false;
42
43 if (HAS_PCH_SPLIT(dev))
e9a632a5 44 dpll_reg = PCH_DPLL(pipe);
d8157a36
DV		 45 else
46 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
47
48 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
49}
50
51static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
52{
53 struct drm_i915_private *dev_priv = dev->dev_private;
54 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
55 u32 *array;
56 int i;
57
58 if (!i915_pipe_enabled(dev, pipe))
59 return;
60
61 if (HAS_PCH_SPLIT(dev))
62 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
63
64 if (pipe == PIPE_A)
65 array = dev_priv->regfile.save_palette_a;
66 else
67 array = dev_priv->regfile.save_palette_b;
68
69 for (i = 0; i < 256; i++)
70 array[i] = I915_READ(reg + (i << 2));
71}
72
73static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
77 u32 *array;
78 int i;
79
80 if (!i915_pipe_enabled(dev, pipe))
81 return;
82
83 if (HAS_PCH_SPLIT(dev))
84 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
85
86 if (pipe == PIPE_A)
87 array = dev_priv->regfile.save_palette_a;
88 else
89 array = dev_priv->regfile.save_palette_b;
90
91 for (i = 0; i < 256; i++)
92 I915_WRITE(reg + (i << 2), array[i]);
93}
94
95void i915_save_display_reg(struct drm_device *dev)
96{
97 struct drm_i915_private *dev_priv = dev->dev_private;
98 int i;
99
100 /* Cursor state */
101 dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
102 dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
103 dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
104 dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
105 dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
106 dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
107 if (IS_GEN2(dev))
108 dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
109
110 if (HAS_PCH_SPLIT(dev)) {
111 dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
112 dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
113 }
114
115 /* Pipe & plane A info */
116 dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
117 dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
118 if (HAS_PCH_SPLIT(dev)) {
119 dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
120 dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
121 dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
122 } else {
123 dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
124 dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
125 dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
126 }
127 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
128 dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
129 dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
130 dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
131 dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
132 dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
133 dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
134 dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
135 if (!HAS_PCH_SPLIT(dev))
136 dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
137
138 if (HAS_PCH_SPLIT(dev)) {
139 dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
140 dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
141 dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
142 dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
143
144 dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
145 dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
146
147 dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
148 dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
149 dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
150
ab9412ba 151 dev_priv->regfile.saveTRANSACONF = I915_READ(_PCH_TRANSACONF);
275f01b2
DV		 152 dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_PCH_TRANS_HTOTAL_A);
153 dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_PCH_TRANS_HBLANK_A);
154 dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_PCH_TRANS_HSYNC_A);
155 dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_PCH_TRANS_VTOTAL_A);
156 dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_PCH_TRANS_VBLANK_A);
157 dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_PCH_TRANS_VSYNC_A);
d8157a36
DV		 158 }
159
160 dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
161 dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
162 dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
163 dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
164 dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
165 if (INTEL_INFO(dev)->gen >= 4) {
166 dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
167 dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
168 }
169 i915_save_palette(dev, PIPE_A);
170 dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
171
172 /* Pipe & plane B info */
173 dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
174 dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
175 if (HAS_PCH_SPLIT(dev)) {
176 dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
177 dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
178 dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
179 } else {
180 dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
181 dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
182 dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
183 }
184 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
185 dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
186 dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
187 dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
188 dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
189 dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
190 dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
191 dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
192 if (!HAS_PCH_SPLIT(dev))
193 dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
194
195 if (HAS_PCH_SPLIT(dev)) {
196 dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
197 dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
198 dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
199 dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
200
201 dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
202 dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
203
204 dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
205 dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
206 dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
207
ab9412ba 208 dev_priv->regfile.saveTRANSBCONF = I915_READ(_PCH_TRANSBCONF);
275f01b2
DV		 209 dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_PCH_TRANS_HTOTAL_B);
210 dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_PCH_TRANS_HBLANK_B);
211 dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_PCH_TRANS_HSYNC_B);
212 dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_PCH_TRANS_VTOTAL_B);
213 dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_PCH_TRANS_VBLANK_B);
214 dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_PCH_TRANS_VSYNC_B);
d8157a36
DV		 215 }
216
217 dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
218 dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
219 dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
220 dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
221 dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
222 if (INTEL_INFO(dev)->gen >= 4) {
223 dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
224 dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
225 }
226 i915_save_palette(dev, PIPE_B);
227 dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
228
229 /* Fences */
230 switch (INTEL_INFO(dev)->gen) {
231 case 7:
232 case 6:
233 for (i = 0; i < 16; i++)
234 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
235 break;
236 case 5:
237 case 4:
238 for (i = 0; i < 16; i++)
239 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
240 break;
241 case 3:
242 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
243 for (i = 0; i < 8; i++)
244 dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
245 case 2:
246 for (i = 0; i < 8; i++)
247 dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
248 break;
249 }
250
251 /* CRT state */
252 if (HAS_PCH_SPLIT(dev))
253 dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
254 else
255 dev_priv->regfile.saveADPA = I915_READ(ADPA);
256
a65e827d
DV		 257 /* Display Port state */
258 if (SUPPORTS_INTEGRATED_DP(dev)) {
259 dev_priv->regfile.saveDP_B = I915_READ(DP_B);
260 dev_priv->regfile.saveDP_C = I915_READ(DP_C);
261 dev_priv->regfile.saveDP_D = I915_READ(DP_D);
e3b95f1e
DV		 262 dev_priv->regfile.savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_DATA_M_G4X);
263 dev_priv->regfile.savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_DATA_M_G4X);
264 dev_priv->regfile.savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_DATA_N_G4X);
265 dev_priv->regfile.savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_DATA_N_G4X);
266 dev_priv->regfile.savePIPEA_DP_LINK_M = I915_READ(_PIPEA_LINK_M_G4X);
267 dev_priv->regfile.savePIPEB_DP_LINK_M = I915_READ(_PIPEB_LINK_M_G4X);
268 dev_priv->regfile.savePIPEA_DP_LINK_N = I915_READ(_PIPEA_LINK_N_G4X);
269 dev_priv->regfile.savePIPEB_DP_LINK_N = I915_READ(_PIPEB_LINK_N_G4X);
a65e827d
DV		 270 }
271 /* FIXME: regfile.save TV & SDVO state */
272
565ee389 273 /* Backlight */
7f1bdbcb
DV		 274 if (INTEL_INFO(dev)->gen <= 4)
275 pci_read_config_byte(dev->pdev, PCI_LBPC,
276 &dev_priv->regfile.saveLBB);
277
565ee389
JN		 278 if (HAS_PCH_SPLIT(dev)) {
279 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
280 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
281 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
282 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
283 } else {
284 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
285 if (INTEL_INFO(dev)->gen >= 4)
286 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
287 }
288
d8157a36
DV		 289 return;
290}
291
292void i915_restore_display_reg(struct drm_device *dev)
293{
294 struct drm_i915_private *dev_priv = dev->dev_private;
295 int dpll_a_reg, fpa0_reg, fpa1_reg;
296 int dpll_b_reg, fpb0_reg, fpb1_reg;
297 int i;
298
565ee389 299 /* Backlight */
7f1bdbcb
DV		 300 if (INTEL_INFO(dev)->gen <= 4)
301 pci_write_config_byte(dev->pdev, PCI_LBPC,
302 dev_priv->regfile.saveLBB);
303
565ee389
JN		 304 if (HAS_PCH_SPLIT(dev)) {
305 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
306 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
307 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
308 * otherwise we get blank eDP screen after S3 on some machines
309 */
310 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
311 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
312 } else {
313 if (INTEL_INFO(dev)->gen >= 4)
314 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
315 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
316 }
317
d8157a36
DV		 318 /* Display port ratios (must be done before clock is set) */
319 if (SUPPORTS_INTEGRATED_DP(dev)) {
e3b95f1e
DV		 320 I915_WRITE(_PIPEA_DATA_M_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
321 I915_WRITE(_PIPEB_DATA_M_G4X, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
322 I915_WRITE(_PIPEA_DATA_N_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
323 I915_WRITE(_PIPEB_DATA_N_G4X, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
324 I915_WRITE(_PIPEA_LINK_M_G4X, dev_priv->regfile.savePIPEA_DP_LINK_M);
325 I915_WRITE(_PIPEB_LINK_M_G4X, dev_priv->regfile.savePIPEB_DP_LINK_M);
326 I915_WRITE(_PIPEA_LINK_N_G4X, dev_priv->regfile.savePIPEA_DP_LINK_N);
327 I915_WRITE(_PIPEB_LINK_N_G4X, dev_priv->regfile.savePIPEB_DP_LINK_N);
d8157a36
DV		 328 }
329
330 /* Fences */
331 switch (INTEL_INFO(dev)->gen) {
332 case 7:
333 case 6:
334 for (i = 0; i < 16; i++)
335 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
336 break;
337 case 5:
338 case 4:
339 for (i = 0; i < 16; i++)
340 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
341 break;
342 case 3:
343 case 2:
344 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
345 for (i = 0; i < 8; i++)
346 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
347 for (i = 0; i < 8; i++)
348 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
349 break;
350 }
351
352
353 if (HAS_PCH_SPLIT(dev)) {
354 dpll_a_reg = _PCH_DPLL_A;
355 dpll_b_reg = _PCH_DPLL_B;
356 fpa0_reg = _PCH_FPA0;
357 fpb0_reg = _PCH_FPB0;
358 fpa1_reg = _PCH_FPA1;
359 fpb1_reg = _PCH_FPB1;
360 } else {
361 dpll_a_reg = _DPLL_A;
362 dpll_b_reg = _DPLL_B;
363 fpa0_reg = _FPA0;
364 fpb0_reg = _FPB0;
365 fpa1_reg = _FPA1;
366 fpb1_reg = _FPB1;
367 }
368
369 if (HAS_PCH_SPLIT(dev)) {
370 I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
371 I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
372 }
373
374 /* Pipe & plane A info */
375 /* Prime the clock */
376 if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
377 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
378 ~DPLL_VCO_ENABLE);
379 POSTING_READ(dpll_a_reg);
380 udelay(150);
381 }
382 I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
383 I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
384 /* Actually enable it */
385 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
386 POSTING_READ(dpll_a_reg);
387 udelay(150);
388 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
389 I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
390 POSTING_READ(_DPLL_A_MD);
391 }
392 udelay(150);
393
394 /* Restore mode */
395 I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
396 I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
397 I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
398 I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
399 I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
400 I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
401 if (!HAS_PCH_SPLIT(dev))
402 I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
403
404 if (HAS_PCH_SPLIT(dev)) {
405 I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
406 I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
407 I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
408 I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
409
410 I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
411 I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
412
413 I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
414 I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
415 I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
416
ab9412ba 417 I915_WRITE(_PCH_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
275f01b2
DV		 418 I915_WRITE(_PCH_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
419 I915_WRITE(_PCH_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
420 I915_WRITE(_PCH_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
421 I915_WRITE(_PCH_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
422 I915_WRITE(_PCH_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
423 I915_WRITE(_PCH_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
d8157a36
DV		 424 }
425
426 /* Restore plane info */
427 I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
428 I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
429 I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
430 I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
431 I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
432 if (INTEL_INFO(dev)->gen >= 4) {
433 I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
434 I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
435 }
436
437 I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
438
439 i915_restore_palette(dev, PIPE_A);
440 /* Enable the plane */
441 I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
442 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
443
444 /* Pipe & plane B info */
445 if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
446 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
447 ~DPLL_VCO_ENABLE);
448 POSTING_READ(dpll_b_reg);
449 udelay(150);
450 }
451 I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
452 I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
453 /* Actually enable it */
454 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
455 POSTING_READ(dpll_b_reg);
456 udelay(150);
457 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
458 I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
459 POSTING_READ(_DPLL_B_MD);
460 }
461 udelay(150);
462
463 /* Restore mode */
464 I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
465 I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
466 I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
467 I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
468 I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
469 I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
470 if (!HAS_PCH_SPLIT(dev))
471 I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
472
473 if (HAS_PCH_SPLIT(dev)) {
474 I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
475 I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
476 I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
477 I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
478
479 I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
480 I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
481
482 I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
483 I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
484 I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
485
ab9412ba 486 I915_WRITE(_PCH_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
275f01b2
DV		 487 I915_WRITE(_PCH_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
488 I915_WRITE(_PCH_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
489 I915_WRITE(_PCH_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
490 I915_WRITE(_PCH_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
491 I915_WRITE(_PCH_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
492 I915_WRITE(_PCH_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
d8157a36
DV		 493 }
494
495 /* Restore plane info */
496 I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
497 I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
498 I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
499 I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
500 I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
501 if (INTEL_INFO(dev)->gen >= 4) {
502 I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
503 I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
504 }
505
506 I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
507
508 i915_restore_palette(dev, PIPE_B);
509 /* Enable the plane */
510 I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
511 I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
512
513 /* Cursor state */
514 I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
515 I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
516 I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
517 I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
518 I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
519 I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
520 if (IS_GEN2(dev))
521 I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
522
523 /* CRT state */
524 if (HAS_PCH_SPLIT(dev))
525 I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
526 else
527 I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
528
a65e827d
DV		 529 /* Display Port state */
530 if (SUPPORTS_INTEGRATED_DP(dev)) {
531 I915_WRITE(DP_B, dev_priv->regfile.saveDP_B);
532 I915_WRITE(DP_C, dev_priv->regfile.saveDP_C);
533 I915_WRITE(DP_D, dev_priv->regfile.saveDP_D);
534 }
535 /* FIXME: restore TV & SDVO state */
536
d8157a36
DV		 537 return;
538}
Linux kernel - Deliverables
This page took 0.098171 seconds and 5 git commands to generate.