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cf9d2890 YZ |
1 | /* |
2 | * Copyright(c) 2011-2015 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | */ | |
23 | ||
24 | #ifndef _I915_VGPU_H_ | |
25 | #define _I915_VGPU_H_ | |
26 | ||
27 | /* The MMIO offset of the shared info between guest and host emulator */ | |
28 | #define VGT_PVINFO_PAGE 0x78000 | |
29 | #define VGT_PVINFO_SIZE 0x1000 | |
30 | ||
31 | /* | |
32 | * The following structure pages are defined in GEN MMIO space | |
33 | * for virtualization. (One page for now) | |
34 | */ | |
41659ab7 | 35 | #define VGT_MAGIC 0x4776544776544776ULL /* 'vGTvGTvG' */ |
cf9d2890 YZ |
36 | #define VGT_VERSION_MAJOR 1 |
37 | #define VGT_VERSION_MINOR 0 | |
38 | ||
39 | #define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor)) | |
40 | #define INTEL_VGT_IF_VERSION \ | |
41 | INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR) | |
42 | ||
532beabf ZL |
43 | /* |
44 | * notifications from guest to vgpu device model | |
45 | */ | |
46 | enum vgt_g2v_type { | |
47 | VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2, | |
48 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY, | |
49 | VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE, | |
50 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY, | |
51 | VGT_G2V_EXECLIST_CONTEXT_CREATE, | |
52 | VGT_G2V_EXECLIST_CONTEXT_DESTROY, | |
53 | VGT_G2V_MAX, | |
54 | }; | |
55 | ||
cf9d2890 YZ |
56 | struct vgt_if { |
57 | uint64_t magic; /* VGT_MAGIC */ | |
58 | uint16_t version_major; | |
59 | uint16_t version_minor; | |
60 | uint32_t vgt_id; /* ID of vGT instance */ | |
61 | uint32_t rsv1[12]; /* pad to offset 0x40 */ | |
62 | /* | |
63 | * Data structure to describe the balooning info of resources. | |
64 | * Each VM can only have one portion of continuous area for now. | |
65 | * (May support scattered resource in future) | |
66 | * (starting from offset 0x40) | |
67 | */ | |
68 | struct { | |
69 | /* Aperture register balooning */ | |
70 | struct { | |
71 | uint32_t base; | |
72 | uint32_t size; | |
73 | } mappable_gmadr; /* aperture */ | |
74 | /* GMADR register balooning */ | |
75 | struct { | |
76 | uint32_t base; | |
77 | uint32_t size; | |
78 | } nonmappable_gmadr; /* non aperture */ | |
79 | /* allowed fence registers */ | |
80 | uint32_t fence_num; | |
81 | uint32_t rsv2[3]; | |
82 | } avail_rs; /* available/assigned resource */ | |
83 | uint32_t rsv3[0x200 - 24]; /* pad to half page */ | |
84 | /* | |
85 | * The bottom half page is for response from Gfx driver to hypervisor. | |
cf9d2890 YZ |
86 | */ |
87 | uint32_t rsv4; | |
88 | uint32_t display_ready; /* ready for display owner switch */ | |
532beabf ZL |
89 | |
90 | uint32_t rsv5[4]; | |
91 | ||
92 | uint32_t g2v_notify; | |
93 | uint32_t rsv6[7]; | |
94 | ||
ab75bb5d VS |
95 | struct { |
96 | uint32_t lo; | |
97 | uint32_t hi; | |
98 | } pdp[4]; | |
532beabf ZL |
99 | |
100 | uint32_t execlist_context_descriptor_lo; | |
101 | uint32_t execlist_context_descriptor_hi; | |
102 | ||
103 | uint32_t rsv7[0x200 - 24]; /* pad to one page */ | |
cf9d2890 YZ |
104 | } __packed; |
105 | ||
106 | #define vgtif_reg(x) \ | |
f0f59a00 | 107 | _MMIO((VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x)) |
cf9d2890 | 108 | |
e21fd552 YZ |
109 | /* vGPU display status to be used by the host side */ |
110 | #define VGT_DRV_DISPLAY_NOT_READY 0 | |
111 | #define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */ | |
112 | ||
cf9d2890 | 113 | extern void i915_check_vgpu(struct drm_device *dev); |
5dda8fa3 YZ |
114 | extern int intel_vgt_balloon(struct drm_device *dev); |
115 | extern void intel_vgt_deballoon(void); | |
cf9d2890 YZ |
116 | |
117 | #endif /* _I915_VGPU_H_ */ |