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5ee67f1c MR |
1 | /* |
2 | * Copyright © 2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | /** | |
25 | * DOC: atomic modeset support | |
26 | * | |
27 | * The functions here implement the state management and hardware programming | |
28 | * dispatch required by the atomic modeset infrastructure. | |
29 | * See intel_atomic_plane.c for the plane-specific atomic functionality. | |
30 | */ | |
31 | ||
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_atomic.h> | |
34 | #include <drm/drm_atomic_helper.h> | |
35 | #include <drm/drm_plane_helper.h> | |
36 | #include "intel_drv.h" | |
37 | ||
38 | ||
39 | /** | |
40 | * intel_atomic_check - validate state object | |
41 | * @dev: drm device | |
42 | * @state: state to validate | |
43 | */ | |
44 | int intel_atomic_check(struct drm_device *dev, | |
45 | struct drm_atomic_state *state) | |
46 | { | |
47 | int nplanes = dev->mode_config.num_total_plane; | |
48 | int ncrtcs = dev->mode_config.num_crtc; | |
49 | int nconnectors = dev->mode_config.num_connector; | |
50 | enum pipe nuclear_pipe = INVALID_PIPE; | |
e04fa803 CK |
51 | struct intel_crtc *nuclear_crtc = NULL; |
52 | struct intel_crtc_state *crtc_state = NULL; | |
5ee67f1c MR |
53 | int ret; |
54 | int i; | |
55 | bool not_nuclear = false; | |
56 | ||
57 | /* | |
58 | * FIXME: At the moment, we only support "nuclear pageflip" on a | |
59 | * single CRTC. Cross-crtc updates will be added later. | |
60 | */ | |
61 | for (i = 0; i < nplanes; i++) { | |
62 | struct intel_plane *plane = to_intel_plane(state->planes[i]); | |
63 | if (!plane) | |
64 | continue; | |
65 | ||
66 | if (nuclear_pipe == INVALID_PIPE) { | |
67 | nuclear_pipe = plane->pipe; | |
68 | } else if (nuclear_pipe != plane->pipe) { | |
69 | DRM_DEBUG_KMS("i915 only support atomic plane operations on a single CRTC at the moment\n"); | |
70 | return -EINVAL; | |
71 | } | |
72 | } | |
73 | ||
74 | /* | |
75 | * FIXME: We only handle planes for now; make sure there are no CRTC's | |
76 | * or connectors involved. | |
77 | */ | |
78 | state->allow_modeset = false; | |
79 | for (i = 0; i < ncrtcs; i++) { | |
80 | struct intel_crtc *crtc = to_intel_crtc(state->crtcs[i]); | |
f1e2daea MR |
81 | if (crtc) |
82 | memset(&crtc->atomic, 0, sizeof(crtc->atomic)); | |
5ee67f1c MR |
83 | if (crtc && crtc->pipe != nuclear_pipe) |
84 | not_nuclear = true; | |
e04fa803 CK |
85 | if (crtc && crtc->pipe == nuclear_pipe) { |
86 | nuclear_crtc = crtc; | |
87 | crtc_state = to_intel_crtc_state(state->crtc_states[i]); | |
88 | } | |
5ee67f1c MR |
89 | } |
90 | for (i = 0; i < nconnectors; i++) | |
91 | if (state->connectors[i] != NULL) | |
92 | not_nuclear = true; | |
93 | ||
94 | if (not_nuclear) { | |
95 | DRM_DEBUG_KMS("i915 only supports atomic plane operations at the moment\n"); | |
96 | return -EINVAL; | |
97 | } | |
98 | ||
99 | ret = drm_atomic_helper_check_planes(dev, state); | |
100 | if (ret) | |
101 | return ret; | |
102 | ||
6d3a1ce7 ML |
103 | /* |
104 | * FIXME: move to crtc atomic check function once this is | |
105 | * more atomic friendly. | |
106 | */ | |
e04fa803 CK |
107 | ret = intel_atomic_setup_scalers(dev, nuclear_crtc, crtc_state); |
108 | if (ret) | |
109 | return ret; | |
110 | ||
5ee67f1c MR |
111 | return ret; |
112 | } | |
113 | ||
114 | ||
115 | /** | |
116 | * intel_atomic_commit - commit validated state object | |
117 | * @dev: DRM device | |
118 | * @state: the top-level driver state object | |
119 | * @async: asynchronous commit | |
120 | * | |
121 | * This function commits a top-level state object that has been validated | |
122 | * with drm_atomic_helper_check(). | |
123 | * | |
124 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
125 | * we can only handle plane-related operations and do not yet support | |
126 | * asynchronous commit. | |
127 | * | |
128 | * RETURNS | |
129 | * Zero for success or -errno. | |
130 | */ | |
131 | int intel_atomic_commit(struct drm_device *dev, | |
132 | struct drm_atomic_state *state, | |
133 | bool async) | |
134 | { | |
61c05498 ML |
135 | struct drm_crtc_state *crtc_state; |
136 | struct drm_crtc *crtc; | |
5ee67f1c MR |
137 | int ret; |
138 | int i; | |
139 | ||
140 | if (async) { | |
141 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
142 | return -EINVAL; | |
143 | } | |
144 | ||
145 | ret = drm_atomic_helper_prepare_planes(dev, state); | |
146 | if (ret) | |
147 | return ret; | |
148 | ||
149 | /* Point of no return */ | |
61c05498 ML |
150 | drm_atomic_helper_swap_state(dev, state); |
151 | ||
152 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
153 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); | |
154 | ||
155 | if (INTEL_INFO(dev)->gen >= 9) | |
156 | skl_detach_scalers(to_intel_crtc(crtc)); | |
5ac1c4bc ML |
157 | |
158 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); | |
61c05498 | 159 | } |
5ee67f1c | 160 | |
5ac1c4bc | 161 | /* FIXME: This function should eventually call __intel_set_mode when needed */ |
61c05498 | 162 | |
5ee67f1c MR |
163 | drm_atomic_helper_wait_for_vblanks(dev, state); |
164 | drm_atomic_helper_cleanup_planes(dev, state); | |
165 | drm_atomic_state_free(state); | |
166 | ||
167 | return 0; | |
168 | } | |
2545e4a6 MR |
169 | |
170 | /** | |
171 | * intel_connector_atomic_get_property - fetch connector property value | |
172 | * @connector: connector to fetch property for | |
173 | * @state: state containing the property value | |
174 | * @property: property to look up | |
175 | * @val: pointer to write property value into | |
176 | * | |
177 | * The DRM core does not store shadow copies of properties for | |
178 | * atomic-capable drivers. This entrypoint is used to fetch | |
179 | * the current value of a driver-specific connector property. | |
180 | */ | |
181 | int | |
182 | intel_connector_atomic_get_property(struct drm_connector *connector, | |
183 | const struct drm_connector_state *state, | |
184 | struct drm_property *property, | |
185 | uint64_t *val) | |
186 | { | |
187 | int i; | |
188 | ||
189 | /* | |
190 | * TODO: We only have atomic modeset for planes at the moment, so the | |
191 | * crtc/connector code isn't quite ready yet. Until it's ready, | |
192 | * continue to look up all property values in the DRM's shadow copy | |
193 | * in obj->properties->values[]. | |
194 | * | |
195 | * When the crtc/connector state work matures, this function should | |
196 | * be updated to read the values out of the state structure instead. | |
197 | */ | |
198 | for (i = 0; i < connector->base.properties->count; i++) { | |
199 | if (connector->base.properties->properties[i] == property) { | |
200 | *val = connector->base.properties->values[i]; | |
201 | return 0; | |
202 | } | |
203 | } | |
204 | ||
205 | return -EINVAL; | |
206 | } | |
1356837e MR |
207 | |
208 | /* | |
209 | * intel_crtc_duplicate_state - duplicate crtc state | |
210 | * @crtc: drm crtc | |
211 | * | |
212 | * Allocates and returns a copy of the crtc state (both common and | |
213 | * Intel-specific) for the specified crtc. | |
214 | * | |
215 | * Returns: The newly allocated crtc state, or NULL on failure. | |
216 | */ | |
217 | struct drm_crtc_state * | |
218 | intel_crtc_duplicate_state(struct drm_crtc *crtc) | |
219 | { | |
220 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
a91572f3 | 221 | struct intel_crtc_state *crtc_state; |
1356837e MR |
222 | |
223 | if (WARN_ON(!intel_crtc->config)) | |
a91572f3 ACO |
224 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
225 | else | |
226 | crtc_state = kmemdup(intel_crtc->config, | |
227 | sizeof(*intel_crtc->config), GFP_KERNEL); | |
1356837e | 228 | |
f0c60574 ACO |
229 | if (!crtc_state) |
230 | return NULL; | |
231 | ||
232 | __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base); | |
233 | ||
234 | crtc_state->base.crtc = crtc; | |
a91572f3 ACO |
235 | |
236 | return &crtc_state->base; | |
1356837e MR |
237 | } |
238 | ||
239 | /** | |
240 | * intel_crtc_destroy_state - destroy crtc state | |
241 | * @crtc: drm crtc | |
242 | * | |
243 | * Destroys the crtc state (both common and Intel-specific) for the | |
244 | * specified crtc. | |
245 | */ | |
246 | void | |
247 | intel_crtc_destroy_state(struct drm_crtc *crtc, | |
248 | struct drm_crtc_state *state) | |
249 | { | |
250 | drm_atomic_helper_crtc_destroy_state(crtc, state); | |
251 | } | |
d03c93d4 CK |
252 | |
253 | /** | |
254 | * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests | |
255 | * @dev: DRM device | |
256 | * @crtc: intel crtc | |
257 | * @crtc_state: incoming crtc_state to validate and setup scalers | |
258 | * | |
259 | * This function sets up scalers based on staged scaling requests for | |
260 | * a @crtc and its planes. It is called from crtc level check path. If request | |
261 | * is a supportable request, it attaches scalers to requested planes and crtc. | |
262 | * | |
263 | * This function takes into account the current scaler(s) in use by any planes | |
264 | * not being part of this atomic state | |
265 | * | |
266 | * Returns: | |
267 | * 0 - scalers were setup succesfully | |
268 | * error code - otherwise | |
269 | */ | |
270 | int intel_atomic_setup_scalers(struct drm_device *dev, | |
271 | struct intel_crtc *intel_crtc, | |
272 | struct intel_crtc_state *crtc_state) | |
273 | { | |
274 | struct drm_plane *plane = NULL; | |
275 | struct intel_plane *intel_plane; | |
276 | struct intel_plane_state *plane_state = NULL; | |
277 | struct intel_crtc_scaler_state *scaler_state; | |
278 | struct drm_atomic_state *drm_state; | |
279 | int num_scalers_need; | |
280 | int i, j; | |
281 | ||
282 | if (INTEL_INFO(dev)->gen < 9 || !intel_crtc || !crtc_state) | |
283 | return 0; | |
284 | ||
285 | scaler_state = &crtc_state->scaler_state; | |
286 | drm_state = crtc_state->base.state; | |
287 | ||
288 | num_scalers_need = hweight32(scaler_state->scaler_users); | |
289 | DRM_DEBUG_KMS("crtc_state = %p need = %d avail = %d scaler_users = 0x%x\n", | |
290 | crtc_state, num_scalers_need, intel_crtc->num_scalers, | |
291 | scaler_state->scaler_users); | |
292 | ||
293 | /* | |
294 | * High level flow: | |
295 | * - staged scaler requests are already in scaler_state->scaler_users | |
296 | * - check whether staged scaling requests can be supported | |
297 | * - add planes using scalers that aren't in current transaction | |
298 | * - assign scalers to requested users | |
299 | * - as part of plane commit, scalers will be committed | |
300 | * (i.e., either attached or detached) to respective planes in hw | |
301 | * - as part of crtc_commit, scaler will be either attached or detached | |
302 | * to crtc in hw | |
303 | */ | |
304 | ||
305 | /* fail if required scalers > available scalers */ | |
306 | if (num_scalers_need > intel_crtc->num_scalers){ | |
307 | DRM_DEBUG_KMS("Too many scaling requests %d > %d\n", | |
308 | num_scalers_need, intel_crtc->num_scalers); | |
309 | return -EINVAL; | |
310 | } | |
311 | ||
312 | /* walkthrough scaler_users bits and start assigning scalers */ | |
313 | for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { | |
314 | int *scaler_id; | |
133b0d12 ML |
315 | const char *name; |
316 | int idx; | |
d03c93d4 CK |
317 | |
318 | /* skip if scaler not required */ | |
319 | if (!(scaler_state->scaler_users & (1 << i))) | |
320 | continue; | |
321 | ||
322 | if (i == SKL_CRTC_INDEX) { | |
133b0d12 ML |
323 | name = "CRTC"; |
324 | idx = intel_crtc->base.base.id; | |
325 | ||
d03c93d4 CK |
326 | /* panel fitter case: assign as a crtc scaler */ |
327 | scaler_id = &scaler_state->scaler_id; | |
328 | } else { | |
133b0d12 ML |
329 | name = "PLANE"; |
330 | idx = plane->base.id; | |
331 | ||
d03c93d4 CK |
332 | if (!drm_state) |
333 | continue; | |
334 | ||
335 | /* plane scaler case: assign as a plane scaler */ | |
336 | /* find the plane that set the bit as scaler_user */ | |
337 | plane = drm_state->planes[i]; | |
338 | ||
339 | /* | |
340 | * to enable/disable hq mode, add planes that are using scaler | |
341 | * into this transaction | |
342 | */ | |
343 | if (!plane) { | |
344 | struct drm_plane_state *state; | |
345 | plane = drm_plane_from_index(dev, i); | |
346 | state = drm_atomic_get_plane_state(drm_state, plane); | |
347 | if (IS_ERR(state)) { | |
348 | DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n", | |
349 | plane->base.id); | |
350 | return PTR_ERR(state); | |
351 | } | |
352 | } | |
353 | ||
354 | intel_plane = to_intel_plane(plane); | |
355 | ||
356 | /* plane on different crtc cannot be a scaler user of this crtc */ | |
357 | if (WARN_ON(intel_plane->pipe != intel_crtc->pipe)) { | |
358 | continue; | |
359 | } | |
360 | ||
361 | plane_state = to_intel_plane_state(drm_state->plane_states[i]); | |
362 | scaler_id = &plane_state->scaler_id; | |
363 | } | |
364 | ||
365 | if (*scaler_id < 0) { | |
366 | /* find a free scaler */ | |
367 | for (j = 0; j < intel_crtc->num_scalers; j++) { | |
368 | if (!scaler_state->scalers[j].in_use) { | |
369 | scaler_state->scalers[j].in_use = 1; | |
133b0d12 | 370 | *scaler_id = j; |
d03c93d4 | 371 | DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n", |
133b0d12 | 372 | intel_crtc->pipe, *scaler_id, name, idx); |
d03c93d4 CK |
373 | break; |
374 | } | |
375 | } | |
376 | } | |
377 | ||
378 | if (WARN_ON(*scaler_id < 0)) { | |
133b0d12 | 379 | DRM_DEBUG_KMS("Cannot find scaler for %s:%d\n", name, idx); |
d03c93d4 CK |
380 | continue; |
381 | } | |
382 | ||
383 | /* set scaler mode */ | |
384 | if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) { | |
385 | /* | |
386 | * when only 1 scaler is in use on either pipe A or B, | |
387 | * scaler 0 operates in high quality (HQ) mode. | |
388 | * In this case use scaler 0 to take advantage of HQ mode | |
389 | */ | |
390 | *scaler_id = 0; | |
391 | scaler_state->scalers[0].in_use = 1; | |
392 | scaler_state->scalers[0].mode = PS_SCALER_MODE_HQ; | |
393 | scaler_state->scalers[1].in_use = 0; | |
394 | } else { | |
395 | scaler_state->scalers[*scaler_id].mode = PS_SCALER_MODE_DYN; | |
396 | } | |
397 | } | |
398 | ||
399 | return 0; | |
400 | } | |
de419ab6 | 401 | |
f7217905 | 402 | static void |
de419ab6 ML |
403 | intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv, |
404 | struct intel_shared_dpll_config *shared_dpll) | |
405 | { | |
406 | enum intel_dpll_id i; | |
407 | ||
408 | /* Copy shared dpll state */ | |
409 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
410 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
411 | ||
412 | shared_dpll[i] = pll->config; | |
413 | } | |
414 | } | |
415 | ||
416 | struct intel_shared_dpll_config * | |
417 | intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) | |
418 | { | |
419 | struct intel_atomic_state *state = to_intel_atomic_state(s); | |
420 | ||
421 | WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); | |
422 | ||
423 | if (!state->dpll_set) { | |
424 | state->dpll_set = true; | |
425 | ||
426 | intel_atomic_duplicate_dpll_state(to_i915(s->dev), | |
427 | state->shared_dpll); | |
428 | } | |
429 | ||
430 | return state->shared_dpll; | |
431 | } | |
432 | ||
433 | struct drm_atomic_state * | |
434 | intel_atomic_state_alloc(struct drm_device *dev) | |
435 | { | |
436 | struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); | |
437 | ||
438 | if (!state || drm_atomic_state_init(dev, &state->base) < 0) { | |
439 | kfree(state); | |
440 | return NULL; | |
441 | } | |
442 | ||
443 | return &state->base; | |
444 | } | |
445 | ||
446 | void intel_atomic_state_clear(struct drm_atomic_state *s) | |
447 | { | |
448 | struct intel_atomic_state *state = to_intel_atomic_state(s); | |
449 | drm_atomic_state_default_clear(&state->base); | |
450 | state->dpll_set = false; | |
451 | } |