[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_audio.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <linux/kernel.h>
#include <linux/component.h>
#include <drm/i915_component.h>
#include "intel_drv.h"

#include <drm/drmP.h>
#include <drm/drm_edid.h>
#include "intel_drv.h"
#include "i915_drv.h"

/**
 * DOC: High Definition Audio over HDMI and Display Port
 *
 * The graphics and audio drivers together support High Definition Audio over
 * HDMI and Display Port. The audio programming sequences are divided into audio
 * codec and controller enable and disable sequences. The graphics driver
 * handles the audio codec sequences, while the audio driver handles the audio
 * controller sequences.
 *
 * The disable sequences must be performed before disabling the transcoder or
 * port. The enable sequences may only be performed after enabling the
 * transcoder and port, and after completed link training.
 *
 * The codec and controller sequences could be done either parallel or serial,
 * but generally the ELDV/PD change in the codec sequence indicates to the audio
 * driver that the controller sequence should start. Indeed, most of the
 * co-operation between the graphics and audio drivers is handled via audio
 * related registers. (The notable exception is the power management, not
 * covered here.)
 */

static const struct {
	int clock;
	u32 config;
} hdmi_audio_clock[] = {
	{ DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
	{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
	{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
	{ 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
	{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
	{ 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
	{ DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
	{ DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
};

/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
		if (mode->clock == hdmi_audio_clock[i].clock)
			break;
	}

	if (i == ARRAY_SIZE(hdmi_audio_clock)) {
		DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
		i = 1;
	}

	DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
		      hdmi_audio_clock[i].clock,
		      hdmi_audio_clock[i].config);

	return hdmi_audio_clock[i].config;
}

static bool intel_eld_uptodate(struct drm_connector *connector,
			       int reg_eldv, uint32_t bits_eldv,
			       int reg_elda, uint32_t bits_elda,
			       int reg_edid)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t tmp;
	int i;

	tmp = I915_READ(reg_eldv);
	tmp &= bits_eldv;

	if (!tmp)
		return false;

	tmp = I915_READ(reg_elda);
	tmp &= ~bits_elda;
	I915_WRITE(reg_elda, tmp);

	for (i = 0; i < drm_eld_size(eld) / 4; i++)
		if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
			return false;

	return true;
}

static void g4x_audio_codec_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	uint32_t eldv, tmp;

	DRM_DEBUG_KMS("Disable audio codec\n");

	tmp = I915_READ(G4X_AUD_VID_DID);
	if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
		eldv = G4X_ELDV_DEVCL_DEVBLC;
	else
		eldv = G4X_ELDV_DEVCTG;

	/* Invalidate ELD */
	tmp = I915_READ(G4X_AUD_CNTL_ST);
	tmp &= ~eldv;
	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
}

static void g4x_audio_codec_enable(struct drm_connector *connector,
				   struct intel_encoder *encoder,
				   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t tmp;
	int len, i;

	DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);

	tmp = I915_READ(G4X_AUD_VID_DID);
	if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
		eldv = G4X_ELDV_DEVCL_DEVBLC;
	else
		eldv = G4X_ELDV_DEVCTG;

	if (intel_eld_uptodate(connector,
			       G4X_AUD_CNTL_ST, eldv,
			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
			       G4X_HDMIW_HDMIEDID))
		return;

	tmp = I915_READ(G4X_AUD_CNTL_ST);
	tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
	len = (tmp >> 9) & 0x1f;		/* ELD buffer size */
	I915_WRITE(G4X_AUD_CNTL_ST, tmp);

	len = min(drm_eld_size(eld) / 4, len);
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));

	tmp = I915_READ(G4X_AUD_CNTL_ST);
	tmp |= eldv;
	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
}

static void hsw_audio_codec_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	enum pipe pipe = intel_crtc->pipe;
	uint32_t tmp;

	DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));

	/* Disable timestamps */
	tmp = I915_READ(HSW_AUD_CFG(pipe));
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp |= AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	I915_WRITE(HSW_AUD_CFG(pipe), tmp);

	/* Invalidate ELD */
	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
	tmp &= ~AUDIO_ELD_VALID(pipe);
	tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
}

static void hsw_audio_codec_enable(struct drm_connector *connector,
				   struct intel_encoder *encoder,
				   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	enum pipe pipe = intel_crtc->pipe;
	const uint8_t *eld = connector->eld;
	uint32_t tmp;
	int len, i;

	DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
		      pipe_name(pipe), drm_eld_size(eld));

	/* Enable audio presence detect, invalidate ELD */
	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
	tmp |= AUDIO_OUTPUT_ENABLE(pipe);
	tmp &= ~AUDIO_ELD_VALID(pipe);
	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);

	/*
	 * FIXME: We're supposed to wait for vblank here, but we have vblanks
	 * disabled during the mode set. The proper fix would be to push the
	 * rest of the setup into a vblank work item, queued here, but the
	 * infrastructure is not there yet.
	 */

	/* Reset ELD write address */
	tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
	tmp &= ~IBX_ELD_ADDRESS_MASK;
	I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);

	/* Up to 84 bytes of hw ELD buffer */
	len = min(drm_eld_size(eld), 84);
	for (i = 0; i < len / 4; i++)
		I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));

	/* ELD valid */
	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
	tmp |= AUDIO_ELD_VALID(pipe);
	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);

	/* Enable timestamps */
	tmp = I915_READ(HSW_AUD_CFG(pipe));
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	else
		tmp |= audio_config_hdmi_pixel_clock(mode);
	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
}

static void ilk_audio_codec_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_digital_port *intel_dig_port =
		enc_to_dig_port(&encoder->base);
	enum port port = intel_dig_port->port;
	enum pipe pipe = intel_crtc->pipe;
	uint32_t tmp, eldv;
	int aud_config;
	int aud_cntrl_st2;

	DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
		      port_name(port), pipe_name(pipe));

	if (HAS_PCH_IBX(dev_priv->dev)) {
		aud_config = IBX_AUD_CFG(pipe);
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
	} else if (IS_VALLEYVIEW(dev_priv)) {
		aud_config = VLV_AUD_CFG(pipe);
		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	} else {
		aud_config = CPT_AUD_CFG(pipe);
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	}

	/* Disable timestamps */
	tmp = I915_READ(aud_config);
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp |= AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	I915_WRITE(aud_config, tmp);

	if (WARN_ON(!port)) {
		eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) |
			IBX_ELD_VALID(PORT_D);
	} else {
		eldv = IBX_ELD_VALID(port);
	}

	/* Invalidate ELD */
	tmp = I915_READ(aud_cntrl_st2);
	tmp &= ~eldv;
	I915_WRITE(aud_cntrl_st2, tmp);
}

static void ilk_audio_codec_enable(struct drm_connector *connector,
				   struct intel_encoder *encoder,
				   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_digital_port *intel_dig_port =
		enc_to_dig_port(&encoder->base);
	enum port port = intel_dig_port->port;
	enum pipe pipe = intel_crtc->pipe;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t tmp;
	int len, i;
	int hdmiw_hdmiedid;
	int aud_config;
	int aud_cntl_st;
	int aud_cntrl_st2;

	DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
		      port_name(port), pipe_name(pipe), drm_eld_size(eld));

	/*
	 * FIXME: We're supposed to wait for vblank here, but we have vblanks
	 * disabled during the mode set. The proper fix would be to push the
	 * rest of the setup into a vblank work item, queued here, but the
	 * infrastructure is not there yet.
	 */

	if (HAS_PCH_IBX(connector->dev)) {
		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		aud_config = IBX_AUD_CFG(pipe);
		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
	} else if (IS_VALLEYVIEW(connector->dev)) {
		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
		aud_config = VLV_AUD_CFG(pipe);
		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	} else {
		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		aud_config = CPT_AUD_CFG(pipe);
		aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	}

	if (WARN_ON(!port)) {
		eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) |
			IBX_ELD_VALID(PORT_D);
	} else {
		eldv = IBX_ELD_VALID(port);
	}

	/* Invalidate ELD */
	tmp = I915_READ(aud_cntrl_st2);
	tmp &= ~eldv;
	I915_WRITE(aud_cntrl_st2, tmp);

	/* Reset ELD write address */
	tmp = I915_READ(aud_cntl_st);
	tmp &= ~IBX_ELD_ADDRESS_MASK;
	I915_WRITE(aud_cntl_st, tmp);

	/* Up to 84 bytes of hw ELD buffer */
	len = min(drm_eld_size(eld), 84);
	for (i = 0; i < len / 4; i++)
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

	/* ELD valid */
	tmp = I915_READ(aud_cntrl_st2);
	tmp |= eldv;
	I915_WRITE(aud_cntrl_st2, tmp);

	/* Enable timestamps */
	tmp = I915_READ(aud_config);
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	else
		tmp |= audio_config_hdmi_pixel_clock(mode);
	I915_WRITE(aud_config, tmp);
}

/**
 * intel_audio_codec_enable - Enable the audio codec for HD audio
 * @intel_encoder: encoder on which to enable audio
 *
 * The enable sequences may only be performed after enabling the transcoder and
 * port, and after completed link training.
 */
void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
{
	struct drm_encoder *encoder = &intel_encoder->base;
	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
	struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
	struct drm_connector *connector;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	connector = drm_select_eld(encoder, mode);
	if (!connector)
		return;

	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
			 connector->base.id,
			 connector->name,
			 connector->encoder->base.id,
			 connector->encoder->name);

	/* ELD Conn_Type */
	connector->eld[5] &= ~(3 << 2);
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
		connector->eld[5] |= (1 << 2);

	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;

	if (dev_priv->display.audio_codec_enable)
		dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
}

/**
 * intel_audio_codec_disable - Disable the audio codec for HD audio
 * @encoder: encoder on which to disable audio
 *
 * The disable sequences must be performed before disabling the transcoder or
 * port.
 */
void intel_audio_codec_disable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (dev_priv->display.audio_codec_disable)
		dev_priv->display.audio_codec_disable(encoder);
}

/**
 * intel_init_audio - Set up chip specific audio functions
 * @dev: drm device
 */
void intel_init_audio(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (IS_G4X(dev)) {
		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
	} else if (IS_VALLEYVIEW(dev)) {
		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
	} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
	} else if (HAS_PCH_SPLIT(dev)) {
		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
	}
}

static void i915_audio_component_get_power(struct device *dev)
{
	intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
}

static void i915_audio_component_put_power(struct device *dev)
{
	intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
}

/* Get CDCLK in kHz  */
static int i915_audio_component_get_cdclk_freq(struct device *dev)
{
	struct drm_i915_private *dev_priv = dev_to_i915(dev);
	int ret;

	if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
		return -ENODEV;

	intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
	ret = intel_ddi_get_cdclk_freq(dev_priv);
	intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);

	return ret;
}

static const struct i915_audio_component_ops i915_audio_component_ops = {
	.owner		= THIS_MODULE,
	.get_power	= i915_audio_component_get_power,
	.put_power	= i915_audio_component_put_power,
	.get_cdclk_freq	= i915_audio_component_get_cdclk_freq,
};

static int i915_audio_component_bind(struct device *i915_dev,
				     struct device *hda_dev, void *data)
{
	struct i915_audio_component *acomp = data;

	if (WARN_ON(acomp->ops || acomp->dev))
		return -EEXIST;

	acomp->ops = &i915_audio_component_ops;
	acomp->dev = i915_dev;

	return 0;
}

static void i915_audio_component_unbind(struct device *i915_dev,
					struct device *hda_dev, void *data)
{
	struct i915_audio_component *acomp = data;

	acomp->ops = NULL;
	acomp->dev = NULL;
}

static const struct component_ops i915_audio_component_bind_ops = {
	.bind	= i915_audio_component_bind,
	.unbind	= i915_audio_component_unbind,
};

/**
 * i915_audio_component_init - initialize and register the audio component
 * @dev_priv: i915 device instance
 *
 * This will register with the component framework a child component which
 * will bind dynamically to the snd_hda_intel driver's corresponding master
 * component when the latter is registered. During binding the child
 * initializes an instance of struct i915_audio_component which it receives
 * from the master. The master can then start to use the interface defined by
 * this struct. Each side can break the binding at any point by deregistering
 * its own component after which each side's component unbind callback is
 * called.
 *
 * We ignore any error during registration and continue with reduced
 * functionality (i.e. without HDMI audio).
 */
void i915_audio_component_init(struct drm_i915_private *dev_priv)
{
	int ret;

	ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
	if (ret < 0) {
		DRM_ERROR("failed to add audio component (%d)\n", ret);
		/* continue with reduced functionality */
		return;
	}

	dev_priv->audio_component_registered = true;
}

/**
 * i915_audio_component_cleanup - deregister the audio component
 * @dev_priv: i915 device instance
 *
 * Deregisters the audio component, breaking any existing binding to the
 * corresponding snd_hda_intel driver's master component.
 */
void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
{
	if (!dev_priv->audio_component_registered)
		return;

	component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
	dev_priv->audio_component_registered = false;
}
Commit	Line	Data
7c10a2b5 JN	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*/
	23
	24	#include <linux/kernel.h>
58fddc28 ID	25	#include <linux/component.h>
	26	#include <drm/i915_component.h>
	27	#include "intel_drv.h"
7c10a2b5 JN	28
	29	#include <drm/drmP.h>
	30	#include <drm/drm_edid.h>
	31	#include "intel_drv.h"
	32	#include "i915_drv.h"
	33
28855d2a JN	34	/**
	35	* DOC: High Definition Audio over HDMI and Display Port
	36	*
	37	* The graphics and audio drivers together support High Definition Audio over
	38	* HDMI and Display Port. The audio programming sequences are divided into audio
	39	* codec and controller enable and disable sequences. The graphics driver
	40	* handles the audio codec sequences, while the audio driver handles the audio
	41	* controller sequences.
	42	*
	43	* The disable sequences must be performed before disabling the transcoder or
	44	* port. The enable sequences may only be performed after enabling the
	45	* transcoder and port, and after completed link training.
	46	*
	47	* The codec and controller sequences could be done either parallel or serial,
	48	* but generally the ELDV/PD change in the codec sequence indicates to the audio
	49	* driver that the controller sequence should start. Indeed, most of the
	50	* co-operation between the graphics and audio drivers is handled via audio
	51	* related registers. (The notable exception is the power management, not
	52	* covered here.)
	53	*/
	54
87fcb2ad	55	static const struct {
7c10a2b5 JN	56	int clock;
	57	u32 config;
	58	} hdmi_audio_clock[] = {
	59	{ DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
	60	{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
	61	{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
	62	{ 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
	63	{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
	64	{ 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
	65	{ DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
	66	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
	67	{ DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
	68	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
	69	};
	70
	71	/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
	72	static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
	73	{
	74	int i;
	75
	76	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
	77	if (mode->clock == hdmi_audio_clock[i].clock)
	78	break;
	79	}
	80
	81	if (i == ARRAY_SIZE(hdmi_audio_clock)) {
	82	DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
	83	i = 1;
	84	}
	85
	86	DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
	87	hdmi_audio_clock[i].clock,
	88	hdmi_audio_clock[i].config);
	89
	90	return hdmi_audio_clock[i].config;
	91	}
	92
	93	static bool intel_eld_uptodate(struct drm_connector *connector,
	94	int reg_eldv, uint32_t bits_eldv,
	95	int reg_elda, uint32_t bits_elda,
	96	int reg_edid)
	97	{
	98	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	99	uint8_t *eld = connector->eld;
f9f682ae JN	100	uint32_t tmp;
f9f682ae JN	101	int i;
7c10a2b5	102
f9f682ae JN	103	tmp = I915_READ(reg_eldv);
f9f682ae JN	104	tmp &= bits_eldv;
7c10a2b5	105
f9f682ae	106	if (!tmp)
7c10a2b5 JN	107	return false;
7c10a2b5 JN	108
f9f682ae JN	109	tmp = I915_READ(reg_elda);
	110	tmp &= ~bits_elda;
	111	I915_WRITE(reg_elda, tmp);
7c10a2b5	112
938fd8aa	113	for (i = 0; i < drm_eld_size(eld) / 4; i++)
7c10a2b5 JN	114	if (I915_READ(reg_edid) != ((uint32_t )eld + i))
	115	return false;
	116
	117	return true;
	118	}
	119
76d8d3e5 JN	120	static void g4x_audio_codec_disable(struct intel_encoder *encoder)
	121	{
	122	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	123	uint32_t eldv, tmp;
	124
	125	DRM_DEBUG_KMS("Disable audio codec\n");
	126
	127	tmp = I915_READ(G4X_AUD_VID_DID);
	128	if (tmp == INTEL_AUDIO_DEVBLC \|\| tmp == INTEL_AUDIO_DEVCL)
	129	eldv = G4X_ELDV_DEVCL_DEVBLC;
	130	else
	131	eldv = G4X_ELDV_DEVCTG;
	132
	133	/* Invalidate ELD */
	134	tmp = I915_READ(G4X_AUD_CNTL_ST);
	135	tmp &= ~eldv;
	136	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
	137	}
	138
69bfe1a9 JN	139	static void g4x_audio_codec_enable(struct drm_connector *connector,
	140	struct intel_encoder *encoder,
	141	struct drm_display_mode *mode)
7c10a2b5 JN	142	{
	143	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	144	uint8_t *eld = connector->eld;
	145	uint32_t eldv;
f9f682ae JN	146	uint32_t tmp;
f9f682ae JN	147	int len, i;
7c10a2b5	148
d5ee08de JN	149	DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
d5ee08de JN	150
f9f682ae JN	151	tmp = I915_READ(G4X_AUD_VID_DID);
f9f682ae JN	152	if (tmp == INTEL_AUDIO_DEVBLC \|\| tmp == INTEL_AUDIO_DEVCL)
7c10a2b5 JN	153	eldv = G4X_ELDV_DEVCL_DEVBLC;
	154	else
	155	eldv = G4X_ELDV_DEVCTG;
	156
	157	if (intel_eld_uptodate(connector,
	158	G4X_AUD_CNTL_ST, eldv,
c46f111f	159	G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
7c10a2b5 JN	160	G4X_HDMIW_HDMIEDID))
	161	return;
	162
f9f682ae	163	tmp = I915_READ(G4X_AUD_CNTL_ST);
c46f111f	164	tmp &= ~(eldv \| G4X_ELD_ADDR_MASK);
f9f682ae JN	165	len = (tmp >> 9) & 0x1f; /* ELD buffer size */
f9f682ae JN	166	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
7c10a2b5	167
938fd8aa	168	len = min(drm_eld_size(eld) / 4, len);
7c10a2b5 JN	169	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	170	for (i = 0; i < len; i++)
	171	I915_WRITE(G4X_HDMIW_HDMIEDID, ((uint32_t )eld + i));
	172
f9f682ae JN	173	tmp = I915_READ(G4X_AUD_CNTL_ST);
	174	tmp \|= eldv;
	175	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
7c10a2b5 JN	176	}
7c10a2b5 JN	177
69bfe1a9 JN	178	static void hsw_audio_codec_disable(struct intel_encoder *encoder)
69bfe1a9 JN	179	{
5fad84a7 JN	180	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	181	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	182	enum pipe pipe = intel_crtc->pipe;
69bfe1a9 JN	183	uint32_t tmp;
69bfe1a9 JN	184
5fad84a7 JN	185	DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
	186
	187	/* Disable timestamps */
	188	tmp = I915_READ(HSW_AUD_CFG(pipe));
	189	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	190	tmp \|= AUD_CONFIG_N_PROG_ENABLE;
	191	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	192	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
	193	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
	194	tmp \|= AUD_CONFIG_N_VALUE_INDEX;
	195	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
	196
	197	/* Invalidate ELD */
69bfe1a9	198	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6	199	tmp &= ~AUDIO_ELD_VALID(pipe);
eb45fa0b	200	tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
69bfe1a9 JN	201	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
	202	}
	203
	204	static void hsw_audio_codec_enable(struct drm_connector *connector,
	205	struct intel_encoder *encoder,
	206	struct drm_display_mode *mode)
7c10a2b5 JN	207	{
7c10a2b5 JN	208	struct drm_i915_private *dev_priv = connector->dev->dev_private;
820d2d77	209	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
5fad84a7 JN	210	enum pipe pipe = intel_crtc->pipe;
5fad84a7 JN	211	const uint8_t *eld = connector->eld;
f9f682ae JN	212	uint32_t tmp;
f9f682ae JN	213	int len, i;
7c10a2b5	214
5fad84a7	215	DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
938fd8aa	216	pipe_name(pipe), drm_eld_size(eld));
7c10a2b5	217
5fad84a7 JN	218	/* Enable audio presence detect, invalidate ELD */
5fad84a7 JN	219	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 JN	220	tmp \|= AUDIO_OUTPUT_ENABLE(pipe);
82910ac6 JN	221	tmp &= ~AUDIO_ELD_VALID(pipe);
5fad84a7	222	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
7c10a2b5	223
5fad84a7 JN	224	/*
	225	* FIXME: We're supposed to wait for vblank here, but we have vblanks
	226	* disabled during the mode set. The proper fix would be to push the
	227	* rest of the setup into a vblank work item, queued here, but the
	228	* infrastructure is not there yet.
	229	*/
7c10a2b5	230
5fad84a7 JN	231	/* Reset ELD write address */
5fad84a7 JN	232	tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
c46f111f	233	tmp &= ~IBX_ELD_ADDRESS_MASK;
5fad84a7	234	I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
7c10a2b5	235
5fad84a7	236	/* Up to 84 bytes of hw ELD buffer */
938fd8aa JN	237	len = min(drm_eld_size(eld), 84);
938fd8aa JN	238	for (i = 0; i < len / 4; i++)
5fad84a7	239	I915_WRITE(HSW_AUD_EDID_DATA(pipe), ((uint32_t )eld + i));
7c10a2b5	240
5fad84a7	241	/* ELD valid */
69bfe1a9	242	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6	243	tmp \|= AUDIO_ELD_VALID(pipe);
69bfe1a9	244	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
5fad84a7 JN	245
	246	/* Enable timestamps */
	247	tmp = I915_READ(HSW_AUD_CFG(pipe));
	248	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	249	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	250	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	251	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
	252	tmp \|= AUD_CONFIG_N_VALUE_INDEX;
	253	else
	254	tmp \|= audio_config_hdmi_pixel_clock(mode);
	255	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
7c10a2b5 JN	256	}
7c10a2b5 JN	257
495a5bb8 JN	258	static void ilk_audio_codec_disable(struct intel_encoder *encoder)
	259	{
	260	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	261	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	262	struct intel_digital_port *intel_dig_port =
	263	enc_to_dig_port(&encoder->base);
	264	enum port port = intel_dig_port->port;
	265	enum pipe pipe = intel_crtc->pipe;
	266	uint32_t tmp, eldv;
	267	int aud_config;
	268	int aud_cntrl_st2;
	269
	270	DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
	271	port_name(port), pipe_name(pipe));
	272
	273	if (HAS_PCH_IBX(dev_priv->dev)) {
	274	aud_config = IBX_AUD_CFG(pipe);
	275	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
	276	} else if (IS_VALLEYVIEW(dev_priv)) {
	277	aud_config = VLV_AUD_CFG(pipe);
	278	aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	279	} else {
	280	aud_config = CPT_AUD_CFG(pipe);
	281	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	282	}
	283
	284	/* Disable timestamps */
	285	tmp = I915_READ(aud_config);
	286	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	287	tmp \|= AUD_CONFIG_N_PROG_ENABLE;
	288	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	289	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
	290	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
	291	tmp \|= AUD_CONFIG_N_VALUE_INDEX;
	292	I915_WRITE(aud_config, tmp);
	293
	294	if (WARN_ON(!port)) {
82910ac6 JN	295	eldv = IBX_ELD_VALID(PORT_B) \| IBX_ELD_VALID(PORT_C) \|
82910ac6 JN	296	IBX_ELD_VALID(PORT_D);
495a5bb8	297	} else {
82910ac6	298	eldv = IBX_ELD_VALID(port);
495a5bb8 JN	299	}
	300
	301	/* Invalidate ELD */
	302	tmp = I915_READ(aud_cntrl_st2);
	303	tmp &= ~eldv;
	304	I915_WRITE(aud_cntrl_st2, tmp);
	305	}
	306
69bfe1a9 JN	307	static void ilk_audio_codec_enable(struct drm_connector *connector,
	308	struct intel_encoder *encoder,
	309	struct drm_display_mode *mode)
7c10a2b5 JN	310	{
7c10a2b5 JN	311	struct drm_i915_private *dev_priv = connector->dev->dev_private;
820d2d77	312	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
c6bde93b JN	313	struct intel_digital_port *intel_dig_port =
	314	enc_to_dig_port(&encoder->base);
	315	enum port port = intel_dig_port->port;
	316	enum pipe pipe = intel_crtc->pipe;
7c10a2b5 JN	317	uint8_t *eld = connector->eld;
7c10a2b5 JN	318	uint32_t eldv;
f9f682ae JN	319	uint32_t tmp;
f9f682ae JN	320	int len, i;
7c10a2b5 JN	321	int hdmiw_hdmiedid;
	322	int aud_config;
	323	int aud_cntl_st;
	324	int aud_cntrl_st2;
c6bde93b JN	325
c6bde93b JN	326	DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
938fd8aa	327	port_name(port), pipe_name(pipe), drm_eld_size(eld));
c6bde93b JN	328
	329	/*
	330	* FIXME: We're supposed to wait for vblank here, but we have vblanks
	331	* disabled during the mode set. The proper fix would be to push the
	332	* rest of the setup into a vblank work item, queued here, but the
	333	* infrastructure is not there yet.
	334	*/
7c10a2b5 JN	335
	336	if (HAS_PCH_IBX(connector->dev)) {
	337	hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
	338	aud_config = IBX_AUD_CFG(pipe);
	339	aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
	340	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
	341	} else if (IS_VALLEYVIEW(connector->dev)) {
	342	hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
	343	aud_config = VLV_AUD_CFG(pipe);
	344	aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
	345	aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	346	} else {
	347	hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
	348	aud_config = CPT_AUD_CFG(pipe);
	349	aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
	350	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	351	}
	352
c6bde93b	353	if (WARN_ON(!port)) {
82910ac6 JN	354	eldv = IBX_ELD_VALID(PORT_B) \| IBX_ELD_VALID(PORT_C) \|
82910ac6 JN	355	IBX_ELD_VALID(PORT_D);
7c10a2b5	356	} else {
82910ac6	357	eldv = IBX_ELD_VALID(port);
7c10a2b5 JN	358	}
7c10a2b5 JN	359
c6bde93b	360	/* Invalidate ELD */
f9f682ae JN	361	tmp = I915_READ(aud_cntrl_st2);
	362	tmp &= ~eldv;
	363	I915_WRITE(aud_cntrl_st2, tmp);
7c10a2b5	364
c6bde93b	365	/* Reset ELD write address */
f9f682ae	366	tmp = I915_READ(aud_cntl_st);
c46f111f	367	tmp &= ~IBX_ELD_ADDRESS_MASK;
f9f682ae	368	I915_WRITE(aud_cntl_st, tmp);
7c10a2b5	369
c6bde93b	370	/* Up to 84 bytes of hw ELD buffer */
938fd8aa JN	371	len = min(drm_eld_size(eld), 84);
938fd8aa JN	372	for (i = 0; i < len / 4; i++)
7c10a2b5 JN	373	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
7c10a2b5 JN	374
c6bde93b	375	/* ELD valid */
f9f682ae JN	376	tmp = I915_READ(aud_cntrl_st2);
	377	tmp \|= eldv;
	378	I915_WRITE(aud_cntrl_st2, tmp);
c6bde93b JN	379
	380	/* Enable timestamps */
	381	tmp = I915_READ(aud_config);
	382	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	383	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	384	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	385	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
	386	tmp \|= AUD_CONFIG_N_VALUE_INDEX;
	387	else
	388	tmp \|= audio_config_hdmi_pixel_clock(mode);
	389	I915_WRITE(aud_config, tmp);
7c10a2b5 JN	390	}
7c10a2b5 JN	391
69bfe1a9 JN	392	/**
	393	* intel_audio_codec_enable - Enable the audio codec for HD audio
	394	* @intel_encoder: encoder on which to enable audio
	395	*
	396	* The enable sequences may only be performed after enabling the transcoder and
	397	* port, and after completed link training.
	398	*/
	399	void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
7c10a2b5	400	{
33d1e7c6 JN	401	struct drm_encoder *encoder = &intel_encoder->base;
33d1e7c6 JN	402	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6e3c9717	403	struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
7c10a2b5 JN	404	struct drm_connector *connector;
	405	struct drm_device *dev = encoder->dev;
	406	struct drm_i915_private *dev_priv = dev->dev_private;
	407
	408	connector = drm_select_eld(encoder, mode);
	409	if (!connector)
	410	return;
	411
	412	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
	413	connector->base.id,
	414	connector->name,
	415	connector->encoder->base.id,
	416	connector->encoder->name);
	417
6189b036 JN	418	/* ELD Conn_Type */
	419	connector->eld[5] &= ~(3 << 2);
	420	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
	421	connector->eld[5] \|= (1 << 2);
	422
7c10a2b5 JN	423	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7c10a2b5 JN	424
69bfe1a9 JN	425	if (dev_priv->display.audio_codec_enable)
	426	dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
	427	}
	428
	429	/**
	430	* intel_audio_codec_disable - Disable the audio codec for HD audio
	431	* @encoder: encoder on which to disable audio
	432	*
	433	* The disable sequences must be performed before disabling the transcoder or
	434	* port.
	435	*/
	436	void intel_audio_codec_disable(struct intel_encoder *encoder)
	437	{
	438	struct drm_device *dev = encoder->base.dev;
	439	struct drm_i915_private *dev_priv = dev->dev_private;
	440
	441	if (dev_priv->display.audio_codec_disable)
	442	dev_priv->display.audio_codec_disable(encoder);
7c10a2b5 JN	443	}
	444
	445	/**
	446	* intel_init_audio - Set up chip specific audio functions
	447	* @dev: drm device
	448	*/
	449	void intel_init_audio(struct drm_device *dev)
	450	{
	451	struct drm_i915_private *dev_priv = dev->dev_private;
	452
69bfe1a9 JN	453	if (IS_G4X(dev)) {
69bfe1a9 JN	454	dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
76d8d3e5	455	dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
69bfe1a9 JN	456	} else if (IS_VALLEYVIEW(dev)) {
69bfe1a9 JN	457	dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
495a5bb8	458	dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
69bfe1a9 JN	459	} else if (IS_HASWELL(dev) \|\| INTEL_INFO(dev)->gen >= 8) {
	460	dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
	461	dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
	462	} else if (HAS_PCH_SPLIT(dev)) {
	463	dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
495a5bb8	464	dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
69bfe1a9	465	}
7c10a2b5	466	}
58fddc28 ID	467
	468	static void i915_audio_component_get_power(struct device *dev)
	469	{
	470	intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
	471	}
	472
	473	static void i915_audio_component_put_power(struct device *dev)
	474	{
	475	intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
	476	}
	477
	478	/* Get CDCLK in kHz */
	479	static int i915_audio_component_get_cdclk_freq(struct device *dev)
	480	{
	481	struct drm_i915_private *dev_priv = dev_to_i915(dev);
	482	int ret;
	483
	484	if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
	485	return -ENODEV;
	486
	487	intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
	488	ret = intel_ddi_get_cdclk_freq(dev_priv);
	489	intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
	490
	491	return ret;
	492	}
	493
	494	static const struct i915_audio_component_ops i915_audio_component_ops = {
	495	.owner = THIS_MODULE,
	496	.get_power = i915_audio_component_get_power,
	497	.put_power = i915_audio_component_put_power,
	498	.get_cdclk_freq = i915_audio_component_get_cdclk_freq,
	499	};
	500
	501	static int i915_audio_component_bind(struct device *i915_dev,
	502	struct device hda_dev, void data)
	503	{
	504	struct i915_audio_component *acomp = data;
	505
	506	if (WARN_ON(acomp->ops \|\| acomp->dev))
	507	return -EEXIST;
	508
	509	acomp->ops = &i915_audio_component_ops;
	510	acomp->dev = i915_dev;
	511
	512	return 0;
	513	}
	514
	515	static void i915_audio_component_unbind(struct device *i915_dev,
	516	struct device hda_dev, void data)
	517	{
	518	struct i915_audio_component *acomp = data;
	519
	520	acomp->ops = NULL;
	521	acomp->dev = NULL;
	522	}
	523
	524	static const struct component_ops i915_audio_component_bind_ops = {
	525	.bind = i915_audio_component_bind,
	526	.unbind = i915_audio_component_unbind,
	527	};
	528
	529	/**
	530	* i915_audio_component_init - initialize and register the audio component
531	* @dev_priv: i915 device instance
532	*
533	* This will register with the component framework a child component which
534	* will bind dynamically to the snd_hda_intel driver's corresponding master
535	* component when the latter is registered. During binding the child
536	* initializes an instance of struct i915_audio_component which it receives
537	* from the master. The master can then start to use the interface defined by
538	* this struct. Each side can break the binding at any point by deregistering
539	* its own component after which each side's component unbind callback is
540	* called.
541	*
542	* We ignore any error during registration and continue with reduced
543	* functionality (i.e. without HDMI audio).
544	*/
545	void i915_audio_component_init(struct drm_i915_private *dev_priv)
546	{
547	int ret;
548
549	ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
550	if (ret < 0) {
551	DRM_ERROR("failed to add audio component (%d)\n", ret);
552	/* continue with reduced functionality */
553	return;
554	}
555
556	dev_priv->audio_component_registered = true;
557	}
558
559	/**
560	* i915_audio_component_cleanup - deregister the audio component
561	* @dev_priv: i915 device instance
562	*
563	* Deregisters the audio component, breaking any existing binding to the
564	* corresponding snd_hda_intel driver's master component.
565	*/
566	void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
567	{
568	if (!dev_priv->audio_component_registered)
569	return;
570
571	component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
572	dev_priv->audio_component_registered = false;
573	}