Commit | Line | Data |
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7c10a2b5 JN |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
58fddc28 ID |
25 | #include <linux/component.h> |
26 | #include <drm/i915_component.h> | |
27 | #include "intel_drv.h" | |
7c10a2b5 JN |
28 | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/drm_edid.h> | |
7c10a2b5 JN |
31 | #include "i915_drv.h" |
32 | ||
28855d2a JN |
33 | /** |
34 | * DOC: High Definition Audio over HDMI and Display Port | |
35 | * | |
36 | * The graphics and audio drivers together support High Definition Audio over | |
37 | * HDMI and Display Port. The audio programming sequences are divided into audio | |
38 | * codec and controller enable and disable sequences. The graphics driver | |
39 | * handles the audio codec sequences, while the audio driver handles the audio | |
40 | * controller sequences. | |
41 | * | |
42 | * The disable sequences must be performed before disabling the transcoder or | |
43 | * port. The enable sequences may only be performed after enabling the | |
3e6da4a9 JN |
44 | * transcoder and port, and after completed link training. Therefore the audio |
45 | * enable/disable sequences are part of the modeset sequence. | |
28855d2a JN |
46 | * |
47 | * The codec and controller sequences could be done either parallel or serial, | |
48 | * but generally the ELDV/PD change in the codec sequence indicates to the audio | |
49 | * driver that the controller sequence should start. Indeed, most of the | |
50 | * co-operation between the graphics and audio drivers is handled via audio | |
51 | * related registers. (The notable exception is the power management, not | |
52 | * covered here.) | |
cb422619 | 53 | * |
62cacc79 DV |
54 | * The struct &i915_audio_component is used to interact between the graphics |
55 | * and audio drivers. The struct &i915_audio_component_ops @ops in it is | |
cb422619 | 56 | * defined in graphics driver and called in audio driver. The |
62cacc79 | 57 | * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. |
28855d2a JN |
58 | */ |
59 | ||
87fcb2ad | 60 | static const struct { |
7c10a2b5 JN |
61 | int clock; |
62 | u32 config; | |
63 | } hdmi_audio_clock[] = { | |
606bb5e0 | 64 | { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
7c10a2b5 JN |
65 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
66 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
606bb5e0 | 67 | { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
7c10a2b5 | 68 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
606bb5e0 VS |
69 | { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
70 | { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7c10a2b5 | 71 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
606bb5e0 | 72 | { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
7c10a2b5 JN |
73 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
74 | }; | |
75 | ||
4a21ef7d LY |
76 | /* HDMI N/CTS table */ |
77 | #define TMDS_297M 297000 | |
606bb5e0 | 78 | #define TMDS_296M 296703 |
4a21ef7d LY |
79 | static const struct { |
80 | int sample_rate; | |
81 | int clock; | |
82 | int n; | |
83 | int cts; | |
84 | } aud_ncts[] = { | |
85 | { 44100, TMDS_296M, 4459, 234375 }, | |
86 | { 44100, TMDS_297M, 4704, 247500 }, | |
87 | { 48000, TMDS_296M, 5824, 281250 }, | |
88 | { 48000, TMDS_297M, 5120, 247500 }, | |
89 | { 32000, TMDS_296M, 5824, 421875 }, | |
90 | { 32000, TMDS_297M, 3072, 222750 }, | |
91 | { 88200, TMDS_296M, 8918, 234375 }, | |
92 | { 88200, TMDS_297M, 9408, 247500 }, | |
93 | { 96000, TMDS_296M, 11648, 281250 }, | |
94 | { 96000, TMDS_297M, 10240, 247500 }, | |
95 | { 176400, TMDS_296M, 17836, 234375 }, | |
96 | { 176400, TMDS_297M, 18816, 247500 }, | |
97 | { 192000, TMDS_296M, 23296, 281250 }, | |
98 | { 192000, TMDS_297M, 20480, 247500 }, | |
99 | }; | |
100 | ||
7c10a2b5 | 101 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
5e7234c9 | 102 | static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode) |
7c10a2b5 JN |
103 | { |
104 | int i; | |
105 | ||
106 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
aad941d5 | 107 | if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) |
7c10a2b5 JN |
108 | break; |
109 | } | |
110 | ||
111 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
5e7234c9 | 112 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", |
aad941d5 | 113 | adjusted_mode->crtc_clock); |
7c10a2b5 JN |
114 | i = 1; |
115 | } | |
116 | ||
117 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
118 | hdmi_audio_clock[i].clock, | |
119 | hdmi_audio_clock[i].config); | |
120 | ||
121 | return hdmi_audio_clock[i].config; | |
122 | } | |
123 | ||
4a21ef7d LY |
124 | static int audio_config_get_n(const struct drm_display_mode *mode, int rate) |
125 | { | |
126 | int i; | |
127 | ||
128 | for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) { | |
129 | if ((rate == aud_ncts[i].sample_rate) && | |
130 | (mode->clock == aud_ncts[i].clock)) { | |
131 | return aud_ncts[i].n; | |
132 | } | |
133 | } | |
134 | return 0; | |
135 | } | |
136 | ||
7e8275c2 LY |
137 | static uint32_t audio_config_setup_n_reg(int n, uint32_t val) |
138 | { | |
139 | int n_low, n_up; | |
140 | uint32_t tmp = val; | |
141 | ||
142 | n_low = n & 0xfff; | |
143 | n_up = (n >> 12) & 0xff; | |
144 | tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK); | |
145 | tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) | | |
146 | (n_low << AUD_CONFIG_LOWER_N_SHIFT) | | |
147 | AUD_CONFIG_N_PROG_ENABLE); | |
148 | return tmp; | |
149 | } | |
150 | ||
4a21ef7d LY |
151 | /* check whether N/CTS/M need be set manually */ |
152 | static bool audio_rate_need_prog(struct intel_crtc *crtc, | |
87f77eff | 153 | const struct drm_display_mode *mode) |
4a21ef7d LY |
154 | { |
155 | if (((mode->clock == TMDS_297M) || | |
156 | (mode->clock == TMDS_296M)) && | |
2d84d2b3 | 157 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) |
4a21ef7d LY |
158 | return true; |
159 | else | |
160 | return false; | |
161 | } | |
162 | ||
7c10a2b5 | 163 | static bool intel_eld_uptodate(struct drm_connector *connector, |
f0f59a00 VS |
164 | i915_reg_t reg_eldv, uint32_t bits_eldv, |
165 | i915_reg_t reg_elda, uint32_t bits_elda, | |
166 | i915_reg_t reg_edid) | |
7c10a2b5 | 167 | { |
fac5e23e | 168 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
7c10a2b5 | 169 | uint8_t *eld = connector->eld; |
f9f682ae JN |
170 | uint32_t tmp; |
171 | int i; | |
7c10a2b5 | 172 | |
f9f682ae JN |
173 | tmp = I915_READ(reg_eldv); |
174 | tmp &= bits_eldv; | |
7c10a2b5 | 175 | |
f9f682ae | 176 | if (!tmp) |
7c10a2b5 JN |
177 | return false; |
178 | ||
f9f682ae JN |
179 | tmp = I915_READ(reg_elda); |
180 | tmp &= ~bits_elda; | |
181 | I915_WRITE(reg_elda, tmp); | |
7c10a2b5 | 182 | |
938fd8aa | 183 | for (i = 0; i < drm_eld_size(eld) / 4; i++) |
7c10a2b5 JN |
184 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
185 | return false; | |
186 | ||
187 | return true; | |
188 | } | |
189 | ||
76d8d3e5 JN |
190 | static void g4x_audio_codec_disable(struct intel_encoder *encoder) |
191 | { | |
fac5e23e | 192 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
76d8d3e5 JN |
193 | uint32_t eldv, tmp; |
194 | ||
195 | DRM_DEBUG_KMS("Disable audio codec\n"); | |
196 | ||
197 | tmp = I915_READ(G4X_AUD_VID_DID); | |
198 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
199 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
200 | else | |
201 | eldv = G4X_ELDV_DEVCTG; | |
202 | ||
203 | /* Invalidate ELD */ | |
204 | tmp = I915_READ(G4X_AUD_CNTL_ST); | |
205 | tmp &= ~eldv; | |
206 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
207 | } | |
208 | ||
69bfe1a9 JN |
209 | static void g4x_audio_codec_enable(struct drm_connector *connector, |
210 | struct intel_encoder *encoder, | |
5e7234c9 | 211 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 | 212 | { |
fac5e23e | 213 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
7c10a2b5 JN |
214 | uint8_t *eld = connector->eld; |
215 | uint32_t eldv; | |
f9f682ae JN |
216 | uint32_t tmp; |
217 | int len, i; | |
7c10a2b5 | 218 | |
d5ee08de JN |
219 | DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); |
220 | ||
f9f682ae JN |
221 | tmp = I915_READ(G4X_AUD_VID_DID); |
222 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
7c10a2b5 JN |
223 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
224 | else | |
225 | eldv = G4X_ELDV_DEVCTG; | |
226 | ||
227 | if (intel_eld_uptodate(connector, | |
228 | G4X_AUD_CNTL_ST, eldv, | |
c46f111f | 229 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, |
7c10a2b5 JN |
230 | G4X_HDMIW_HDMIEDID)) |
231 | return; | |
232 | ||
f9f682ae | 233 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
c46f111f | 234 | tmp &= ~(eldv | G4X_ELD_ADDR_MASK); |
f9f682ae JN |
235 | len = (tmp >> 9) & 0x1f; /* ELD buffer size */ |
236 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 | 237 | |
938fd8aa | 238 | len = min(drm_eld_size(eld) / 4, len); |
7c10a2b5 JN |
239 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
240 | for (i = 0; i < len; i++) | |
241 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
242 | ||
f9f682ae JN |
243 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
244 | tmp |= eldv; | |
245 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 JN |
246 | } |
247 | ||
69bfe1a9 JN |
248 | static void hsw_audio_codec_disable(struct intel_encoder *encoder) |
249 | { | |
fac5e23e | 250 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5fad84a7 JN |
251 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
252 | enum pipe pipe = intel_crtc->pipe; | |
69bfe1a9 JN |
253 | uint32_t tmp; |
254 | ||
5fad84a7 JN |
255 | DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); |
256 | ||
4a21ef7d LY |
257 | mutex_lock(&dev_priv->av_mutex); |
258 | ||
5fad84a7 JN |
259 | /* Disable timestamps */ |
260 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
261 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
262 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
263 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
264 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
2210ce7f | 265 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5fad84a7 JN |
266 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
267 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
268 | ||
269 | /* Invalidate ELD */ | |
69bfe1a9 | 270 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 271 | tmp &= ~AUDIO_ELD_VALID(pipe); |
eb45fa0b | 272 | tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); |
69bfe1a9 | 273 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
4a21ef7d LY |
274 | |
275 | mutex_unlock(&dev_priv->av_mutex); | |
69bfe1a9 JN |
276 | } |
277 | ||
278 | static void hsw_audio_codec_enable(struct drm_connector *connector, | |
279 | struct intel_encoder *encoder, | |
5e7234c9 | 280 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 | 281 | { |
fac5e23e | 282 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
820d2d77 | 283 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5fad84a7 | 284 | enum pipe pipe = intel_crtc->pipe; |
7e8275c2 | 285 | struct i915_audio_component *acomp = dev_priv->audio_component; |
5fad84a7 | 286 | const uint8_t *eld = connector->eld; |
7e8275c2 LY |
287 | struct intel_digital_port *intel_dig_port = |
288 | enc_to_dig_port(&encoder->base); | |
289 | enum port port = intel_dig_port->port; | |
f9f682ae JN |
290 | uint32_t tmp; |
291 | int len, i; | |
7e8275c2 | 292 | int n, rate; |
7c10a2b5 | 293 | |
5fad84a7 | 294 | DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", |
938fd8aa | 295 | pipe_name(pipe), drm_eld_size(eld)); |
7c10a2b5 | 296 | |
4a21ef7d LY |
297 | mutex_lock(&dev_priv->av_mutex); |
298 | ||
5fad84a7 JN |
299 | /* Enable audio presence detect, invalidate ELD */ |
300 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
82910ac6 JN |
301 | tmp |= AUDIO_OUTPUT_ENABLE(pipe); |
302 | tmp &= ~AUDIO_ELD_VALID(pipe); | |
5fad84a7 | 303 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
7c10a2b5 | 304 | |
5fad84a7 JN |
305 | /* |
306 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
307 | * disabled during the mode set. The proper fix would be to push the | |
308 | * rest of the setup into a vblank work item, queued here, but the | |
309 | * infrastructure is not there yet. | |
310 | */ | |
7c10a2b5 | 311 | |
5fad84a7 JN |
312 | /* Reset ELD write address */ |
313 | tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); | |
c46f111f | 314 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
5fad84a7 | 315 | I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); |
7c10a2b5 | 316 | |
5fad84a7 | 317 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
318 | len = min(drm_eld_size(eld), 84); |
319 | for (i = 0; i < len / 4; i++) | |
5fad84a7 | 320 | I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); |
7c10a2b5 | 321 | |
5fad84a7 | 322 | /* ELD valid */ |
69bfe1a9 | 323 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 324 | tmp |= AUDIO_ELD_VALID(pipe); |
69bfe1a9 | 325 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
5fad84a7 JN |
326 | |
327 | /* Enable timestamps */ | |
328 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
329 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
5fad84a7 | 330 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; |
2210ce7f | 331 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5fad84a7 JN |
332 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
333 | else | |
5e7234c9 | 334 | tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); |
7e8275c2 LY |
335 | |
336 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
28446598 | 337 | if (audio_rate_need_prog(intel_crtc, adjusted_mode)) { |
7e8275c2 LY |
338 | if (!acomp) |
339 | rate = 0; | |
340 | else if (port >= PORT_A && port <= PORT_E) | |
341 | rate = acomp->aud_sample_rate[port]; | |
342 | else { | |
343 | DRM_ERROR("invalid port: %d\n", port); | |
344 | rate = 0; | |
345 | } | |
28446598 | 346 | n = audio_config_get_n(adjusted_mode, rate); |
7e8275c2 LY |
347 | if (n != 0) |
348 | tmp = audio_config_setup_n_reg(n, tmp); | |
349 | else | |
350 | DRM_DEBUG_KMS("no suitable N value is found\n"); | |
351 | } | |
352 | ||
5fad84a7 | 353 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
4a21ef7d LY |
354 | |
355 | mutex_unlock(&dev_priv->av_mutex); | |
7c10a2b5 JN |
356 | } |
357 | ||
495a5bb8 JN |
358 | static void ilk_audio_codec_disable(struct intel_encoder *encoder) |
359 | { | |
fac5e23e | 360 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
495a5bb8 | 361 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
38cb2eca | 362 | enum port port = enc_to_dig_port(&encoder->base)->port; |
495a5bb8 JN |
363 | enum pipe pipe = intel_crtc->pipe; |
364 | uint32_t tmp, eldv; | |
f0f59a00 | 365 | i915_reg_t aud_config, aud_cntrl_st2; |
495a5bb8 JN |
366 | |
367 | DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", | |
368 | port_name(port), pipe_name(pipe)); | |
369 | ||
d3902c3e JN |
370 | if (WARN_ON(port == PORT_A)) |
371 | return; | |
372 | ||
2d1fe073 | 373 | if (HAS_PCH_IBX(dev_priv)) { |
495a5bb8 JN |
374 | aud_config = IBX_AUD_CFG(pipe); |
375 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
666a4537 | 376 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
495a5bb8 JN |
377 | aud_config = VLV_AUD_CFG(pipe); |
378 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
379 | } else { | |
380 | aud_config = CPT_AUD_CFG(pipe); | |
381 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
382 | } | |
383 | ||
384 | /* Disable timestamps */ | |
385 | tmp = I915_READ(aud_config); | |
386 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
387 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
388 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
389 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
2210ce7f | 390 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
495a5bb8 JN |
391 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
392 | I915_WRITE(aud_config, tmp); | |
393 | ||
d3902c3e | 394 | eldv = IBX_ELD_VALID(port); |
495a5bb8 JN |
395 | |
396 | /* Invalidate ELD */ | |
397 | tmp = I915_READ(aud_cntrl_st2); | |
398 | tmp &= ~eldv; | |
399 | I915_WRITE(aud_cntrl_st2, tmp); | |
400 | } | |
401 | ||
69bfe1a9 JN |
402 | static void ilk_audio_codec_enable(struct drm_connector *connector, |
403 | struct intel_encoder *encoder, | |
5e7234c9 | 404 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 | 405 | { |
fac5e23e | 406 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
820d2d77 | 407 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
38cb2eca | 408 | enum port port = enc_to_dig_port(&encoder->base)->port; |
c6bde93b | 409 | enum pipe pipe = intel_crtc->pipe; |
7c10a2b5 | 410 | uint8_t *eld = connector->eld; |
38cb2eca | 411 | uint32_t tmp, eldv; |
f9f682ae | 412 | int len, i; |
f0f59a00 | 413 | i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; |
c6bde93b JN |
414 | |
415 | DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", | |
938fd8aa | 416 | port_name(port), pipe_name(pipe), drm_eld_size(eld)); |
c6bde93b | 417 | |
d3902c3e JN |
418 | if (WARN_ON(port == PORT_A)) |
419 | return; | |
420 | ||
c6bde93b JN |
421 | /* |
422 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
423 | * disabled during the mode set. The proper fix would be to push the | |
424 | * rest of the setup into a vblank work item, queued here, but the | |
425 | * infrastructure is not there yet. | |
426 | */ | |
7c10a2b5 JN |
427 | |
428 | if (HAS_PCH_IBX(connector->dev)) { | |
429 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); | |
430 | aud_config = IBX_AUD_CFG(pipe); | |
431 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
432 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
666a4537 WB |
433 | } else if (IS_VALLEYVIEW(connector->dev) || |
434 | IS_CHERRYVIEW(connector->dev)) { | |
7c10a2b5 JN |
435 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
436 | aud_config = VLV_AUD_CFG(pipe); | |
437 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
438 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
439 | } else { | |
440 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); | |
441 | aud_config = CPT_AUD_CFG(pipe); | |
442 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
443 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
444 | } | |
445 | ||
d3902c3e | 446 | eldv = IBX_ELD_VALID(port); |
7c10a2b5 | 447 | |
c6bde93b | 448 | /* Invalidate ELD */ |
f9f682ae JN |
449 | tmp = I915_READ(aud_cntrl_st2); |
450 | tmp &= ~eldv; | |
451 | I915_WRITE(aud_cntrl_st2, tmp); | |
7c10a2b5 | 452 | |
c6bde93b | 453 | /* Reset ELD write address */ |
f9f682ae | 454 | tmp = I915_READ(aud_cntl_st); |
c46f111f | 455 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
f9f682ae | 456 | I915_WRITE(aud_cntl_st, tmp); |
7c10a2b5 | 457 | |
c6bde93b | 458 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
459 | len = min(drm_eld_size(eld), 84); |
460 | for (i = 0; i < len / 4; i++) | |
7c10a2b5 JN |
461 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
462 | ||
c6bde93b | 463 | /* ELD valid */ |
f9f682ae JN |
464 | tmp = I915_READ(aud_cntrl_st2); |
465 | tmp |= eldv; | |
466 | I915_WRITE(aud_cntrl_st2, tmp); | |
c6bde93b JN |
467 | |
468 | /* Enable timestamps */ | |
469 | tmp = I915_READ(aud_config); | |
470 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
471 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
472 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
2210ce7f | 473 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
c6bde93b JN |
474 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
475 | else | |
5e7234c9 | 476 | tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); |
c6bde93b | 477 | I915_WRITE(aud_config, tmp); |
7c10a2b5 JN |
478 | } |
479 | ||
69bfe1a9 JN |
480 | /** |
481 | * intel_audio_codec_enable - Enable the audio codec for HD audio | |
482 | * @intel_encoder: encoder on which to enable audio | |
483 | * | |
484 | * The enable sequences may only be performed after enabling the transcoder and | |
485 | * port, and after completed link training. | |
486 | */ | |
487 | void intel_audio_codec_enable(struct intel_encoder *intel_encoder) | |
7c10a2b5 | 488 | { |
33d1e7c6 JN |
489 | struct drm_encoder *encoder = &intel_encoder->base; |
490 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); | |
7c5f93b0 | 491 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
7c10a2b5 JN |
492 | struct drm_connector *connector; |
493 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 494 | struct drm_i915_private *dev_priv = to_i915(dev); |
51e1d83c DH |
495 | struct i915_audio_component *acomp = dev_priv->audio_component; |
496 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); | |
497 | enum port port = intel_dig_port->port; | |
7c10a2b5 | 498 | |
9e5a3b52 | 499 | connector = drm_select_eld(encoder); |
7c10a2b5 JN |
500 | if (!connector) |
501 | return; | |
502 | ||
503 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
504 | connector->base.id, | |
505 | connector->name, | |
506 | connector->encoder->base.id, | |
507 | connector->encoder->name); | |
508 | ||
6189b036 JN |
509 | /* ELD Conn_Type */ |
510 | connector->eld[5] &= ~(3 << 2); | |
2210ce7f | 511 | if (intel_crtc_has_dp_encoder(crtc->config)) |
6189b036 JN |
512 | connector->eld[5] |= (1 << 2); |
513 | ||
124abe07 | 514 | connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; |
7c10a2b5 | 515 | |
69bfe1a9 | 516 | if (dev_priv->display.audio_codec_enable) |
124abe07 VS |
517 | dev_priv->display.audio_codec_enable(connector, intel_encoder, |
518 | adjusted_mode); | |
51e1d83c | 519 | |
cae666ce TI |
520 | mutex_lock(&dev_priv->av_mutex); |
521 | intel_dig_port->audio_connector = connector; | |
9dfbffcf TI |
522 | /* referred in audio callbacks */ |
523 | dev_priv->dig_port_map[port] = intel_encoder; | |
cae666ce TI |
524 | mutex_unlock(&dev_priv->av_mutex); |
525 | ||
51e1d83c | 526 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) |
f0675d4a | 527 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port); |
69bfe1a9 JN |
528 | } |
529 | ||
530 | /** | |
531 | * intel_audio_codec_disable - Disable the audio codec for HD audio | |
95d0be61 | 532 | * @intel_encoder: encoder on which to disable audio |
69bfe1a9 JN |
533 | * |
534 | * The disable sequences must be performed before disabling the transcoder or | |
535 | * port. | |
536 | */ | |
51e1d83c | 537 | void intel_audio_codec_disable(struct intel_encoder *intel_encoder) |
69bfe1a9 | 538 | { |
51e1d83c DH |
539 | struct drm_encoder *encoder = &intel_encoder->base; |
540 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 541 | struct drm_i915_private *dev_priv = to_i915(dev); |
51e1d83c DH |
542 | struct i915_audio_component *acomp = dev_priv->audio_component; |
543 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); | |
544 | enum port port = intel_dig_port->port; | |
69bfe1a9 JN |
545 | |
546 | if (dev_priv->display.audio_codec_disable) | |
51e1d83c DH |
547 | dev_priv->display.audio_codec_disable(intel_encoder); |
548 | ||
cae666ce TI |
549 | mutex_lock(&dev_priv->av_mutex); |
550 | intel_dig_port->audio_connector = NULL; | |
9dfbffcf | 551 | dev_priv->dig_port_map[port] = NULL; |
cae666ce TI |
552 | mutex_unlock(&dev_priv->av_mutex); |
553 | ||
51e1d83c | 554 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) |
f0675d4a | 555 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port); |
7c10a2b5 JN |
556 | } |
557 | ||
558 | /** | |
88212941 ID |
559 | * intel_init_audio_hooks - Set up chip specific audio hooks |
560 | * @dev_priv: device private | |
7c10a2b5 | 561 | */ |
88212941 | 562 | void intel_init_audio_hooks(struct drm_i915_private *dev_priv) |
7c10a2b5 | 563 | { |
88212941 | 564 | if (IS_G4X(dev_priv)) { |
69bfe1a9 | 565 | dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; |
76d8d3e5 | 566 | dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; |
88212941 | 567 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
69bfe1a9 | 568 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
495a5bb8 | 569 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
88212941 | 570 | } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) { |
69bfe1a9 JN |
571 | dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; |
572 | dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; | |
88212941 | 573 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
69bfe1a9 | 574 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
495a5bb8 | 575 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
69bfe1a9 | 576 | } |
7c10a2b5 | 577 | } |
58fddc28 | 578 | |
c49d13ee | 579 | static void i915_audio_component_get_power(struct device *kdev) |
58fddc28 | 580 | { |
c49d13ee | 581 | intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO); |
58fddc28 ID |
582 | } |
583 | ||
c49d13ee | 584 | static void i915_audio_component_put_power(struct device *kdev) |
58fddc28 | 585 | { |
c49d13ee | 586 | intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO); |
58fddc28 ID |
587 | } |
588 | ||
c49d13ee | 589 | static void i915_audio_component_codec_wake_override(struct device *kdev, |
632f3ab9 LH |
590 | bool enable) |
591 | { | |
c49d13ee | 592 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
632f3ab9 LH |
593 | u32 tmp; |
594 | ||
ef11bdb3 | 595 | if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) |
632f3ab9 LH |
596 | return; |
597 | ||
c49d13ee | 598 | i915_audio_component_get_power(kdev); |
d838a110 | 599 | |
632f3ab9 LH |
600 | /* |
601 | * Enable/disable generating the codec wake signal, overriding the | |
602 | * internal logic to generate the codec wake to controller. | |
603 | */ | |
604 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
605 | tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; | |
606 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
607 | usleep_range(1000, 1500); | |
608 | ||
609 | if (enable) { | |
610 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
611 | tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; | |
612 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
613 | usleep_range(1000, 1500); | |
614 | } | |
d838a110 | 615 | |
c49d13ee | 616 | i915_audio_component_put_power(kdev); |
632f3ab9 LH |
617 | } |
618 | ||
58fddc28 | 619 | /* Get CDCLK in kHz */ |
c49d13ee | 620 | static int i915_audio_component_get_cdclk_freq(struct device *kdev) |
58fddc28 | 621 | { |
c49d13ee | 622 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
58fddc28 ID |
623 | |
624 | if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) | |
625 | return -ENODEV; | |
626 | ||
1033f92e | 627 | return dev_priv->cdclk_freq; |
58fddc28 ID |
628 | } |
629 | ||
c49d13ee | 630 | static int i915_audio_component_sync_audio_rate(struct device *kdev, |
4a21ef7d LY |
631 | int port, int rate) |
632 | { | |
c49d13ee | 633 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
4a21ef7d | 634 | struct intel_encoder *intel_encoder; |
4a21ef7d LY |
635 | struct intel_crtc *crtc; |
636 | struct drm_display_mode *mode; | |
7e8275c2 | 637 | struct i915_audio_component *acomp = dev_priv->audio_component; |
0bdf5a05 | 638 | enum pipe pipe = INVALID_PIPE; |
4a21ef7d | 639 | u32 tmp; |
7e8275c2 | 640 | int n; |
0bdf5a05 | 641 | int err = 0; |
4a21ef7d | 642 | |
ef11bdb3 | 643 | /* HSW, BDW, SKL, KBL need this fix */ |
4a21ef7d | 644 | if (!IS_SKYLAKE(dev_priv) && |
ef11bdb3 RV |
645 | !IS_KABYLAKE(dev_priv) && |
646 | !IS_BROADWELL(dev_priv) && | |
647 | !IS_HASWELL(dev_priv)) | |
4a21ef7d LY |
648 | return 0; |
649 | ||
c49d13ee | 650 | i915_audio_component_get_power(kdev); |
4a21ef7d LY |
651 | mutex_lock(&dev_priv->av_mutex); |
652 | /* 1. get the pipe */ | |
0bdf5a05 TI |
653 | intel_encoder = dev_priv->dig_port_map[port]; |
654 | /* intel_encoder might be NULL for DP MST */ | |
655 | if (!intel_encoder || !intel_encoder->base.crtc || | |
656 | intel_encoder->type != INTEL_OUTPUT_HDMI) { | |
657 | DRM_DEBUG_KMS("no valid port %c\n", port_name(port)); | |
658 | err = -ENODEV; | |
659 | goto unlock; | |
4a21ef7d | 660 | } |
0bdf5a05 TI |
661 | crtc = to_intel_crtc(intel_encoder->base.crtc); |
662 | pipe = crtc->pipe; | |
4a21ef7d LY |
663 | if (pipe == INVALID_PIPE) { |
664 | DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port)); | |
0bdf5a05 TI |
665 | err = -ENODEV; |
666 | goto unlock; | |
4a21ef7d | 667 | } |
0bdf5a05 | 668 | |
4a21ef7d LY |
669 | DRM_DEBUG_KMS("pipe %c connects port %c\n", |
670 | pipe_name(pipe), port_name(port)); | |
671 | mode = &crtc->config->base.adjusted_mode; | |
672 | ||
7e8275c2 LY |
673 | /* port must be valid now, otherwise the pipe will be invalid */ |
674 | acomp->aud_sample_rate[port] = rate; | |
675 | ||
4a21ef7d LY |
676 | /* 2. check whether to set the N/CTS/M manually or not */ |
677 | if (!audio_rate_need_prog(crtc, mode)) { | |
678 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
679 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
680 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
0bdf5a05 | 681 | goto unlock; |
4a21ef7d LY |
682 | } |
683 | ||
684 | n = audio_config_get_n(mode, rate); | |
685 | if (n == 0) { | |
686 | DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n", | |
687 | port_name(port)); | |
688 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
689 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
690 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
0bdf5a05 | 691 | goto unlock; |
4a21ef7d | 692 | } |
4a21ef7d | 693 | |
7e8275c2 | 694 | /* 3. set the N/CTS/M */ |
4a21ef7d | 695 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
7e8275c2 | 696 | tmp = audio_config_setup_n_reg(n, tmp); |
4a21ef7d LY |
697 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
698 | ||
0bdf5a05 | 699 | unlock: |
4a21ef7d | 700 | mutex_unlock(&dev_priv->av_mutex); |
c49d13ee | 701 | i915_audio_component_put_power(kdev); |
0bdf5a05 | 702 | return err; |
4a21ef7d LY |
703 | } |
704 | ||
c49d13ee | 705 | static int i915_audio_component_get_eld(struct device *kdev, int port, |
cae666ce TI |
706 | bool *enabled, |
707 | unsigned char *buf, int max_bytes) | |
708 | { | |
c49d13ee | 709 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
cae666ce TI |
710 | struct intel_encoder *intel_encoder; |
711 | struct intel_digital_port *intel_dig_port; | |
712 | const u8 *eld; | |
713 | int ret = -EINVAL; | |
714 | ||
715 | mutex_lock(&dev_priv->av_mutex); | |
0bdf5a05 TI |
716 | intel_encoder = dev_priv->dig_port_map[port]; |
717 | /* intel_encoder might be NULL for DP MST */ | |
718 | if (intel_encoder) { | |
719 | ret = 0; | |
cae666ce | 720 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
0bdf5a05 TI |
721 | *enabled = intel_dig_port->audio_connector != NULL; |
722 | if (*enabled) { | |
cae666ce TI |
723 | eld = intel_dig_port->audio_connector->eld; |
724 | ret = drm_eld_size(eld); | |
725 | memcpy(buf, eld, min(max_bytes, ret)); | |
cae666ce TI |
726 | } |
727 | } | |
728 | ||
729 | mutex_unlock(&dev_priv->av_mutex); | |
730 | return ret; | |
4a21ef7d LY |
731 | } |
732 | ||
58fddc28 ID |
733 | static const struct i915_audio_component_ops i915_audio_component_ops = { |
734 | .owner = THIS_MODULE, | |
735 | .get_power = i915_audio_component_get_power, | |
736 | .put_power = i915_audio_component_put_power, | |
632f3ab9 | 737 | .codec_wake_override = i915_audio_component_codec_wake_override, |
58fddc28 | 738 | .get_cdclk_freq = i915_audio_component_get_cdclk_freq, |
4a21ef7d | 739 | .sync_audio_rate = i915_audio_component_sync_audio_rate, |
cae666ce | 740 | .get_eld = i915_audio_component_get_eld, |
58fddc28 ID |
741 | }; |
742 | ||
c49d13ee DW |
743 | static int i915_audio_component_bind(struct device *i915_kdev, |
744 | struct device *hda_kdev, void *data) | |
58fddc28 ID |
745 | { |
746 | struct i915_audio_component *acomp = data; | |
c49d13ee | 747 | struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); |
7e8275c2 | 748 | int i; |
58fddc28 ID |
749 | |
750 | if (WARN_ON(acomp->ops || acomp->dev)) | |
751 | return -EEXIST; | |
752 | ||
91c8a326 | 753 | drm_modeset_lock_all(&dev_priv->drm); |
58fddc28 | 754 | acomp->ops = &i915_audio_component_ops; |
c49d13ee | 755 | acomp->dev = i915_kdev; |
7e8275c2 LY |
756 | BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); |
757 | for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) | |
758 | acomp->aud_sample_rate[i] = 0; | |
51e1d83c | 759 | dev_priv->audio_component = acomp; |
91c8a326 | 760 | drm_modeset_unlock_all(&dev_priv->drm); |
58fddc28 ID |
761 | |
762 | return 0; | |
763 | } | |
764 | ||
c49d13ee DW |
765 | static void i915_audio_component_unbind(struct device *i915_kdev, |
766 | struct device *hda_kdev, void *data) | |
58fddc28 ID |
767 | { |
768 | struct i915_audio_component *acomp = data; | |
c49d13ee | 769 | struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); |
58fddc28 | 770 | |
91c8a326 | 771 | drm_modeset_lock_all(&dev_priv->drm); |
58fddc28 ID |
772 | acomp->ops = NULL; |
773 | acomp->dev = NULL; | |
51e1d83c | 774 | dev_priv->audio_component = NULL; |
91c8a326 | 775 | drm_modeset_unlock_all(&dev_priv->drm); |
58fddc28 ID |
776 | } |
777 | ||
778 | static const struct component_ops i915_audio_component_bind_ops = { | |
779 | .bind = i915_audio_component_bind, | |
780 | .unbind = i915_audio_component_unbind, | |
781 | }; | |
782 | ||
783 | /** | |
784 | * i915_audio_component_init - initialize and register the audio component | |
785 | * @dev_priv: i915 device instance | |
786 | * | |
787 | * This will register with the component framework a child component which | |
788 | * will bind dynamically to the snd_hda_intel driver's corresponding master | |
789 | * component when the latter is registered. During binding the child | |
790 | * initializes an instance of struct i915_audio_component which it receives | |
791 | * from the master. The master can then start to use the interface defined by | |
792 | * this struct. Each side can break the binding at any point by deregistering | |
793 | * its own component after which each side's component unbind callback is | |
794 | * called. | |
795 | * | |
796 | * We ignore any error during registration and continue with reduced | |
797 | * functionality (i.e. without HDMI audio). | |
798 | */ | |
799 | void i915_audio_component_init(struct drm_i915_private *dev_priv) | |
800 | { | |
801 | int ret; | |
802 | ||
91c8a326 | 803 | ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops); |
58fddc28 ID |
804 | if (ret < 0) { |
805 | DRM_ERROR("failed to add audio component (%d)\n", ret); | |
806 | /* continue with reduced functionality */ | |
807 | return; | |
808 | } | |
809 | ||
810 | dev_priv->audio_component_registered = true; | |
811 | } | |
812 | ||
813 | /** | |
814 | * i915_audio_component_cleanup - deregister the audio component | |
815 | * @dev_priv: i915 device instance | |
816 | * | |
817 | * Deregisters the audio component, breaking any existing binding to the | |
818 | * corresponding snd_hda_intel driver's master component. | |
819 | */ | |
820 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) | |
821 | { | |
822 | if (!dev_priv->audio_component_registered) | |
823 | return; | |
824 | ||
91c8a326 | 825 | component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); |
58fddc28 ID |
826 | dev_priv->audio_component_registered = false; |
827 | } |