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7c10a2b5 JN |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
58fddc28 ID |
25 | #include <linux/component.h> |
26 | #include <drm/i915_component.h> | |
27 | #include "intel_drv.h" | |
7c10a2b5 JN |
28 | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/drm_edid.h> | |
7c10a2b5 JN |
31 | #include "i915_drv.h" |
32 | ||
28855d2a JN |
33 | /** |
34 | * DOC: High Definition Audio over HDMI and Display Port | |
35 | * | |
36 | * The graphics and audio drivers together support High Definition Audio over | |
37 | * HDMI and Display Port. The audio programming sequences are divided into audio | |
38 | * codec and controller enable and disable sequences. The graphics driver | |
39 | * handles the audio codec sequences, while the audio driver handles the audio | |
40 | * controller sequences. | |
41 | * | |
42 | * The disable sequences must be performed before disabling the transcoder or | |
43 | * port. The enable sequences may only be performed after enabling the | |
3e6da4a9 JN |
44 | * transcoder and port, and after completed link training. Therefore the audio |
45 | * enable/disable sequences are part of the modeset sequence. | |
28855d2a JN |
46 | * |
47 | * The codec and controller sequences could be done either parallel or serial, | |
48 | * but generally the ELDV/PD change in the codec sequence indicates to the audio | |
49 | * driver that the controller sequence should start. Indeed, most of the | |
50 | * co-operation between the graphics and audio drivers is handled via audio | |
51 | * related registers. (The notable exception is the power management, not | |
52 | * covered here.) | |
53 | */ | |
54 | ||
87fcb2ad | 55 | static const struct { |
7c10a2b5 JN |
56 | int clock; |
57 | u32 config; | |
58 | } hdmi_audio_clock[] = { | |
59 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
60 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
61 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
62 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
63 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
64 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
65 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
66 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
67 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
68 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
69 | }; | |
70 | ||
71 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
5e7234c9 | 72 | static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode) |
7c10a2b5 JN |
73 | { |
74 | int i; | |
75 | ||
76 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
aad941d5 | 77 | if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) |
7c10a2b5 JN |
78 | break; |
79 | } | |
80 | ||
81 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
5e7234c9 | 82 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", |
aad941d5 | 83 | adjusted_mode->crtc_clock); |
7c10a2b5 JN |
84 | i = 1; |
85 | } | |
86 | ||
87 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
88 | hdmi_audio_clock[i].clock, | |
89 | hdmi_audio_clock[i].config); | |
90 | ||
91 | return hdmi_audio_clock[i].config; | |
92 | } | |
93 | ||
94 | static bool intel_eld_uptodate(struct drm_connector *connector, | |
95 | int reg_eldv, uint32_t bits_eldv, | |
96 | int reg_elda, uint32_t bits_elda, | |
97 | int reg_edid) | |
98 | { | |
99 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
100 | uint8_t *eld = connector->eld; | |
f9f682ae JN |
101 | uint32_t tmp; |
102 | int i; | |
7c10a2b5 | 103 | |
f9f682ae JN |
104 | tmp = I915_READ(reg_eldv); |
105 | tmp &= bits_eldv; | |
7c10a2b5 | 106 | |
f9f682ae | 107 | if (!tmp) |
7c10a2b5 JN |
108 | return false; |
109 | ||
f9f682ae JN |
110 | tmp = I915_READ(reg_elda); |
111 | tmp &= ~bits_elda; | |
112 | I915_WRITE(reg_elda, tmp); | |
7c10a2b5 | 113 | |
938fd8aa | 114 | for (i = 0; i < drm_eld_size(eld) / 4; i++) |
7c10a2b5 JN |
115 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
116 | return false; | |
117 | ||
118 | return true; | |
119 | } | |
120 | ||
76d8d3e5 JN |
121 | static void g4x_audio_codec_disable(struct intel_encoder *encoder) |
122 | { | |
123 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
124 | uint32_t eldv, tmp; | |
125 | ||
126 | DRM_DEBUG_KMS("Disable audio codec\n"); | |
127 | ||
128 | tmp = I915_READ(G4X_AUD_VID_DID); | |
129 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
130 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
131 | else | |
132 | eldv = G4X_ELDV_DEVCTG; | |
133 | ||
134 | /* Invalidate ELD */ | |
135 | tmp = I915_READ(G4X_AUD_CNTL_ST); | |
136 | tmp &= ~eldv; | |
137 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
138 | } | |
139 | ||
69bfe1a9 JN |
140 | static void g4x_audio_codec_enable(struct drm_connector *connector, |
141 | struct intel_encoder *encoder, | |
5e7234c9 | 142 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 JN |
143 | { |
144 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
145 | uint8_t *eld = connector->eld; | |
146 | uint32_t eldv; | |
f9f682ae JN |
147 | uint32_t tmp; |
148 | int len, i; | |
7c10a2b5 | 149 | |
d5ee08de JN |
150 | DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); |
151 | ||
f9f682ae JN |
152 | tmp = I915_READ(G4X_AUD_VID_DID); |
153 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) | |
7c10a2b5 JN |
154 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
155 | else | |
156 | eldv = G4X_ELDV_DEVCTG; | |
157 | ||
158 | if (intel_eld_uptodate(connector, | |
159 | G4X_AUD_CNTL_ST, eldv, | |
c46f111f | 160 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, |
7c10a2b5 JN |
161 | G4X_HDMIW_HDMIEDID)) |
162 | return; | |
163 | ||
f9f682ae | 164 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
c46f111f | 165 | tmp &= ~(eldv | G4X_ELD_ADDR_MASK); |
f9f682ae JN |
166 | len = (tmp >> 9) & 0x1f; /* ELD buffer size */ |
167 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 | 168 | |
938fd8aa | 169 | len = min(drm_eld_size(eld) / 4, len); |
7c10a2b5 JN |
170 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
171 | for (i = 0; i < len; i++) | |
172 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
173 | ||
f9f682ae JN |
174 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
175 | tmp |= eldv; | |
176 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); | |
7c10a2b5 JN |
177 | } |
178 | ||
69bfe1a9 JN |
179 | static void hsw_audio_codec_disable(struct intel_encoder *encoder) |
180 | { | |
5fad84a7 JN |
181 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
182 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
183 | enum pipe pipe = intel_crtc->pipe; | |
69bfe1a9 JN |
184 | uint32_t tmp; |
185 | ||
5fad84a7 JN |
186 | DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); |
187 | ||
188 | /* Disable timestamps */ | |
189 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
190 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
191 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
192 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
193 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
194 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
195 | tmp |= AUD_CONFIG_N_VALUE_INDEX; | |
196 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | |
197 | ||
198 | /* Invalidate ELD */ | |
69bfe1a9 | 199 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 200 | tmp &= ~AUDIO_ELD_VALID(pipe); |
eb45fa0b | 201 | tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); |
69bfe1a9 JN |
202 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
203 | } | |
204 | ||
205 | static void hsw_audio_codec_enable(struct drm_connector *connector, | |
206 | struct intel_encoder *encoder, | |
5e7234c9 | 207 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 JN |
208 | { |
209 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
820d2d77 | 210 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5fad84a7 JN |
211 | enum pipe pipe = intel_crtc->pipe; |
212 | const uint8_t *eld = connector->eld; | |
f9f682ae JN |
213 | uint32_t tmp; |
214 | int len, i; | |
7c10a2b5 | 215 | |
5fad84a7 | 216 | DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", |
938fd8aa | 217 | pipe_name(pipe), drm_eld_size(eld)); |
7c10a2b5 | 218 | |
5fad84a7 JN |
219 | /* Enable audio presence detect, invalidate ELD */ |
220 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
82910ac6 JN |
221 | tmp |= AUDIO_OUTPUT_ENABLE(pipe); |
222 | tmp &= ~AUDIO_ELD_VALID(pipe); | |
5fad84a7 | 223 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
7c10a2b5 | 224 | |
5fad84a7 JN |
225 | /* |
226 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
227 | * disabled during the mode set. The proper fix would be to push the | |
228 | * rest of the setup into a vblank work item, queued here, but the | |
229 | * infrastructure is not there yet. | |
230 | */ | |
7c10a2b5 | 231 | |
5fad84a7 JN |
232 | /* Reset ELD write address */ |
233 | tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); | |
c46f111f | 234 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
5fad84a7 | 235 | I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); |
7c10a2b5 | 236 | |
5fad84a7 | 237 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
238 | len = min(drm_eld_size(eld), 84); |
239 | for (i = 0; i < len / 4; i++) | |
5fad84a7 | 240 | I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); |
7c10a2b5 | 241 | |
5fad84a7 | 242 | /* ELD valid */ |
69bfe1a9 | 243 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 244 | tmp |= AUDIO_ELD_VALID(pipe); |
69bfe1a9 | 245 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
5fad84a7 JN |
246 | |
247 | /* Enable timestamps */ | |
248 | tmp = I915_READ(HSW_AUD_CFG(pipe)); | |
249 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
250 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
251 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
252 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
253 | tmp |= AUD_CONFIG_N_VALUE_INDEX; | |
254 | else | |
5e7234c9 | 255 | tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); |
5fad84a7 | 256 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
7c10a2b5 JN |
257 | } |
258 | ||
495a5bb8 JN |
259 | static void ilk_audio_codec_disable(struct intel_encoder *encoder) |
260 | { | |
261 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
262 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
263 | struct intel_digital_port *intel_dig_port = | |
264 | enc_to_dig_port(&encoder->base); | |
265 | enum port port = intel_dig_port->port; | |
266 | enum pipe pipe = intel_crtc->pipe; | |
267 | uint32_t tmp, eldv; | |
268 | int aud_config; | |
269 | int aud_cntrl_st2; | |
270 | ||
271 | DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", | |
272 | port_name(port), pipe_name(pipe)); | |
273 | ||
d3902c3e JN |
274 | if (WARN_ON(port == PORT_A)) |
275 | return; | |
276 | ||
495a5bb8 JN |
277 | if (HAS_PCH_IBX(dev_priv->dev)) { |
278 | aud_config = IBX_AUD_CFG(pipe); | |
279 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
280 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
281 | aud_config = VLV_AUD_CFG(pipe); | |
282 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
283 | } else { | |
284 | aud_config = CPT_AUD_CFG(pipe); | |
285 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
286 | } | |
287 | ||
288 | /* Disable timestamps */ | |
289 | tmp = I915_READ(aud_config); | |
290 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
291 | tmp |= AUD_CONFIG_N_PROG_ENABLE; | |
292 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; | |
293 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; | |
294 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
295 | tmp |= AUD_CONFIG_N_VALUE_INDEX; | |
296 | I915_WRITE(aud_config, tmp); | |
297 | ||
d3902c3e | 298 | eldv = IBX_ELD_VALID(port); |
495a5bb8 JN |
299 | |
300 | /* Invalidate ELD */ | |
301 | tmp = I915_READ(aud_cntrl_st2); | |
302 | tmp &= ~eldv; | |
303 | I915_WRITE(aud_cntrl_st2, tmp); | |
304 | } | |
305 | ||
69bfe1a9 JN |
306 | static void ilk_audio_codec_enable(struct drm_connector *connector, |
307 | struct intel_encoder *encoder, | |
5e7234c9 | 308 | const struct drm_display_mode *adjusted_mode) |
7c10a2b5 JN |
309 | { |
310 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
820d2d77 | 311 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
c6bde93b JN |
312 | struct intel_digital_port *intel_dig_port = |
313 | enc_to_dig_port(&encoder->base); | |
314 | enum port port = intel_dig_port->port; | |
315 | enum pipe pipe = intel_crtc->pipe; | |
7c10a2b5 JN |
316 | uint8_t *eld = connector->eld; |
317 | uint32_t eldv; | |
f9f682ae JN |
318 | uint32_t tmp; |
319 | int len, i; | |
7c10a2b5 JN |
320 | int hdmiw_hdmiedid; |
321 | int aud_config; | |
322 | int aud_cntl_st; | |
323 | int aud_cntrl_st2; | |
c6bde93b JN |
324 | |
325 | DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", | |
938fd8aa | 326 | port_name(port), pipe_name(pipe), drm_eld_size(eld)); |
c6bde93b | 327 | |
d3902c3e JN |
328 | if (WARN_ON(port == PORT_A)) |
329 | return; | |
330 | ||
c6bde93b JN |
331 | /* |
332 | * FIXME: We're supposed to wait for vblank here, but we have vblanks | |
333 | * disabled during the mode set. The proper fix would be to push the | |
334 | * rest of the setup into a vblank work item, queued here, but the | |
335 | * infrastructure is not there yet. | |
336 | */ | |
7c10a2b5 JN |
337 | |
338 | if (HAS_PCH_IBX(connector->dev)) { | |
339 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); | |
340 | aud_config = IBX_AUD_CFG(pipe); | |
341 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
342 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
343 | } else if (IS_VALLEYVIEW(connector->dev)) { | |
344 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
345 | aud_config = VLV_AUD_CFG(pipe); | |
346 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
347 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
348 | } else { | |
349 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); | |
350 | aud_config = CPT_AUD_CFG(pipe); | |
351 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
352 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
353 | } | |
354 | ||
d3902c3e | 355 | eldv = IBX_ELD_VALID(port); |
7c10a2b5 | 356 | |
c6bde93b | 357 | /* Invalidate ELD */ |
f9f682ae JN |
358 | tmp = I915_READ(aud_cntrl_st2); |
359 | tmp &= ~eldv; | |
360 | I915_WRITE(aud_cntrl_st2, tmp); | |
7c10a2b5 | 361 | |
c6bde93b | 362 | /* Reset ELD write address */ |
f9f682ae | 363 | tmp = I915_READ(aud_cntl_st); |
c46f111f | 364 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
f9f682ae | 365 | I915_WRITE(aud_cntl_st, tmp); |
7c10a2b5 | 366 | |
c6bde93b | 367 | /* Up to 84 bytes of hw ELD buffer */ |
938fd8aa JN |
368 | len = min(drm_eld_size(eld), 84); |
369 | for (i = 0; i < len / 4; i++) | |
7c10a2b5 JN |
370 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
371 | ||
c6bde93b | 372 | /* ELD valid */ |
f9f682ae JN |
373 | tmp = I915_READ(aud_cntrl_st2); |
374 | tmp |= eldv; | |
375 | I915_WRITE(aud_cntrl_st2, tmp); | |
c6bde93b JN |
376 | |
377 | /* Enable timestamps */ | |
378 | tmp = I915_READ(aud_config); | |
379 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; | |
380 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; | |
381 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; | |
382 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
383 | tmp |= AUD_CONFIG_N_VALUE_INDEX; | |
384 | else | |
5e7234c9 | 385 | tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); |
c6bde93b | 386 | I915_WRITE(aud_config, tmp); |
7c10a2b5 JN |
387 | } |
388 | ||
69bfe1a9 JN |
389 | /** |
390 | * intel_audio_codec_enable - Enable the audio codec for HD audio | |
391 | * @intel_encoder: encoder on which to enable audio | |
392 | * | |
393 | * The enable sequences may only be performed after enabling the transcoder and | |
394 | * port, and after completed link training. | |
395 | */ | |
396 | void intel_audio_codec_enable(struct intel_encoder *intel_encoder) | |
7c10a2b5 | 397 | { |
33d1e7c6 JN |
398 | struct drm_encoder *encoder = &intel_encoder->base; |
399 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); | |
7c5f93b0 | 400 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
7c10a2b5 JN |
401 | struct drm_connector *connector; |
402 | struct drm_device *dev = encoder->dev; | |
403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
51e1d83c DH |
404 | struct i915_audio_component *acomp = dev_priv->audio_component; |
405 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); | |
406 | enum port port = intel_dig_port->port; | |
7c10a2b5 | 407 | |
9e5a3b52 | 408 | connector = drm_select_eld(encoder); |
7c10a2b5 JN |
409 | if (!connector) |
410 | return; | |
411 | ||
412 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
413 | connector->base.id, | |
414 | connector->name, | |
415 | connector->encoder->base.id, | |
416 | connector->encoder->name); | |
417 | ||
6189b036 JN |
418 | /* ELD Conn_Type */ |
419 | connector->eld[5] &= ~(3 << 2); | |
420 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
421 | connector->eld[5] |= (1 << 2); | |
422 | ||
124abe07 | 423 | connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; |
7c10a2b5 | 424 | |
69bfe1a9 | 425 | if (dev_priv->display.audio_codec_enable) |
124abe07 VS |
426 | dev_priv->display.audio_codec_enable(connector, intel_encoder, |
427 | adjusted_mode); | |
51e1d83c DH |
428 | |
429 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) | |
f0675d4a | 430 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port); |
69bfe1a9 JN |
431 | } |
432 | ||
433 | /** | |
434 | * intel_audio_codec_disable - Disable the audio codec for HD audio | |
95d0be61 | 435 | * @intel_encoder: encoder on which to disable audio |
69bfe1a9 JN |
436 | * |
437 | * The disable sequences must be performed before disabling the transcoder or | |
438 | * port. | |
439 | */ | |
51e1d83c | 440 | void intel_audio_codec_disable(struct intel_encoder *intel_encoder) |
69bfe1a9 | 441 | { |
51e1d83c DH |
442 | struct drm_encoder *encoder = &intel_encoder->base; |
443 | struct drm_device *dev = encoder->dev; | |
69bfe1a9 | 444 | struct drm_i915_private *dev_priv = dev->dev_private; |
51e1d83c DH |
445 | struct i915_audio_component *acomp = dev_priv->audio_component; |
446 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); | |
447 | enum port port = intel_dig_port->port; | |
69bfe1a9 JN |
448 | |
449 | if (dev_priv->display.audio_codec_disable) | |
51e1d83c DH |
450 | dev_priv->display.audio_codec_disable(intel_encoder); |
451 | ||
452 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) | |
f0675d4a | 453 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port); |
7c10a2b5 JN |
454 | } |
455 | ||
456 | /** | |
457 | * intel_init_audio - Set up chip specific audio functions | |
458 | * @dev: drm device | |
459 | */ | |
460 | void intel_init_audio(struct drm_device *dev) | |
461 | { | |
462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
463 | ||
69bfe1a9 JN |
464 | if (IS_G4X(dev)) { |
465 | dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; | |
76d8d3e5 | 466 | dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; |
69bfe1a9 JN |
467 | } else if (IS_VALLEYVIEW(dev)) { |
468 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; | |
495a5bb8 | 469 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
69bfe1a9 JN |
470 | } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) { |
471 | dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; | |
472 | dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; | |
473 | } else if (HAS_PCH_SPLIT(dev)) { | |
474 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; | |
495a5bb8 | 475 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
69bfe1a9 | 476 | } |
7c10a2b5 | 477 | } |
58fddc28 ID |
478 | |
479 | static void i915_audio_component_get_power(struct device *dev) | |
480 | { | |
481 | intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO); | |
482 | } | |
483 | ||
484 | static void i915_audio_component_put_power(struct device *dev) | |
485 | { | |
486 | intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO); | |
487 | } | |
488 | ||
632f3ab9 LH |
489 | static void i915_audio_component_codec_wake_override(struct device *dev, |
490 | bool enable) | |
491 | { | |
492 | struct drm_i915_private *dev_priv = dev_to_i915(dev); | |
493 | u32 tmp; | |
494 | ||
495 | if (!IS_SKYLAKE(dev_priv)) | |
496 | return; | |
497 | ||
498 | /* | |
499 | * Enable/disable generating the codec wake signal, overriding the | |
500 | * internal logic to generate the codec wake to controller. | |
501 | */ | |
502 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
503 | tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; | |
504 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
505 | usleep_range(1000, 1500); | |
506 | ||
507 | if (enable) { | |
508 | tmp = I915_READ(HSW_AUD_CHICKENBIT); | |
509 | tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; | |
510 | I915_WRITE(HSW_AUD_CHICKENBIT, tmp); | |
511 | usleep_range(1000, 1500); | |
512 | } | |
513 | } | |
514 | ||
58fddc28 ID |
515 | /* Get CDCLK in kHz */ |
516 | static int i915_audio_component_get_cdclk_freq(struct device *dev) | |
517 | { | |
518 | struct drm_i915_private *dev_priv = dev_to_i915(dev); | |
519 | int ret; | |
520 | ||
521 | if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) | |
522 | return -ENODEV; | |
523 | ||
524 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); | |
1652d19e VS |
525 | ret = dev_priv->display.get_display_clock_speed(dev_priv->dev); |
526 | ||
58fddc28 ID |
527 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
528 | ||
529 | return ret; | |
530 | } | |
531 | ||
532 | static const struct i915_audio_component_ops i915_audio_component_ops = { | |
533 | .owner = THIS_MODULE, | |
534 | .get_power = i915_audio_component_get_power, | |
535 | .put_power = i915_audio_component_put_power, | |
632f3ab9 | 536 | .codec_wake_override = i915_audio_component_codec_wake_override, |
58fddc28 ID |
537 | .get_cdclk_freq = i915_audio_component_get_cdclk_freq, |
538 | }; | |
539 | ||
540 | static int i915_audio_component_bind(struct device *i915_dev, | |
541 | struct device *hda_dev, void *data) | |
542 | { | |
543 | struct i915_audio_component *acomp = data; | |
51e1d83c | 544 | struct drm_i915_private *dev_priv = dev_to_i915(i915_dev); |
58fddc28 ID |
545 | |
546 | if (WARN_ON(acomp->ops || acomp->dev)) | |
547 | return -EEXIST; | |
548 | ||
d5f362a7 | 549 | drm_modeset_lock_all(dev_priv->dev); |
58fddc28 ID |
550 | acomp->ops = &i915_audio_component_ops; |
551 | acomp->dev = i915_dev; | |
51e1d83c | 552 | dev_priv->audio_component = acomp; |
d5f362a7 | 553 | drm_modeset_unlock_all(dev_priv->dev); |
58fddc28 ID |
554 | |
555 | return 0; | |
556 | } | |
557 | ||
558 | static void i915_audio_component_unbind(struct device *i915_dev, | |
559 | struct device *hda_dev, void *data) | |
560 | { | |
561 | struct i915_audio_component *acomp = data; | |
51e1d83c | 562 | struct drm_i915_private *dev_priv = dev_to_i915(i915_dev); |
58fddc28 | 563 | |
d5f362a7 | 564 | drm_modeset_lock_all(dev_priv->dev); |
58fddc28 ID |
565 | acomp->ops = NULL; |
566 | acomp->dev = NULL; | |
51e1d83c | 567 | dev_priv->audio_component = NULL; |
d5f362a7 | 568 | drm_modeset_unlock_all(dev_priv->dev); |
58fddc28 ID |
569 | } |
570 | ||
571 | static const struct component_ops i915_audio_component_bind_ops = { | |
572 | .bind = i915_audio_component_bind, | |
573 | .unbind = i915_audio_component_unbind, | |
574 | }; | |
575 | ||
576 | /** | |
577 | * i915_audio_component_init - initialize and register the audio component | |
578 | * @dev_priv: i915 device instance | |
579 | * | |
580 | * This will register with the component framework a child component which | |
581 | * will bind dynamically to the snd_hda_intel driver's corresponding master | |
582 | * component when the latter is registered. During binding the child | |
583 | * initializes an instance of struct i915_audio_component which it receives | |
584 | * from the master. The master can then start to use the interface defined by | |
585 | * this struct. Each side can break the binding at any point by deregistering | |
586 | * its own component after which each side's component unbind callback is | |
587 | * called. | |
588 | * | |
589 | * We ignore any error during registration and continue with reduced | |
590 | * functionality (i.e. without HDMI audio). | |
591 | */ | |
592 | void i915_audio_component_init(struct drm_i915_private *dev_priv) | |
593 | { | |
594 | int ret; | |
595 | ||
596 | ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops); | |
597 | if (ret < 0) { | |
598 | DRM_ERROR("failed to add audio component (%d)\n", ret); | |
599 | /* continue with reduced functionality */ | |
600 | return; | |
601 | } | |
602 | ||
603 | dev_priv->audio_component_registered = true; | |
604 | } | |
605 | ||
606 | /** | |
607 | * i915_audio_component_cleanup - deregister the audio component | |
608 | * @dev_priv: i915 device instance | |
609 | * | |
610 | * Deregisters the audio component, breaking any existing binding to the | |
611 | * corresponding snd_hda_intel driver's master component. | |
612 | */ | |
613 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) | |
614 | { | |
615 | if (!dev_priv->audio_component_registered) | |
616 | return; | |
617 | ||
618 | component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops); | |
619 | dev_priv->audio_component_registered = false; | |
620 | } |