[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_audio.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <linux/kernel.h>

#include <drm/drmP.h>
#include <drm/drm_edid.h>
#include "intel_drv.h"
#include "i915_drv.h"

static const struct {
	int clock;
	u32 config;
} hdmi_audio_clock[] = {
	{ DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
	{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
	{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
	{ 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
	{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
	{ 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
	{ DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
	{ DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
};

/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
		if (mode->clock == hdmi_audio_clock[i].clock)
			break;
	}

	if (i == ARRAY_SIZE(hdmi_audio_clock)) {
		DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
		i = 1;
	}

	DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
		      hdmi_audio_clock[i].clock,
		      hdmi_audio_clock[i].config);

	return hdmi_audio_clock[i].config;
}

static bool intel_eld_uptodate(struct drm_connector *connector,
			       int reg_eldv, uint32_t bits_eldv,
			       int reg_elda, uint32_t bits_elda,
			       int reg_edid)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t tmp;
	int i;

	tmp = I915_READ(reg_eldv);
	tmp &= bits_eldv;

	if (!tmp)
		return false;

	tmp = I915_READ(reg_elda);
	tmp &= ~bits_elda;
	I915_WRITE(reg_elda, tmp);

	for (i = 0; i < eld[2]; i++)
		if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
			return false;

	return true;
}

static void g4x_audio_codec_enable(struct drm_connector *connector,
				   struct intel_encoder *encoder,
				   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t tmp;
	int len, i;

	tmp = I915_READ(G4X_AUD_VID_DID);
	if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
		eldv = G4X_ELDV_DEVCL_DEVBLC;
	else
		eldv = G4X_ELDV_DEVCTG;

	if (intel_eld_uptodate(connector,
			       G4X_AUD_CNTL_ST, eldv,
			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
			       G4X_HDMIW_HDMIEDID))
		return;

	tmp = I915_READ(G4X_AUD_CNTL_ST);
	tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
	len = (tmp >> 9) & 0x1f;		/* ELD buffer size */
	I915_WRITE(G4X_AUD_CNTL_ST, tmp);

	len = min_t(int, eld[2], len);
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));

	tmp = I915_READ(G4X_AUD_CNTL_ST);
	tmp |= eldv;
	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
}

static void hsw_audio_codec_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	enum pipe pipe = intel_crtc->pipe;
	uint32_t tmp;

	DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));

	/* Disable timestamps */
	tmp = I915_READ(HSW_AUD_CFG(pipe));
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp |= AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	I915_WRITE(HSW_AUD_CFG(pipe), tmp);

	/* Invalidate ELD */
	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
	tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
}

static void hsw_audio_codec_enable(struct drm_connector *connector,
				   struct intel_encoder *encoder,
				   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	enum pipe pipe = intel_crtc->pipe;
	const uint8_t *eld = connector->eld;
	uint32_t tmp;
	int len, i;

	DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
		      pipe_name(pipe), eld[2]);

	/* Enable audio presence detect, invalidate ELD */
	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
	tmp |= AUDIO_OUTPUT_ENABLE_A << (pipe * 4);
	tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);

	/*
	 * FIXME: We're supposed to wait for vblank here, but we have vblanks
	 * disabled during the mode set. The proper fix would be to push the
	 * rest of the setup into a vblank work item, queued here, but the
	 * infrastructure is not there yet.
	 */

	/* Reset ELD write address */
	tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
	tmp &= ~IBX_ELD_ADDRESS_MASK;
	I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);

	/* Up to 84 bytes of hw ELD buffer */
	len = min_t(int, eld[2], 21);
	for (i = 0; i < len; i++)
		I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));

	/* ELD valid */
	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
	tmp |= AUDIO_ELD_VALID_A << (pipe * 4);
	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);

	/* Enable timestamps */
	tmp = I915_READ(HSW_AUD_CFG(pipe));
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	else
		tmp |= audio_config_hdmi_pixel_clock(mode);
	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
}

static void ilk_audio_codec_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_digital_port *intel_dig_port =
		enc_to_dig_port(&encoder->base);
	enum port port = intel_dig_port->port;
	enum pipe pipe = intel_crtc->pipe;
	uint32_t tmp, eldv;
	int aud_config;
	int aud_cntrl_st2;

	DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
		      port_name(port), pipe_name(pipe));

	if (HAS_PCH_IBX(dev_priv->dev)) {
		aud_config = IBX_AUD_CFG(pipe);
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
	} else if (IS_VALLEYVIEW(dev_priv)) {
		aud_config = VLV_AUD_CFG(pipe);
		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	} else {
		aud_config = CPT_AUD_CFG(pipe);
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	}

	/* Disable timestamps */
	tmp = I915_READ(aud_config);
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp |= AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	I915_WRITE(aud_config, tmp);

	if (WARN_ON(!port)) {
		eldv = IBX_ELD_VALIDB;
		eldv |= IBX_ELD_VALIDB << 4;
		eldv |= IBX_ELD_VALIDB << 8;
	} else {
		eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
	}

	/* Invalidate ELD */
	tmp = I915_READ(aud_cntrl_st2);
	tmp &= ~eldv;
	I915_WRITE(aud_cntrl_st2, tmp);
}

static void ilk_audio_codec_enable(struct drm_connector *connector,
				   struct intel_encoder *encoder,
				   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_digital_port *intel_dig_port =
		enc_to_dig_port(&encoder->base);
	enum port port = intel_dig_port->port;
	enum pipe pipe = intel_crtc->pipe;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t tmp;
	int len, i;
	int hdmiw_hdmiedid;
	int aud_config;
	int aud_cntl_st;
	int aud_cntrl_st2;

	DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
		      port_name(port), pipe_name(pipe), eld[2]);

	/*
	 * FIXME: We're supposed to wait for vblank here, but we have vblanks
	 * disabled during the mode set. The proper fix would be to push the
	 * rest of the setup into a vblank work item, queued here, but the
	 * infrastructure is not there yet.
	 */

	if (HAS_PCH_IBX(connector->dev)) {
		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		aud_config = IBX_AUD_CFG(pipe);
		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
	} else if (IS_VALLEYVIEW(connector->dev)) {
		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
		aud_config = VLV_AUD_CFG(pipe);
		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	} else {
		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		aud_config = CPT_AUD_CFG(pipe);
		aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	}

	if (WARN_ON(!port)) {
		eldv = IBX_ELD_VALIDB;
		eldv |= IBX_ELD_VALIDB << 4;
		eldv |= IBX_ELD_VALIDB << 8;
	} else {
		eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
	}

	/* Invalidate ELD */
	tmp = I915_READ(aud_cntrl_st2);
	tmp &= ~eldv;
	I915_WRITE(aud_cntrl_st2, tmp);

	/* Reset ELD write address */
	tmp = I915_READ(aud_cntl_st);
	tmp &= ~IBX_ELD_ADDRESS_MASK;
	I915_WRITE(aud_cntl_st, tmp);

	/* Up to 84 bytes of hw ELD buffer */
	len = min_t(int, eld[2], 21);
	for (i = 0; i < len; i++)
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

	/* ELD valid */
	tmp = I915_READ(aud_cntrl_st2);
	tmp |= eldv;
	I915_WRITE(aud_cntrl_st2, tmp);

	/* Enable timestamps */
	tmp = I915_READ(aud_config);
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	else
		tmp |= audio_config_hdmi_pixel_clock(mode);
	I915_WRITE(aud_config, tmp);
}

/**
 * intel_audio_codec_enable - Enable the audio codec for HD audio
 * @intel_encoder: encoder on which to enable audio
 *
 * The enable sequences may only be performed after enabling the transcoder and
 * port, and after completed link training.
 */
void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
{
	struct drm_encoder *encoder = &intel_encoder->base;
	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
	struct drm_display_mode *mode = &crtc->config.adjusted_mode;
	struct drm_connector *connector;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	connector = drm_select_eld(encoder, mode);
	if (!connector)
		return;

	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
			 connector->base.id,
			 connector->name,
			 connector->encoder->base.id,
			 connector->encoder->name);

	/* ELD Conn_Type */
	connector->eld[5] &= ~(3 << 2);
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
		connector->eld[5] |= (1 << 2);

	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;

	if (dev_priv->display.audio_codec_enable)
		dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
}

/**
 * intel_audio_codec_disable - Disable the audio codec for HD audio
 * @encoder: encoder on which to disable audio
 *
 * The disable sequences must be performed before disabling the transcoder or
 * port.
 */
void intel_audio_codec_disable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (dev_priv->display.audio_codec_disable)
		dev_priv->display.audio_codec_disable(encoder);
}

/**
 * intel_init_audio - Set up chip specific audio functions
 * @dev: drm device
 */
void intel_init_audio(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (IS_G4X(dev)) {
		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
	} else if (IS_VALLEYVIEW(dev)) {
		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
	} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
	} else if (HAS_PCH_SPLIT(dev)) {
		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
	}
}
Commit	Line	Data
7c10a2b5 JN	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*/
	23
	24	#include <linux/kernel.h>
	25
	26	#include <drm/drmP.h>
	27	#include <drm/drm_edid.h>
	28	#include "intel_drv.h"
	29	#include "i915_drv.h"
	30
87fcb2ad	31	static const struct {
7c10a2b5 JN	32	int clock;
	33	u32 config;
	34	} hdmi_audio_clock[] = {
	35	{ DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
	36	{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
	37	{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
	38	{ 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
	39	{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
	40	{ 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
	41	{ DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
	42	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
	43	{ DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
	44	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
	45	};
	46
	47	/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
	48	static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
	49	{
	50	int i;
	51
	52	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
	53	if (mode->clock == hdmi_audio_clock[i].clock)
	54	break;
	55	}
	56
	57	if (i == ARRAY_SIZE(hdmi_audio_clock)) {
	58	DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
	59	i = 1;
	60	}
	61
	62	DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
	63	hdmi_audio_clock[i].clock,
	64	hdmi_audio_clock[i].config);
	65
	66	return hdmi_audio_clock[i].config;
	67	}
	68
	69	static bool intel_eld_uptodate(struct drm_connector *connector,
	70	int reg_eldv, uint32_t bits_eldv,
	71	int reg_elda, uint32_t bits_elda,
	72	int reg_edid)
	73	{
	74	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	75	uint8_t *eld = connector->eld;
f9f682ae JN	76	uint32_t tmp;
f9f682ae JN	77	int i;
7c10a2b5	78
f9f682ae JN	79	tmp = I915_READ(reg_eldv);
f9f682ae JN	80	tmp &= bits_eldv;
7c10a2b5	81
f9f682ae	82	if (!tmp)
7c10a2b5 JN	83	return false;
7c10a2b5 JN	84
f9f682ae JN	85	tmp = I915_READ(reg_elda);
	86	tmp &= ~bits_elda;
	87	I915_WRITE(reg_elda, tmp);
7c10a2b5 JN	88
	89	for (i = 0; i < eld[2]; i++)
	90	if (I915_READ(reg_edid) != ((uint32_t )eld + i))
	91	return false;
	92
	93	return true;
	94	}
	95
69bfe1a9 JN	96	static void g4x_audio_codec_enable(struct drm_connector *connector,
	97	struct intel_encoder *encoder,
	98	struct drm_display_mode *mode)
7c10a2b5 JN	99	{
	100	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	101	uint8_t *eld = connector->eld;
	102	uint32_t eldv;
f9f682ae JN	103	uint32_t tmp;
f9f682ae JN	104	int len, i;
7c10a2b5	105
f9f682ae JN	106	tmp = I915_READ(G4X_AUD_VID_DID);
f9f682ae JN	107	if (tmp == INTEL_AUDIO_DEVBLC \|\| tmp == INTEL_AUDIO_DEVCL)
7c10a2b5 JN	108	eldv = G4X_ELDV_DEVCL_DEVBLC;
	109	else
	110	eldv = G4X_ELDV_DEVCTG;
	111
	112	if (intel_eld_uptodate(connector,
	113	G4X_AUD_CNTL_ST, eldv,
c46f111f	114	G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
7c10a2b5 JN	115	G4X_HDMIW_HDMIEDID))
	116	return;
	117
f9f682ae	118	tmp = I915_READ(G4X_AUD_CNTL_ST);
c46f111f	119	tmp &= ~(eldv \| G4X_ELD_ADDR_MASK);
f9f682ae JN	120	len = (tmp >> 9) & 0x1f; /* ELD buffer size */
f9f682ae JN	121	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
7c10a2b5	122
f9f682ae	123	len = min_t(int, eld[2], len);
7c10a2b5 JN	124	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	125	for (i = 0; i < len; i++)
	126	I915_WRITE(G4X_HDMIW_HDMIEDID, ((uint32_t )eld + i));
	127
f9f682ae JN	128	tmp = I915_READ(G4X_AUD_CNTL_ST);
	129	tmp \|= eldv;
	130	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
7c10a2b5 JN	131	}
7c10a2b5 JN	132
69bfe1a9 JN	133	static void hsw_audio_codec_disable(struct intel_encoder *encoder)
69bfe1a9 JN	134	{
5fad84a7 JN	135	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	136	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	137	enum pipe pipe = intel_crtc->pipe;
69bfe1a9 JN	138	uint32_t tmp;
69bfe1a9 JN	139
5fad84a7 JN	140	DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
	141
	142	/* Disable timestamps */
	143	tmp = I915_READ(HSW_AUD_CFG(pipe));
	144	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	145	tmp \|= AUD_CONFIG_N_PROG_ENABLE;
	146	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	147	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
	148	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
	149	tmp \|= AUD_CONFIG_N_VALUE_INDEX;
	150	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
	151
	152	/* Invalidate ELD */
69bfe1a9	153	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
5fad84a7	154	tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
69bfe1a9 JN	155	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
	156	}
	157
	158	static void hsw_audio_codec_enable(struct drm_connector *connector,
	159	struct intel_encoder *encoder,
	160	struct drm_display_mode *mode)
7c10a2b5 JN	161	{
7c10a2b5 JN	162	struct drm_i915_private *dev_priv = connector->dev->dev_private;
820d2d77	163	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
5fad84a7 JN	164	enum pipe pipe = intel_crtc->pipe;
5fad84a7 JN	165	const uint8_t *eld = connector->eld;
f9f682ae JN	166	uint32_t tmp;
f9f682ae JN	167	int len, i;
7c10a2b5	168
5fad84a7 JN	169	DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
5fad84a7 JN	170	pipe_name(pipe), eld[2]);
7c10a2b5	171
5fad84a7 JN	172	/* Enable audio presence detect, invalidate ELD */
	173	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
	174	tmp \|= AUDIO_OUTPUT_ENABLE_A << (pipe * 4);
	175	tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
	176	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
7c10a2b5	177
5fad84a7 JN	178	/*
	179	* FIXME: We're supposed to wait for vblank here, but we have vblanks
	180	* disabled during the mode set. The proper fix would be to push the
	181	* rest of the setup into a vblank work item, queued here, but the
	182	* infrastructure is not there yet.
	183	*/
7c10a2b5	184
5fad84a7 JN	185	/* Reset ELD write address */
5fad84a7 JN	186	tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
c46f111f	187	tmp &= ~IBX_ELD_ADDRESS_MASK;
5fad84a7	188	I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
7c10a2b5	189
5fad84a7 JN	190	/* Up to 84 bytes of hw ELD buffer */
5fad84a7 JN	191	len = min_t(int, eld[2], 21);
7c10a2b5	192	for (i = 0; i < len; i++)
5fad84a7	193	I915_WRITE(HSW_AUD_EDID_DATA(pipe), ((uint32_t )eld + i));
7c10a2b5	194
5fad84a7	195	/* ELD valid */
69bfe1a9	196	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
5fad84a7	197	tmp \|= AUDIO_ELD_VALID_A << (pipe * 4);
69bfe1a9	198	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
5fad84a7 JN	199
	200	/* Enable timestamps */
	201	tmp = I915_READ(HSW_AUD_CFG(pipe));
	202	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	203	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	204	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	205	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
	206	tmp \|= AUD_CONFIG_N_VALUE_INDEX;
	207	else
	208	tmp \|= audio_config_hdmi_pixel_clock(mode);
	209	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
7c10a2b5 JN	210	}
7c10a2b5 JN	211
495a5bb8 JN	212	static void ilk_audio_codec_disable(struct intel_encoder *encoder)
	213	{
	214	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	215	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	216	struct intel_digital_port *intel_dig_port =
	217	enc_to_dig_port(&encoder->base);
	218	enum port port = intel_dig_port->port;
	219	enum pipe pipe = intel_crtc->pipe;
	220	uint32_t tmp, eldv;
	221	int aud_config;
	222	int aud_cntrl_st2;
	223
	224	DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
	225	port_name(port), pipe_name(pipe));
	226
	227	if (HAS_PCH_IBX(dev_priv->dev)) {
	228	aud_config = IBX_AUD_CFG(pipe);
	229	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
	230	} else if (IS_VALLEYVIEW(dev_priv)) {
	231	aud_config = VLV_AUD_CFG(pipe);
	232	aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	233	} else {
	234	aud_config = CPT_AUD_CFG(pipe);
	235	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	236	}
	237
	238	/* Disable timestamps */
	239	tmp = I915_READ(aud_config);
	240	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	241	tmp \|= AUD_CONFIG_N_PROG_ENABLE;
	242	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	243	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
	244	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
	245	tmp \|= AUD_CONFIG_N_VALUE_INDEX;
	246	I915_WRITE(aud_config, tmp);
	247
	248	if (WARN_ON(!port)) {
	249	eldv = IBX_ELD_VALIDB;
	250	eldv \|= IBX_ELD_VALIDB << 4;
	251	eldv \|= IBX_ELD_VALIDB << 8;
	252	} else {
	253	eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
	254	}
	255
	256	/* Invalidate ELD */
	257	tmp = I915_READ(aud_cntrl_st2);
	258	tmp &= ~eldv;
	259	I915_WRITE(aud_cntrl_st2, tmp);
	260	}
	261
69bfe1a9 JN	262	static void ilk_audio_codec_enable(struct drm_connector *connector,
	263	struct intel_encoder *encoder,
	264	struct drm_display_mode *mode)
7c10a2b5 JN	265	{
7c10a2b5 JN	266	struct drm_i915_private *dev_priv = connector->dev->dev_private;
820d2d77	267	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
c6bde93b JN	268	struct intel_digital_port *intel_dig_port =
	269	enc_to_dig_port(&encoder->base);
	270	enum port port = intel_dig_port->port;
	271	enum pipe pipe = intel_crtc->pipe;
7c10a2b5 JN	272	uint8_t *eld = connector->eld;
7c10a2b5 JN	273	uint32_t eldv;
f9f682ae JN	274	uint32_t tmp;
f9f682ae JN	275	int len, i;
7c10a2b5 JN	276	int hdmiw_hdmiedid;
	277	int aud_config;
	278	int aud_cntl_st;
	279	int aud_cntrl_st2;
c6bde93b JN	280
	281	DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
	282	port_name(port), pipe_name(pipe), eld[2]);
	283
	284	/*
	285	* FIXME: We're supposed to wait for vblank here, but we have vblanks
	286	* disabled during the mode set. The proper fix would be to push the
	287	* rest of the setup into a vblank work item, queued here, but the
	288	* infrastructure is not there yet.
	289	*/
7c10a2b5 JN	290
	291	if (HAS_PCH_IBX(connector->dev)) {
	292	hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
	293	aud_config = IBX_AUD_CFG(pipe);
	294	aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
	295	aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
	296	} else if (IS_VALLEYVIEW(connector->dev)) {
	297	hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
	298	aud_config = VLV_AUD_CFG(pipe);
	299	aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
	300	aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	301	} else {
	302	hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
	303	aud_config = CPT_AUD_CFG(pipe);
	304	aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
	305	aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	306	}
	307
c6bde93b	308	if (WARN_ON(!port)) {
7c10a2b5 JN	309	eldv = IBX_ELD_VALIDB;
	310	eldv \|= IBX_ELD_VALIDB << 4;
	311	eldv \|= IBX_ELD_VALIDB << 8;
	312	} else {
f9f682ae	313	eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
7c10a2b5 JN	314	}
7c10a2b5 JN	315
c6bde93b	316	/* Invalidate ELD */
f9f682ae JN	317	tmp = I915_READ(aud_cntrl_st2);
	318	tmp &= ~eldv;
	319	I915_WRITE(aud_cntrl_st2, tmp);
7c10a2b5	320
c6bde93b	321	/* Reset ELD write address */
f9f682ae	322	tmp = I915_READ(aud_cntl_st);
c46f111f	323	tmp &= ~IBX_ELD_ADDRESS_MASK;
f9f682ae	324	I915_WRITE(aud_cntl_st, tmp);
7c10a2b5	325
c6bde93b JN	326	/* Up to 84 bytes of hw ELD buffer */
c6bde93b JN	327	len = min_t(int, eld[2], 21);
7c10a2b5 JN	328	for (i = 0; i < len; i++)
	329	I915_WRITE(hdmiw_hdmiedid, ((uint32_t )eld + i));
	330
c6bde93b	331	/* ELD valid */
f9f682ae JN	332	tmp = I915_READ(aud_cntrl_st2);
	333	tmp \|= eldv;
	334	I915_WRITE(aud_cntrl_st2, tmp);
c6bde93b JN	335
	336	/* Enable timestamps */
	337	tmp = I915_READ(aud_config);
	338	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	339	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	340	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	341	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
	342	tmp \|= AUD_CONFIG_N_VALUE_INDEX;
	343	else
	344	tmp \|= audio_config_hdmi_pixel_clock(mode);
	345	I915_WRITE(aud_config, tmp);
7c10a2b5 JN	346	}
7c10a2b5 JN	347
69bfe1a9 JN	348	/**
	349	* intel_audio_codec_enable - Enable the audio codec for HD audio
	350	* @intel_encoder: encoder on which to enable audio
	351	*
	352	* The enable sequences may only be performed after enabling the transcoder and
	353	* port, and after completed link training.
	354	*/
	355	void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
7c10a2b5	356	{
33d1e7c6 JN	357	struct drm_encoder *encoder = &intel_encoder->base;
	358	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
	359	struct drm_display_mode *mode = &crtc->config.adjusted_mode;
7c10a2b5 JN	360	struct drm_connector *connector;
	361	struct drm_device *dev = encoder->dev;
	362	struct drm_i915_private *dev_priv = dev->dev_private;
	363
	364	connector = drm_select_eld(encoder, mode);
	365	if (!connector)
	366	return;
	367
	368	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
	369	connector->base.id,
	370	connector->name,
	371	connector->encoder->base.id,
	372	connector->encoder->name);
	373
6189b036 JN	374	/* ELD Conn_Type */
	375	connector->eld[5] &= ~(3 << 2);
	376	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
	377	connector->eld[5] \|= (1 << 2);
	378
7c10a2b5 JN	379	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7c10a2b5 JN	380
69bfe1a9 JN	381	if (dev_priv->display.audio_codec_enable)
	382	dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
	383	}
	384
	385	/**
	386	* intel_audio_codec_disable - Disable the audio codec for HD audio
	387	* @encoder: encoder on which to disable audio
	388	*
	389	* The disable sequences must be performed before disabling the transcoder or
	390	* port.
	391	*/
	392	void intel_audio_codec_disable(struct intel_encoder *encoder)
	393	{
	394	struct drm_device *dev = encoder->base.dev;
	395	struct drm_i915_private *dev_priv = dev->dev_private;
	396
	397	if (dev_priv->display.audio_codec_disable)
	398	dev_priv->display.audio_codec_disable(encoder);
7c10a2b5 JN	399	}
	400
	401	/**
	402	* intel_init_audio - Set up chip specific audio functions
	403	* @dev: drm device
	404	*/
	405	void intel_init_audio(struct drm_device *dev)
	406	{
	407	struct drm_i915_private *dev_priv = dev->dev_private;
	408
69bfe1a9 JN	409	if (IS_G4X(dev)) {
	410	dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
	411	} else if (IS_VALLEYVIEW(dev)) {
	412	dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
495a5bb8	413	dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
69bfe1a9 JN	414	} else if (IS_HASWELL(dev) \|\| INTEL_INFO(dev)->gen >= 8) {
	415	dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
	416	dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
	417	} else if (HAS_PCH_SPLIT(dev)) {
	418	dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
495a5bb8	419	dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
69bfe1a9	420	}
7c10a2b5	421	}