drm/i915: Fix crash when failing to parse MIPI VBT
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_bios.c
CommitLineData
79e53945 1/*
39507259 2 * Copyright © 2006 Intel Corporation
79e53945
JB
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
25e341cf 27#include <linux/dmi.h>
9f0e7ff4 28#include <drm/drm_dp_helper.h>
760285e7
DH
29#include <drm/drmP.h>
30#include <drm/i915_drm.h>
79e53945
JB
31#include "i915_drv.h"
32#include "intel_bios.h"
33
9b9d172d 34#define SLAVE_ADDR1 0x70
35#define SLAVE_ADDR2 0x72
79e53945 36
500a8cc4
ZW
37static int panel_type;
38
79e53945
JB
39static void *
40find_section(struct bdb_header *bdb, int section_id)
41{
42 u8 *base = (u8 *)bdb;
43 int index = 0;
44 u16 total, current_size;
45 u8 current_id;
46
47 /* skip to first section */
48 index += bdb->header_size;
49 total = bdb->bdb_size;
50
51 /* walk the sections looking for section_id */
d1f13fd2 52 while (index + 3 < total) {
79e53945
JB
53 current_id = *(base + index);
54 index++;
d1f13fd2 55
79e53945
JB
56 current_size = *((u16 *)(base + index));
57 index += 2;
d1f13fd2
CW
58
59 if (index + current_size > total)
60 return NULL;
61
79e53945
JB
62 if (current_id == section_id)
63 return base + index;
d1f13fd2 64
79e53945
JB
65 index += current_size;
66 }
67
68 return NULL;
69}
70
db545019
DMEA
71static u16
72get_blocksize(void *p)
73{
74 u16 *block_ptr, block_size;
75
76 block_ptr = (u16 *)((char *)p - 2);
77 block_size = *block_ptr;
78 return block_size;
79}
80
79e53945 81static void
88631706 82fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
99834ea4 83 const struct lvds_dvo_timing *dvo_timing)
88631706
ML
84{
85 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
86 dvo_timing->hactive_lo;
87 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
88 ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
89 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
90 dvo_timing->hsync_pulse_width;
91 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
92 ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
93
94 panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
95 dvo_timing->vactive_lo;
96 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
97 dvo_timing->vsync_off;
98 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
99 dvo_timing->vsync_pulse_width;
100 panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
101 ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
102 panel_fixed_mode->clock = dvo_timing->clock * 10;
103 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
104
9bc35499
AJ
105 if (dvo_timing->hsync_positive)
106 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
107 else
108 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
109
110 if (dvo_timing->vsync_positive)
111 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
112 else
113 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
114
88631706
ML
115 /* Some VBTs have bogus h/vtotal values */
116 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
117 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
118 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
119 panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
120
121 drm_mode_set_name(panel_fixed_mode);
122}
123
99834ea4
CW
124static bool
125lvds_dvo_timing_equal_size(const struct lvds_dvo_timing *a,
126 const struct lvds_dvo_timing *b)
127{
128 if (a->hactive_hi != b->hactive_hi ||
129 a->hactive_lo != b->hactive_lo)
130 return false;
131
132 if (a->hsync_off_hi != b->hsync_off_hi ||
133 a->hsync_off_lo != b->hsync_off_lo)
134 return false;
135
136 if (a->hsync_pulse_width != b->hsync_pulse_width)
137 return false;
138
139 if (a->hblank_hi != b->hblank_hi ||
140 a->hblank_lo != b->hblank_lo)
141 return false;
142
143 if (a->vactive_hi != b->vactive_hi ||
144 a->vactive_lo != b->vactive_lo)
145 return false;
146
147 if (a->vsync_off != b->vsync_off)
148 return false;
149
150 if (a->vsync_pulse_width != b->vsync_pulse_width)
151 return false;
152
153 if (a->vblank_hi != b->vblank_hi ||
154 a->vblank_lo != b->vblank_lo)
155 return false;
156
157 return true;
158}
159
160static const struct lvds_dvo_timing *
161get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data,
162 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs,
163 int index)
164{
165 /*
166 * the size of fp_timing varies on the different platform.
167 * So calculate the DVO timing relative offset in LVDS data
168 * entry to get the DVO timing entry
169 */
170
171 int lfp_data_size =
172 lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset -
173 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
174 int dvo_timing_offset =
175 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
176 lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
177 char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index;
178
179 return (struct lvds_dvo_timing *)(entry + dvo_timing_offset);
180}
181
b0354385
TI
182/* get lvds_fp_timing entry
183 * this function may return NULL if the corresponding entry is invalid
184 */
185static const struct lvds_fp_timing *
186get_lvds_fp_timing(const struct bdb_header *bdb,
187 const struct bdb_lvds_lfp_data *data,
188 const struct bdb_lvds_lfp_data_ptrs *ptrs,
189 int index)
190{
191 size_t data_ofs = (const u8 *)data - (const u8 *)bdb;
192 u16 data_size = ((const u16 *)data)[-1]; /* stored in header */
193 size_t ofs;
194
195 if (index >= ARRAY_SIZE(ptrs->ptr))
196 return NULL;
197 ofs = ptrs->ptr[index].fp_timing_offset;
198 if (ofs < data_ofs ||
199 ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size)
200 return NULL;
201 return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
202}
203
88631706
ML
204/* Try to find integrated panel data */
205static void
206parse_lfp_panel_data(struct drm_i915_private *dev_priv,
207 struct bdb_header *bdb)
79e53945 208{
99834ea4
CW
209 const struct bdb_lvds_options *lvds_options;
210 const struct bdb_lvds_lfp_data *lvds_lfp_data;
211 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
212 const struct lvds_dvo_timing *panel_dvo_timing;
b0354385 213 const struct lvds_fp_timing *fp_timing;
79e53945 214 struct drm_display_mode *panel_fixed_mode;
83a7280e 215 int i, downclock, drrs_mode;
79e53945 216
79e53945
JB
217 lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
218 if (!lvds_options)
219 return;
220
41aa3448 221 dev_priv->vbt.lvds_dither = lvds_options->pixel_dither;
79e53945
JB
222 if (lvds_options->panel_type == 0xff)
223 return;
6a04002b 224
500a8cc4 225 panel_type = lvds_options->panel_type;
79e53945 226
83a7280e
PB
227 drrs_mode = (lvds_options->dps_panel_type_bits
228 >> (panel_type * 2)) & MODE_MASK;
229 /*
230 * VBT has static DRRS = 0 and seamless DRRS = 2.
231 * The below piece of code is required to adjust vbt.drrs_type
232 * to match the enum drrs_support_type.
233 */
234 switch (drrs_mode) {
235 case 0:
236 dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
237 DRM_DEBUG_KMS("DRRS supported mode is static\n");
238 break;
239 case 2:
240 dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
241 DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
242 break;
243 default:
244 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
245 DRM_DEBUG_KMS("DRRS not supported (VBT input)\n");
246 break;
247 }
248
79e53945
JB
249 lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
250 if (!lvds_lfp_data)
251 return;
252
1b16de0b
JB
253 lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
254 if (!lvds_lfp_data_ptrs)
255 return;
256
41aa3448 257 dev_priv->vbt.lvds_vbt = 1;
79e53945 258
99834ea4
CW
259 panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
260 lvds_lfp_data_ptrs,
261 lvds_options->panel_type);
79e53945 262
9a298b2a 263 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
6edc3242
CW
264 if (!panel_fixed_mode)
265 return;
79e53945 266
99834ea4 267 fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
79e53945 268
41aa3448 269 dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
79e53945 270
28c97730 271 DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");
88631706 272 drm_mode_debug_printmodeline(panel_fixed_mode);
37df9673 273
d1fcea6a 274 /*
99834ea4
CW
275 * Iterate over the LVDS panel timing info to find the lowest clock
276 * for the native resolution.
d1fcea6a 277 */
99834ea4 278 downclock = panel_dvo_timing->clock;
d1fcea6a 279 for (i = 0; i < 16; i++) {
99834ea4
CW
280 const struct lvds_dvo_timing *dvo_timing;
281
282 dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
283 lvds_lfp_data_ptrs,
284 i);
285 if (lvds_dvo_timing_equal_size(dvo_timing, panel_dvo_timing) &&
286 dvo_timing->clock < downclock)
287 downclock = dvo_timing->clock;
d1fcea6a 288 }
99834ea4 289
d330a953 290 if (downclock < panel_dvo_timing->clock && i915.lvds_downclock) {
d1fcea6a 291 dev_priv->lvds_downclock_avail = 1;
99834ea4 292 dev_priv->lvds_downclock = downclock * 10;
bbb0aef5
JP
293 DRM_DEBUG_KMS("LVDS downclock is found in VBT. "
294 "Normal Clock %dKHz, downclock %dKHz\n",
99834ea4 295 panel_fixed_mode->clock, 10*downclock);
d1fcea6a 296 }
b0354385
TI
297
298 fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data,
299 lvds_lfp_data_ptrs,
300 lvds_options->panel_type);
301 if (fp_timing) {
302 /* check the resolution, just to be sure */
303 if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
304 fp_timing->y_res == panel_fixed_mode->vdisplay) {
41aa3448 305 dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val;
b0354385 306 DRM_DEBUG_KMS("VBT initial LVDS value %x\n",
41aa3448 307 dev_priv->vbt.bios_lvds_val);
b0354385
TI
308 }
309 }
88631706
ML
310}
311
f00076d2
JN
312static void
313parse_lfp_backlight(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
314{
315 const struct bdb_lfp_backlight_data *backlight_data;
316 const struct bdb_lfp_backlight_data_entry *entry;
317
318 backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
319 if (!backlight_data)
320 return;
321
322 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) {
323 DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n",
324 backlight_data->entry_size);
325 return;
326 }
327
328 entry = &backlight_data->data[panel_type];
329
39fbc9c8
JN
330 dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
331 if (!dev_priv->vbt.backlight.present) {
332 DRM_DEBUG_KMS("PWM backlight not present in VBT (type %u)\n",
333 entry->type);
334 return;
335 }
336
f00076d2
JN
337 dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
338 dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
1de6068e 339 dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
f00076d2
JN
340 DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, "
341 "active %s, min brightness %u, level %u\n",
342 dev_priv->vbt.backlight.pwm_freq_hz,
343 dev_priv->vbt.backlight.active_low_pwm ? "low" : "high",
1de6068e 344 dev_priv->vbt.backlight.min_brightness,
f00076d2
JN
345 backlight_data->level[panel_type]);
346}
347
88631706
ML
348/* Try to find sdvo panel data */
349static void
350parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
351 struct bdb_header *bdb)
352{
88631706
ML
353 struct lvds_dvo_timing *dvo_timing;
354 struct drm_display_mode *panel_fixed_mode;
5a1e5b6c 355 int index;
79e53945 356
d330a953 357 index = i915.vbt_sdvo_panel_type;
c10e408a
MF
358 if (index == -2) {
359 DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n");
360 return;
361 }
362
5a1e5b6c
CW
363 if (index == -1) {
364 struct bdb_sdvo_lvds_options *sdvo_lvds_options;
365
366 sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
367 if (!sdvo_lvds_options)
368 return;
369
370 index = sdvo_lvds_options->panel_type;
371 }
88631706
ML
372
373 dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);
374 if (!dvo_timing)
375 return;
376
9a298b2a 377 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
88631706
ML
378 if (!panel_fixed_mode)
379 return;
380
5a1e5b6c 381 fill_detail_timing_data(panel_fixed_mode, dvo_timing + index);
88631706 382
41aa3448 383 dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
79e53945 384
5a1e5b6c
CW
385 DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n");
386 drm_mode_debug_printmodeline(panel_fixed_mode);
79e53945
JB
387}
388
9a4114ff
BF
389static int intel_bios_ssc_frequency(struct drm_device *dev,
390 bool alternate)
391{
392 switch (INTEL_INFO(dev)->gen) {
393 case 2:
e91e941b 394 return alternate ? 66667 : 48000;
9a4114ff
BF
395 case 3:
396 case 4:
e91e941b 397 return alternate ? 100000 : 96000;
9a4114ff 398 default:
e91e941b 399 return alternate ? 100000 : 120000;
9a4114ff
BF
400 }
401}
402
79e53945
JB
403static void
404parse_general_features(struct drm_i915_private *dev_priv,
405 struct bdb_header *bdb)
406{
bad720ff 407 struct drm_device *dev = dev_priv->dev;
79e53945
JB
408 struct bdb_general_features *general;
409
79e53945
JB
410 general = find_section(bdb, BDB_GENERAL_FEATURES);
411 if (general) {
41aa3448
RV
412 dev_priv->vbt.int_tv_support = general->int_tv_support;
413 dev_priv->vbt.int_crt_support = general->int_crt_support;
414 dev_priv->vbt.lvds_use_ssc = general->enable_ssc;
415 dev_priv->vbt.lvds_ssc_freq =
9a4114ff 416 intel_bios_ssc_frequency(dev, general->ssc_freq);
41aa3448
RV
417 dev_priv->vbt.display_clock_mode = general->display_clock_mode;
418 dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
3f704fa2 419 DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
41aa3448
RV
420 dev_priv->vbt.int_tv_support,
421 dev_priv->vbt.int_crt_support,
422 dev_priv->vbt.lvds_use_ssc,
423 dev_priv->vbt.lvds_ssc_freq,
424 dev_priv->vbt.display_clock_mode,
425 dev_priv->vbt.fdi_rx_polarity_inverted);
79e53945
JB
426 }
427}
428
db545019
DMEA
429static void
430parse_general_definitions(struct drm_i915_private *dev_priv,
431 struct bdb_header *bdb)
432{
433 struct bdb_general_definitions *general;
db545019 434
db545019
DMEA
435 general = find_section(bdb, BDB_GENERAL_DEFINITIONS);
436 if (general) {
437 u16 block_size = get_blocksize(general);
438 if (block_size >= sizeof(*general)) {
439 int bus_pin = general->crt_ddc_gmbus_pin;
28c97730 440 DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
3bd7d909 441 if (intel_gmbus_is_port_valid(bus_pin))
41aa3448 442 dev_priv->vbt.crt_ddc_pin = bus_pin;
db545019 443 } else {
28c97730 444 DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n",
3bd7d909 445 block_size);
db545019
DMEA
446 }
447 }
448}
449
9b9d172d 450static void
451parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
44834a67 452 struct bdb_header *bdb)
9b9d172d 453{
454 struct sdvo_device_mapping *p_mapping;
455 struct bdb_general_definitions *p_defs;
768f69c9 456 union child_device_config *p_child;
9b9d172d 457 int i, child_device_num, count;
db545019 458 u16 block_size;
9b9d172d 459
460 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
461 if (!p_defs) {
44834a67 462 DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n");
9b9d172d 463 return;
464 }
465 /* judge whether the size of child device meets the requirements.
466 * If the child device size obtained from general definition block
467 * is different with sizeof(struct child_device_config), skip the
468 * parsing of sdvo device info
469 */
470 if (p_defs->child_dev_size != sizeof(*p_child)) {
471 /* different child dev size . Ignore it */
28c97730 472 DRM_DEBUG_KMS("different child size is found. Invalid.\n");
9b9d172d 473 return;
474 }
475 /* get the block size of general definitions */
db545019 476 block_size = get_blocksize(p_defs);
9b9d172d 477 /* get the number of child device */
478 child_device_num = (block_size - sizeof(*p_defs)) /
479 sizeof(*p_child);
480 count = 0;
481 for (i = 0; i < child_device_num; i++) {
482 p_child = &(p_defs->devices[i]);
768f69c9 483 if (!p_child->old.device_type) {
9b9d172d 484 /* skip the device block if device type is invalid */
485 continue;
486 }
768f69c9
PZ
487 if (p_child->old.slave_addr != SLAVE_ADDR1 &&
488 p_child->old.slave_addr != SLAVE_ADDR2) {
9b9d172d 489 /*
490 * If the slave address is neither 0x70 nor 0x72,
491 * it is not a SDVO device. Skip it.
492 */
493 continue;
494 }
768f69c9
PZ
495 if (p_child->old.dvo_port != DEVICE_PORT_DVOB &&
496 p_child->old.dvo_port != DEVICE_PORT_DVOC) {
9b9d172d 497 /* skip the incorrect SDVO port */
0206e353 498 DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n");
9b9d172d 499 continue;
500 }
28c97730
ZY
501 DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
502 " %s port\n",
768f69c9
PZ
503 p_child->old.slave_addr,
504 (p_child->old.dvo_port == DEVICE_PORT_DVOB) ?
9b9d172d 505 "SDVOB" : "SDVOC");
768f69c9 506 p_mapping = &(dev_priv->sdvo_mappings[p_child->old.dvo_port - 1]);
9b9d172d 507 if (!p_mapping->initialized) {
768f69c9
PZ
508 p_mapping->dvo_port = p_child->old.dvo_port;
509 p_mapping->slave_addr = p_child->old.slave_addr;
510 p_mapping->dvo_wiring = p_child->old.dvo_wiring;
511 p_mapping->ddc_pin = p_child->old.ddc_pin;
512 p_mapping->i2c_pin = p_child->old.i2c_pin;
9b9d172d 513 p_mapping->initialized = 1;
46eb3036 514 DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",
e957d772
CW
515 p_mapping->dvo_port,
516 p_mapping->slave_addr,
517 p_mapping->dvo_wiring,
518 p_mapping->ddc_pin,
46eb3036 519 p_mapping->i2c_pin);
9b9d172d 520 } else {
28c97730 521 DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
9b9d172d 522 "two SDVO device.\n");
523 }
768f69c9 524 if (p_child->old.slave2_addr) {
9b9d172d 525 /* Maybe this is a SDVO device with multiple inputs */
526 /* And the mapping info is not added */
28c97730
ZY
527 DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"
528 " is a SDVO device with multiple inputs.\n");
9b9d172d 529 }
530 count++;
531 }
532
533 if (!count) {
534 /* No SDVO device info is found */
28c97730 535 DRM_DEBUG_KMS("No SDVO device info is found in VBT\n");
9b9d172d 536 }
537 return;
538}
32f9d658
ZW
539
540static void
541parse_driver_features(struct drm_i915_private *dev_priv,
542 struct bdb_header *bdb)
543{
32f9d658
ZW
544 struct bdb_driver_features *driver;
545
32f9d658 546 driver = find_section(bdb, BDB_DRIVER_FEATURES);
652c393a
JB
547 if (!driver)
548 return;
549
6fca55b1 550 if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
41aa3448 551 dev_priv->vbt.edp_support = 1;
652c393a 552
5ceb0f9b 553 if (driver->dual_frequency)
652c393a 554 dev_priv->render_reclock_avail = true;
83a7280e
PB
555
556 DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
557 /*
558 * If DRRS is not supported, drrs_type has to be set to 0.
559 * This is because, VBT is configured in such a way that
560 * static DRRS is 0 and DRRS not supported is represented by
561 * driver->drrs_enabled=false
562 */
563 if (!driver->drrs_enabled)
564 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
32f9d658
ZW
565}
566
500a8cc4
ZW
567static void
568parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
569{
570 struct bdb_edp *edp;
9f0e7ff4
JB
571 struct edp_power_seq *edp_pps;
572 struct edp_link_params *edp_link_params;
500a8cc4
ZW
573
574 edp = find_section(bdb, BDB_EDP);
575 if (!edp) {
6fca55b1 576 if (dev_priv->vbt.edp_support)
9a30a61f 577 DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported.\n");
500a8cc4
ZW
578 return;
579 }
580
581 switch ((edp->color_depth >> (panel_type * 2)) & 3) {
582 case EDP_18BPP:
41aa3448 583 dev_priv->vbt.edp_bpp = 18;
500a8cc4
ZW
584 break;
585 case EDP_24BPP:
41aa3448 586 dev_priv->vbt.edp_bpp = 24;
500a8cc4
ZW
587 break;
588 case EDP_30BPP:
41aa3448 589 dev_priv->vbt.edp_bpp = 30;
500a8cc4
ZW
590 break;
591 }
5ceb0f9b 592
9f0e7ff4
JB
593 /* Get the eDP sequencing and link info */
594 edp_pps = &edp->power_seqs[panel_type];
595 edp_link_params = &edp->link_params[panel_type];
5ceb0f9b 596
41aa3448 597 dev_priv->vbt.edp_pps = *edp_pps;
5ceb0f9b 598
e13e2b2c
JN
599 switch (edp_link_params->rate) {
600 case EDP_RATE_1_62:
601 dev_priv->vbt.edp_rate = DP_LINK_BW_1_62;
602 break;
603 case EDP_RATE_2_7:
604 dev_priv->vbt.edp_rate = DP_LINK_BW_2_7;
605 break;
606 default:
607 DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n",
608 edp_link_params->rate);
609 break;
610 }
611
9f0e7ff4 612 switch (edp_link_params->lanes) {
e13e2b2c 613 case EDP_LANE_1:
41aa3448 614 dev_priv->vbt.edp_lanes = 1;
9f0e7ff4 615 break;
e13e2b2c 616 case EDP_LANE_2:
41aa3448 617 dev_priv->vbt.edp_lanes = 2;
9f0e7ff4 618 break;
e13e2b2c 619 case EDP_LANE_4:
41aa3448 620 dev_priv->vbt.edp_lanes = 4;
9f0e7ff4 621 break;
e13e2b2c
JN
622 default:
623 DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n",
624 edp_link_params->lanes);
625 break;
9f0e7ff4 626 }
e13e2b2c 627
9f0e7ff4 628 switch (edp_link_params->preemphasis) {
e13e2b2c 629 case EDP_PREEMPHASIS_NONE:
41aa3448 630 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_0;
9f0e7ff4 631 break;
e13e2b2c 632 case EDP_PREEMPHASIS_3_5dB:
41aa3448 633 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5;
9f0e7ff4 634 break;
e13e2b2c 635 case EDP_PREEMPHASIS_6dB:
41aa3448 636 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_6;
9f0e7ff4 637 break;
e13e2b2c 638 case EDP_PREEMPHASIS_9_5dB:
41aa3448 639 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5;
9f0e7ff4 640 break;
e13e2b2c
JN
641 default:
642 DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
643 edp_link_params->preemphasis);
644 break;
9f0e7ff4 645 }
e13e2b2c 646
9f0e7ff4 647 switch (edp_link_params->vswing) {
e13e2b2c 648 case EDP_VSWING_0_4V:
41aa3448 649 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_400;
9f0e7ff4 650 break;
e13e2b2c 651 case EDP_VSWING_0_6V:
41aa3448 652 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_600;
9f0e7ff4 653 break;
e13e2b2c 654 case EDP_VSWING_0_8V:
41aa3448 655 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_800;
9f0e7ff4 656 break;
e13e2b2c 657 case EDP_VSWING_1_2V:
41aa3448 658 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_1200;
9f0e7ff4 659 break;
e13e2b2c
JN
660 default:
661 DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
662 edp_link_params->vswing);
663 break;
9f0e7ff4 664 }
500a8cc4
ZW
665}
666
d3b542fc
SK
667static u8 *goto_next_sequence(u8 *data, int *size)
668{
669 u16 len;
670 int tmp = *size;
671
672 if (--tmp < 0)
673 return NULL;
674
675 /* goto first element */
676 data++;
677 while (1) {
678 switch (*data) {
679 case MIPI_SEQ_ELEM_SEND_PKT:
680 /*
681 * skip by this element payload size
682 * skip elem id, command flag and data type
683 */
b0256cdc
SK
684 tmp -= 5;
685 if (tmp < 0)
d3b542fc
SK
686 return NULL;
687
688 data += 3;
689 len = *((u16 *)data);
690
b0256cdc
SK
691 tmp -= len;
692 if (tmp < 0)
d3b542fc
SK
693 return NULL;
694
695 /* skip by len */
696 data = data + 2 + len;
697 break;
698 case MIPI_SEQ_ELEM_DELAY:
699 /* skip by elem id, and delay is 4 bytes */
b0256cdc
SK
700 tmp -= 5;
701 if (tmp < 0)
d3b542fc
SK
702 return NULL;
703
704 data += 5;
705 break;
706 case MIPI_SEQ_ELEM_GPIO:
b0256cdc
SK
707 tmp -= 3;
708 if (tmp < 0)
d3b542fc
SK
709 return NULL;
710
711 data += 3;
712 break;
713 default:
714 DRM_ERROR("Unknown element\n");
715 return NULL;
716 }
717
718 /* end of sequence ? */
719 if (*data == 0)
720 break;
721 }
722
723 /* goto next sequence or end of block byte */
724 if (--tmp < 0)
725 return NULL;
726
727 data++;
728
729 /* update amount of data left for the sequence block to be parsed */
730 *size = tmp;
731 return data;
732}
733
d17c5443
SK
734static void
735parse_mipi(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
736{
d3b542fc
SK
737 struct bdb_mipi_config *start;
738 struct bdb_mipi_sequence *sequence;
739 struct mipi_config *config;
740 struct mipi_pps_data *pps;
741 u8 *data, *seq_data;
742 int i, panel_id, seq_size;
743 u16 block_size;
744
3e6bd011
SK
745 /* parse MIPI blocks only if LFP type is MIPI */
746 if (!dev_priv->vbt.has_mipi)
747 return;
748
d3b542fc
SK
749 /* Initialize this to undefined indicating no generic MIPI support */
750 dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
751
752 /* Block #40 is already parsed and panel_fixed_mode is
753 * stored in dev_priv->lfp_lvds_vbt_mode
754 * resuse this when needed
755 */
d17c5443 756
d3b542fc
SK
757 /* Parse #52 for panel index used from panel_type already
758 * parsed
759 */
760 start = find_section(bdb, BDB_MIPI_CONFIG);
761 if (!start) {
762 DRM_DEBUG_KMS("No MIPI config BDB found");
d17c5443
SK
763 return;
764 }
765
d3b542fc
SK
766 DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n",
767 panel_type);
768
769 /*
770 * get hold of the correct configuration block and pps data as per
771 * the panel_type as index
772 */
773 config = &start->config[panel_type];
774 pps = &start->pps[panel_type];
775
776 /* store as of now full data. Trim when we realise all is not needed */
777 dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
778 if (!dev_priv->vbt.dsi.config)
779 return;
780
781 dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
782 if (!dev_priv->vbt.dsi.pps) {
783 kfree(dev_priv->vbt.dsi.config);
784 return;
785 }
786
787 /* We have mandatory mipi config blocks. Initialize as generic panel */
ea9a6baf 788 dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
d3b542fc
SK
789
790 /* Check if we have sequence block as well */
791 sequence = find_section(bdb, BDB_MIPI_SEQUENCE);
792 if (!sequence) {
793 DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n");
794 return;
795 }
796
797 DRM_DEBUG_DRIVER("Found MIPI sequence block\n");
798
799 block_size = get_blocksize(sequence);
800
801 /*
802 * parse the sequence block for individual sequences
803 */
804 dev_priv->vbt.dsi.seq_version = sequence->version;
805
806 seq_data = &sequence->data[0];
807
808 /*
809 * sequence block is variable length and hence we need to parse and
810 * get the sequence data for specific panel id
811 */
812 for (i = 0; i < MAX_MIPI_CONFIGURATIONS; i++) {
813 panel_id = *seq_data;
814 seq_size = *((u16 *) (seq_data + 1));
815 if (panel_id == panel_type)
816 break;
817
818 /* skip the sequence including seq header of 3 bytes */
819 seq_data = seq_data + 3 + seq_size;
820 if ((seq_data - &sequence->data[0]) > block_size) {
821 DRM_ERROR("Sequence start is beyond sequence block size, corrupted sequence block\n");
822 return;
823 }
824 }
825
826 if (i == MAX_MIPI_CONFIGURATIONS) {
827 DRM_ERROR("Sequence block detected but no valid configuration\n");
828 return;
829 }
830
831 /* check if found sequence is completely within the sequence block
832 * just being paranoid */
833 if (seq_size > block_size) {
834 DRM_ERROR("Corrupted sequence/size, bailing out\n");
835 return;
836 }
837
838 /* skip the panel id(1 byte) and seq size(2 bytes) */
839 dev_priv->vbt.dsi.data = kmemdup(seq_data + 3, seq_size, GFP_KERNEL);
840 if (!dev_priv->vbt.dsi.data)
841 return;
842
843 /*
844 * loop into the sequence data and split into multiple sequneces
845 * There are only 5 types of sequences as of now
846 */
847 data = dev_priv->vbt.dsi.data;
848 dev_priv->vbt.dsi.size = seq_size;
849
850 /* two consecutive 0x00 indicate end of all sequences */
851 while (1) {
852 int seq_id = *data;
853 if (MIPI_SEQ_MAX > seq_id && seq_id > MIPI_SEQ_UNDEFINED) {
854 dev_priv->vbt.dsi.sequence[seq_id] = data;
855 DRM_DEBUG_DRIVER("Found mipi sequence - %d\n", seq_id);
856 } else {
857 DRM_ERROR("undefined sequence\n");
858 goto err;
859 }
860
861 /* partial parsing to skip elements */
862 data = goto_next_sequence(data, &seq_size);
863
864 if (data == NULL) {
865 DRM_ERROR("Sequence elements going beyond block itself. Sequence block parsing failed\n");
866 goto err;
867 }
868
869 if (*data == 0)
870 break; /* end of sequence reached */
871 }
872
873 DRM_DEBUG_DRIVER("MIPI related vbt parsing complete\n");
874 return;
875err:
876 kfree(dev_priv->vbt.dsi.data);
877 dev_priv->vbt.dsi.data = NULL;
878
879 /* error during parsing so set all pointers to null
880 * because of partial parsing */
ed3b6679 881 memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence));
d17c5443
SK
882}
883
6acab15a
PZ
884static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
885 struct bdb_header *bdb)
886{
887 union child_device_config *it, *child = NULL;
888 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
889 uint8_t hdmi_level_shift;
890 int i, j;
554d6af5 891 bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
6bf19e7c 892 uint8_t aux_channel;
6acab15a
PZ
893 /* Each DDI port can have more than one value on the "DVO Port" field,
894 * so look for all the possible values for each port and abort if more
895 * than one is found. */
896 int dvo_ports[][2] = {
897 {DVO_PORT_HDMIA, DVO_PORT_DPA},
898 {DVO_PORT_HDMIB, DVO_PORT_DPB},
899 {DVO_PORT_HDMIC, DVO_PORT_DPC},
900 {DVO_PORT_HDMID, DVO_PORT_DPD},
901 {DVO_PORT_CRT, -1 /* Port E can only be DVO_PORT_CRT */ },
902 };
903
904 /* Find the child device to use, abort if more than one found. */
905 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
906 it = dev_priv->vbt.child_dev + i;
907
908 for (j = 0; j < 2; j++) {
909 if (dvo_ports[port][j] == -1)
910 break;
911
912 if (it->common.dvo_port == dvo_ports[port][j]) {
913 if (child) {
914 DRM_DEBUG_KMS("More than one child device for port %c in VBT.\n",
915 port_name(port));
916 return;
917 }
918 child = it;
919 }
920 }
921 }
922 if (!child)
923 return;
924
6bf19e7c
PZ
925 aux_channel = child->raw[25];
926
78eb06c3
VS
927 is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
928 is_dp = child->common.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
929 is_crt = child->common.device_type & DEVICE_TYPE_ANALOG_OUTPUT;
930 is_hdmi = is_dvi && (child->common.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
931 is_edp = is_dp && (child->common.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
554d6af5 932
311a2094
PZ
933 info->supports_dvi = is_dvi;
934 info->supports_hdmi = is_hdmi;
935 info->supports_dp = is_dp;
936
554d6af5
PZ
937 DRM_DEBUG_KMS("Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d\n",
938 port_name(port), is_dp, is_hdmi, is_dvi, is_edp, is_crt);
939
940 if (is_edp && is_dvi)
941 DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n",
942 port_name(port));
943 if (is_crt && port != PORT_E)
944 DRM_DEBUG_KMS("Port %c is analog\n", port_name(port));
945 if (is_crt && (is_dvi || is_dp))
946 DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n",
947 port_name(port));
948 if (is_dvi && (port == PORT_A || port == PORT_E))
949 DRM_DEBUG_KMS("Port %c is TMDS compabile\n", port_name(port));
950 if (!is_dvi && !is_dp && !is_crt)
951 DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n",
952 port_name(port));
953 if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E))
954 DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port));
6bf19e7c
PZ
955
956 if (is_dvi) {
957 if (child->common.ddc_pin == 0x05 && port != PORT_B)
958 DRM_DEBUG_KMS("Unexpected DDC pin for port B\n");
959 if (child->common.ddc_pin == 0x04 && port != PORT_C)
960 DRM_DEBUG_KMS("Unexpected DDC pin for port C\n");
961 if (child->common.ddc_pin == 0x06 && port != PORT_D)
962 DRM_DEBUG_KMS("Unexpected DDC pin for port D\n");
963 }
964
965 if (is_dp) {
966 if (aux_channel == 0x40 && port != PORT_A)
967 DRM_DEBUG_KMS("Unexpected AUX channel for port A\n");
968 if (aux_channel == 0x10 && port != PORT_B)
969 DRM_DEBUG_KMS("Unexpected AUX channel for port B\n");
970 if (aux_channel == 0x20 && port != PORT_C)
971 DRM_DEBUG_KMS("Unexpected AUX channel for port C\n");
972 if (aux_channel == 0x30 && port != PORT_D)
973 DRM_DEBUG_KMS("Unexpected AUX channel for port D\n");
974 }
975
6acab15a
PZ
976 if (bdb->version >= 158) {
977 /* The VBT HDMI level shift values match the table we have. */
978 hdmi_level_shift = child->raw[7] & 0xF;
979 if (hdmi_level_shift < 0xC) {
980 DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
981 port_name(port),
982 hdmi_level_shift);
983 info->hdmi_level_shift = hdmi_level_shift;
984 }
985 }
986}
987
988static void parse_ddi_ports(struct drm_i915_private *dev_priv,
989 struct bdb_header *bdb)
990{
991 struct drm_device *dev = dev_priv->dev;
992 enum port port;
993
994 if (!HAS_DDI(dev))
995 return;
996
997 if (!dev_priv->vbt.child_dev_num)
998 return;
999
1000 if (bdb->version < 155)
1001 return;
1002
1003 for (port = PORT_A; port < I915_MAX_PORTS; port++)
1004 parse_ddi_port(dev_priv, port, bdb);
1005}
1006
6363ee6f
ZY
1007static void
1008parse_device_mapping(struct drm_i915_private *dev_priv,
1009 struct bdb_header *bdb)
1010{
1011 struct bdb_general_definitions *p_defs;
768f69c9 1012 union child_device_config *p_child, *child_dev_ptr;
6363ee6f
ZY
1013 int i, child_device_num, count;
1014 u16 block_size;
1015
1016 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
1017 if (!p_defs) {
44834a67 1018 DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
6363ee6f
ZY
1019 return;
1020 }
1021 /* judge whether the size of child device meets the requirements.
1022 * If the child device size obtained from general definition block
1023 * is different with sizeof(struct child_device_config), skip the
1024 * parsing of sdvo device info
1025 */
1026 if (p_defs->child_dev_size != sizeof(*p_child)) {
1027 /* different child dev size . Ignore it */
1028 DRM_DEBUG_KMS("different child size is found. Invalid.\n");
1029 return;
1030 }
1031 /* get the block size of general definitions */
1032 block_size = get_blocksize(p_defs);
1033 /* get the number of child device */
1034 child_device_num = (block_size - sizeof(*p_defs)) /
1035 sizeof(*p_child);
1036 count = 0;
1037 /* get the number of child device that is present */
1038 for (i = 0; i < child_device_num; i++) {
1039 p_child = &(p_defs->devices[i]);
768f69c9 1040 if (!p_child->common.device_type) {
6363ee6f
ZY
1041 /* skip the device block if device type is invalid */
1042 continue;
1043 }
1044 count++;
1045 }
1046 if (!count) {
0206e353 1047 DRM_DEBUG_KMS("no child dev is parsed from VBT\n");
6363ee6f
ZY
1048 return;
1049 }
41aa3448
RV
1050 dev_priv->vbt.child_dev = kcalloc(count, sizeof(*p_child), GFP_KERNEL);
1051 if (!dev_priv->vbt.child_dev) {
6363ee6f
ZY
1052 DRM_DEBUG_KMS("No memory space for child device\n");
1053 return;
1054 }
1055
41aa3448 1056 dev_priv->vbt.child_dev_num = count;
6363ee6f
ZY
1057 count = 0;
1058 for (i = 0; i < child_device_num; i++) {
1059 p_child = &(p_defs->devices[i]);
768f69c9 1060 if (!p_child->common.device_type) {
6363ee6f
ZY
1061 /* skip the device block if device type is invalid */
1062 continue;
1063 }
3e6bd011
SK
1064
1065 if (p_child->common.dvo_port >= DVO_PORT_MIPIA
1066 && p_child->common.dvo_port <= DVO_PORT_MIPID
1067 &&p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT) {
1068 DRM_DEBUG_KMS("Found MIPI as LFP\n");
1069 dev_priv->vbt.has_mipi = 1;
1070 dev_priv->vbt.dsi.port = p_child->common.dvo_port;
1071 }
1072
41aa3448 1073 child_dev_ptr = dev_priv->vbt.child_dev + count;
6363ee6f
ZY
1074 count++;
1075 memcpy((void *)child_dev_ptr, (void *)p_child,
1076 sizeof(*p_child));
1077 }
1078 return;
1079}
44834a67 1080
6a04002b
SQ
1081static void
1082init_vbt_defaults(struct drm_i915_private *dev_priv)
1083{
9a4114ff 1084 struct drm_device *dev = dev_priv->dev;
6acab15a 1085 enum port port;
9a4114ff 1086
41aa3448 1087 dev_priv->vbt.crt_ddc_pin = GMBUS_PORT_VGADDC;
6a04002b 1088
56c4b63a
JN
1089 /* Default to having backlight */
1090 dev_priv->vbt.backlight.present = true;
1091
6a04002b 1092 /* LFP panel data */
41aa3448
RV
1093 dev_priv->vbt.lvds_dither = 1;
1094 dev_priv->vbt.lvds_vbt = 0;
6a04002b
SQ
1095
1096 /* SDVO panel data */
41aa3448 1097 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
6a04002b
SQ
1098
1099 /* general features */
41aa3448
RV
1100 dev_priv->vbt.int_tv_support = 1;
1101 dev_priv->vbt.int_crt_support = 1;
9a4114ff
BF
1102
1103 /* Default to using SSC */
41aa3448 1104 dev_priv->vbt.lvds_use_ssc = 1;
f69e5156
DL
1105 /*
1106 * Core/SandyBridge/IvyBridge use alternative (120MHz) reference
1107 * clock for LVDS.
1108 */
1109 dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev,
1110 !HAS_PCH_SPLIT(dev));
e91e941b 1111 DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq);
6acab15a
PZ
1112
1113 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
311a2094
PZ
1114 struct ddi_vbt_port_info *info =
1115 &dev_priv->vbt.ddi_port_info[port];
1116
6acab15a 1117 /* Recommended BSpec default: 800mV 0dB. */
311a2094
PZ
1118 info->hdmi_level_shift = 6;
1119
1120 info->supports_dvi = (port != PORT_A && port != PORT_E);
1121 info->supports_hdmi = info->supports_dvi;
1122 info->supports_dp = (port != PORT_E);
6acab15a 1123 }
6a04002b
SQ
1124}
1125
25e341cf
DV
1126static int __init intel_no_opregion_vbt_callback(const struct dmi_system_id *id)
1127{
1128 DRM_DEBUG_KMS("Falling back to manually reading VBT from "
1129 "VBIOS ROM for %s\n",
1130 id->ident);
1131 return 1;
1132}
1133
1134static const struct dmi_system_id intel_no_opregion_vbt[] = {
1135 {
1136 .callback = intel_no_opregion_vbt_callback,
1137 .ident = "ThinkCentre A57",
1138 .matches = {
1139 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1140 DMI_MATCH(DMI_PRODUCT_NAME, "97027RG"),
1141 },
1142 },
1143 { }
1144};
1145
3dd4e846
CW
1146static struct bdb_header *validate_vbt(char *base, size_t size,
1147 struct vbt_header *vbt,
1148 const char *source)
1149{
1150 size_t offset;
1151 struct bdb_header *bdb;
1152
1153 if (vbt == NULL) {
1154 DRM_DEBUG_DRIVER("VBT signature missing\n");
1155 return NULL;
1156 }
1157
1158 offset = (char *)vbt - base;
1159 if (offset + sizeof(struct vbt_header) > size) {
1160 DRM_DEBUG_DRIVER("VBT header incomplete\n");
1161 return NULL;
1162 }
1163
1164 if (memcmp(vbt->signature, "$VBT", 4)) {
1165 DRM_DEBUG_DRIVER("VBT invalid signature\n");
1166 return NULL;
1167 }
1168
1169 offset += vbt->bdb_offset;
1170 if (offset + sizeof(struct bdb_header) > size) {
1171 DRM_DEBUG_DRIVER("BDB header incomplete\n");
1172 return NULL;
1173 }
1174
1175 bdb = (struct bdb_header *)(base + offset);
1176 if (offset + bdb->bdb_size > size) {
1177 DRM_DEBUG_DRIVER("BDB incomplete\n");
1178 return NULL;
1179 }
1180
1181 DRM_DEBUG_KMS("Using VBT from %s: %20s\n",
1182 source, vbt->signature);
1183 return bdb;
1184}
1185
79e53945 1186/**
6d139a87 1187 * intel_parse_bios - find VBT and initialize settings from the BIOS
79e53945
JB
1188 * @dev: DRM device
1189 *
1190 * Loads the Video BIOS and checks that the VBT exists. Sets scratch registers
1191 * to appropriate values.
1192 *
79e53945
JB
1193 * Returns 0 on success, nonzero on failure.
1194 */
0317c6ce 1195int
6d139a87 1196intel_parse_bios(struct drm_device *dev)
79e53945
JB
1197{
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 struct pci_dev *pdev = dev->pdev;
44834a67
CW
1200 struct bdb_header *bdb = NULL;
1201 u8 __iomem *bios = NULL;
1202
ab5c608b
BW
1203 if (HAS_PCH_NOP(dev))
1204 return -ENODEV;
1205
6a04002b 1206 init_vbt_defaults(dev_priv);
f899fc64 1207
44834a67 1208 /* XXX Should this validation be moved to intel_opregion.c? */
3dd4e846
CW
1209 if (!dmi_check_system(intel_no_opregion_vbt) && dev_priv->opregion.vbt)
1210 bdb = validate_vbt((char *)dev_priv->opregion.header, OPREGION_SIZE,
1211 (struct vbt_header *)dev_priv->opregion.vbt,
1212 "OpRegion");
79e53945 1213
44834a67 1214 if (bdb == NULL) {
3dd4e846 1215 size_t i, size;
79e53945 1216
44834a67
CW
1217 bios = pci_map_rom(pdev, &size);
1218 if (!bios)
1219 return -1;
1220
1221 /* Scour memory looking for the VBT signature */
1222 for (i = 0; i + 4 < size; i++) {
3dd4e846
CW
1223 if (memcmp(bios + i, "$VBT", 4) == 0) {
1224 bdb = validate_vbt(bios, size,
1225 (struct vbt_header *)(bios + i),
1226 "PCI ROM");
44834a67
CW
1227 break;
1228 }
1229 }
1230
3dd4e846 1231 if (!bdb) {
44834a67
CW
1232 pci_unmap_rom(pdev, bios);
1233 return -1;
1234 }
44834a67 1235 }
79e53945
JB
1236
1237 /* Grab useful general definitions */
1238 parse_general_features(dev_priv, bdb);
db545019 1239 parse_general_definitions(dev_priv, bdb);
88631706 1240 parse_lfp_panel_data(dev_priv, bdb);
f00076d2 1241 parse_lfp_backlight(dev_priv, bdb);
88631706 1242 parse_sdvo_panel_data(dev_priv, bdb);
9b9d172d 1243 parse_sdvo_device_mapping(dev_priv, bdb);
6363ee6f 1244 parse_device_mapping(dev_priv, bdb);
32f9d658 1245 parse_driver_features(dev_priv, bdb);
500a8cc4 1246 parse_edp(dev_priv, bdb);
d17c5443 1247 parse_mipi(dev_priv, bdb);
6acab15a 1248 parse_ddi_ports(dev_priv, bdb);
32f9d658 1249
44834a67
CW
1250 if (bios)
1251 pci_unmap_rom(pdev, bios);
79e53945
JB
1252
1253 return 0;
1254}
6d139a87
BF
1255
1256/* Ensure that vital registers have been initialised, even if the BIOS
1257 * is absent or just failing to do its job.
1258 */
1259void intel_setup_bios(struct drm_device *dev)
1260{
1261 struct drm_i915_private *dev_priv = dev->dev_private;
1262
1263 /* Set the Panel Power On/Off timings if uninitialized. */
42d42e7e
DL
1264 if (!HAS_PCH_SPLIT(dev) &&
1265 I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) {
6d139a87
BF
1266 /* Set T2 to 40ms and T5 to 200ms */
1267 I915_WRITE(PP_ON_DELAYS, 0x019007d0);
1268
1269 /* Set T3 to 35ms and Tx to 200ms */
1270 I915_WRITE(PP_OFF_DELAYS, 0x015e07d0);
1271 }
1272}
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