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drm/i915: move dev_priv->suspend around
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_bios.h
CommitLineData
79e53945 1/*
f01eca2e 2 * Copyright © 2006 Intel Corporation
79e53945
JB		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#ifndef _I830_BIOS_H_
29#define _I830_BIOS_H_
30
760285e7 31#include <drm/drmP.h>
79e53945
JB		 32
33struct vbt_header {
34 u8 signature[20]; /**< Always starts with 'VBT$' */
35 u16 version; /**< decimal */
36 u16 header_size; /**< in bytes */
37 u16 vbt_size; /**< in bytes */
38 u8 vbt_checksum;
39 u8 reserved0;
40 u32 bdb_offset; /**< from beginning of VBT */
41 u32 aim_offset[4]; /**< from beginning of VBT */
e4451239 42} __packed;
79e53945
JB		 43
44struct bdb_header {
45 u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
46 u16 version; /**< decimal */
47 u16 header_size; /**< in bytes */
48 u16 bdb_size; /**< in bytes */
49};
50
51/* strictly speaking, this is a "skip" block, but it has interesting info */
52struct vbios_data {
53 u8 type; /* 0 == desktop, 1 == mobile */
54 u8 relstage;
55 u8 chipset;
56 u8 lvds_present:1;
57 u8 tv_present:1;
58 u8 rsvd2:6; /* finish byte */
59 u8 rsvd3[4];
60 u8 signon[155];
61 u8 copyright[61];
62 u16 code_segment;
63 u8 dos_boot_mode;
64 u8 bandwidth_percent;
65 u8 rsvd4; /* popup memory size */
66 u8 resize_pci_bios;
67 u8 rsvd5; /* is crt already on ddc2 */
e4451239 68} __packed;
79e53945
JB		 69
70/*
71 * There are several types of BIOS data blocks (BDBs), each block has
72 * an ID and size in the first 3 bytes (ID in first, size in next 2).
73 * Known types are listed below.
74 */
75#define BDB_GENERAL_FEATURES 1
76#define BDB_GENERAL_DEFINITIONS 2
77#define BDB_OLD_TOGGLE_LIST 3
78#define BDB_MODE_SUPPORT_LIST 4
79#define BDB_GENERIC_MODE_TABLE 5
80#define BDB_EXT_MMIO_REGS 6
81#define BDB_SWF_IO 7
82#define BDB_SWF_MMIO 8
83#define BDB_DOT_CLOCK_TABLE 9
84#define BDB_MODE_REMOVAL_TABLE 10
85#define BDB_CHILD_DEVICE_TABLE 11
86#define BDB_DRIVER_FEATURES 12
87#define BDB_DRIVER_PERSISTENCE 13
88#define BDB_EXT_TABLE_PTRS 14
89#define BDB_DOT_CLOCK_OVERRIDE 15
90#define BDB_DISPLAY_SELECT 16
91/* 17 rsvd */
92#define BDB_DRIVER_ROTATION 18
93#define BDB_DISPLAY_REMOVE 19
94#define BDB_OEM_CUSTOM 20
95#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
96#define BDB_SDVO_LVDS_OPTIONS 22
97#define BDB_SDVO_PANEL_DTDS 23
98#define BDB_SDVO_LVDS_PNP_IDS 24
99#define BDB_SDVO_LVDS_POWER_SEQ 25
100#define BDB_TV_OPTIONS 26
500a8cc4 101#define BDB_EDP 27
79e53945
JB		 102#define BDB_LVDS_OPTIONS 40
103#define BDB_LVDS_LFP_DATA_PTRS 41
104#define BDB_LVDS_LFP_DATA 42
105#define BDB_LVDS_BACKLIGHT 43
106#define BDB_LVDS_POWER 44
ea9a6baf
SK		 107#define BDB_MIPI_CONFIG 52
108#define BDB_MIPI_SEQUENCE 53
79e53945
JB		 109#define BDB_SKIP 254 /* VBIOS private block, ignore */
110
111struct bdb_general_features {
112 /* bits 1 */
113 u8 panel_fitting:2;
114 u8 flexaim:1;
115 u8 msg_enable:1;
116 u8 clear_screen:3;
117 u8 color_flip:1;
118
119 /* bits 2 */
120 u8 download_ext_vbt:1;
121 u8 enable_ssc:1;
122 u8 ssc_freq:1;
123 u8 enable_lfp_on_override:1;
124 u8 disable_ssc_ddt:1;
abd06860
KP		 125 u8 rsvd7:1;
126 u8 display_clock_mode:1;
127 u8 rsvd8:1; /* finish byte */
79e53945
JB		 128
129 /* bits 3 */
130 u8 disable_smooth_vision:1;
131 u8 single_dvi:1;
3f704fa2
PZ		 132 u8 rsvd9:1;
133 u8 fdi_rx_polarity_inverted:1;
134 u8 rsvd10:4; /* finish byte */
79e53945
JB		 135
136 /* bits 4 */
137 u8 legacy_monitor_detect;
138
139 /* bits 5 */
140 u8 int_crt_support:1;
141 u8 int_tv_support:1;
d2830bdb
KP		 142 u8 int_efp_support:1;
143 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */
144 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
145 u8 rsvd11:3; /* finish byte */
e4451239 146} __packed;
79e53945 147
59a036cf 148/* pre-915 */
149#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
150#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
151#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
152#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
153
154/* Pre 915 */
155#define DEVICE_TYPE_NONE 0x00
156#define DEVICE_TYPE_CRT 0x01
157#define DEVICE_TYPE_TV 0x09
158#define DEVICE_TYPE_EFP 0x12
159#define DEVICE_TYPE_LFP 0x22
160/* On 915+ */
161#define DEVICE_TYPE_CRT_DPMS 0x6001
162#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
163#define DEVICE_TYPE_TV_COMPOSITE 0x0209
164#define DEVICE_TYPE_TV_MACROVISION 0x0289
165#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
166#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
167#define DEVICE_TYPE_TV_SCART 0x0209
168#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
169#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
170#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
171#define DEVICE_TYPE_EFP_DVI_I 0x6053
172#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
173#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
174#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
175#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
176#define DEVICE_TYPE_LFP_PANELLINK 0x5012
177#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
178#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
179#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
180#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
181
182#define DEVICE_CFG_NONE 0x00
183#define DEVICE_CFG_12BIT_DVOB 0x01
184#define DEVICE_CFG_12BIT_DVOC 0x02
185#define DEVICE_CFG_24BIT_DVOBC 0x09
186#define DEVICE_CFG_24BIT_DVOCB 0x0a
187#define DEVICE_CFG_DUAL_DVOB 0x11
188#define DEVICE_CFG_DUAL_DVOC 0x12
189#define DEVICE_CFG_DUAL_DVOBC 0x13
190#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
191#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
192
193#define DEVICE_WIRE_NONE 0x00
194#define DEVICE_WIRE_DVOB 0x01
195#define DEVICE_WIRE_DVOC 0x02
196#define DEVICE_WIRE_DVOBC 0x03
197#define DEVICE_WIRE_DVOBB 0x05
198#define DEVICE_WIRE_DVOCC 0x06
199#define DEVICE_WIRE_DVOB_MASTER 0x0d
200#define DEVICE_WIRE_DVOC_MASTER 0x0e
201
202#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
203#define DEVICE_PORT_DVOB 0x01
204#define DEVICE_PORT_DVOC 0x02
205
768f69c9
PZ		 206/* We used to keep this struct but without any version control. We should avoid
207 * using it in the future, but it should be safe to keep using it in the old
208 * code. */
209struct old_child_dev_config {
59a036cf 210 u16 handle;
211 u16 device_type;
46eb3036 212 u8 device_id[10]; /* ascii string */
59a036cf 213 u16 addin_offset;
214 u8 dvo_port; /* See Device_PORT_* above */
215 u8 i2c_pin;
216 u8 slave_addr;
217 u8 ddc_pin;
218 u16 edid_ptr;
219 u8 dvo_cfg; /* See DEVICE_CFG_* above */
220 u8 dvo2_port;
221 u8 i2c2_pin;
222 u8 slave2_addr;
223 u8 ddc2_pin;
224 u8 capabilities;
225 u8 dvo_wiring;/* See DEVICE_WIRE_* above */
226 u8 dvo2_wiring;
227 u16 extended_type;
228 u8 dvo_function;
e4451239 229} __packed;
59a036cf 230
768f69c9
PZ		 231/* This one contains field offsets that are known to be common for all BDB
232 * versions. Notice that the meaning of the contents contents may still change,
233 * but at least the offsets are consistent. */
234struct common_child_dev_config {
235 u16 handle;
236 u16 device_type;
237 u8 not_common1[12];
238 u8 dvo_port;
239 u8 not_common2[2];
240 u8 ddc_pin;
241 u16 edid_ptr;
e4451239 242} __packed;
768f69c9
PZ		 243
244/* This field changes depending on the BDB version, so the most reliable way to
245 * read it is by checking the BDB version and reading the raw pointer. */
246union child_device_config {
247 /* This one is safe to be used anywhere, but the code should still check
248 * the BDB version. */
249 u8 raw[33];
250 /* This one should only be kept for legacy code. */
251 struct old_child_dev_config old;
252 /* This one should also be safe to use anywhere, even without version
253 * checks. */
254 struct common_child_dev_config common;
255};
256
79e53945
JB		 257struct bdb_general_definitions {
258 /* DDC GPIO */
259 u8 crt_ddc_gmbus_pin;
260
261 /* DPMS bits */
262 u8 dpms_acpi:1;
263 u8 skip_boot_crt_detect:1;
264 u8 dpms_aim:1;
265 u8 rsvd1:5; /* finish byte */
266
267 /* boot device bits */
268 u8 boot_display[2];
269 u8 child_dev_size;
270
59a036cf 271 /*
272 * Device info:
273 * If TV is present, it'll be at devices[0].
274 * LVDS will be next, either devices[0] or [1], if present.
275 * On some platforms the number of device is 6. But could be as few as
276 * 4 if both TV and LVDS are missing.
277 * And the device num is related with the size of general definition
278 * block. It is obtained by using the following formula:
279 * number = (block_size - sizeof(bdb_general_definitions))/
0206e353 280 * sizeof(child_device_config);
59a036cf 281 */
768f69c9 282 union child_device_config devices[0];
e4451239 283} __packed;
79e53945
JB		 284
285struct bdb_lvds_options {
286 u8 panel_type;
287 u8 rsvd1;
288 /* LVDS capabilities, stored in a dword */
79e53945 289 u8 pfit_mode:2;
2b5cde2b
LP		 290 u8 pfit_text_mode_enhanced:1;
291 u8 pfit_gfx_mode_enhanced:1;
292 u8 pfit_ratio_auto:1;
293 u8 pixel_dither:1;
294 u8 lvds_edid:1;
295 u8 rsvd2:1;
79e53945 296 u8 rsvd4;
e4451239 297} __packed;
79e53945
JB		 298
299/* LFP pointer table contains entries to the struct below */
300struct bdb_lvds_lfp_data_ptr {
301 u16 fp_timing_offset; /* offsets are from start of bdb */
302 u8 fp_table_size;
303 u16 dvo_timing_offset;
304 u8 dvo_table_size;
305 u16 panel_pnp_id_offset;
306 u8 pnp_table_size;
e4451239 307} __packed;
79e53945
JB		 308
309struct bdb_lvds_lfp_data_ptrs {
310 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
311 struct bdb_lvds_lfp_data_ptr ptr[16];
e4451239 312} __packed;
79e53945
JB		 313
314/* LFP data has 3 blocks per entry */
315struct lvds_fp_timing {
316 u16 x_res;
317 u16 y_res;
318 u32 lvds_reg;
319 u32 lvds_reg_val;
320 u32 pp_on_reg;
321 u32 pp_on_reg_val;
322 u32 pp_off_reg;
323 u32 pp_off_reg_val;
324 u32 pp_cycle_reg;
325 u32 pp_cycle_reg_val;
326 u32 pfit_reg;
327 u32 pfit_reg_val;
328 u16 terminator;
e4451239 329} __packed;
79e53945
JB		 330
331struct lvds_dvo_timing {
332 u16 clock; /**< In 10khz */
333 u8 hactive_lo;
334 u8 hblank_lo;
335 u8 hblank_hi:4;
336 u8 hactive_hi:4;
337 u8 vactive_lo;
338 u8 vblank_lo;
339 u8 vblank_hi:4;
340 u8 vactive_hi:4;
341 u8 hsync_off_lo;
342 u8 hsync_pulse_width;
343 u8 vsync_pulse_width:4;
344 u8 vsync_off:4;
345 u8 rsvd0:6;
346 u8 hsync_off_hi:2;
347 u8 h_image;
348 u8 v_image;
349 u8 max_hv;
350 u8 h_border;
351 u8 v_border;
352 u8 rsvd1:3;
353 u8 digital:2;
354 u8 vsync_positive:1;
355 u8 hsync_positive:1;
356 u8 rsvd2:1;
e4451239 357} __packed;
79e53945
JB		 358
359struct lvds_pnp_id {
360 u16 mfg_name;
361 u16 product_code;
362 u32 serial;
363 u8 mfg_week;
364 u8 mfg_year;
e4451239 365} __packed;
79e53945
JB		 366
367struct bdb_lvds_lfp_data_entry {
368 struct lvds_fp_timing fp_timing;
369 struct lvds_dvo_timing dvo_timing;
370 struct lvds_pnp_id pnp_id;
e4451239 371} __packed;
79e53945
JB		 372
373struct bdb_lvds_lfp_data {
374 struct bdb_lvds_lfp_data_entry data[16];
e4451239 375} __packed;
79e53945 376
f00076d2
JN		 377struct bdb_lfp_backlight_data_entry {
378 u8 type:2;
379 u8 active_low_pwm:1;
380 u8 obsolete1:5;
381 u16 pwm_freq_hz;
382 u8 min_brightness;
383 u8 obsolete2;
384 u8 obsolete3;
385} __packed;
386
387struct bdb_lfp_backlight_data {
388 u8 entry_size;
389 struct bdb_lfp_backlight_data_entry data[16];
390 u8 level[16];
391} __packed;
392
79e53945
JB		 393struct aimdb_header {
394 char signature[16];
395 char oem_device[20];
396 u16 aimdb_version;
397 u16 aimdb_header_size;
398 u16 aimdb_size;
e4451239 399} __packed;
79e53945
JB		 400
401struct aimdb_block {
402 u8 aimdb_id;
403 u16 aimdb_size;
e4451239 404} __packed;
79e53945
JB		 405
406struct vch_panel_data {
407 u16 fp_timing_offset;
408 u8 fp_timing_size;
409 u16 dvo_timing_offset;
410 u8 dvo_timing_size;
411 u16 text_fitting_offset;
412 u8 text_fitting_size;
413 u16 graphics_fitting_offset;
414 u8 graphics_fitting_size;
e4451239 415} __packed;
79e53945
JB		 416
417struct vch_bdb_22 {
418 struct aimdb_block aimdb_block;
419 struct vch_panel_data panels[16];
e4451239 420} __packed;
79e53945 421
88631706
ML		 422struct bdb_sdvo_lvds_options {
423 u8 panel_backlight;
424 u8 h40_set_panel_type;
425 u8 panel_type;
426 u8 ssc_clk_freq;
427 u16 als_low_trip;
428 u16 als_high_trip;
429 u8 sclalarcoeff_tab_row_num;
430 u8 sclalarcoeff_tab_row_size;
431 u8 coefficient[8];
432 u8 panel_misc_bits_1;
433 u8 panel_misc_bits_2;
434 u8 panel_misc_bits_3;
435 u8 panel_misc_bits_4;
e4451239 436} __packed;
88631706
ML		 437
438
32f9d658
ZW		 439#define BDB_DRIVER_FEATURE_NO_LVDS 0
440#define BDB_DRIVER_FEATURE_INT_LVDS 1
441#define BDB_DRIVER_FEATURE_SDVO_LVDS 2
442#define BDB_DRIVER_FEATURE_EDP 3
443
444struct bdb_driver_features {
445 u8 boot_dev_algorithm:1;
446 u8 block_display_switch:1;
447 u8 allow_display_switch:1;
448 u8 hotplug_dvo:1;
449 u8 dual_view_zoom:1;
450 u8 int15h_hook:1;
451 u8 sprite_in_clone:1;
452 u8 primary_lfp_id:1;
453
454 u16 boot_mode_x;
455 u16 boot_mode_y;
456 u8 boot_mode_bpp;
457 u8 boot_mode_refresh;
458
459 u16 enable_lfp_primary:1;
460 u16 selective_mode_pruning:1;
461 u16 dual_frequency:1;
462 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
463 u16 nt_clone_support:1;
464 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
465 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
466 u16 cui_aspect_scaling:1;
467 u16 preserve_aspect_ratio:1;
468 u16 sdvo_device_power_down:1;
469 u16 crt_hotplug:1;
470 u16 lvds_config:2;
471 u16 tv_hotplug:1;
472 u16 hdmi_config:2;
473
474 u8 static_display:1;
475 u8 reserved2:7;
476 u16 legacy_crt_max_x;
477 u16 legacy_crt_max_y;
478 u8 legacy_crt_max_refresh;
479
480 u8 hdmi_termination;
481 u8 custom_vbt_version;
e4451239 482} __packed;
32f9d658 483
500a8cc4
ZW		 484#define EDP_18BPP 0
485#define EDP_24BPP 1
486#define EDP_30BPP 2
487#define EDP_RATE_1_62 0
488#define EDP_RATE_2_7 1
489#define EDP_LANE_1 0
490#define EDP_LANE_2 1
491#define EDP_LANE_4 3
492#define EDP_PREEMPHASIS_NONE 0
493#define EDP_PREEMPHASIS_3_5dB 1
494#define EDP_PREEMPHASIS_6dB 2
495#define EDP_PREEMPHASIS_9_5dB 3
496#define EDP_VSWING_0_4V 0
497#define EDP_VSWING_0_6V 1
498#define EDP_VSWING_0_8V 2
499#define EDP_VSWING_1_2V 3
500
501struct edp_power_seq {
f01eca2e
KP		 502 u16 t1_t3;
503 u16 t8;
500a8cc4
ZW		 504 u16 t9;
505 u16 t10;
f01eca2e 506 u16 t11_t12;
e4451239 507} __packed;
500a8cc4
ZW		 508
509struct edp_link_params {
510 u8 rate:4;
511 u8 lanes:4;
512 u8 preemphasis:4;
513 u8 vswing:4;
e4451239 514} __packed;
500a8cc4
ZW		 515
516struct bdb_edp {
517 struct edp_power_seq power_seqs[16];
518 u32 color_depth;
500a8cc4 519 struct edp_link_params link_params[16];
96c0a2f5
RJ		 520 u32 sdrrs_msa_timing_delay;
521
522 /* ith bit indicates enabled/disabled for (i+1)th panel */
523 u16 edp_s3d_feature;
524 u16 edp_t3_optimization;
e4451239 525} __packed;
500a8cc4 526
6d139a87 527void intel_setup_bios(struct drm_device *dev);
0317c6ce 528int intel_parse_bios(struct drm_device *dev);
79e53945
JB		 529
530/*
531 * Driver<->VBIOS interaction occurs through scratch bits in
532 * GR18 & SWF*.
533 */
534
535/* GR18 bits are set on display switch and hotkey events */
536#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
537#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
538#define GR18_HK_NONE (0x0<<3)
539#define GR18_HK_LFP_STRETCH (0x1<<3)
540#define GR18_HK_TOGGLE_DISP (0x2<<3)
541#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
542#define GR18_HK_POPUP_DISABLED (0x6<<3)
543#define GR18_HK_POPUP_ENABLED (0x7<<3)
544#define GR18_HK_PFIT (0x8<<3)
545#define GR18_HK_APM_CHANGE (0xa<<3)
546#define GR18_HK_MULTIPLE (0xc<<3)
547#define GR18_USER_INT_EN (1<<2)
548#define GR18_A0000_FLUSH_EN (1<<1)
549#define GR18_SMM_EN (1<<0)
550
551/* Set by driver, cleared by VBIOS */
552#define SWF00_YRES_SHIFT 16
553#define SWF00_XRES_SHIFT 0
554#define SWF00_RES_MASK 0xffff
555
556/* Set by VBIOS at boot time and driver at runtime */
557#define SWF01_TV2_FORMAT_SHIFT 8
558#define SWF01_TV1_FORMAT_SHIFT 0
559#define SWF01_TV_FORMAT_MASK 0xffff
560
561#define SWF10_VBIOS_BLC_I2C_EN (1<<29)
562#define SWF10_GTT_OVERRIDE_EN (1<<28)
563#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
564#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
565#define SWF10_OLD_TOGGLE 0x0
566#define SWF10_TOGGLE_LIST_1 0x1
567#define SWF10_TOGGLE_LIST_2 0x2
568#define SWF10_TOGGLE_LIST_3 0x3
569#define SWF10_TOGGLE_LIST_4 0x4
570#define SWF10_PANNING_EN (1<<23)
571#define SWF10_DRIVER_LOADED (1<<22)
572#define SWF10_EXTENDED_DESKTOP (1<<21)
573#define SWF10_EXCLUSIVE_MODE (1<<20)
574#define SWF10_OVERLAY_EN (1<<19)
575#define SWF10_PLANEB_HOLDOFF (1<<18)
576#define SWF10_PLANEA_HOLDOFF (1<<17)
577#define SWF10_VGA_HOLDOFF (1<<16)
578#define SWF10_ACTIVE_DISP_MASK 0xffff
579#define SWF10_PIPEB_LFP2 (1<<15)
580#define SWF10_PIPEB_EFP2 (1<<14)
581#define SWF10_PIPEB_TV2 (1<<13)
582#define SWF10_PIPEB_CRT2 (1<<12)
583#define SWF10_PIPEB_LFP (1<<11)
584#define SWF10_PIPEB_EFP (1<<10)
585#define SWF10_PIPEB_TV (1<<9)
586#define SWF10_PIPEB_CRT (1<<8)
587#define SWF10_PIPEA_LFP2 (1<<7)
588#define SWF10_PIPEA_EFP2 (1<<6)
589#define SWF10_PIPEA_TV2 (1<<5)
590#define SWF10_PIPEA_CRT2 (1<<4)
591#define SWF10_PIPEA_LFP (1<<3)
592#define SWF10_PIPEA_EFP (1<<2)
593#define SWF10_PIPEA_TV (1<<1)
594#define SWF10_PIPEA_CRT (1<<0)
595
596#define SWF11_MEMORY_SIZE_SHIFT 16
597#define SWF11_SV_TEST_EN (1<<15)
598#define SWF11_IS_AGP (1<<14)
599#define SWF11_DISPLAY_HOLDOFF (1<<13)
600#define SWF11_DPMS_REDUCED (1<<12)
601#define SWF11_IS_VBE_MODE (1<<11)
602#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
603#define SWF11_DPMS_MASK 0x07
604#define SWF11_DPMS_OFF (1<<2)
605#define SWF11_DPMS_SUSPEND (1<<1)
606#define SWF11_DPMS_STANDBY (1<<0)
607#define SWF11_DPMS_ON 0
608
609#define SWF14_GFX_PFIT_EN (1<<31)
610#define SWF14_TEXT_PFIT_EN (1<<30)
611#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
612#define SWF14_POPUP_EN (1<<28)
613#define SWF14_DISPLAY_HOLDOFF (1<<27)
614#define SWF14_DISP_DETECT_EN (1<<26)
615#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
616#define SWF14_DRIVER_STATUS (1<<24)
617#define SWF14_OS_TYPE_WIN9X (1<<23)
618#define SWF14_OS_TYPE_WINNT (1<<22)
619/* 21:19 rsvd */
620#define SWF14_PM_TYPE_MASK 0x00070000
621#define SWF14_PM_ACPI_VIDEO (0x4 << 16)
622#define SWF14_PM_ACPI (0x3 << 16)
623#define SWF14_PM_APM_12 (0x2 << 16)
624#define SWF14_PM_APM_11 (0x1 << 16)
625#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
626 /* if GR18 indicates a display switch */
627#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
628#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
629#define SWF14_DS_PIPEB_TV2_EN (1<<13)
630#define SWF14_DS_PIPEB_CRT2_EN (1<<12)
631#define SWF14_DS_PIPEB_LFP_EN (1<<11)
632#define SWF14_DS_PIPEB_EFP_EN (1<<10)
633#define SWF14_DS_PIPEB_TV_EN (1<<9)
634#define SWF14_DS_PIPEB_CRT_EN (1<<8)
635#define SWF14_DS_PIPEA_LFP2_EN (1<<7)
636#define SWF14_DS_PIPEA_EFP2_EN (1<<6)
637#define SWF14_DS_PIPEA_TV2_EN (1<<5)
638#define SWF14_DS_PIPEA_CRT2_EN (1<<4)
639#define SWF14_DS_PIPEA_LFP_EN (1<<3)
640#define SWF14_DS_PIPEA_EFP_EN (1<<2)
641#define SWF14_DS_PIPEA_TV_EN (1<<1)
642#define SWF14_DS_PIPEA_CRT_EN (1<<0)
643 /* if GR18 indicates a panel fitting request */
644#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
645 /* if GR18 indicates an APM change request */
646#define SWF14_APM_HIBERNATE 0x4
647#define SWF14_APM_SUSPEND 0x3
648#define SWF14_APM_STANDBY 0x1
649#define SWF14_APM_RESTORE 0x0
650
6363ee6f
ZY		 651/* Add the device class for LFP, TV, HDMI */
652#define DEVICE_TYPE_INT_LFP 0x1022
653#define DEVICE_TYPE_INT_TV 0x1009
654#define DEVICE_TYPE_HDMI 0x60D2
655#define DEVICE_TYPE_DP 0x68C6
656#define DEVICE_TYPE_eDP 0x78C6
657
78eb06c3
VS		 658#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15)
659#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14)
660#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13)
661#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
662#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11)
663#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10)
664#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9)
665#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8)
666#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6)
667#define DEVICE_TYPE_LVDS_SINGALING (1 << 5)
668#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
669#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3)
670#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
671#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
672#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
673
f02586df
VS		 674/*
675 * Bits we care about when checking for DEVICE_TYPE_eDP
676 * Depending on the system, the other bits may or may not
677 * be set for eDP outputs.
678 */
679#define DEVICE_TYPE_eDP_BITS \
680 (DEVICE_TYPE_INTERNAL_CONNECTOR | \
681 DEVICE_TYPE_NOT_HDMI_OUTPUT | \
682 DEVICE_TYPE_MIPI_OUTPUT | \
683 DEVICE_TYPE_COMPOSITE_OUTPUT | \
684 DEVICE_TYPE_DUAL_CHANNEL | \
685 DEVICE_TYPE_LVDS_SINGALING | \
686 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
687 DEVICE_TYPE_VIDEO_SIGNALING | \
688 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
689 DEVICE_TYPE_DIGITAL_OUTPUT | \
690 DEVICE_TYPE_ANALOG_OUTPUT)
691
6363ee6f
ZY		 692/* define the DVO port for HDMI output type */
693#define DVO_B 1
694#define DVO_C 2
695#define DVO_D 3
696
697/* define the PORT for DP output type */
698#define PORT_IDPB 7
699#define PORT_IDPC 8
700#define PORT_IDPD 9
701
6acab15a
PZ		 702/* Possible values for the "DVO Port" field for versions >= 155: */
703#define DVO_PORT_HDMIA 0
704#define DVO_PORT_HDMIB 1
705#define DVO_PORT_HDMIC 2
706#define DVO_PORT_HDMID 3
707#define DVO_PORT_LVDS 4
708#define DVO_PORT_TV 5
709#define DVO_PORT_CRT 6
710#define DVO_PORT_DPB 7
711#define DVO_PORT_DPC 8
712#define DVO_PORT_DPD 9
713#define DVO_PORT_DPA 10
714
ea9a6baf
SK		 715/* Block 52 contains MIPI Panel info
716 * 6 such enteries will there. Index into correct
717 * entery is based on the panel_index in #40 LFP
718 */
719#define MAX_MIPI_CONFIGURATIONS 6
d17c5443 720
ea9a6baf
SK		 721#define MIPI_DSI_UNDEFINED_PANEL_ID 0
722#define MIPI_DSI_GENERIC_PANEL_ID 1
d17c5443 723
ea9a6baf
SK		 724struct mipi_config {
725 u16 panel_id;
d17c5443 726
ea9a6baf
SK		 727 /* General Params */
728 u32 enable_dithering:1;
729 u32 rsvd1:1;
730 u32 is_bridge:1;
731
732 u32 panel_arch_type:2;
733 u32 is_cmd_mode:1;
734
735#define NON_BURST_SYNC_PULSE 0x1
736#define NON_BURST_SYNC_EVENTS 0x2
737#define BURST_MODE 0x3
738 u32 video_transfer_mode:2;
739
740 u32 cabc_supported:1;
741 u32 pwm_blc:1;
742
743 /* Bit 13:10 */
744#define PIXEL_FORMAT_RGB565 0x1
745#define PIXEL_FORMAT_RGB666 0x2
746#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3
747#define PIXEL_FORMAT_RGB888 0x4
748 u32 videomode_color_format:4;
749
750 /* Bit 15:14 */
751#define ENABLE_ROTATION_0 0x0
752#define ENABLE_ROTATION_90 0x1
753#define ENABLE_ROTATION_180 0x2
754#define ENABLE_ROTATION_270 0x3
755 u32 rotation:2;
756 u32 bta_enabled:1;
757 u32 rsvd2:15;
758
759 /* 2 byte Port Description */
760#define DUAL_LINK_NOT_SUPPORTED 0
761#define DUAL_LINK_FRONT_BACK 1
762#define DUAL_LINK_PIXEL_ALT 2
763 u16 dual_link:2;
764 u16 lane_cnt:2;
765 u16 rsvd3:12;
766
767 u16 rsvd4;
768
769 u8 rsvd5[5];
770 u32 dsi_ddr_clk;
d17c5443 771 u32 bridge_ref_clk;
d17c5443 772
ea9a6baf
SK		 773#define BYTE_CLK_SEL_20MHZ 0
774#define BYTE_CLK_SEL_10MHZ 1
775#define BYTE_CLK_SEL_5MHZ 2
776 u8 byte_clk_sel:2;
777
778 u8 rsvd6:6;
779
780 /* DPHY Flags */
781 u16 dphy_param_valid:1;
782 u16 eot_pkt_disabled:1;
783 u16 enable_clk_stop:1;
784 u16 rsvd7:13;
785
786 u32 hs_tx_timeout;
787 u32 lp_rx_timeout;
788 u32 turn_around_timeout;
789 u32 device_reset_timer;
790 u32 master_init_timer;
791 u32 dbi_bw_timer;
792 u32 lp_byte_clk_val;
793
794 /* 4 byte Dphy Params */
795 u32 prepare_cnt:6;
796 u32 rsvd8:2;
d17c5443
SK		 797 u32 clk_zero_cnt:8;
798 u32 trail_cnt:5;
ea9a6baf 799 u32 rsvd9:3;
d17c5443 800 u32 exit_zero_cnt:6;
ea9a6baf 801 u32 rsvd10:2;
d17c5443 802
d17c5443 803 u32 clk_lane_switch_cnt;
ea9a6baf
SK		 804 u32 hl_switch_cnt;
805
806 u32 rsvd11[6];
807
808 /* timings based on dphy spec */
809 u8 tclk_miss;
810 u8 tclk_post;
811 u8 rsvd12;
812 u8 tclk_pre;
813 u8 tclk_prepare;
814 u8 tclk_settle;
815 u8 tclk_term_enable;
816 u8 tclk_trail;
817 u16 tclk_prepare_clkzero;
818 u8 rsvd13;
819 u8 td_term_enable;
820 u8 teot;
821 u8 ths_exit;
822 u8 ths_prepare;
823 u16 ths_prepare_hszero;
824 u8 rsvd14;
825 u8 ths_settle;
826 u8 ths_skip;
827 u8 ths_trail;
828 u8 tinit;
829 u8 tlpx;
830 u8 rsvd15[3];
831
832 /* GPIOs */
833 u8 panel_enable;
834 u8 bl_enable;
835 u8 pwm_enable;
836 u8 reset_r_n;
837 u8 pwr_down_r;
838 u8 stdby_r_n;
839
e4451239 840} __packed;
d17c5443 841
ea9a6baf
SK		 842/* Block 52 contains MIPI configuration block
843 * 6 * bdb_mipi_config, followed by 6 pps data
844 * block below
845 *
846 * all delays has a unit of 100us
847 */
848struct mipi_pps_data {
849 u16 panel_on_delay;
850 u16 bl_enable_delay;
851 u16 bl_disable_delay;
852 u16 panel_off_delay;
853 u16 panel_power_cycle_delay;
854};
855
856struct bdb_mipi_config {
857 struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
858 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
859};
860
861/* Block 53 contains MIPI sequences as needed by the panel
862 * for enabling it. This block can be variable in size and
863 * can be maximum of 6 blocks
864 */
865struct bdb_mipi_sequence {
866 u8 version;
867 u8 data[0];
868};
869
79e53945 870#endif /* _I830_BIOS_H_ */
Linux kernel - Deliverables
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