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8563b1e8 LL |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #include "intel_drv.h" | |
26 | ||
27 | /* | |
28 | * Set up the pipe CSC unit. | |
29 | * | |
30 | * Currently only full range RGB to limited range RGB conversion | |
31 | * is supported, but eventually this should handle various | |
32 | * RGB<->YCbCr scenarios as well. | |
33 | */ | |
34 | static void i9xx_load_csc_matrix(struct drm_crtc *crtc) | |
35 | { | |
36 | struct drm_device *dev = crtc->dev; | |
37 | struct drm_i915_private *dev_priv = dev->dev_private; | |
38 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
39 | int pipe = intel_crtc->pipe; | |
40 | uint16_t coeff = 0x7800; /* 1.0 */ | |
41 | ||
42 | /* | |
43 | * TODO: Check what kind of values actually come out of the pipe | |
44 | * with these coeff/postoff values and adjust to get the best | |
45 | * accuracy. Perhaps we even need to take the bpc value into | |
46 | * consideration. | |
47 | */ | |
48 | ||
49 | if (intel_crtc->config->limited_color_range) | |
50 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ | |
51 | ||
52 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
53 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
54 | ||
55 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
56 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
57 | ||
58 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
59 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
60 | ||
61 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
62 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
63 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
64 | ||
65 | if (INTEL_INFO(dev)->gen > 6) { | |
66 | uint16_t postoff = 0; | |
67 | ||
68 | if (intel_crtc->config->limited_color_range) | |
69 | postoff = (16 * (1 << 12) / 255) & 0x1fff; | |
70 | ||
71 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
72 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
73 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
74 | ||
75 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
76 | } else { | |
77 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
78 | ||
79 | if (intel_crtc->config->limited_color_range) | |
80 | mode |= CSC_BLACK_SCREEN_OFFSET; | |
81 | ||
82 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
83 | } | |
84 | } | |
85 | ||
86 | void intel_color_set_csc(struct drm_crtc *crtc) | |
87 | { | |
88 | i9xx_load_csc_matrix(crtc); | |
89 | } | |
90 | ||
91 | /* Loads the palette/gamma unit for the CRTC with the prepared values. */ | |
92 | static void i9xx_load_luts(struct drm_crtc *crtc) | |
93 | { | |
94 | struct drm_device *dev = crtc->dev; | |
95 | struct drm_i915_private *dev_priv = dev->dev_private; | |
96 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
97 | enum pipe pipe = intel_crtc->pipe; | |
98 | int i; | |
99 | ||
100 | if (HAS_GMCH_DISPLAY(dev)) { | |
101 | if (intel_crtc->config->has_dsi_encoder) | |
102 | assert_dsi_pll_enabled(dev_priv); | |
103 | else | |
104 | assert_pll_enabled(dev_priv, pipe); | |
105 | } | |
106 | ||
107 | for (i = 0; i < 256; i++) { | |
108 | uint32_t word = (intel_crtc->lut_r[i] << 16) | | |
109 | (intel_crtc->lut_g[i] << 8) | | |
110 | intel_crtc->lut_b[i]; | |
111 | if (HAS_GMCH_DISPLAY(dev)) | |
112 | I915_WRITE(PALETTE(pipe, i), word); | |
113 | else | |
114 | I915_WRITE(LGC_PALETTE(pipe, i), word); | |
115 | } | |
116 | } | |
117 | ||
118 | /* Loads the legacy palette/gamma unit for the CRTC on Haswell+. */ | |
119 | static void haswell_load_luts(struct drm_crtc *crtc) | |
120 | { | |
121 | struct drm_device *dev = crtc->dev; | |
122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
123 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05dc698c LL |
124 | struct intel_crtc_state *intel_crtc_state = |
125 | to_intel_crtc_state(crtc->state); | |
8563b1e8 LL |
126 | bool reenable_ips = false; |
127 | ||
128 | /* | |
129 | * Workaround : Do not read or write the pipe palette/gamma data while | |
130 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
131 | */ | |
132 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && | |
05dc698c | 133 | (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) { |
8563b1e8 LL |
134 | hsw_disable_ips(intel_crtc); |
135 | reenable_ips = true; | |
136 | } | |
05dc698c LL |
137 | |
138 | intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; | |
8563b1e8 LL |
139 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
140 | ||
141 | i9xx_load_luts(crtc); | |
142 | ||
143 | if (reenable_ips) | |
144 | hsw_enable_ips(intel_crtc); | |
145 | } | |
146 | ||
147 | void intel_color_load_luts(struct drm_crtc *crtc) | |
148 | { | |
149 | struct drm_device *dev = crtc->dev; | |
150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
151 | ||
152 | /* The clocks have to be on to load the palette. */ | |
153 | if (!crtc->state->active) | |
154 | return; | |
155 | ||
156 | dev_priv->display.load_luts(crtc); | |
157 | } | |
158 | ||
159 | void intel_color_legacy_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, | |
160 | u16 *blue, uint32_t start, uint32_t size) | |
161 | { | |
162 | int end = (start + size > 256) ? 256 : start + size, i; | |
163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
164 | ||
165 | for (i = start; i < end; i++) { | |
166 | intel_crtc->lut_r[i] = red[i] >> 8; | |
167 | intel_crtc->lut_g[i] = green[i] >> 8; | |
168 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
169 | } | |
170 | ||
171 | intel_color_load_luts(crtc); | |
172 | } | |
173 | ||
174 | void intel_color_init(struct drm_crtc *crtc) | |
175 | { | |
176 | struct drm_device *dev = crtc->dev; | |
177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
178 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
179 | int i; | |
180 | ||
181 | drm_mode_crtc_set_gamma_size(crtc, 256); | |
182 | for (i = 0; i < 256; i++) { | |
183 | intel_crtc->lut_r[i] = i; | |
184 | intel_crtc->lut_g[i] = i; | |
185 | intel_crtc->lut_b[i] = i; | |
186 | } | |
187 | ||
188 | if (IS_HASWELL(dev) || | |
189 | (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev))) { | |
190 | dev_priv->display.load_luts = haswell_load_luts; | |
191 | } else { | |
192 | dev_priv->display.load_luts = i9xx_load_luts; | |
193 | } | |
194 | } |