Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 DH |
30 | #include <drm/drmP.h> |
31 | #include <drm/drm_crtc.h> | |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_edid.h> | |
79e53945 | 34 | #include "intel_drv.h" |
760285e7 | 35 | #include <drm/i915_drm.h> |
79e53945 JB |
36 | #include "i915_drv.h" |
37 | ||
e7dbb2f2 KP |
38 | /* Here's the desired hotplug mode */ |
39 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
40 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
41 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
42 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
43 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
44 | ADPA_CRT_HOTPLUG_ENABLE) | |
45 | ||
c9a1c4cd CW |
46 | struct intel_crt { |
47 | struct intel_encoder base; | |
637f44d2 AJ |
48 | /* DPMS state is stored in the connector, which we need in the |
49 | * encoder's enable/disable callbacks */ | |
50 | struct intel_connector *connector; | |
e7dbb2f2 | 51 | bool force_hotplug_required; |
540a8950 | 52 | u32 adpa_reg; |
c9a1c4cd CW |
53 | }; |
54 | ||
eebe6f0b | 55 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 56 | { |
eebe6f0b | 57 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
58 | } |
59 | ||
eebe6f0b | 60 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
79e53945 | 61 | { |
eebe6f0b | 62 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 DV |
63 | } |
64 | ||
e403fc94 DV |
65 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
66 | enum pipe *pipe) | |
79e53945 | 67 | { |
e403fc94 | 68 | struct drm_device *dev = encoder->base.dev; |
79e53945 | 69 | struct drm_i915_private *dev_priv = dev->dev_private; |
e403fc94 | 70 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
6d129bea | 71 | enum intel_display_power_domain power_domain; |
e403fc94 DV |
72 | u32 tmp; |
73 | ||
6d129bea ID |
74 | power_domain = intel_display_port_power_domain(encoder); |
75 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
76 | return false; | |
77 | ||
e403fc94 DV |
78 | tmp = I915_READ(crt->adpa_reg); |
79 | ||
80 | if (!(tmp & ADPA_DAC_ENABLE)) | |
81 | return false; | |
82 | ||
83 | if (HAS_PCH_CPT(dev)) | |
84 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
85 | else | |
86 | *pipe = PORT_TO_PIPE(tmp); | |
87 | ||
88 | return true; | |
89 | } | |
90 | ||
6801c18c | 91 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
045ac3b5 JB |
92 | { |
93 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
94 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
95 | u32 tmp, flags = 0; | |
96 | ||
97 | tmp = I915_READ(crt->adpa_reg); | |
98 | ||
99 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
100 | flags |= DRM_MODE_FLAG_PHSYNC; | |
101 | else | |
102 | flags |= DRM_MODE_FLAG_NHSYNC; | |
103 | ||
104 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
105 | flags |= DRM_MODE_FLAG_PVSYNC; | |
106 | else | |
107 | flags |= DRM_MODE_FLAG_NVSYNC; | |
108 | ||
6801c18c VS |
109 | return flags; |
110 | } | |
111 | ||
112 | static void intel_crt_get_config(struct intel_encoder *encoder, | |
113 | struct intel_crtc_config *pipe_config) | |
114 | { | |
115 | struct drm_device *dev = encoder->base.dev; | |
116 | int dotclock; | |
117 | ||
118 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); | |
18442d08 VS |
119 | |
120 | dotclock = pipe_config->port_clock; | |
121 | ||
6801c18c | 122 | if (HAS_PCH_SPLIT(dev)) |
18442d08 VS |
123 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
124 | ||
241bfc38 | 125 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
126 | } |
127 | ||
6801c18c VS |
128 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
129 | struct intel_crtc_config *pipe_config) | |
130 | { | |
131 | intel_ddi_get_config(encoder, pipe_config); | |
132 | ||
133 | pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | | |
134 | DRM_MODE_FLAG_NHSYNC | | |
135 | DRM_MODE_FLAG_PVSYNC | | |
136 | DRM_MODE_FLAG_NVSYNC); | |
137 | pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); | |
138 | } | |
139 | ||
b2cabb0e DV |
140 | /* Note: The caller is required to filter out dpms modes not supported by the |
141 | * platform. */ | |
142 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) | |
df0323c4 | 143 | { |
b2cabb0e | 144 | struct drm_device *dev = encoder->base.dev; |
df0323c4 | 145 | struct drm_i915_private *dev_priv = dev->dev_private; |
b2cabb0e | 146 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
894ed1ec DV |
147 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
148 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
149 | u32 adpa; | |
150 | ||
151 | if (INTEL_INFO(dev)->gen >= 5) | |
152 | adpa = ADPA_HOTPLUG_BITS; | |
153 | else | |
154 | adpa = 0; | |
df0323c4 | 155 | |
894ed1ec DV |
156 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
157 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
158 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
159 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
160 | ||
161 | /* For CPT allow 3 pipe config, for others just use A or B */ | |
162 | if (HAS_PCH_LPT(dev)) | |
163 | ; /* Those bits don't exist here */ | |
164 | else if (HAS_PCH_CPT(dev)) | |
165 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); | |
166 | else if (crtc->pipe == 0) | |
167 | adpa |= ADPA_PIPE_A_SELECT; | |
168 | else | |
169 | adpa |= ADPA_PIPE_B_SELECT; | |
170 | ||
171 | if (!HAS_PCH_SPLIT(dev)) | |
172 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
79e53945 | 173 | |
0206e353 | 174 | switch (mode) { |
79e53945 | 175 | case DRM_MODE_DPMS_ON: |
894ed1ec | 176 | adpa |= ADPA_DAC_ENABLE; |
79e53945 JB |
177 | break; |
178 | case DRM_MODE_DPMS_STANDBY: | |
894ed1ec | 179 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
79e53945 JB |
180 | break; |
181 | case DRM_MODE_DPMS_SUSPEND: | |
894ed1ec | 182 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
183 | break; |
184 | case DRM_MODE_DPMS_OFF: | |
894ed1ec | 185 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
186 | break; |
187 | } | |
188 | ||
894ed1ec | 189 | I915_WRITE(crt->adpa_reg, adpa); |
df0323c4 | 190 | } |
2c07245f | 191 | |
637f44d2 AJ |
192 | static void intel_disable_crt(struct intel_encoder *encoder) |
193 | { | |
194 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); | |
195 | } | |
196 | ||
197 | static void intel_enable_crt(struct intel_encoder *encoder) | |
198 | { | |
199 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
200 | ||
201 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); | |
202 | } | |
203 | ||
6b1c087b | 204 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
b2cabb0e | 205 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
df0323c4 | 206 | { |
b2cabb0e DV |
207 | struct drm_device *dev = connector->dev; |
208 | struct intel_encoder *encoder = intel_attached_encoder(connector); | |
209 | struct drm_crtc *crtc; | |
210 | int old_dpms; | |
79e53945 | 211 | |
b2cabb0e | 212 | /* PCH platforms and VLV only support on/off. */ |
4a8dece2 | 213 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
bd9e8413 JB |
214 | mode = DRM_MODE_DPMS_OFF; |
215 | ||
b2cabb0e DV |
216 | if (mode == connector->dpms) |
217 | return; | |
218 | ||
219 | old_dpms = connector->dpms; | |
220 | connector->dpms = mode; | |
221 | ||
222 | /* Only need to change hw state when actually enabled */ | |
223 | crtc = encoder->base.crtc; | |
224 | if (!crtc) { | |
225 | encoder->connectors_active = false; | |
226 | return; | |
79e53945 JB |
227 | } |
228 | ||
b2cabb0e DV |
229 | /* We need the pipe to run for anything but OFF. */ |
230 | if (mode == DRM_MODE_DPMS_OFF) | |
231 | encoder->connectors_active = false; | |
232 | else | |
233 | encoder->connectors_active = true; | |
234 | ||
6b1c087b JN |
235 | /* We call connector dpms manually below in case pipe dpms doesn't |
236 | * change due to cloning. */ | |
b2cabb0e DV |
237 | if (mode < old_dpms) { |
238 | /* From off to on, enable the pipe first. */ | |
239 | intel_crtc_update_dpms(crtc); | |
240 | ||
241 | intel_crt_set_dpms(encoder, mode); | |
242 | } else { | |
243 | intel_crt_set_dpms(encoder, mode); | |
244 | ||
245 | intel_crtc_update_dpms(crtc); | |
246 | } | |
0a91ca29 | 247 | |
b980514c | 248 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
249 | } |
250 | ||
c19de8eb DL |
251 | static enum drm_mode_status |
252 | intel_crt_mode_valid(struct drm_connector *connector, | |
253 | struct drm_display_mode *mode) | |
79e53945 | 254 | { |
6bcdcd9e ZY |
255 | struct drm_device *dev = connector->dev; |
256 | ||
257 | int max_clock = 0; | |
79e53945 JB |
258 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
259 | return MODE_NO_DBLESCAN; | |
260 | ||
6bcdcd9e ZY |
261 | if (mode->clock < 25000) |
262 | return MODE_CLOCK_LOW; | |
263 | ||
a6c45cf0 | 264 | if (IS_GEN2(dev)) |
6bcdcd9e ZY |
265 | max_clock = 350000; |
266 | else | |
267 | max_clock = 400000; | |
268 | if (mode->clock > max_clock) | |
269 | return MODE_CLOCK_HIGH; | |
79e53945 | 270 | |
d4b1931c PZ |
271 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
272 | if (HAS_PCH_LPT(dev) && | |
273 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) | |
274 | return MODE_CLOCK_HIGH; | |
275 | ||
79e53945 JB |
276 | return MODE_OK; |
277 | } | |
278 | ||
5bfe2ac0 DV |
279 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
280 | struct intel_crtc_config *pipe_config) | |
79e53945 | 281 | { |
5bfe2ac0 DV |
282 | struct drm_device *dev = encoder->base.dev; |
283 | ||
284 | if (HAS_PCH_SPLIT(dev)) | |
285 | pipe_config->has_pch_encoder = true; | |
286 | ||
2a7aceec DV |
287 | /* LPT FDI RX only supports 8bpc. */ |
288 | if (HAS_PCH_LPT(dev)) | |
289 | pipe_config->pipe_bpp = 24; | |
290 | ||
8f7abfd8 VS |
291 | /* FDI must always be 2.7 GHz */ |
292 | if (HAS_DDI(dev)) | |
293 | pipe_config->port_clock = 135000 * 2; | |
294 | ||
79e53945 JB |
295 | return true; |
296 | } | |
297 | ||
f2b115e6 | 298 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
299 | { |
300 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 301 | struct intel_crt *crt = intel_attached_crt(connector); |
2c07245f | 302 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7dbb2f2 | 303 | u32 adpa; |
2c07245f ZW |
304 | bool ret; |
305 | ||
e7dbb2f2 KP |
306 | /* The first time through, trigger an explicit detection cycle */ |
307 | if (crt->force_hotplug_required) { | |
308 | bool turn_off_dac = HAS_PCH_SPLIT(dev); | |
309 | u32 save_adpa; | |
67941da2 | 310 | |
e7dbb2f2 KP |
311 | crt->force_hotplug_required = 0; |
312 | ||
ca54b810 | 313 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
314 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
315 | ||
316 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
317 | if (turn_off_dac) | |
318 | adpa &= ~ADPA_DAC_ENABLE; | |
319 | ||
ca54b810 | 320 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 321 | |
ca54b810 | 322 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
e7dbb2f2 KP |
323 | 1000)) |
324 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
325 | ||
326 | if (turn_off_dac) { | |
ca54b810 VS |
327 | I915_WRITE(crt->adpa_reg, save_adpa); |
328 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 329 | } |
a4a6b901 ZW |
330 | } |
331 | ||
2c07245f | 332 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 333 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 334 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
335 | ret = true; |
336 | else | |
337 | ret = false; | |
e7dbb2f2 | 338 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 339 | |
2c07245f | 340 | return ret; |
79e53945 JB |
341 | } |
342 | ||
7d2c24e8 JB |
343 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
344 | { | |
345 | struct drm_device *dev = connector->dev; | |
ca54b810 | 346 | struct intel_crt *crt = intel_attached_crt(connector); |
7d2c24e8 JB |
347 | struct drm_i915_private *dev_priv = dev->dev_private; |
348 | u32 adpa; | |
349 | bool ret; | |
350 | u32 save_adpa; | |
351 | ||
ca54b810 | 352 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
353 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
354 | ||
355 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
356 | ||
ca54b810 | 357 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 358 | |
ca54b810 | 359 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
7d2c24e8 JB |
360 | 1000)) { |
361 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
ca54b810 | 362 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
363 | } |
364 | ||
365 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 366 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
367 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
368 | ret = true; | |
369 | else | |
370 | ret = false; | |
371 | ||
372 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
373 | ||
7d2c24e8 JB |
374 | return ret; |
375 | } | |
376 | ||
79e53945 JB |
377 | /** |
378 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
379 | * | |
380 | * Not for i915G/i915GM | |
381 | * | |
382 | * \return true if CRT is connected. | |
383 | * \return false if CRT is disconnected. | |
384 | */ | |
385 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
386 | { | |
387 | struct drm_device *dev = connector->dev; | |
388 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a772c49 AJ |
389 | u32 hotplug_en, orig, stat; |
390 | bool ret = false; | |
771cb081 | 391 | int i, tries = 0; |
2c07245f | 392 | |
bad720ff | 393 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 394 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 395 | |
7d2c24e8 JB |
396 | if (IS_VALLEYVIEW(dev)) |
397 | return valleyview_crt_detect_hotplug(connector); | |
398 | ||
771cb081 ZY |
399 | /* |
400 | * On 4 series desktop, CRT detect sequence need to be done twice | |
401 | * to get a reliable result. | |
402 | */ | |
79e53945 | 403 | |
771cb081 ZY |
404 | if (IS_G4X(dev) && !IS_GM45(dev)) |
405 | tries = 2; | |
406 | else | |
407 | tries = 1; | |
7a772c49 | 408 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
771cb081 ZY |
409 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
410 | ||
771cb081 | 411 | for (i = 0; i < tries ; i++) { |
771cb081 ZY |
412 | /* turn on the FORCE_DETECT */ |
413 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
771cb081 | 414 | /* wait for FORCE_DETECT to go off */ |
913d8d11 CW |
415 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
416 | CRT_HOTPLUG_FORCE_DETECT) == 0, | |
481b6af3 | 417 | 1000)) |
79077319 | 418 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 419 | } |
79e53945 | 420 | |
7a772c49 AJ |
421 | stat = I915_READ(PORT_HOTPLUG_STAT); |
422 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
423 | ret = true; | |
424 | ||
425 | /* clear the interrupt we just generated, if any */ | |
426 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 427 | |
7a772c49 AJ |
428 | /* and put the bits back */ |
429 | I915_WRITE(PORT_HOTPLUG_EN, orig); | |
430 | ||
431 | return ret; | |
79e53945 JB |
432 | } |
433 | ||
f1a2f5b7 JN |
434 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
435 | struct i2c_adapter *i2c) | |
436 | { | |
437 | struct edid *edid; | |
438 | ||
439 | edid = drm_get_edid(connector, i2c); | |
440 | ||
441 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
442 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
443 | intel_gmbus_force_bit(i2c, true); | |
444 | edid = drm_get_edid(connector, i2c); | |
445 | intel_gmbus_force_bit(i2c, false); | |
446 | } | |
447 | ||
448 | return edid; | |
449 | } | |
450 | ||
451 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
452 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
453 | struct i2c_adapter *adapter) | |
454 | { | |
455 | struct edid *edid; | |
ebda95a9 | 456 | int ret; |
f1a2f5b7 JN |
457 | |
458 | edid = intel_crt_get_edid(connector, adapter); | |
459 | if (!edid) | |
460 | return 0; | |
461 | ||
ebda95a9 JN |
462 | ret = intel_connector_update_modes(connector, edid); |
463 | kfree(edid); | |
464 | ||
465 | return ret; | |
f1a2f5b7 JN |
466 | } |
467 | ||
f5afcd3d | 468 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 469 | { |
f5afcd3d | 470 | struct intel_crt *crt = intel_attached_crt(connector); |
c9a1c4cd | 471 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
a2bd1f54 DV |
472 | struct edid *edid; |
473 | struct i2c_adapter *i2c; | |
79e53945 | 474 | |
a2bd1f54 | 475 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 476 | |
41aa3448 | 477 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 478 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 DV |
479 | |
480 | if (edid) { | |
481 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 482 | |
f5afcd3d DM |
483 | /* |
484 | * This may be a DVI-I connector with a shared DDC | |
485 | * link between analog and digital outputs, so we | |
486 | * have to check the EDID input spec of the attached device. | |
487 | */ | |
f5afcd3d DM |
488 | if (!is_digital) { |
489 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
490 | return true; | |
491 | } | |
a2bd1f54 DV |
492 | |
493 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
494 | } else { | |
495 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
496 | } |
497 | ||
a2bd1f54 DV |
498 | kfree(edid); |
499 | ||
6ec3d0c0 | 500 | return false; |
79e53945 JB |
501 | } |
502 | ||
e4a5d54f | 503 | static enum drm_connector_status |
7173188d | 504 | intel_crt_load_detect(struct intel_crt *crt) |
e4a5d54f | 505 | { |
7173188d | 506 | struct drm_device *dev = crt->base.base.dev; |
e4a5d54f | 507 | struct drm_i915_private *dev_priv = dev->dev_private; |
7173188d | 508 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
e4a5d54f ML |
509 | uint32_t save_bclrpat; |
510 | uint32_t save_vtotal; | |
511 | uint32_t vtotal, vactive; | |
512 | uint32_t vsample; | |
513 | uint32_t vblank, vblank_start, vblank_end; | |
514 | uint32_t dsl; | |
515 | uint32_t bclrpat_reg; | |
516 | uint32_t vtotal_reg; | |
517 | uint32_t vblank_reg; | |
518 | uint32_t vsync_reg; | |
519 | uint32_t pipeconf_reg; | |
520 | uint32_t pipe_dsl_reg; | |
521 | uint8_t st00; | |
522 | enum drm_connector_status status; | |
523 | ||
6ec3d0c0 CW |
524 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
525 | ||
9db4a9c7 JB |
526 | bclrpat_reg = BCLRPAT(pipe); |
527 | vtotal_reg = VTOTAL(pipe); | |
528 | vblank_reg = VBLANK(pipe); | |
529 | vsync_reg = VSYNC(pipe); | |
530 | pipeconf_reg = PIPECONF(pipe); | |
531 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
532 | |
533 | save_bclrpat = I915_READ(bclrpat_reg); | |
534 | save_vtotal = I915_READ(vtotal_reg); | |
535 | vblank = I915_READ(vblank_reg); | |
536 | ||
537 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
538 | vactive = (save_vtotal & 0x7ff) + 1; | |
539 | ||
540 | vblank_start = (vblank & 0xfff) + 1; | |
541 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
542 | ||
543 | /* Set the border color to purple. */ | |
544 | I915_WRITE(bclrpat_reg, 0x500050); | |
545 | ||
a6c45cf0 | 546 | if (!IS_GEN2(dev)) { |
e4a5d54f ML |
547 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
548 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 549 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
550 | /* Wait for next Vblank to substitue |
551 | * border color for Color info */ | |
9d0498a2 | 552 | intel_wait_for_vblank(dev, pipe); |
e4a5d54f ML |
553 | st00 = I915_READ8(VGA_MSR_WRITE); |
554 | status = ((st00 & (1 << 4)) != 0) ? | |
555 | connector_status_connected : | |
556 | connector_status_disconnected; | |
557 | ||
558 | I915_WRITE(pipeconf_reg, pipeconf); | |
559 | } else { | |
560 | bool restore_vblank = false; | |
561 | int count, detect; | |
562 | ||
563 | /* | |
564 | * If there isn't any border, add some. | |
565 | * Yes, this will flicker | |
566 | */ | |
567 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
568 | uint32_t vsync = I915_READ(vsync_reg); | |
569 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
570 | ||
571 | vblank_start = vsync_start; | |
572 | I915_WRITE(vblank_reg, | |
573 | (vblank_start - 1) | | |
574 | ((vblank_end - 1) << 16)); | |
575 | restore_vblank = true; | |
576 | } | |
577 | /* sample in the vertical border, selecting the larger one */ | |
578 | if (vblank_start - vactive >= vtotal - vblank_end) | |
579 | vsample = (vblank_start + vactive) >> 1; | |
580 | else | |
581 | vsample = (vtotal + vblank_end) >> 1; | |
582 | ||
583 | /* | |
584 | * Wait for the border to be displayed | |
585 | */ | |
586 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
587 | ; | |
588 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
589 | ; | |
590 | /* | |
591 | * Watch ST00 for an entire scanline | |
592 | */ | |
593 | detect = 0; | |
594 | count = 0; | |
595 | do { | |
596 | count++; | |
597 | /* Read the ST00 VGA status register */ | |
598 | st00 = I915_READ8(VGA_MSR_WRITE); | |
599 | if (st00 & (1 << 4)) | |
600 | detect++; | |
601 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
602 | ||
603 | /* restore vblank if necessary */ | |
604 | if (restore_vblank) | |
605 | I915_WRITE(vblank_reg, vblank); | |
606 | /* | |
607 | * If more than 3/4 of the scanline detected a monitor, | |
608 | * then it is assumed to be present. This works even on i830, | |
609 | * where there isn't any way to force the border color across | |
610 | * the screen | |
611 | */ | |
612 | status = detect * 4 > count * 3 ? | |
613 | connector_status_connected : | |
614 | connector_status_disconnected; | |
615 | } | |
616 | ||
617 | /* Restore previous settings */ | |
618 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
619 | ||
620 | return status; | |
621 | } | |
622 | ||
7b334fcb | 623 | static enum drm_connector_status |
930a9e28 | 624 | intel_crt_detect(struct drm_connector *connector, bool force) |
79e53945 JB |
625 | { |
626 | struct drm_device *dev = connector->dev; | |
c19a0df2 | 627 | struct drm_i915_private *dev_priv = dev->dev_private; |
c9a1c4cd | 628 | struct intel_crt *crt = intel_attached_crt(connector); |
671dedd2 ID |
629 | struct intel_encoder *intel_encoder = &crt->base; |
630 | enum intel_display_power_domain power_domain; | |
e4a5d54f | 631 | enum drm_connector_status status; |
e95c8438 | 632 | struct intel_load_detect_pipe tmp; |
51fd371b | 633 | struct drm_modeset_acquire_ctx ctx; |
79e53945 | 634 | |
c19a0df2 PZ |
635 | intel_runtime_pm_get(dev_priv); |
636 | ||
164c8598 | 637 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
c23cc417 | 638 | connector->base.id, connector->name, |
164c8598 CW |
639 | force); |
640 | ||
671dedd2 ID |
641 | power_domain = intel_display_port_power_domain(intel_encoder); |
642 | intel_display_power_get(dev_priv, power_domain); | |
643 | ||
a6c45cf0 | 644 | if (I915_HAS_HOTPLUG(dev)) { |
aaa37730 DV |
645 | /* We can not rely on the HPD pin always being correctly wired |
646 | * up, for example many KVM do not pass it through, and so | |
647 | * only trust an assertion that the monitor is connected. | |
648 | */ | |
6ec3d0c0 CW |
649 | if (intel_crt_detect_hotplug(connector)) { |
650 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
c19a0df2 PZ |
651 | status = connector_status_connected; |
652 | goto out; | |
aaa37730 | 653 | } else |
e7dbb2f2 | 654 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
655 | } |
656 | ||
c19a0df2 PZ |
657 | if (intel_crt_detect_ddc(connector)) { |
658 | status = connector_status_connected; | |
659 | goto out; | |
660 | } | |
79e53945 | 661 | |
aaa37730 DV |
662 | /* Load detection is broken on HPD capable machines. Whoever wants a |
663 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
664 | * to have the right resistors for HP detection) needs to fix this up. | |
665 | * For now just bail out. */ | |
c19a0df2 PZ |
666 | if (I915_HAS_HOTPLUG(dev)) { |
667 | status = connector_status_disconnected; | |
668 | goto out; | |
669 | } | |
aaa37730 | 670 | |
c19a0df2 PZ |
671 | if (!force) { |
672 | status = connector->status; | |
673 | goto out; | |
674 | } | |
7b334fcb | 675 | |
e4a5d54f | 676 | /* for pre-945g platforms use load detect */ |
51fd371b | 677 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
e95c8438 DV |
678 | if (intel_crt_detect_ddc(connector)) |
679 | status = connector_status_connected; | |
680 | else | |
681 | status = intel_crt_load_detect(crt); | |
51fd371b | 682 | intel_release_load_detect_pipe(connector, &tmp, &ctx); |
e95c8438 DV |
683 | } else |
684 | status = connector_status_unknown; | |
e4a5d54f | 685 | |
c19a0df2 | 686 | out: |
671dedd2 | 687 | intel_display_power_put(dev_priv, power_domain); |
c19a0df2 | 688 | intel_runtime_pm_put(dev_priv); |
671dedd2 | 689 | |
e4a5d54f | 690 | return status; |
79e53945 JB |
691 | } |
692 | ||
693 | static void intel_crt_destroy(struct drm_connector *connector) | |
694 | { | |
79e53945 JB |
695 | drm_connector_cleanup(connector); |
696 | kfree(connector); | |
697 | } | |
698 | ||
699 | static int intel_crt_get_modes(struct drm_connector *connector) | |
700 | { | |
8e4d36b9 | 701 | struct drm_device *dev = connector->dev; |
f899fc64 | 702 | struct drm_i915_private *dev_priv = dev->dev_private; |
671dedd2 ID |
703 | struct intel_crt *crt = intel_attached_crt(connector); |
704 | struct intel_encoder *intel_encoder = &crt->base; | |
705 | enum intel_display_power_domain power_domain; | |
890f3359 | 706 | int ret; |
3bd7d909 | 707 | struct i2c_adapter *i2c; |
8e4d36b9 | 708 | |
671dedd2 ID |
709 | power_domain = intel_display_port_power_domain(intel_encoder); |
710 | intel_display_power_get(dev_priv, power_domain); | |
711 | ||
41aa3448 | 712 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 713 | ret = intel_crt_ddc_get_modes(connector, i2c); |
8e4d36b9 | 714 | if (ret || !IS_G4X(dev)) |
671dedd2 | 715 | goto out; |
8e4d36b9 | 716 | |
8e4d36b9 | 717 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
3bd7d909 | 718 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
671dedd2 ID |
719 | ret = intel_crt_ddc_get_modes(connector, i2c); |
720 | ||
721 | out: | |
722 | intel_display_power_put(dev_priv, power_domain); | |
723 | ||
724 | return ret; | |
79e53945 JB |
725 | } |
726 | ||
727 | static int intel_crt_set_property(struct drm_connector *connector, | |
728 | struct drm_property *property, | |
729 | uint64_t value) | |
730 | { | |
79e53945 JB |
731 | return 0; |
732 | } | |
733 | ||
f3269058 CW |
734 | static void intel_crt_reset(struct drm_connector *connector) |
735 | { | |
736 | struct drm_device *dev = connector->dev; | |
2e938892 | 737 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3269058 CW |
738 | struct intel_crt *crt = intel_attached_crt(connector); |
739 | ||
10603caa | 740 | if (INTEL_INFO(dev)->gen >= 5) { |
2e938892 DV |
741 | u32 adpa; |
742 | ||
ca54b810 | 743 | adpa = I915_READ(crt->adpa_reg); |
2e938892 DV |
744 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
745 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
746 | I915_WRITE(crt->adpa_reg, adpa); |
747 | POSTING_READ(crt->adpa_reg); | |
2e938892 DV |
748 | |
749 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); | |
f3269058 | 750 | crt->force_hotplug_required = 1; |
2e938892 DV |
751 | } |
752 | ||
f3269058 CW |
753 | } |
754 | ||
79e53945 JB |
755 | /* |
756 | * Routines for controlling stuff on the analog port | |
757 | */ | |
758 | ||
79e53945 | 759 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
f3269058 | 760 | .reset = intel_crt_reset, |
b2cabb0e | 761 | .dpms = intel_crt_dpms, |
79e53945 JB |
762 | .detect = intel_crt_detect, |
763 | .fill_modes = drm_helper_probe_single_connector_modes, | |
764 | .destroy = intel_crt_destroy, | |
765 | .set_property = intel_crt_set_property, | |
766 | }; | |
767 | ||
768 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
769 | .mode_valid = intel_crt_mode_valid, | |
770 | .get_modes = intel_crt_get_modes, | |
df0e9248 | 771 | .best_encoder = intel_best_encoder, |
79e53945 JB |
772 | }; |
773 | ||
79e53945 | 774 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
ea5b213a | 775 | .destroy = intel_encoder_destroy, |
79e53945 JB |
776 | }; |
777 | ||
8ca4013d DL |
778 | static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
779 | { | |
bc0daf48 | 780 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
8ca4013d DL |
781 | return 1; |
782 | } | |
783 | ||
784 | static const struct dmi_system_id intel_no_crt[] = { | |
785 | { | |
786 | .callback = intel_no_crt_dmi_callback, | |
787 | .ident = "ACER ZGB", | |
788 | .matches = { | |
789 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
790 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
791 | }, | |
792 | }, | |
10b6ee4a GC |
793 | { |
794 | .callback = intel_no_crt_dmi_callback, | |
795 | .ident = "DELL XPS 8700", | |
796 | .matches = { | |
797 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
798 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), | |
799 | }, | |
800 | }, | |
8ca4013d DL |
801 | { } |
802 | }; | |
803 | ||
79e53945 JB |
804 | void intel_crt_init(struct drm_device *dev) |
805 | { | |
806 | struct drm_connector *connector; | |
c9a1c4cd | 807 | struct intel_crt *crt; |
454c1ca8 | 808 | struct intel_connector *intel_connector; |
db545019 | 809 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 810 | |
8ca4013d DL |
811 | /* Skip machines without VGA that falsely report hotplug events */ |
812 | if (dmi_check_system(intel_no_crt)) | |
813 | return; | |
814 | ||
c9a1c4cd CW |
815 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
816 | if (!crt) | |
79e53945 JB |
817 | return; |
818 | ||
b14c5679 | 819 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
454c1ca8 | 820 | if (!intel_connector) { |
c9a1c4cd | 821 | kfree(crt); |
454c1ca8 ZW |
822 | return; |
823 | } | |
824 | ||
825 | connector = &intel_connector->base; | |
637f44d2 | 826 | crt->connector = intel_connector; |
454c1ca8 | 827 | drm_connector_init(dev, &intel_connector->base, |
79e53945 JB |
828 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
829 | ||
c9a1c4cd | 830 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
79e53945 JB |
831 | DRM_MODE_ENCODER_DAC); |
832 | ||
c9a1c4cd | 833 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 834 | |
c9a1c4cd | 835 | crt->base.type = INTEL_OUTPUT_ANALOG; |
301ea74a | 836 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
d63fa0dc | 837 | if (IS_I830(dev)) |
59c859d6 ED |
838 | crt->base.crtc_mask = (1 << 0); |
839 | else | |
0826874a | 840 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
59c859d6 | 841 | |
dbb02575 DV |
842 | if (IS_GEN2(dev)) |
843 | connector->interlace_allowed = 0; | |
844 | else | |
845 | connector->interlace_allowed = 1; | |
79e53945 JB |
846 | connector->doublescan_allowed = 0; |
847 | ||
df0323c4 | 848 | if (HAS_PCH_SPLIT(dev)) |
540a8950 DV |
849 | crt->adpa_reg = PCH_ADPA; |
850 | else if (IS_VALLEYVIEW(dev)) | |
851 | crt->adpa_reg = VLV_ADPA; | |
df0323c4 | 852 | else |
540a8950 DV |
853 | crt->adpa_reg = ADPA; |
854 | ||
5bfe2ac0 | 855 | crt->base.compute_config = intel_crt_compute_config; |
2124604b DV |
856 | crt->base.disable = intel_disable_crt; |
857 | crt->base.enable = intel_enable_crt; | |
1d843f9d EE |
858 | if (I915_HAS_HOTPLUG(dev)) |
859 | crt->base.hpd_pin = HPD_CRT; | |
a2985791 VS |
860 | if (HAS_DDI(dev)) { |
861 | crt->base.get_config = hsw_crt_get_config; | |
4eda01b2 | 862 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
a2985791 VS |
863 | } else { |
864 | crt->base.get_config = intel_crt_get_config; | |
4eda01b2 | 865 | crt->base.get_hw_state = intel_crt_get_hw_state; |
a2985791 | 866 | } |
e403fc94 | 867 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
4932e2c3 | 868 | intel_connector->unregister = intel_connector_unregister; |
df0323c4 | 869 | |
79e53945 JB |
870 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
871 | ||
872 | drm_sysfs_connector_add(connector); | |
b01f2c3a | 873 | |
821450c6 EE |
874 | if (!I915_HAS_HOTPLUG(dev)) |
875 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
eb1f8e4f | 876 | |
e7dbb2f2 KP |
877 | /* |
878 | * Configure the automatic hotplug detection stuff | |
879 | */ | |
880 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 881 | |
68d18ad7 | 882 | /* |
3e68320e DL |
883 | * TODO: find a proper way to discover whether we need to set the the |
884 | * polarity and link reversal bits or not, instead of relying on the | |
885 | * BIOS. | |
68d18ad7 | 886 | */ |
3e68320e DL |
887 | if (HAS_PCH_LPT(dev)) { |
888 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | | |
889 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
890 | ||
891 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; | |
892 | } | |
754970ee DV |
893 | |
894 | intel_crt_reset(connector); | |
79e53945 | 895 | } |