Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 DH |
30 | #include <drm/drmP.h> |
31 | #include <drm/drm_crtc.h> | |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_edid.h> | |
79e53945 | 34 | #include "intel_drv.h" |
760285e7 | 35 | #include <drm/i915_drm.h> |
79e53945 JB |
36 | #include "i915_drv.h" |
37 | ||
e7dbb2f2 KP |
38 | /* Here's the desired hotplug mode */ |
39 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
40 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
41 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
42 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
43 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
44 | ADPA_CRT_HOTPLUG_ENABLE) | |
45 | ||
c9a1c4cd CW |
46 | struct intel_crt { |
47 | struct intel_encoder base; | |
637f44d2 AJ |
48 | /* DPMS state is stored in the connector, which we need in the |
49 | * encoder's enable/disable callbacks */ | |
50 | struct intel_connector *connector; | |
e7dbb2f2 | 51 | bool force_hotplug_required; |
540a8950 | 52 | u32 adpa_reg; |
c9a1c4cd CW |
53 | }; |
54 | ||
eebe6f0b | 55 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 56 | { |
eebe6f0b | 57 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
58 | } |
59 | ||
eebe6f0b | 60 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
79e53945 | 61 | { |
eebe6f0b | 62 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 DV |
63 | } |
64 | ||
e403fc94 DV |
65 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
66 | enum pipe *pipe) | |
79e53945 | 67 | { |
e403fc94 | 68 | struct drm_device *dev = encoder->base.dev; |
79e53945 | 69 | struct drm_i915_private *dev_priv = dev->dev_private; |
e403fc94 DV |
70 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
71 | u32 tmp; | |
72 | ||
73 | tmp = I915_READ(crt->adpa_reg); | |
74 | ||
75 | if (!(tmp & ADPA_DAC_ENABLE)) | |
76 | return false; | |
77 | ||
78 | if (HAS_PCH_CPT(dev)) | |
79 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
80 | else | |
81 | *pipe = PORT_TO_PIPE(tmp); | |
82 | ||
83 | return true; | |
84 | } | |
85 | ||
045ac3b5 JB |
86 | static void intel_crt_get_config(struct intel_encoder *encoder, |
87 | struct intel_crtc_config *pipe_config) | |
88 | { | |
89 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
90 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
91 | u32 tmp, flags = 0; | |
92 | ||
93 | tmp = I915_READ(crt->adpa_reg); | |
94 | ||
95 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
96 | flags |= DRM_MODE_FLAG_PHSYNC; | |
97 | else | |
98 | flags |= DRM_MODE_FLAG_NHSYNC; | |
99 | ||
100 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
101 | flags |= DRM_MODE_FLAG_PVSYNC; | |
102 | else | |
103 | flags |= DRM_MODE_FLAG_NVSYNC; | |
104 | ||
105 | pipe_config->adjusted_mode.flags |= flags; | |
106 | } | |
107 | ||
b2cabb0e DV |
108 | /* Note: The caller is required to filter out dpms modes not supported by the |
109 | * platform. */ | |
110 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) | |
df0323c4 | 111 | { |
b2cabb0e | 112 | struct drm_device *dev = encoder->base.dev; |
df0323c4 | 113 | struct drm_i915_private *dev_priv = dev->dev_private; |
b2cabb0e | 114 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
df0323c4 JB |
115 | u32 temp; |
116 | ||
b2cabb0e | 117 | temp = I915_READ(crt->adpa_reg); |
79e53945 | 118 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
febc7694 | 119 | temp &= ~ADPA_DAC_ENABLE; |
79e53945 | 120 | |
0206e353 | 121 | switch (mode) { |
79e53945 JB |
122 | case DRM_MODE_DPMS_ON: |
123 | temp |= ADPA_DAC_ENABLE; | |
124 | break; | |
125 | case DRM_MODE_DPMS_STANDBY: | |
126 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; | |
127 | break; | |
128 | case DRM_MODE_DPMS_SUSPEND: | |
129 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; | |
130 | break; | |
131 | case DRM_MODE_DPMS_OFF: | |
132 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; | |
133 | break; | |
134 | } | |
135 | ||
b2cabb0e | 136 | I915_WRITE(crt->adpa_reg, temp); |
df0323c4 | 137 | } |
2c07245f | 138 | |
637f44d2 AJ |
139 | static void intel_disable_crt(struct intel_encoder *encoder) |
140 | { | |
141 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); | |
142 | } | |
143 | ||
144 | static void intel_enable_crt(struct intel_encoder *encoder) | |
145 | { | |
146 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
147 | ||
148 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); | |
149 | } | |
150 | ||
6b1c087b | 151 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
b2cabb0e | 152 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
df0323c4 | 153 | { |
b2cabb0e DV |
154 | struct drm_device *dev = connector->dev; |
155 | struct intel_encoder *encoder = intel_attached_encoder(connector); | |
156 | struct drm_crtc *crtc; | |
157 | int old_dpms; | |
79e53945 | 158 | |
b2cabb0e | 159 | /* PCH platforms and VLV only support on/off. */ |
4a8dece2 | 160 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
bd9e8413 JB |
161 | mode = DRM_MODE_DPMS_OFF; |
162 | ||
b2cabb0e DV |
163 | if (mode == connector->dpms) |
164 | return; | |
165 | ||
166 | old_dpms = connector->dpms; | |
167 | connector->dpms = mode; | |
168 | ||
169 | /* Only need to change hw state when actually enabled */ | |
170 | crtc = encoder->base.crtc; | |
171 | if (!crtc) { | |
172 | encoder->connectors_active = false; | |
173 | return; | |
79e53945 JB |
174 | } |
175 | ||
b2cabb0e DV |
176 | /* We need the pipe to run for anything but OFF. */ |
177 | if (mode == DRM_MODE_DPMS_OFF) | |
178 | encoder->connectors_active = false; | |
179 | else | |
180 | encoder->connectors_active = true; | |
181 | ||
6b1c087b JN |
182 | /* We call connector dpms manually below in case pipe dpms doesn't |
183 | * change due to cloning. */ | |
b2cabb0e DV |
184 | if (mode < old_dpms) { |
185 | /* From off to on, enable the pipe first. */ | |
186 | intel_crtc_update_dpms(crtc); | |
187 | ||
188 | intel_crt_set_dpms(encoder, mode); | |
189 | } else { | |
190 | intel_crt_set_dpms(encoder, mode); | |
191 | ||
192 | intel_crtc_update_dpms(crtc); | |
193 | } | |
0a91ca29 | 194 | |
b980514c | 195 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
196 | } |
197 | ||
198 | static int intel_crt_mode_valid(struct drm_connector *connector, | |
199 | struct drm_display_mode *mode) | |
200 | { | |
6bcdcd9e ZY |
201 | struct drm_device *dev = connector->dev; |
202 | ||
203 | int max_clock = 0; | |
79e53945 JB |
204 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
205 | return MODE_NO_DBLESCAN; | |
206 | ||
6bcdcd9e ZY |
207 | if (mode->clock < 25000) |
208 | return MODE_CLOCK_LOW; | |
209 | ||
a6c45cf0 | 210 | if (IS_GEN2(dev)) |
6bcdcd9e ZY |
211 | max_clock = 350000; |
212 | else | |
213 | max_clock = 400000; | |
214 | if (mode->clock > max_clock) | |
215 | return MODE_CLOCK_HIGH; | |
79e53945 | 216 | |
d4b1931c PZ |
217 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
218 | if (HAS_PCH_LPT(dev) && | |
219 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) | |
220 | return MODE_CLOCK_HIGH; | |
221 | ||
79e53945 JB |
222 | return MODE_OK; |
223 | } | |
224 | ||
5bfe2ac0 DV |
225 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
226 | struct intel_crtc_config *pipe_config) | |
79e53945 | 227 | { |
5bfe2ac0 DV |
228 | struct drm_device *dev = encoder->base.dev; |
229 | ||
230 | if (HAS_PCH_SPLIT(dev)) | |
231 | pipe_config->has_pch_encoder = true; | |
232 | ||
2a7aceec DV |
233 | /* LPT FDI RX only supports 8bpc. */ |
234 | if (HAS_PCH_LPT(dev)) | |
235 | pipe_config->pipe_bpp = 24; | |
236 | ||
79e53945 JB |
237 | return true; |
238 | } | |
239 | ||
eebe6f0b | 240 | static void intel_crt_mode_set(struct intel_encoder *encoder) |
79e53945 JB |
241 | { |
242 | ||
eebe6f0b DV |
243 | struct drm_device *dev = encoder->base.dev; |
244 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
245 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
79e53945 | 246 | struct drm_i915_private *dev_priv = dev->dev_private; |
eebe6f0b | 247 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
6478d414 | 248 | u32 adpa; |
79e53945 | 249 | |
912d812e DV |
250 | if (HAS_PCH_SPLIT(dev)) |
251 | adpa = ADPA_HOTPLUG_BITS; | |
252 | else | |
253 | adpa = 0; | |
254 | ||
79e53945 JB |
255 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
256 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
257 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
258 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
259 | ||
75770564 | 260 | /* For CPT allow 3 pipe config, for others just use A or B */ |
4837813a PZ |
261 | if (HAS_PCH_LPT(dev)) |
262 | ; /* Those bits don't exist here */ | |
263 | else if (HAS_PCH_CPT(dev)) | |
eebe6f0b DV |
264 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
265 | else if (crtc->pipe == 0) | |
75770564 JB |
266 | adpa |= ADPA_PIPE_A_SELECT; |
267 | else | |
268 | adpa |= ADPA_PIPE_B_SELECT; | |
79e53945 | 269 | |
9db4a9c7 | 270 | if (!HAS_PCH_SPLIT(dev)) |
eebe6f0b | 271 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
9db4a9c7 | 272 | |
540a8950 | 273 | I915_WRITE(crt->adpa_reg, adpa); |
2c07245f ZW |
274 | } |
275 | ||
f2b115e6 | 276 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
277 | { |
278 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 279 | struct intel_crt *crt = intel_attached_crt(connector); |
2c07245f | 280 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7dbb2f2 | 281 | u32 adpa; |
2c07245f ZW |
282 | bool ret; |
283 | ||
e7dbb2f2 KP |
284 | /* The first time through, trigger an explicit detection cycle */ |
285 | if (crt->force_hotplug_required) { | |
286 | bool turn_off_dac = HAS_PCH_SPLIT(dev); | |
287 | u32 save_adpa; | |
67941da2 | 288 | |
e7dbb2f2 KP |
289 | crt->force_hotplug_required = 0; |
290 | ||
ca54b810 | 291 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
292 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
293 | ||
294 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
295 | if (turn_off_dac) | |
296 | adpa &= ~ADPA_DAC_ENABLE; | |
297 | ||
ca54b810 | 298 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 299 | |
ca54b810 | 300 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
e7dbb2f2 KP |
301 | 1000)) |
302 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
303 | ||
304 | if (turn_off_dac) { | |
ca54b810 VS |
305 | I915_WRITE(crt->adpa_reg, save_adpa); |
306 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 307 | } |
a4a6b901 ZW |
308 | } |
309 | ||
2c07245f | 310 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 311 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 312 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
313 | ret = true; |
314 | else | |
315 | ret = false; | |
e7dbb2f2 | 316 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 317 | |
2c07245f | 318 | return ret; |
79e53945 JB |
319 | } |
320 | ||
7d2c24e8 JB |
321 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
322 | { | |
323 | struct drm_device *dev = connector->dev; | |
ca54b810 | 324 | struct intel_crt *crt = intel_attached_crt(connector); |
7d2c24e8 JB |
325 | struct drm_i915_private *dev_priv = dev->dev_private; |
326 | u32 adpa; | |
327 | bool ret; | |
328 | u32 save_adpa; | |
329 | ||
ca54b810 | 330 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
331 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
332 | ||
333 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
334 | ||
ca54b810 | 335 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 336 | |
ca54b810 | 337 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
7d2c24e8 JB |
338 | 1000)) { |
339 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
ca54b810 | 340 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
341 | } |
342 | ||
343 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 344 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
345 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
346 | ret = true; | |
347 | else | |
348 | ret = false; | |
349 | ||
350 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
351 | ||
352 | /* FIXME: debug force function and remove */ | |
353 | ret = true; | |
354 | ||
355 | return ret; | |
356 | } | |
357 | ||
79e53945 JB |
358 | /** |
359 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
360 | * | |
361 | * Not for i915G/i915GM | |
362 | * | |
363 | * \return true if CRT is connected. | |
364 | * \return false if CRT is disconnected. | |
365 | */ | |
366 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
367 | { | |
368 | struct drm_device *dev = connector->dev; | |
369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a772c49 AJ |
370 | u32 hotplug_en, orig, stat; |
371 | bool ret = false; | |
771cb081 | 372 | int i, tries = 0; |
2c07245f | 373 | |
bad720ff | 374 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 375 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 376 | |
7d2c24e8 JB |
377 | if (IS_VALLEYVIEW(dev)) |
378 | return valleyview_crt_detect_hotplug(connector); | |
379 | ||
771cb081 ZY |
380 | /* |
381 | * On 4 series desktop, CRT detect sequence need to be done twice | |
382 | * to get a reliable result. | |
383 | */ | |
79e53945 | 384 | |
771cb081 ZY |
385 | if (IS_G4X(dev) && !IS_GM45(dev)) |
386 | tries = 2; | |
387 | else | |
388 | tries = 1; | |
7a772c49 | 389 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
771cb081 ZY |
390 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
391 | ||
771cb081 | 392 | for (i = 0; i < tries ; i++) { |
771cb081 ZY |
393 | /* turn on the FORCE_DETECT */ |
394 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
771cb081 | 395 | /* wait for FORCE_DETECT to go off */ |
913d8d11 CW |
396 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
397 | CRT_HOTPLUG_FORCE_DETECT) == 0, | |
481b6af3 | 398 | 1000)) |
79077319 | 399 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 400 | } |
79e53945 | 401 | |
7a772c49 AJ |
402 | stat = I915_READ(PORT_HOTPLUG_STAT); |
403 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
404 | ret = true; | |
405 | ||
406 | /* clear the interrupt we just generated, if any */ | |
407 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 408 | |
7a772c49 AJ |
409 | /* and put the bits back */ |
410 | I915_WRITE(PORT_HOTPLUG_EN, orig); | |
411 | ||
412 | return ret; | |
79e53945 JB |
413 | } |
414 | ||
f1a2f5b7 JN |
415 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
416 | struct i2c_adapter *i2c) | |
417 | { | |
418 | struct edid *edid; | |
419 | ||
420 | edid = drm_get_edid(connector, i2c); | |
421 | ||
422 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
423 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
424 | intel_gmbus_force_bit(i2c, true); | |
425 | edid = drm_get_edid(connector, i2c); | |
426 | intel_gmbus_force_bit(i2c, false); | |
427 | } | |
428 | ||
429 | return edid; | |
430 | } | |
431 | ||
432 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
433 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
434 | struct i2c_adapter *adapter) | |
435 | { | |
436 | struct edid *edid; | |
ebda95a9 | 437 | int ret; |
f1a2f5b7 JN |
438 | |
439 | edid = intel_crt_get_edid(connector, adapter); | |
440 | if (!edid) | |
441 | return 0; | |
442 | ||
ebda95a9 JN |
443 | ret = intel_connector_update_modes(connector, edid); |
444 | kfree(edid); | |
445 | ||
446 | return ret; | |
f1a2f5b7 JN |
447 | } |
448 | ||
f5afcd3d | 449 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 450 | { |
f5afcd3d | 451 | struct intel_crt *crt = intel_attached_crt(connector); |
c9a1c4cd | 452 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
a2bd1f54 DV |
453 | struct edid *edid; |
454 | struct i2c_adapter *i2c; | |
79e53945 | 455 | |
a2bd1f54 | 456 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 457 | |
41aa3448 | 458 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 459 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 DV |
460 | |
461 | if (edid) { | |
462 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 463 | |
f5afcd3d DM |
464 | /* |
465 | * This may be a DVI-I connector with a shared DDC | |
466 | * link between analog and digital outputs, so we | |
467 | * have to check the EDID input spec of the attached device. | |
468 | */ | |
f5afcd3d DM |
469 | if (!is_digital) { |
470 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
471 | return true; | |
472 | } | |
a2bd1f54 DV |
473 | |
474 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
475 | } else { | |
476 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
477 | } |
478 | ||
a2bd1f54 DV |
479 | kfree(edid); |
480 | ||
6ec3d0c0 | 481 | return false; |
79e53945 JB |
482 | } |
483 | ||
e4a5d54f | 484 | static enum drm_connector_status |
7173188d | 485 | intel_crt_load_detect(struct intel_crt *crt) |
e4a5d54f | 486 | { |
7173188d | 487 | struct drm_device *dev = crt->base.base.dev; |
e4a5d54f | 488 | struct drm_i915_private *dev_priv = dev->dev_private; |
7173188d | 489 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
e4a5d54f ML |
490 | uint32_t save_bclrpat; |
491 | uint32_t save_vtotal; | |
492 | uint32_t vtotal, vactive; | |
493 | uint32_t vsample; | |
494 | uint32_t vblank, vblank_start, vblank_end; | |
495 | uint32_t dsl; | |
496 | uint32_t bclrpat_reg; | |
497 | uint32_t vtotal_reg; | |
498 | uint32_t vblank_reg; | |
499 | uint32_t vsync_reg; | |
500 | uint32_t pipeconf_reg; | |
501 | uint32_t pipe_dsl_reg; | |
502 | uint8_t st00; | |
503 | enum drm_connector_status status; | |
504 | ||
6ec3d0c0 CW |
505 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
506 | ||
9db4a9c7 JB |
507 | bclrpat_reg = BCLRPAT(pipe); |
508 | vtotal_reg = VTOTAL(pipe); | |
509 | vblank_reg = VBLANK(pipe); | |
510 | vsync_reg = VSYNC(pipe); | |
511 | pipeconf_reg = PIPECONF(pipe); | |
512 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
513 | |
514 | save_bclrpat = I915_READ(bclrpat_reg); | |
515 | save_vtotal = I915_READ(vtotal_reg); | |
516 | vblank = I915_READ(vblank_reg); | |
517 | ||
518 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
519 | vactive = (save_vtotal & 0x7ff) + 1; | |
520 | ||
521 | vblank_start = (vblank & 0xfff) + 1; | |
522 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
523 | ||
524 | /* Set the border color to purple. */ | |
525 | I915_WRITE(bclrpat_reg, 0x500050); | |
526 | ||
a6c45cf0 | 527 | if (!IS_GEN2(dev)) { |
e4a5d54f ML |
528 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
529 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 530 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
531 | /* Wait for next Vblank to substitue |
532 | * border color for Color info */ | |
9d0498a2 | 533 | intel_wait_for_vblank(dev, pipe); |
e4a5d54f ML |
534 | st00 = I915_READ8(VGA_MSR_WRITE); |
535 | status = ((st00 & (1 << 4)) != 0) ? | |
536 | connector_status_connected : | |
537 | connector_status_disconnected; | |
538 | ||
539 | I915_WRITE(pipeconf_reg, pipeconf); | |
540 | } else { | |
541 | bool restore_vblank = false; | |
542 | int count, detect; | |
543 | ||
544 | /* | |
545 | * If there isn't any border, add some. | |
546 | * Yes, this will flicker | |
547 | */ | |
548 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
549 | uint32_t vsync = I915_READ(vsync_reg); | |
550 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
551 | ||
552 | vblank_start = vsync_start; | |
553 | I915_WRITE(vblank_reg, | |
554 | (vblank_start - 1) | | |
555 | ((vblank_end - 1) << 16)); | |
556 | restore_vblank = true; | |
557 | } | |
558 | /* sample in the vertical border, selecting the larger one */ | |
559 | if (vblank_start - vactive >= vtotal - vblank_end) | |
560 | vsample = (vblank_start + vactive) >> 1; | |
561 | else | |
562 | vsample = (vtotal + vblank_end) >> 1; | |
563 | ||
564 | /* | |
565 | * Wait for the border to be displayed | |
566 | */ | |
567 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
568 | ; | |
569 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
570 | ; | |
571 | /* | |
572 | * Watch ST00 for an entire scanline | |
573 | */ | |
574 | detect = 0; | |
575 | count = 0; | |
576 | do { | |
577 | count++; | |
578 | /* Read the ST00 VGA status register */ | |
579 | st00 = I915_READ8(VGA_MSR_WRITE); | |
580 | if (st00 & (1 << 4)) | |
581 | detect++; | |
582 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
583 | ||
584 | /* restore vblank if necessary */ | |
585 | if (restore_vblank) | |
586 | I915_WRITE(vblank_reg, vblank); | |
587 | /* | |
588 | * If more than 3/4 of the scanline detected a monitor, | |
589 | * then it is assumed to be present. This works even on i830, | |
590 | * where there isn't any way to force the border color across | |
591 | * the screen | |
592 | */ | |
593 | status = detect * 4 > count * 3 ? | |
594 | connector_status_connected : | |
595 | connector_status_disconnected; | |
596 | } | |
597 | ||
598 | /* Restore previous settings */ | |
599 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
600 | ||
601 | return status; | |
602 | } | |
603 | ||
7b334fcb | 604 | static enum drm_connector_status |
930a9e28 | 605 | intel_crt_detect(struct drm_connector *connector, bool force) |
79e53945 JB |
606 | { |
607 | struct drm_device *dev = connector->dev; | |
c9a1c4cd | 608 | struct intel_crt *crt = intel_attached_crt(connector); |
e4a5d54f | 609 | enum drm_connector_status status; |
e95c8438 | 610 | struct intel_load_detect_pipe tmp; |
79e53945 | 611 | |
164c8598 CW |
612 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
613 | connector->base.id, drm_get_connector_name(connector), | |
614 | force); | |
615 | ||
a6c45cf0 | 616 | if (I915_HAS_HOTPLUG(dev)) { |
aaa37730 DV |
617 | /* We can not rely on the HPD pin always being correctly wired |
618 | * up, for example many KVM do not pass it through, and so | |
619 | * only trust an assertion that the monitor is connected. | |
620 | */ | |
6ec3d0c0 CW |
621 | if (intel_crt_detect_hotplug(connector)) { |
622 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
79e53945 | 623 | return connector_status_connected; |
aaa37730 | 624 | } else |
e7dbb2f2 | 625 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
626 | } |
627 | ||
f5afcd3d | 628 | if (intel_crt_detect_ddc(connector)) |
79e53945 JB |
629 | return connector_status_connected; |
630 | ||
aaa37730 DV |
631 | /* Load detection is broken on HPD capable machines. Whoever wants a |
632 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
633 | * to have the right resistors for HP detection) needs to fix this up. | |
634 | * For now just bail out. */ | |
635 | if (I915_HAS_HOTPLUG(dev)) | |
636 | return connector_status_disconnected; | |
637 | ||
930a9e28 | 638 | if (!force) |
7b334fcb CW |
639 | return connector->status; |
640 | ||
e4a5d54f | 641 | /* for pre-945g platforms use load detect */ |
d2434ab7 | 642 | if (intel_get_load_detect_pipe(connector, NULL, &tmp)) { |
e95c8438 DV |
643 | if (intel_crt_detect_ddc(connector)) |
644 | status = connector_status_connected; | |
645 | else | |
646 | status = intel_crt_load_detect(crt); | |
d2434ab7 | 647 | intel_release_load_detect_pipe(connector, &tmp); |
e95c8438 DV |
648 | } else |
649 | status = connector_status_unknown; | |
e4a5d54f ML |
650 | |
651 | return status; | |
79e53945 JB |
652 | } |
653 | ||
654 | static void intel_crt_destroy(struct drm_connector *connector) | |
655 | { | |
79e53945 JB |
656 | drm_sysfs_connector_remove(connector); |
657 | drm_connector_cleanup(connector); | |
658 | kfree(connector); | |
659 | } | |
660 | ||
661 | static int intel_crt_get_modes(struct drm_connector *connector) | |
662 | { | |
8e4d36b9 | 663 | struct drm_device *dev = connector->dev; |
f899fc64 | 664 | struct drm_i915_private *dev_priv = dev->dev_private; |
890f3359 | 665 | int ret; |
3bd7d909 | 666 | struct i2c_adapter *i2c; |
8e4d36b9 | 667 | |
41aa3448 | 668 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 669 | ret = intel_crt_ddc_get_modes(connector, i2c); |
8e4d36b9 | 670 | if (ret || !IS_G4X(dev)) |
f899fc64 | 671 | return ret; |
8e4d36b9 | 672 | |
8e4d36b9 | 673 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
3bd7d909 | 674 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
f1a2f5b7 | 675 | return intel_crt_ddc_get_modes(connector, i2c); |
79e53945 JB |
676 | } |
677 | ||
678 | static int intel_crt_set_property(struct drm_connector *connector, | |
679 | struct drm_property *property, | |
680 | uint64_t value) | |
681 | { | |
79e53945 JB |
682 | return 0; |
683 | } | |
684 | ||
f3269058 CW |
685 | static void intel_crt_reset(struct drm_connector *connector) |
686 | { | |
687 | struct drm_device *dev = connector->dev; | |
2e938892 | 688 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3269058 CW |
689 | struct intel_crt *crt = intel_attached_crt(connector); |
690 | ||
2e938892 DV |
691 | if (HAS_PCH_SPLIT(dev)) { |
692 | u32 adpa; | |
693 | ||
ca54b810 | 694 | adpa = I915_READ(crt->adpa_reg); |
2e938892 DV |
695 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
696 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
697 | I915_WRITE(crt->adpa_reg, adpa); |
698 | POSTING_READ(crt->adpa_reg); | |
2e938892 DV |
699 | |
700 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); | |
f3269058 | 701 | crt->force_hotplug_required = 1; |
2e938892 DV |
702 | } |
703 | ||
f3269058 CW |
704 | } |
705 | ||
79e53945 JB |
706 | /* |
707 | * Routines for controlling stuff on the analog port | |
708 | */ | |
709 | ||
79e53945 | 710 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
f3269058 | 711 | .reset = intel_crt_reset, |
b2cabb0e | 712 | .dpms = intel_crt_dpms, |
79e53945 JB |
713 | .detect = intel_crt_detect, |
714 | .fill_modes = drm_helper_probe_single_connector_modes, | |
715 | .destroy = intel_crt_destroy, | |
716 | .set_property = intel_crt_set_property, | |
717 | }; | |
718 | ||
719 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
720 | .mode_valid = intel_crt_mode_valid, | |
721 | .get_modes = intel_crt_get_modes, | |
df0e9248 | 722 | .best_encoder = intel_best_encoder, |
79e53945 JB |
723 | }; |
724 | ||
79e53945 | 725 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
ea5b213a | 726 | .destroy = intel_encoder_destroy, |
79e53945 JB |
727 | }; |
728 | ||
8ca4013d DL |
729 | static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
730 | { | |
bc0daf48 | 731 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
8ca4013d DL |
732 | return 1; |
733 | } | |
734 | ||
735 | static const struct dmi_system_id intel_no_crt[] = { | |
736 | { | |
737 | .callback = intel_no_crt_dmi_callback, | |
738 | .ident = "ACER ZGB", | |
739 | .matches = { | |
740 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
741 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
742 | }, | |
743 | }, | |
744 | { } | |
745 | }; | |
746 | ||
79e53945 JB |
747 | void intel_crt_init(struct drm_device *dev) |
748 | { | |
749 | struct drm_connector *connector; | |
c9a1c4cd | 750 | struct intel_crt *crt; |
454c1ca8 | 751 | struct intel_connector *intel_connector; |
db545019 | 752 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 753 | |
8ca4013d DL |
754 | /* Skip machines without VGA that falsely report hotplug events */ |
755 | if (dmi_check_system(intel_no_crt)) | |
756 | return; | |
757 | ||
c9a1c4cd CW |
758 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
759 | if (!crt) | |
79e53945 JB |
760 | return; |
761 | ||
454c1ca8 ZW |
762 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
763 | if (!intel_connector) { | |
c9a1c4cd | 764 | kfree(crt); |
454c1ca8 ZW |
765 | return; |
766 | } | |
767 | ||
768 | connector = &intel_connector->base; | |
637f44d2 | 769 | crt->connector = intel_connector; |
454c1ca8 | 770 | drm_connector_init(dev, &intel_connector->base, |
79e53945 JB |
771 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
772 | ||
c9a1c4cd | 773 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
79e53945 JB |
774 | DRM_MODE_ENCODER_DAC); |
775 | ||
c9a1c4cd | 776 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 777 | |
c9a1c4cd | 778 | crt->base.type = INTEL_OUTPUT_ANALOG; |
66a9278e | 779 | crt->base.cloneable = true; |
d63fa0dc | 780 | if (IS_I830(dev)) |
59c859d6 ED |
781 | crt->base.crtc_mask = (1 << 0); |
782 | else | |
0826874a | 783 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
59c859d6 | 784 | |
dbb02575 DV |
785 | if (IS_GEN2(dev)) |
786 | connector->interlace_allowed = 0; | |
787 | else | |
788 | connector->interlace_allowed = 1; | |
79e53945 JB |
789 | connector->doublescan_allowed = 0; |
790 | ||
df0323c4 | 791 | if (HAS_PCH_SPLIT(dev)) |
540a8950 DV |
792 | crt->adpa_reg = PCH_ADPA; |
793 | else if (IS_VALLEYVIEW(dev)) | |
794 | crt->adpa_reg = VLV_ADPA; | |
df0323c4 | 795 | else |
540a8950 DV |
796 | crt->adpa_reg = ADPA; |
797 | ||
5bfe2ac0 | 798 | crt->base.compute_config = intel_crt_compute_config; |
eebe6f0b | 799 | crt->base.mode_set = intel_crt_mode_set; |
2124604b DV |
800 | crt->base.disable = intel_disable_crt; |
801 | crt->base.enable = intel_enable_crt; | |
045ac3b5 | 802 | crt->base.get_config = intel_crt_get_config; |
1d843f9d EE |
803 | if (I915_HAS_HOTPLUG(dev)) |
804 | crt->base.hpd_pin = HPD_CRT; | |
affa9354 | 805 | if (HAS_DDI(dev)) |
4eda01b2 PZ |
806 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
807 | else | |
808 | crt->base.get_hw_state = intel_crt_get_hw_state; | |
e403fc94 | 809 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
df0323c4 | 810 | |
79e53945 JB |
811 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
812 | ||
813 | drm_sysfs_connector_add(connector); | |
b01f2c3a | 814 | |
821450c6 EE |
815 | if (!I915_HAS_HOTPLUG(dev)) |
816 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
eb1f8e4f | 817 | |
e7dbb2f2 KP |
818 | /* |
819 | * Configure the automatic hotplug detection stuff | |
820 | */ | |
821 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 822 | |
68d18ad7 | 823 | /* |
3e68320e DL |
824 | * TODO: find a proper way to discover whether we need to set the the |
825 | * polarity and link reversal bits or not, instead of relying on the | |
826 | * BIOS. | |
68d18ad7 | 827 | */ |
3e68320e DL |
828 | if (HAS_PCH_LPT(dev)) { |
829 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | | |
830 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
831 | ||
832 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; | |
833 | } | |
79e53945 | 834 | } |