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eb805623 DV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include "i915_drv.h" | |
26 | #include "i915_reg.h" | |
27 | ||
aa9145c4 AM |
28 | /** |
29 | * DOC: csr support for dmc | |
30 | * | |
31 | * Display Context Save and Restore (CSR) firmware support added from gen9 | |
32 | * onwards to drive newly added DMC (Display microcontroller) in display | |
33 | * engine to save and restore the state of display engine when it enter into | |
34 | * low-power state and comes back to normal. | |
aa9145c4 AM |
35 | */ |
36 | ||
4aa7fb9c | 37 | #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" |
4922d491 RV |
38 | MODULE_FIRMWARE(I915_CSR_KBL); |
39 | #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1) | |
40 | ||
4aa7fb9c | 41 | #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin" |
4922d491 | 42 | MODULE_FIRMWARE(I915_CSR_SKL); |
4aa7fb9c | 43 | #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26) |
4922d491 | 44 | |
4aa7fb9c | 45 | #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin" |
4922d491 RV |
46 | MODULE_FIRMWARE(I915_CSR_BXT); |
47 | #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) | |
eb805623 | 48 | |
cbfc2d26 CW |
49 | #define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares" |
50 | ||
eb805623 | 51 | |
4922d491 | 52 | |
9c5308ea | 53 | |
eb805623 DV |
54 | #define CSR_MAX_FW_SIZE 0x2FFF |
55 | #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF | |
eb805623 DV |
56 | |
57 | struct intel_css_header { | |
58 | /* 0x09 for DMC */ | |
59 | uint32_t module_type; | |
60 | ||
61 | /* Includes the DMC specific header in dwords */ | |
62 | uint32_t header_len; | |
63 | ||
64 | /* always value would be 0x10000 */ | |
65 | uint32_t header_ver; | |
66 | ||
67 | /* Not used */ | |
68 | uint32_t module_id; | |
69 | ||
70 | /* Not used */ | |
71 | uint32_t module_vendor; | |
72 | ||
73 | /* in YYYYMMDD format */ | |
74 | uint32_t date; | |
75 | ||
76 | /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ | |
77 | uint32_t size; | |
78 | ||
79 | /* Not used */ | |
80 | uint32_t key_size; | |
81 | ||
82 | /* Not used */ | |
83 | uint32_t modulus_size; | |
84 | ||
85 | /* Not used */ | |
86 | uint32_t exponent_size; | |
87 | ||
88 | /* Not used */ | |
89 | uint32_t reserved1[12]; | |
90 | ||
91 | /* Major Minor */ | |
92 | uint32_t version; | |
93 | ||
94 | /* Not used */ | |
95 | uint32_t reserved2[8]; | |
96 | ||
97 | /* Not used */ | |
98 | uint32_t kernel_header_info; | |
99 | } __packed; | |
100 | ||
101 | struct intel_fw_info { | |
102 | uint16_t reserved1; | |
103 | ||
104 | /* Stepping (A, B, C, ..., *). * is a wildcard */ | |
105 | char stepping; | |
106 | ||
107 | /* Sub-stepping (0, 1, ..., *). * is a wildcard */ | |
108 | char substepping; | |
109 | ||
110 | uint32_t offset; | |
111 | uint32_t reserved2; | |
112 | } __packed; | |
113 | ||
114 | struct intel_package_header { | |
115 | /* DMC container header length in dwords */ | |
116 | unsigned char header_len; | |
117 | ||
118 | /* always value would be 0x01 */ | |
119 | unsigned char header_ver; | |
120 | ||
121 | unsigned char reserved[10]; | |
122 | ||
123 | /* Number of valid entries in the FWInfo array below */ | |
124 | uint32_t num_entries; | |
125 | ||
126 | struct intel_fw_info fw_info[20]; | |
127 | } __packed; | |
128 | ||
129 | struct intel_dmc_header { | |
130 | /* always value would be 0x40403E3E */ | |
131 | uint32_t signature; | |
132 | ||
133 | /* DMC binary header length */ | |
134 | unsigned char header_len; | |
135 | ||
136 | /* 0x01 */ | |
137 | unsigned char header_ver; | |
138 | ||
139 | /* Reserved */ | |
140 | uint16_t dmcc_ver; | |
141 | ||
142 | /* Major, Minor */ | |
143 | uint32_t project; | |
144 | ||
145 | /* Firmware program size (excluding header) in dwords */ | |
146 | uint32_t fw_size; | |
147 | ||
148 | /* Major Minor version */ | |
149 | uint32_t fw_version; | |
150 | ||
151 | /* Number of valid MMIO cycles present. */ | |
152 | uint32_t mmio_count; | |
153 | ||
154 | /* MMIO address */ | |
155 | uint32_t mmioaddr[8]; | |
156 | ||
157 | /* MMIO data */ | |
158 | uint32_t mmiodata[8]; | |
159 | ||
160 | /* FW filename */ | |
161 | unsigned char dfile[32]; | |
162 | ||
163 | uint32_t reserved1[2]; | |
164 | } __packed; | |
165 | ||
166 | struct stepping_info { | |
167 | char stepping; | |
168 | char substepping; | |
169 | }; | |
170 | ||
a25c9f00 | 171 | static const struct stepping_info kbl_stepping_info[] = { |
4922d491 RV |
172 | {'A', '0'}, {'B', '0'}, {'C', '0'}, |
173 | {'D', '0'}, {'E', '0'}, {'F', '0'}, | |
174 | {'G', '0'}, {'H', '0'}, {'I', '0'}, | |
a25c9f00 RV |
175 | }; |
176 | ||
eb805623 | 177 | static const struct stepping_info skl_stepping_info[] = { |
84cb00ec JN |
178 | {'A', '0'}, {'B', '0'}, {'C', '0'}, |
179 | {'D', '0'}, {'E', '0'}, {'F', '0'}, | |
a41c8882 MM |
180 | {'G', '0'}, {'H', '0'}, {'I', '0'}, |
181 | {'J', '0'}, {'K', '0'} | |
eb805623 DV |
182 | }; |
183 | ||
b9cd5bfd | 184 | static const struct stepping_info bxt_stepping_info[] = { |
cff765fb AM |
185 | {'A', '0'}, {'A', '1'}, {'A', '2'}, |
186 | {'B', '0'}, {'B', '1'}, {'B', '2'} | |
187 | }; | |
188 | ||
1bb4308e CW |
189 | static const struct stepping_info no_stepping_info = { '*', '*' }; |
190 | ||
191 | static const struct stepping_info * | |
192 | intel_get_stepping_info(struct drm_i915_private *dev_priv) | |
eb805623 | 193 | { |
b1a14c6e JN |
194 | const struct stepping_info *si; |
195 | unsigned int size; | |
196 | ||
1bb4308e | 197 | if (IS_KABYLAKE(dev_priv)) { |
a25c9f00 RV |
198 | size = ARRAY_SIZE(kbl_stepping_info); |
199 | si = kbl_stepping_info; | |
1bb4308e | 200 | } else if (IS_SKYLAKE(dev_priv)) { |
b1a14c6e JN |
201 | size = ARRAY_SIZE(skl_stepping_info); |
202 | si = skl_stepping_info; | |
1bb4308e | 203 | } else if (IS_BROXTON(dev_priv)) { |
b1a14c6e JN |
204 | size = ARRAY_SIZE(bxt_stepping_info); |
205 | si = bxt_stepping_info; | |
206 | } else { | |
1bb4308e | 207 | size = 0; |
b1a14c6e | 208 | } |
eb805623 | 209 | |
1bb4308e CW |
210 | if (INTEL_REVID(dev_priv) < size) |
211 | return si + INTEL_REVID(dev_priv); | |
b1a14c6e | 212 | |
1bb4308e | 213 | return &no_stepping_info; |
eb805623 DV |
214 | } |
215 | ||
2abc525b ID |
216 | static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) |
217 | { | |
218 | uint32_t val, mask; | |
219 | ||
220 | mask = DC_STATE_DEBUG_MASK_MEMORY_UP; | |
221 | ||
222 | if (IS_BROXTON(dev_priv)) | |
223 | mask |= DC_STATE_DEBUG_MASK_CORES; | |
224 | ||
225 | /* The below bit doesn't need to be cleared ever afterwards */ | |
226 | val = I915_READ(DC_STATE_DEBUG); | |
227 | if ((val & mask) != mask) { | |
228 | val |= mask; | |
229 | I915_WRITE(DC_STATE_DEBUG, val); | |
230 | POSTING_READ(DC_STATE_DEBUG); | |
231 | } | |
232 | } | |
233 | ||
aa9145c4 AM |
234 | /** |
235 | * intel_csr_load_program() - write the firmware from memory to register. | |
f4448375 | 236 | * @dev_priv: i915 drm device. |
aa9145c4 AM |
237 | * |
238 | * CSR firmware is read from a .bin file and kept in internal memory one time. | |
239 | * Everytime display comes back from low power state this function is called to | |
240 | * copy the firmware from internal memory to registers. | |
241 | */ | |
2abc525b | 242 | void intel_csr_load_program(struct drm_i915_private *dev_priv) |
eb805623 | 243 | { |
a7f749f9 | 244 | u32 *payload = dev_priv->csr.dmc_payload; |
eb805623 DV |
245 | uint32_t i, fw_size; |
246 | ||
f4448375 | 247 | if (!IS_GEN9(dev_priv)) { |
eb805623 | 248 | DRM_ERROR("No CSR support available for this platform\n"); |
2abc525b | 249 | return; |
eb805623 DV |
250 | } |
251 | ||
fc131bf2 PJ |
252 | if (!dev_priv->csr.dmc_payload) { |
253 | DRM_ERROR("Tried to program CSR with empty payload\n"); | |
2abc525b | 254 | return; |
fc131bf2 | 255 | } |
4b7ab5fc | 256 | |
eb805623 DV |
257 | fw_size = dev_priv->csr.dmc_fw_size; |
258 | for (i = 0; i < fw_size; i++) | |
d2aa5ae8 | 259 | I915_WRITE(CSR_PROGRAM(i), payload[i]); |
eb805623 DV |
260 | |
261 | for (i = 0; i < dev_priv->csr.mmio_count; i++) { | |
262 | I915_WRITE(dev_priv->csr.mmioaddr[i], | |
f98f70d9 | 263 | dev_priv->csr.mmiodata[i]); |
eb805623 | 264 | } |
832dba88 PJ |
265 | |
266 | dev_priv->csr.dc_state = 0; | |
1e657ad7 | 267 | |
2abc525b | 268 | gen9_set_dc_state_debugmask(dev_priv); |
eb805623 DV |
269 | } |
270 | ||
6a6582bf DV |
271 | static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, |
272 | const struct firmware *fw) | |
eb805623 | 273 | { |
eb805623 DV |
274 | struct intel_css_header *css_header; |
275 | struct intel_package_header *package_header; | |
276 | struct intel_dmc_header *dmc_header; | |
277 | struct intel_csr *csr = &dev_priv->csr; | |
1bb4308e | 278 | const struct stepping_info *si = intel_get_stepping_info(dev_priv); |
eb805623 DV |
279 | uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; |
280 | uint32_t i; | |
a7f749f9 | 281 | uint32_t *dmc_payload; |
4aa7fb9c | 282 | uint32_t required_version; |
eb805623 | 283 | |
9c5308ea | 284 | if (!fw) |
6a6582bf | 285 | return NULL; |
eb805623 | 286 | |
eb805623 DV |
287 | /* Extract CSS Header information*/ |
288 | css_header = (struct intel_css_header *)fw->data; | |
289 | if (sizeof(struct intel_css_header) != | |
f98f70d9 | 290 | (css_header->header_len * 4)) { |
eb805623 | 291 | DRM_ERROR("Firmware has wrong CSS header length %u bytes\n", |
f98f70d9 | 292 | (css_header->header_len * 4)); |
6a6582bf | 293 | return NULL; |
eb805623 | 294 | } |
b6e7d894 DL |
295 | |
296 | csr->version = css_header->version; | |
297 | ||
4922d491 | 298 | if (IS_KABYLAKE(dev_priv)) { |
4aa7fb9c | 299 | required_version = KBL_CSR_VERSION_REQUIRED; |
4922d491 | 300 | } else if (IS_SKYLAKE(dev_priv)) { |
4aa7fb9c | 301 | required_version = SKL_CSR_VERSION_REQUIRED; |
e7968531 | 302 | } else if (IS_BROXTON(dev_priv)) { |
4aa7fb9c | 303 | required_version = BXT_CSR_VERSION_REQUIRED; |
e7968531 ID |
304 | } else { |
305 | MISSING_CASE(INTEL_REVID(dev_priv)); | |
4aa7fb9c | 306 | required_version = 0; |
e7968531 ID |
307 | } |
308 | ||
4aa7fb9c PJ |
309 | if (csr->version != required_version) { |
310 | DRM_INFO("Refusing to load DMC firmware v%u.%u," | |
311 | " please use v%u.%u [" FIRMWARE_URL "].\n", | |
9c5308ea MK |
312 | CSR_VERSION_MAJOR(csr->version), |
313 | CSR_VERSION_MINOR(csr->version), | |
4aa7fb9c PJ |
314 | CSR_VERSION_MAJOR(required_version), |
315 | CSR_VERSION_MINOR(required_version)); | |
6a6582bf | 316 | return NULL; |
9c5308ea MK |
317 | } |
318 | ||
eb805623 DV |
319 | readcount += sizeof(struct intel_css_header); |
320 | ||
321 | /* Extract Package Header information*/ | |
322 | package_header = (struct intel_package_header *) | |
f98f70d9 | 323 | &fw->data[readcount]; |
eb805623 | 324 | if (sizeof(struct intel_package_header) != |
f98f70d9 | 325 | (package_header->header_len * 4)) { |
eb805623 | 326 | DRM_ERROR("Firmware has wrong package header length %u bytes\n", |
f98f70d9 | 327 | (package_header->header_len * 4)); |
6a6582bf | 328 | return NULL; |
eb805623 DV |
329 | } |
330 | readcount += sizeof(struct intel_package_header); | |
331 | ||
332 | /* Search for dmc_offset to find firware binary. */ | |
333 | for (i = 0; i < package_header->num_entries; i++) { | |
334 | if (package_header->fw_info[i].substepping == '*' && | |
1bb4308e | 335 | si->stepping == package_header->fw_info[i].stepping) { |
eb805623 DV |
336 | dmc_offset = package_header->fw_info[i].offset; |
337 | break; | |
1bb4308e CW |
338 | } else if (si->stepping == package_header->fw_info[i].stepping && |
339 | si->substepping == package_header->fw_info[i].substepping) { | |
eb805623 DV |
340 | dmc_offset = package_header->fw_info[i].offset; |
341 | break; | |
342 | } else if (package_header->fw_info[i].stepping == '*' && | |
f98f70d9 | 343 | package_header->fw_info[i].substepping == '*') |
eb805623 DV |
344 | dmc_offset = package_header->fw_info[i].offset; |
345 | } | |
346 | if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { | |
1bb4308e CW |
347 | DRM_ERROR("Firmware not supported for %c stepping\n", |
348 | si->stepping); | |
6a6582bf | 349 | return NULL; |
eb805623 DV |
350 | } |
351 | readcount += dmc_offset; | |
352 | ||
353 | /* Extract dmc_header information. */ | |
354 | dmc_header = (struct intel_dmc_header *)&fw->data[readcount]; | |
355 | if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) { | |
356 | DRM_ERROR("Firmware has wrong dmc header length %u bytes\n", | |
f98f70d9 | 357 | (dmc_header->header_len)); |
6a6582bf | 358 | return NULL; |
eb805623 DV |
359 | } |
360 | readcount += sizeof(struct intel_dmc_header); | |
361 | ||
362 | /* Cache the dmc header info. */ | |
363 | if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) { | |
364 | DRM_ERROR("Firmware has wrong mmio count %u\n", | |
f98f70d9 | 365 | dmc_header->mmio_count); |
6a6582bf | 366 | return NULL; |
eb805623 DV |
367 | } |
368 | csr->mmio_count = dmc_header->mmio_count; | |
369 | for (i = 0; i < dmc_header->mmio_count; i++) { | |
982b0b2d | 370 | if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE || |
f98f70d9 | 371 | dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) { |
eb805623 | 372 | DRM_ERROR(" Firmware has wrong mmio address 0x%x\n", |
f98f70d9 | 373 | dmc_header->mmioaddr[i]); |
6a6582bf | 374 | return NULL; |
eb805623 | 375 | } |
f0f59a00 | 376 | csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]); |
eb805623 DV |
377 | csr->mmiodata[i] = dmc_header->mmiodata[i]; |
378 | } | |
379 | ||
380 | /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ | |
381 | nbytes = dmc_header->fw_size * 4; | |
382 | if (nbytes > CSR_MAX_FW_SIZE) { | |
383 | DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes); | |
6a6582bf | 384 | return NULL; |
eb805623 DV |
385 | } |
386 | csr->dmc_fw_size = dmc_header->fw_size; | |
387 | ||
6a6582bf DV |
388 | dmc_payload = kmalloc(nbytes, GFP_KERNEL); |
389 | if (!dmc_payload) { | |
eb805623 | 390 | DRM_ERROR("Memory allocation failed for dmc payload\n"); |
6a6582bf | 391 | return NULL; |
eb805623 DV |
392 | } |
393 | ||
1bb4308e | 394 | return memcpy(dmc_payload, &fw->data[readcount], nbytes); |
6a6582bf DV |
395 | } |
396 | ||
8144ac59 | 397 | static void csr_load_work_fn(struct work_struct *work) |
6a6582bf | 398 | { |
8144ac59 DV |
399 | struct drm_i915_private *dev_priv; |
400 | struct intel_csr *csr; | |
401 | const struct firmware *fw; | |
402 | int ret; | |
403 | ||
404 | dev_priv = container_of(work, typeof(*dev_priv), csr.work); | |
405 | csr = &dev_priv->csr; | |
6a6582bf | 406 | |
8144ac59 | 407 | ret = request_firmware(&fw, dev_priv->csr.fw_path, |
91c8a326 | 408 | &dev_priv->drm.pdev->dev); |
2abc525b ID |
409 | if (fw) |
410 | dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw); | |
6a6582bf | 411 | |
6a6582bf | 412 | if (dev_priv->csr.dmc_payload) { |
2abc525b ID |
413 | intel_csr_load_program(dev_priv); |
414 | ||
01a6908c | 415 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
9c5308ea MK |
416 | |
417 | DRM_INFO("Finished loading %s (v%u.%u)\n", | |
418 | dev_priv->csr.fw_path, | |
419 | CSR_VERSION_MAJOR(csr->version), | |
420 | CSR_VERSION_MINOR(csr->version)); | |
421 | } else { | |
91c8a326 | 422 | dev_notice(dev_priv->drm.dev, |
cbfc2d26 CW |
423 | "Failed to load DMC firmware" |
424 | " [" FIRMWARE_URL "]," | |
425 | " disabling runtime power management.\n"); | |
9c5308ea MK |
426 | } |
427 | ||
eb805623 DV |
428 | release_firmware(fw); |
429 | } | |
430 | ||
aa9145c4 AM |
431 | /** |
432 | * intel_csr_ucode_init() - initialize the firmware loading. | |
f4448375 | 433 | * @dev_priv: i915 drm device. |
aa9145c4 AM |
434 | * |
435 | * This function is called at the time of loading the display driver to read | |
436 | * firmware from a .bin file and copied into a internal memory. | |
437 | */ | |
f4448375 | 438 | void intel_csr_ucode_init(struct drm_i915_private *dev_priv) |
eb805623 | 439 | { |
eb805623 | 440 | struct intel_csr *csr = &dev_priv->csr; |
8144ac59 DV |
441 | |
442 | INIT_WORK(&dev_priv->csr.work, csr_load_work_fn); | |
eb805623 | 443 | |
f4448375 | 444 | if (!HAS_CSR(dev_priv)) |
eb805623 DV |
445 | return; |
446 | ||
4922d491 RV |
447 | if (IS_KABYLAKE(dev_priv)) |
448 | csr->fw_path = I915_CSR_KBL; | |
449 | else if (IS_SKYLAKE(dev_priv)) | |
eb805623 | 450 | csr->fw_path = I915_CSR_SKL; |
18c237c0 AM |
451 | else if (IS_BROXTON(dev_priv)) |
452 | csr->fw_path = I915_CSR_BXT; | |
eb805623 DV |
453 | else { |
454 | DRM_ERROR("Unexpected: no known CSR firmware for platform\n"); | |
455 | return; | |
456 | } | |
457 | ||
abd41dc9 DL |
458 | DRM_DEBUG_KMS("Loading %s\n", csr->fw_path); |
459 | ||
dc174300 SS |
460 | /* |
461 | * Obtain a runtime pm reference, until CSR is loaded, | |
462 | * to avoid entering runtime-suspend. | |
463 | */ | |
01a6908c | 464 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
dc174300 | 465 | |
8144ac59 | 466 | schedule_work(&dev_priv->csr.work); |
eb805623 DV |
467 | } |
468 | ||
f74ed08d ID |
469 | /** |
470 | * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend | |
471 | * @dev_priv: i915 drm device | |
472 | * | |
473 | * Prepare the DMC firmware before entering system suspend. This includes | |
474 | * flushing pending work items and releasing any resources acquired during | |
475 | * init. | |
476 | */ | |
477 | void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) | |
478 | { | |
479 | if (!HAS_CSR(dev_priv)) | |
480 | return; | |
481 | ||
482 | flush_work(&dev_priv->csr.work); | |
483 | ||
484 | /* Drop the reference held in case DMC isn't loaded. */ | |
485 | if (!dev_priv->csr.dmc_payload) | |
486 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
487 | } | |
488 | ||
489 | /** | |
490 | * intel_csr_ucode_resume() - init CSR firmware during system resume | |
491 | * @dev_priv: i915 drm device | |
492 | * | |
493 | * Reinitialize the DMC firmware during system resume, reacquiring any | |
494 | * resources released in intel_csr_ucode_suspend(). | |
495 | */ | |
496 | void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) | |
497 | { | |
498 | if (!HAS_CSR(dev_priv)) | |
499 | return; | |
500 | ||
501 | /* | |
502 | * Reacquire the reference to keep RPM disabled in case DMC isn't | |
503 | * loaded. | |
504 | */ | |
505 | if (!dev_priv->csr.dmc_payload) | |
506 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
507 | } | |
508 | ||
aa9145c4 AM |
509 | /** |
510 | * intel_csr_ucode_fini() - unload the CSR firmware. | |
f4448375 | 511 | * @dev_priv: i915 drm device. |
aa9145c4 | 512 | * |
f74ed08d | 513 | * Firmmware unloading includes freeing the internal memory and reset the |
aa9145c4 AM |
514 | * firmware loading status. |
515 | */ | |
f4448375 | 516 | void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) |
eb805623 | 517 | { |
f4448375 | 518 | if (!HAS_CSR(dev_priv)) |
eb805623 DV |
519 | return; |
520 | ||
f74ed08d | 521 | intel_csr_ucode_suspend(dev_priv); |
15e72c1f | 522 | |
eb805623 DV |
523 | kfree(dev_priv->csr.dmc_payload); |
524 | } |