[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_csr.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */
#include <linux/firmware.h>
#include "i915_drv.h"
#include "i915_reg.h"

/**
 * DOC: csr support for dmc
 *
 * Display Context Save and Restore (CSR) firmware support added from gen9
 * onwards to drive newly added DMC (Display microcontroller) in display
 * engine to save and restore the state of display engine when it enter into
 * low-power state and comes back to normal.
 *
 * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
 * FW_LOADED, FW_FAILED.
 *
 * Once the firmware is written into the registers status will be moved from
 * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
 * be moved to FW_FAILED.
 */

#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
MODULE_FIRMWARE(I915_CSR_KBL);
#define KBL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 1)

#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
MODULE_FIRMWARE(I915_CSR_SKL);
#define SKL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 23)

#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
MODULE_FIRMWARE(I915_CSR_BXT);
#define BXT_CSR_VERSION_REQUIRED	CSR_VERSION(1, 7)

#define FIRMWARE_URL  "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"


#define CSR_MAX_FW_SIZE			0x2FFF
#define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF

struct intel_css_header {
	/* 0x09 for DMC */
	uint32_t module_type;

	/* Includes the DMC specific header in dwords */
	uint32_t header_len;

	/* always value would be 0x10000 */
	uint32_t header_ver;

	/* Not used */
	uint32_t module_id;

	/* Not used */
	uint32_t module_vendor;

	/* in YYYYMMDD format */
	uint32_t date;

	/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
	uint32_t size;

	/* Not used */
	uint32_t key_size;

	/* Not used */
	uint32_t modulus_size;

	/* Not used */
	uint32_t exponent_size;

	/* Not used */
	uint32_t reserved1[12];

	/* Major Minor */
	uint32_t version;

	/* Not used */
	uint32_t reserved2[8];

	/* Not used */
	uint32_t kernel_header_info;
} __packed;

struct intel_fw_info {
	uint16_t reserved1;

	/* Stepping (A, B, C, ..., *). * is a wildcard */
	char stepping;

	/* Sub-stepping (0, 1, ..., *). * is a wildcard */
	char substepping;

	uint32_t offset;
	uint32_t reserved2;
} __packed;

struct intel_package_header {
	/* DMC container header length in dwords */
	unsigned char header_len;

	/* always value would be 0x01 */
	unsigned char header_ver;

	unsigned char reserved[10];

	/* Number of valid entries in the FWInfo array below */
	uint32_t num_entries;

	struct intel_fw_info fw_info[20];
} __packed;

struct intel_dmc_header {
	/* always value would be 0x40403E3E */
	uint32_t signature;

	/* DMC binary header length */
	unsigned char header_len;

	/* 0x01 */
	unsigned char header_ver;

	/* Reserved */
	uint16_t dmcc_ver;

	/* Major, Minor */
	uint32_t	project;

	/* Firmware program size (excluding header) in dwords */
	uint32_t	fw_size;

	/* Major Minor version */
	uint32_t fw_version;

	/* Number of valid MMIO cycles present. */
	uint32_t mmio_count;

	/* MMIO address */
	uint32_t mmioaddr[8];

	/* MMIO data */
	uint32_t mmiodata[8];

	/* FW filename  */
	unsigned char dfile[32];

	uint32_t reserved1[2];
} __packed;

struct stepping_info {
	char stepping;
	char substepping;
};

static const struct stepping_info kbl_stepping_info[] = {
	{'A', '0'}, {'B', '0'}, {'C', '0'},
	{'D', '0'}, {'E', '0'}, {'F', '0'},
	{'G', '0'}, {'H', '0'}, {'I', '0'},
};

static const struct stepping_info skl_stepping_info[] = {
	{'A', '0'}, {'B', '0'}, {'C', '0'},
	{'D', '0'}, {'E', '0'}, {'F', '0'},
	{'G', '0'}, {'H', '0'}, {'I', '0'},
	{'J', '0'}, {'K', '0'}
};

static const struct stepping_info bxt_stepping_info[] = {
	{'A', '0'}, {'A', '1'}, {'A', '2'},
	{'B', '0'}, {'B', '1'}, {'B', '2'}
};

static const struct stepping_info no_stepping_info = { '*', '*' };

static const struct stepping_info *
intel_get_stepping_info(struct drm_i915_private *dev_priv)
{
	const struct stepping_info *si;
	unsigned int size;

	if (IS_KABYLAKE(dev_priv)) {
		size = ARRAY_SIZE(kbl_stepping_info);
		si = kbl_stepping_info;
	} else if (IS_SKYLAKE(dev_priv)) {
		size = ARRAY_SIZE(skl_stepping_info);
		si = skl_stepping_info;
	} else if (IS_BROXTON(dev_priv)) {
		size = ARRAY_SIZE(bxt_stepping_info);
		si = bxt_stepping_info;
	} else {
		size = 0;
	}

	if (INTEL_REVID(dev_priv) < size)
		return si + INTEL_REVID(dev_priv);

	return &no_stepping_info;
}

static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
{
	uint32_t val, mask;

	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;

	if (IS_BROXTON(dev_priv))
		mask |= DC_STATE_DEBUG_MASK_CORES;

	/* The below bit doesn't need to be cleared ever afterwards */
	val = I915_READ(DC_STATE_DEBUG);
	if ((val & mask) != mask) {
		val |= mask;
		I915_WRITE(DC_STATE_DEBUG, val);
		POSTING_READ(DC_STATE_DEBUG);
	}
}

/**
 * intel_csr_load_program() - write the firmware from memory to register.
 * @dev_priv: i915 drm device.
 *
 * CSR firmware is read from a .bin file and kept in internal memory one time.
 * Everytime display comes back from low power state this function is called to
 * copy the firmware from internal memory to registers.
 */
void intel_csr_load_program(struct drm_i915_private *dev_priv)
{
	u32 *payload = dev_priv->csr.dmc_payload;
	uint32_t i, fw_size;

	if (!IS_GEN9(dev_priv)) {
		DRM_ERROR("No CSR support available for this platform\n");
		return;
	}

	if (!dev_priv->csr.dmc_payload) {
		DRM_ERROR("Tried to program CSR with empty payload\n");
		return;
	}

	fw_size = dev_priv->csr.dmc_fw_size;
	for (i = 0; i < fw_size; i++)
		I915_WRITE(CSR_PROGRAM(i), payload[i]);

	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
		I915_WRITE(dev_priv->csr.mmioaddr[i],
			   dev_priv->csr.mmiodata[i]);
	}

	dev_priv->csr.dc_state = 0;

	gen9_set_dc_state_debugmask(dev_priv);
}

static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
			      const struct firmware *fw)
{
	struct intel_css_header *css_header;
	struct intel_package_header *package_header;
	struct intel_dmc_header *dmc_header;
	struct intel_csr *csr = &dev_priv->csr;
	const struct stepping_info *si = intel_get_stepping_info(dev_priv);
	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
	uint32_t i;
	uint32_t *dmc_payload;
	uint32_t required_min_version;

	if (!fw)
		return NULL;

	/* Extract CSS Header information*/
	css_header = (struct intel_css_header *)fw->data;
	if (sizeof(struct intel_css_header) !=
	    (css_header->header_len * 4)) {
		DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
			  (css_header->header_len * 4));
		return NULL;
	}

	csr->version = css_header->version;

	if (IS_KABYLAKE(dev_priv)) {
		required_min_version = KBL_CSR_VERSION_REQUIRED;
	} else if (IS_SKYLAKE(dev_priv)) {
		required_min_version = SKL_CSR_VERSION_REQUIRED;
	} else if (IS_BROXTON(dev_priv)) {
		required_min_version = BXT_CSR_VERSION_REQUIRED;
	} else {
		MISSING_CASE(INTEL_REVID(dev_priv));
		required_min_version = 0;
	}

	if (csr->version < required_min_version) {
		DRM_INFO("Refusing to load old DMC firmware v%u.%u,"
			 " please upgrade to v%u.%u or later"
			   " [" FIRMWARE_URL "].\n",
			 CSR_VERSION_MAJOR(csr->version),
			 CSR_VERSION_MINOR(csr->version),
			 CSR_VERSION_MAJOR(required_min_version),
			 CSR_VERSION_MINOR(required_min_version));
		return NULL;
	}

	readcount += sizeof(struct intel_css_header);

	/* Extract Package Header information*/
	package_header = (struct intel_package_header *)
		&fw->data[readcount];
	if (sizeof(struct intel_package_header) !=
	    (package_header->header_len * 4)) {
		DRM_ERROR("Firmware has wrong package header length %u bytes\n",
			  (package_header->header_len * 4));
		return NULL;
	}
	readcount += sizeof(struct intel_package_header);

	/* Search for dmc_offset to find firware binary. */
	for (i = 0; i < package_header->num_entries; i++) {
		if (package_header->fw_info[i].substepping == '*' &&
		    si->stepping == package_header->fw_info[i].stepping) {
			dmc_offset = package_header->fw_info[i].offset;
			break;
		} else if (si->stepping == package_header->fw_info[i].stepping &&
			   si->substepping == package_header->fw_info[i].substepping) {
			dmc_offset = package_header->fw_info[i].offset;
			break;
		} else if (package_header->fw_info[i].stepping == '*' &&
			   package_header->fw_info[i].substepping == '*')
			dmc_offset = package_header->fw_info[i].offset;
	}
	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
		DRM_ERROR("Firmware not supported for %c stepping\n",
			  si->stepping);
		return NULL;
	}
	readcount += dmc_offset;

	/* Extract dmc_header information. */
	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
		DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
			  (dmc_header->header_len));
		return NULL;
	}
	readcount += sizeof(struct intel_dmc_header);

	/* Cache the dmc header info. */
	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
		DRM_ERROR("Firmware has wrong mmio count %u\n",
			  dmc_header->mmio_count);
		return NULL;
	}
	csr->mmio_count = dmc_header->mmio_count;
	for (i = 0; i < dmc_header->mmio_count; i++) {
		if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
		    dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
			DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
				  dmc_header->mmioaddr[i]);
			return NULL;
		}
		csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
		csr->mmiodata[i] = dmc_header->mmiodata[i];
	}

	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
	nbytes = dmc_header->fw_size * 4;
	if (nbytes > CSR_MAX_FW_SIZE) {
		DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
		return NULL;
	}
	csr->dmc_fw_size = dmc_header->fw_size;

	dmc_payload = kmalloc(nbytes, GFP_KERNEL);
	if (!dmc_payload) {
		DRM_ERROR("Memory allocation failed for dmc payload\n");
		return NULL;
	}

	return memcpy(dmc_payload, &fw->data[readcount], nbytes);
}

static void csr_load_work_fn(struct work_struct *work)
{
	struct drm_i915_private *dev_priv;
	struct intel_csr *csr;
	const struct firmware *fw;
	int ret;

	dev_priv = container_of(work, typeof(*dev_priv), csr.work);
	csr = &dev_priv->csr;

	ret = request_firmware(&fw, dev_priv->csr.fw_path,
			       &dev_priv->dev->pdev->dev);
	if (fw)
		dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);

	if (dev_priv->csr.dmc_payload) {
		intel_csr_load_program(dev_priv);

		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);

		DRM_INFO("Finished loading %s (v%u.%u)\n",
			 dev_priv->csr.fw_path,
			 CSR_VERSION_MAJOR(csr->version),
			 CSR_VERSION_MINOR(csr->version));
	} else {
		dev_notice(dev_priv->dev->dev,
			   "Failed to load DMC firmware"
			   " [" FIRMWARE_URL "],"
			   " disabling runtime power management.\n");
	}

	release_firmware(fw);
}

/**
 * intel_csr_ucode_init() - initialize the firmware loading.
 * @dev_priv: i915 drm device.
 *
 * This function is called at the time of loading the display driver to read
 * firmware from a .bin file and copied into a internal memory.
 */
void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
{
	struct intel_csr *csr = &dev_priv->csr;

	INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);

	if (!HAS_CSR(dev_priv))
		return;

	if (IS_KABYLAKE(dev_priv))
		csr->fw_path = I915_CSR_KBL;
	else if (IS_SKYLAKE(dev_priv))
		csr->fw_path = I915_CSR_SKL;
	else if (IS_BROXTON(dev_priv))
		csr->fw_path = I915_CSR_BXT;
	else {
		DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
		return;
	}

	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);

	/*
	 * Obtain a runtime pm reference, until CSR is loaded,
	 * to avoid entering runtime-suspend.
	 */
	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);

	schedule_work(&dev_priv->csr.work);
}

/**
 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
 * @dev_priv: i915 drm device
 *
 * Prepare the DMC firmware before entering system suspend. This includes
 * flushing pending work items and releasing any resources acquired during
 * init.
 */
void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
{
	if (!HAS_CSR(dev_priv))
		return;

	flush_work(&dev_priv->csr.work);

	/* Drop the reference held in case DMC isn't loaded. */
	if (!dev_priv->csr.dmc_payload)
		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
}

/**
 * intel_csr_ucode_resume() - init CSR firmware during system resume
 * @dev_priv: i915 drm device
 *
 * Reinitialize the DMC firmware during system resume, reacquiring any
 * resources released in intel_csr_ucode_suspend().
 */
void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
{
	if (!HAS_CSR(dev_priv))
		return;

	/*
	 * Reacquire the reference to keep RPM disabled in case DMC isn't
	 * loaded.
	 */
	if (!dev_priv->csr.dmc_payload)
		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
}

/**
 * intel_csr_ucode_fini() - unload the CSR firmware.
 * @dev_priv: i915 drm device.
 *
 * Firmmware unloading includes freeing the internal memory and reset the
 * firmware loading status.
 */
void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
{
	if (!HAS_CSR(dev_priv))
		return;

	intel_csr_ucode_suspend(dev_priv);

	kfree(dev_priv->csr.dmc_payload);
}
Commit	Line	Data
eb805623 DV	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24	#include <linux/firmware.h>
	25	#include "i915_drv.h"
	26	#include "i915_reg.h"
	27
aa9145c4 AM	28	/**
	29	* DOC: csr support for dmc
	30	*
	31	* Display Context Save and Restore (CSR) firmware support added from gen9
	32	* onwards to drive newly added DMC (Display microcontroller) in display
	33	* engine to save and restore the state of display engine when it enter into
	34	* low-power state and comes back to normal.
	35	*
	36	* Firmware loading status will be one of the below states: FW_UNINITIALIZED,
	37	* FW_LOADED, FW_FAILED.
	38	*
	39	* Once the firmware is written into the registers status will be moved from
	40	* FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
	41	* be moved to FW_FAILED.
	42	*/
	43
a4a027a8 RV	44	#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
	45	MODULE_FIRMWARE(I915_CSR_KBL);
	46	#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
	47
bf546f81	48	#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
a4a027a8 RV	49	MODULE_FIRMWARE(I915_CSR_SKL);
	50	#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
	51
18c237c0	52	#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
a4a027a8 RV	53	MODULE_FIRMWARE(I915_CSR_BXT);
a4a027a8 RV	54	#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
eb805623	55
cbfc2d26 CW	56	#define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
cbfc2d26 CW	57
eb805623	58
a4a027a8	59
9c5308ea	60
eb805623 DV	61	#define CSR_MAX_FW_SIZE 0x2FFF
eb805623 DV	62	#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
eb805623 DV	63
	64	struct intel_css_header {
	65	/* 0x09 for DMC */
	66	uint32_t module_type;
	67
	68	/* Includes the DMC specific header in dwords */
	69	uint32_t header_len;
	70
	71	/* always value would be 0x10000 */
	72	uint32_t header_ver;
	73
	74	/* Not used */
	75	uint32_t module_id;
	76
	77	/* Not used */
	78	uint32_t module_vendor;
	79
	80	/* in YYYYMMDD format */
	81	uint32_t date;
	82
	83	/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
	84	uint32_t size;
	85
	86	/* Not used */
	87	uint32_t key_size;
	88
	89	/* Not used */
	90	uint32_t modulus_size;
	91
	92	/* Not used */
	93	uint32_t exponent_size;
	94
	95	/* Not used */
	96	uint32_t reserved1[12];
	97
	98	/* Major Minor */
	99	uint32_t version;
	100
	101	/* Not used */
	102	uint32_t reserved2[8];
	103
	104	/* Not used */
	105	uint32_t kernel_header_info;
	106	} __packed;
	107
	108	struct intel_fw_info {
	109	uint16_t reserved1;
	110
	111	/* Stepping (A, B, C, ..., ). is a wildcard */
	112	char stepping;
	113
	114	/* Sub-stepping (0, 1, ..., ). is a wildcard */
	115	char substepping;
	116
	117	uint32_t offset;
	118	uint32_t reserved2;
	119	} __packed;
	120
	121	struct intel_package_header {
	122	/* DMC container header length in dwords */
	123	unsigned char header_len;
	124
	125	/* always value would be 0x01 */
	126	unsigned char header_ver;
127
128	unsigned char reserved[10];
129
130	/* Number of valid entries in the FWInfo array below */
131	uint32_t num_entries;
132
133	struct intel_fw_info fw_info[20];
134	} __packed;
135
136	struct intel_dmc_header {
137	/* always value would be 0x40403E3E */
138	uint32_t signature;
139
140	/* DMC binary header length */
141	unsigned char header_len;
142
143	/* 0x01 */
144	unsigned char header_ver;
145
146	/* Reserved */
147	uint16_t dmcc_ver;
148
149	/* Major, Minor */
150	uint32_t project;
151
152	/* Firmware program size (excluding header) in dwords */
153	uint32_t fw_size;
154
155	/* Major Minor version */
156	uint32_t fw_version;
157
158	/* Number of valid MMIO cycles present. */
159	uint32_t mmio_count;
160
161	/* MMIO address */
162	uint32_t mmioaddr[8];
163
164	/* MMIO data */
165	uint32_t mmiodata[8];
166
167	/* FW filename */
168	unsigned char dfile[32];
169
170	uint32_t reserved1[2];
171	} __packed;
172
173	struct stepping_info {
174	char stepping;
175	char substepping;
176	};
177
a25c9f00	178	static const struct stepping_info kbl_stepping_info[] = {
a4a027a8 RV	179	{'A', '0'}, {'B', '0'}, {'C', '0'},
	180	{'D', '0'}, {'E', '0'}, {'F', '0'},
	181	{'G', '0'}, {'H', '0'}, {'I', '0'},
a25c9f00 RV	182	};
a25c9f00 RV	183
eb805623	184	static const struct stepping_info skl_stepping_info[] = {
84cb00ec JN	185	{'A', '0'}, {'B', '0'}, {'C', '0'},
84cb00ec JN	186	{'D', '0'}, {'E', '0'}, {'F', '0'},
a41c8882 MM	187	{'G', '0'}, {'H', '0'}, {'I', '0'},
a41c8882 MM	188	{'J', '0'}, {'K', '0'}
eb805623 DV	189	};
eb805623 DV	190
b9cd5bfd	191	static const struct stepping_info bxt_stepping_info[] = {
cff765fb AM	192	{'A', '0'}, {'A', '1'}, {'A', '2'},
	193	{'B', '0'}, {'B', '1'}, {'B', '2'}
	194	};
	195
1bb4308e CW	196	static const struct stepping_info no_stepping_info = { '', '' };
	197
	198	static const struct stepping_info *
	199	intel_get_stepping_info(struct drm_i915_private *dev_priv)
eb805623	200	{
b1a14c6e JN	201	const struct stepping_info *si;
	202	unsigned int size;
	203
1bb4308e	204	if (IS_KABYLAKE(dev_priv)) {
a25c9f00 RV	205	size = ARRAY_SIZE(kbl_stepping_info);
a25c9f00 RV	206	si = kbl_stepping_info;
1bb4308e	207	} else if (IS_SKYLAKE(dev_priv)) {
b1a14c6e JN	208	size = ARRAY_SIZE(skl_stepping_info);
b1a14c6e JN	209	si = skl_stepping_info;
1bb4308e	210	} else if (IS_BROXTON(dev_priv)) {
b1a14c6e JN	211	size = ARRAY_SIZE(bxt_stepping_info);
	212	si = bxt_stepping_info;
	213	} else {
1bb4308e	214	size = 0;
b1a14c6e	215	}
eb805623	216
1bb4308e CW	217	if (INTEL_REVID(dev_priv) < size)
1bb4308e CW	218	return si + INTEL_REVID(dev_priv);
b1a14c6e	219
1bb4308e	220	return &no_stepping_info;
eb805623 DV	221	}
eb805623 DV	222
2abc525b ID	223	static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
	224	{
	225	uint32_t val, mask;
	226
	227	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
	228
	229	if (IS_BROXTON(dev_priv))
	230	mask \|= DC_STATE_DEBUG_MASK_CORES;
	231
	232	/* The below bit doesn't need to be cleared ever afterwards */
	233	val = I915_READ(DC_STATE_DEBUG);
	234	if ((val & mask) != mask) {
	235	val \|= mask;
	236	I915_WRITE(DC_STATE_DEBUG, val);
	237	POSTING_READ(DC_STATE_DEBUG);
	238	}
	239	}
	240
aa9145c4 AM	241	/**
aa9145c4 AM	242	* intel_csr_load_program() - write the firmware from memory to register.
f4448375	243	* @dev_priv: i915 drm device.
aa9145c4 AM	244	*
	245	* CSR firmware is read from a .bin file and kept in internal memory one time.
	246	* Everytime display comes back from low power state this function is called to
	247	* copy the firmware from internal memory to registers.
	248	*/
2abc525b	249	void intel_csr_load_program(struct drm_i915_private *dev_priv)
eb805623	250	{
a7f749f9	251	u32 *payload = dev_priv->csr.dmc_payload;
eb805623 DV	252	uint32_t i, fw_size;
eb805623 DV	253
f4448375	254	if (!IS_GEN9(dev_priv)) {
eb805623	255	DRM_ERROR("No CSR support available for this platform\n");
2abc525b	256	return;
eb805623 DV	257	}
eb805623 DV	258
fc131bf2 PJ	259	if (!dev_priv->csr.dmc_payload) {
fc131bf2 PJ	260	DRM_ERROR("Tried to program CSR with empty payload\n");
2abc525b	261	return;
fc131bf2	262	}
4b7ab5fc	263
eb805623 DV	264	fw_size = dev_priv->csr.dmc_fw_size;
eb805623 DV	265	for (i = 0; i < fw_size; i++)
d2aa5ae8	266	I915_WRITE(CSR_PROGRAM(i), payload[i]);
eb805623 DV	267
	268	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
	269	I915_WRITE(dev_priv->csr.mmioaddr[i],
f98f70d9	270	dev_priv->csr.mmiodata[i]);
eb805623	271	}
832dba88 PJ	272
832dba88 PJ	273	dev_priv->csr.dc_state = 0;
1e657ad7	274
2abc525b	275	gen9_set_dc_state_debugmask(dev_priv);
eb805623 DV	276	}
eb805623 DV	277
6a6582bf DV	278	static uint32_t parse_csr_fw(struct drm_i915_private dev_priv,
6a6582bf DV	279	const struct firmware *fw)
eb805623	280	{
eb805623 DV	281	struct intel_css_header *css_header;
	282	struct intel_package_header *package_header;
	283	struct intel_dmc_header *dmc_header;
	284	struct intel_csr *csr = &dev_priv->csr;
1bb4308e	285	const struct stepping_info *si = intel_get_stepping_info(dev_priv);
eb805623 DV	286	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
eb805623 DV	287	uint32_t i;
a7f749f9	288	uint32_t *dmc_payload;
e7968531	289	uint32_t required_min_version;
eb805623	290
9c5308ea	291	if (!fw)
6a6582bf	292	return NULL;
eb805623	293
eb805623 DV	294	/* Extract CSS Header information*/
	295	css_header = (struct intel_css_header *)fw->data;
	296	if (sizeof(struct intel_css_header) !=
f98f70d9	297	(css_header->header_len * 4)) {
eb805623	298	DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
f98f70d9	299	(css_header->header_len * 4));
6a6582bf	300	return NULL;
eb805623	301	}
b6e7d894 DL	302
	303	csr->version = css_header->version;
	304
a4a027a8 RV	305	if (IS_KABYLAKE(dev_priv)) {
	306	required_min_version = KBL_CSR_VERSION_REQUIRED;
	307	} else if (IS_SKYLAKE(dev_priv)) {
e7968531 ID	308	required_min_version = SKL_CSR_VERSION_REQUIRED;
	309	} else if (IS_BROXTON(dev_priv)) {
	310	required_min_version = BXT_CSR_VERSION_REQUIRED;
	311	} else {
	312	MISSING_CASE(INTEL_REVID(dev_priv));
	313	required_min_version = 0;
	314	}
	315
	316	if (csr->version < required_min_version) {
	317	DRM_INFO("Refusing to load old DMC firmware v%u.%u,"
9c5308ea	318	" please upgrade to v%u.%u or later"
cbfc2d26	319	" [" FIRMWARE_URL "].\n",
9c5308ea MK	320	CSR_VERSION_MAJOR(csr->version),
9c5308ea MK	321	CSR_VERSION_MINOR(csr->version),
e7968531 ID	322	CSR_VERSION_MAJOR(required_min_version),
e7968531 ID	323	CSR_VERSION_MINOR(required_min_version));
6a6582bf	324	return NULL;
9c5308ea MK	325	}
9c5308ea MK	326
eb805623 DV	327	readcount += sizeof(struct intel_css_header);
	328
	329	/* Extract Package Header information*/
	330	package_header = (struct intel_package_header *)
f98f70d9	331	&fw->data[readcount];
eb805623	332	if (sizeof(struct intel_package_header) !=
f98f70d9	333	(package_header->header_len * 4)) {
eb805623	334	DRM_ERROR("Firmware has wrong package header length %u bytes\n",
f98f70d9	335	(package_header->header_len * 4));
6a6582bf	336	return NULL;
eb805623 DV	337	}
	338	readcount += sizeof(struct intel_package_header);
	339
	340	/* Search for dmc_offset to find firware binary. */
	341	for (i = 0; i < package_header->num_entries; i++) {
	342	if (package_header->fw_info[i].substepping == '*' &&
1bb4308e	343	si->stepping == package_header->fw_info[i].stepping) {
eb805623 DV	344	dmc_offset = package_header->fw_info[i].offset;
eb805623 DV	345	break;
1bb4308e CW	346	} else if (si->stepping == package_header->fw_info[i].stepping &&
1bb4308e CW	347	si->substepping == package_header->fw_info[i].substepping) {
eb805623 DV	348	dmc_offset = package_header->fw_info[i].offset;
	349	break;
	350	} else if (package_header->fw_info[i].stepping == '*' &&
f98f70d9	351	package_header->fw_info[i].substepping == '*')
eb805623 DV	352	dmc_offset = package_header->fw_info[i].offset;
	353	}
	354	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
1bb4308e CW	355	DRM_ERROR("Firmware not supported for %c stepping\n",
1bb4308e CW	356	si->stepping);
6a6582bf	357	return NULL;
eb805623 DV	358	}
	359	readcount += dmc_offset;
	360
	361	/* Extract dmc_header information. */
	362	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
	363	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
	364	DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
f98f70d9	365	(dmc_header->header_len));
6a6582bf	366	return NULL;
eb805623 DV	367	}
	368	readcount += sizeof(struct intel_dmc_header);
	369
	370	/* Cache the dmc header info. */
	371	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
	372	DRM_ERROR("Firmware has wrong mmio count %u\n",
f98f70d9	373	dmc_header->mmio_count);
6a6582bf	374	return NULL;
eb805623 DV	375	}
	376	csr->mmio_count = dmc_header->mmio_count;
	377	for (i = 0; i < dmc_header->mmio_count; i++) {
982b0b2d	378	if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE \|\|
f98f70d9	379	dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
eb805623	380	DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
f98f70d9	381	dmc_header->mmioaddr[i]);
6a6582bf	382	return NULL;
eb805623	383	}
f0f59a00	384	csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
eb805623 DV	385	csr->mmiodata[i] = dmc_header->mmiodata[i];
	386	}
	387
	388	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
	389	nbytes = dmc_header->fw_size * 4;
	390	if (nbytes > CSR_MAX_FW_SIZE) {
	391	DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
6a6582bf	392	return NULL;
eb805623 DV	393	}
	394	csr->dmc_fw_size = dmc_header->fw_size;
	395
6a6582bf DV	396	dmc_payload = kmalloc(nbytes, GFP_KERNEL);
6a6582bf DV	397	if (!dmc_payload) {
eb805623	398	DRM_ERROR("Memory allocation failed for dmc payload\n");
6a6582bf	399	return NULL;
eb805623 DV	400	}
eb805623 DV	401
1bb4308e	402	return memcpy(dmc_payload, &fw->data[readcount], nbytes);
6a6582bf DV	403	}
6a6582bf DV	404
8144ac59	405	static void csr_load_work_fn(struct work_struct *work)
6a6582bf	406	{
8144ac59 DV	407	struct drm_i915_private *dev_priv;
	408	struct intel_csr *csr;
	409	const struct firmware *fw;
	410	int ret;
	411
	412	dev_priv = container_of(work, typeof(*dev_priv), csr.work);
	413	csr = &dev_priv->csr;
6a6582bf	414
8144ac59 DV	415	ret = request_firmware(&fw, dev_priv->csr.fw_path,
8144ac59 DV	416	&dev_priv->dev->pdev->dev);
2abc525b ID	417	if (fw)
2abc525b ID	418	dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
6a6582bf	419
6a6582bf	420	if (dev_priv->csr.dmc_payload) {
2abc525b ID	421	intel_csr_load_program(dev_priv);
2abc525b ID	422
01a6908c	423	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
9c5308ea MK	424
	425	DRM_INFO("Finished loading %s (v%u.%u)\n",
	426	dev_priv->csr.fw_path,
	427	CSR_VERSION_MAJOR(csr->version),
	428	CSR_VERSION_MINOR(csr->version));
	429	} else {
cbfc2d26 CW	430	dev_notice(dev_priv->dev->dev,
	431	"Failed to load DMC firmware"
	432	" [" FIRMWARE_URL "],"
	433	" disabling runtime power management.\n");
9c5308ea MK	434	}
9c5308ea MK	435
eb805623 DV	436	release_firmware(fw);
	437	}
	438
aa9145c4 AM	439	/**
aa9145c4 AM	440	* intel_csr_ucode_init() - initialize the firmware loading.
f4448375	441	* @dev_priv: i915 drm device.
aa9145c4 AM	442	*
	443	* This function is called at the time of loading the display driver to read
	444	* firmware from a .bin file and copied into a internal memory.
	445	*/
f4448375	446	void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
eb805623	447	{
eb805623	448	struct intel_csr *csr = &dev_priv->csr;
8144ac59 DV	449
8144ac59 DV	450	INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
eb805623	451
f4448375	452	if (!HAS_CSR(dev_priv))
eb805623 DV	453	return;
eb805623 DV	454
a4a027a8 RV	455	if (IS_KABYLAKE(dev_priv))
	456	csr->fw_path = I915_CSR_KBL;
	457	else if (IS_SKYLAKE(dev_priv))
eb805623	458	csr->fw_path = I915_CSR_SKL;
18c237c0 AM	459	else if (IS_BROXTON(dev_priv))
18c237c0 AM	460	csr->fw_path = I915_CSR_BXT;
eb805623 DV	461	else {
	462	DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
	463	return;
	464	}
	465
abd41dc9 DL	466	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
abd41dc9 DL	467
dc174300 SS	468	/*
	469	* Obtain a runtime pm reference, until CSR is loaded,
	470	* to avoid entering runtime-suspend.
	471	*/
01a6908c	472	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
dc174300	473
8144ac59	474	schedule_work(&dev_priv->csr.work);
eb805623 DV	475	}
eb805623 DV	476
f74ed08d ID	477	/**
	478	* intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
	479	* @dev_priv: i915 drm device
	480	*
	481	* Prepare the DMC firmware before entering system suspend. This includes
	482	* flushing pending work items and releasing any resources acquired during
	483	* init.
	484	*/
	485	void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
	486	{
	487	if (!HAS_CSR(dev_priv))
	488	return;
	489
	490	flush_work(&dev_priv->csr.work);
	491
	492	/* Drop the reference held in case DMC isn't loaded. */
	493	if (!dev_priv->csr.dmc_payload)
	494	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
	495	}
	496
	497	/**
	498	* intel_csr_ucode_resume() - init CSR firmware during system resume
	499	* @dev_priv: i915 drm device
	500	*
	501	* Reinitialize the DMC firmware during system resume, reacquiring any
	502	* resources released in intel_csr_ucode_suspend().
	503	*/
	504	void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
	505	{
	506	if (!HAS_CSR(dev_priv))
	507	return;
	508
	509	/*
	510	* Reacquire the reference to keep RPM disabled in case DMC isn't
	511	* loaded.
	512	*/
	513	if (!dev_priv->csr.dmc_payload)
	514	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
	515	}
	516
aa9145c4 AM	517	/**
aa9145c4 AM	518	* intel_csr_ucode_fini() - unload the CSR firmware.
f4448375	519	* @dev_priv: i915 drm device.
aa9145c4	520	*
f74ed08d	521	* Firmmware unloading includes freeing the internal memory and reset the
aa9145c4 AM	522	* firmware loading status.
aa9145c4 AM	523	*/
f4448375	524	void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
eb805623	525	{
f4448375	526	if (!HAS_CSR(dev_priv))
eb805623 DV	527	return;
eb805623 DV	528
f74ed08d	529	intel_csr_ucode_suspend(dev_priv);
15e72c1f	530
eb805623 DV	531	kfree(dev_priv->csr.dmc_payload);
eb805623 DV	532	}