[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_csr.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */
#include <linux/firmware.h>
#include "i915_drv.h"
#include "i915_reg.h"

/**
 * DOC: csr support for dmc
 *
 * Display Context Save and Restore (CSR) firmware support added from gen9
 * onwards to drive newly added DMC (Display microcontroller) in display
 * engine to save and restore the state of display engine when it enter into
 * low-power state and comes back to normal.
 *
 * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
 * FW_LOADED, FW_FAILED.
 *
 * Once the firmware is written into the registers status will be moved from
 * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
 * be moved to FW_FAILED.
 */

#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"

MODULE_FIRMWARE(I915_CSR_SKL);
MODULE_FIRMWARE(I915_CSR_BXT);

#define SKL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 23)

#define CSR_MAX_FW_SIZE			0x2FFF
#define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF

struct intel_css_header {
	/* 0x09 for DMC */
	uint32_t module_type;

	/* Includes the DMC specific header in dwords */
	uint32_t header_len;

	/* always value would be 0x10000 */
	uint32_t header_ver;

	/* Not used */
	uint32_t module_id;

	/* Not used */
	uint32_t module_vendor;

	/* in YYYYMMDD format */
	uint32_t date;

	/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
	uint32_t size;

	/* Not used */
	uint32_t key_size;

	/* Not used */
	uint32_t modulus_size;

	/* Not used */
	uint32_t exponent_size;

	/* Not used */
	uint32_t reserved1[12];

	/* Major Minor */
	uint32_t version;

	/* Not used */
	uint32_t reserved2[8];

	/* Not used */
	uint32_t kernel_header_info;
} __packed;

struct intel_fw_info {
	uint16_t reserved1;

	/* Stepping (A, B, C, ..., *). * is a wildcard */
	char stepping;

	/* Sub-stepping (0, 1, ..., *). * is a wildcard */
	char substepping;

	uint32_t offset;
	uint32_t reserved2;
} __packed;

struct intel_package_header {
	/* DMC container header length in dwords */
	unsigned char header_len;

	/* always value would be 0x01 */
	unsigned char header_ver;

	unsigned char reserved[10];

	/* Number of valid entries in the FWInfo array below */
	uint32_t num_entries;

	struct intel_fw_info fw_info[20];
} __packed;

struct intel_dmc_header {
	/* always value would be 0x40403E3E */
	uint32_t signature;

	/* DMC binary header length */
	unsigned char header_len;

	/* 0x01 */
	unsigned char header_ver;

	/* Reserved */
	uint16_t dmcc_ver;

	/* Major, Minor */
	uint32_t	project;

	/* Firmware program size (excluding header) in dwords */
	uint32_t	fw_size;

	/* Major Minor version */
	uint32_t fw_version;

	/* Number of valid MMIO cycles present. */
	uint32_t mmio_count;

	/* MMIO address */
	uint32_t mmioaddr[8];

	/* MMIO data */
	uint32_t mmiodata[8];

	/* FW filename  */
	unsigned char dfile[32];

	uint32_t reserved1[2];
} __packed;

struct stepping_info {
	char stepping;
	char substepping;
};

/*
 * Kabylake derivated from Skylake H0, so SKL H0
 * is the right firmware for KBL A0 (revid 0).
 */
static const struct stepping_info kbl_stepping_info[] = {
	{'H', '0'}, {'I', '0'}
};

static const struct stepping_info skl_stepping_info[] = {
	{'A', '0'}, {'B', '0'}, {'C', '0'},
	{'D', '0'}, {'E', '0'}, {'F', '0'},
	{'G', '0'}, {'H', '0'}, {'I', '0'}
};

static const struct stepping_info bxt_stepping_info[] = {
	{'A', '0'}, {'A', '1'}, {'A', '2'},
	{'B', '0'}, {'B', '1'}, {'B', '2'}
};

static const struct stepping_info *intel_get_stepping_info(struct drm_device *dev)
{
	const struct stepping_info *si;
	unsigned int size;

	if (IS_KABYLAKE(dev)) {
		size = ARRAY_SIZE(kbl_stepping_info);
		si = kbl_stepping_info;
	} else if (IS_SKYLAKE(dev)) {
		size = ARRAY_SIZE(skl_stepping_info);
		si = skl_stepping_info;
	} else if (IS_BROXTON(dev)) {
		size = ARRAY_SIZE(bxt_stepping_info);
		si = bxt_stepping_info;
	} else {
		return NULL;
	}

	if (INTEL_REVID(dev) < size)
		return si + INTEL_REVID(dev);

	return NULL;
}

/**
 * intel_csr_load_program() - write the firmware from memory to register.
 * @dev_priv: i915 drm device.
 *
 * CSR firmware is read from a .bin file and kept in internal memory one time.
 * Everytime display comes back from low power state this function is called to
 * copy the firmware from internal memory to registers.
 */
void intel_csr_load_program(struct drm_i915_private *dev_priv)
{
	u32 *payload = dev_priv->csr.dmc_payload;
	uint32_t i, fw_size;

	if (!IS_GEN9(dev_priv)) {
		DRM_ERROR("No CSR support available for this platform\n");
		return;
	}

	if (!dev_priv->csr.dmc_payload) {
		DRM_ERROR("Tried to program CSR with empty payload\n");
		return;
	}

	fw_size = dev_priv->csr.dmc_fw_size;
	for (i = 0; i < fw_size; i++)
		I915_WRITE(CSR_PROGRAM(i), payload[i]);

	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
		I915_WRITE(dev_priv->csr.mmioaddr[i],
			   dev_priv->csr.mmiodata[i]);
	}

	dev_priv->csr.dc_state = 0;
}

static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
			      const struct firmware *fw)
{
	struct drm_device *dev = dev_priv->dev;
	struct intel_css_header *css_header;
	struct intel_package_header *package_header;
	struct intel_dmc_header *dmc_header;
	struct intel_csr *csr = &dev_priv->csr;
	const struct stepping_info *stepping_info = intel_get_stepping_info(dev);
	char stepping, substepping;
	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
	uint32_t i;
	uint32_t *dmc_payload;

	if (!fw)
		return NULL;

	if (!stepping_info) {
		DRM_ERROR("Unknown stepping info, firmware loading failed\n");
		return NULL;
	}

	stepping = stepping_info->stepping;
	substepping = stepping_info->substepping;

	/* Extract CSS Header information*/
	css_header = (struct intel_css_header *)fw->data;
	if (sizeof(struct intel_css_header) !=
	    (css_header->header_len * 4)) {
		DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
			  (css_header->header_len * 4));
		return NULL;
	}

	csr->version = css_header->version;

	if (IS_SKYLAKE(dev) && csr->version < SKL_CSR_VERSION_REQUIRED) {
		DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
			 " please upgrade to v%u.%u or later"
			 " [https://01.org/linuxgraphics/intel-linux-graphics-firmwares].\n",
			 CSR_VERSION_MAJOR(csr->version),
			 CSR_VERSION_MINOR(csr->version),
			 CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
			 CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
		return NULL;
	}

	readcount += sizeof(struct intel_css_header);

	/* Extract Package Header information*/
	package_header = (struct intel_package_header *)
		&fw->data[readcount];
	if (sizeof(struct intel_package_header) !=
	    (package_header->header_len * 4)) {
		DRM_ERROR("Firmware has wrong package header length %u bytes\n",
			  (package_header->header_len * 4));
		return NULL;
	}
	readcount += sizeof(struct intel_package_header);

	/* Search for dmc_offset to find firware binary. */
	for (i = 0; i < package_header->num_entries; i++) {
		if (package_header->fw_info[i].substepping == '*' &&
		    stepping == package_header->fw_info[i].stepping) {
			dmc_offset = package_header->fw_info[i].offset;
			break;
		} else if (stepping == package_header->fw_info[i].stepping &&
			substepping == package_header->fw_info[i].substepping) {
			dmc_offset = package_header->fw_info[i].offset;
			break;
		} else if (package_header->fw_info[i].stepping == '*' &&
			   package_header->fw_info[i].substepping == '*')
			dmc_offset = package_header->fw_info[i].offset;
	}
	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
		DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
		return NULL;
	}
	readcount += dmc_offset;

	/* Extract dmc_header information. */
	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
		DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
			  (dmc_header->header_len));
		return NULL;
	}
	readcount += sizeof(struct intel_dmc_header);

	/* Cache the dmc header info. */
	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
		DRM_ERROR("Firmware has wrong mmio count %u\n",
			  dmc_header->mmio_count);
		return NULL;
	}
	csr->mmio_count = dmc_header->mmio_count;
	for (i = 0; i < dmc_header->mmio_count; i++) {
		if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
		    dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
			DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
				  dmc_header->mmioaddr[i]);
			return NULL;
		}
		csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
		csr->mmiodata[i] = dmc_header->mmiodata[i];
	}

	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
	nbytes = dmc_header->fw_size * 4;
	if (nbytes > CSR_MAX_FW_SIZE) {
		DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
		return NULL;
	}
	csr->dmc_fw_size = dmc_header->fw_size;

	dmc_payload = kmalloc(nbytes, GFP_KERNEL);
	if (!dmc_payload) {
		DRM_ERROR("Memory allocation failed for dmc payload\n");
		return NULL;
	}

	memcpy(dmc_payload, &fw->data[readcount], nbytes);

	return dmc_payload;
}

static void csr_load_work_fn(struct work_struct *work)
{
	struct drm_i915_private *dev_priv;
	struct intel_csr *csr;
	const struct firmware *fw;
	int ret;

	dev_priv = container_of(work, typeof(*dev_priv), csr.work);
	csr = &dev_priv->csr;

	ret = request_firmware(&fw, dev_priv->csr.fw_path,
			       &dev_priv->dev->pdev->dev);
	if (!fw)
		goto out;

	dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
	if (!dev_priv->csr.dmc_payload)
		goto out;

	/* load csr program during system boot, as needed for DC states */
	intel_csr_load_program(dev_priv);

out:
	if (dev_priv->csr.dmc_payload) {
		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);

		DRM_INFO("Finished loading %s (v%u.%u)\n",
			 dev_priv->csr.fw_path,
			 CSR_VERSION_MAJOR(csr->version),
			 CSR_VERSION_MINOR(csr->version));
	} else {
		DRM_ERROR("Failed to load DMC firmware, disabling rpm\n");
	}

	release_firmware(fw);
}

/**
 * intel_csr_ucode_init() - initialize the firmware loading.
 * @dev_priv: i915 drm device.
 *
 * This function is called at the time of loading the display driver to read
 * firmware from a .bin file and copied into a internal memory.
 */
void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
{
	struct intel_csr *csr = &dev_priv->csr;

	INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);

	if (!HAS_CSR(dev_priv))
		return;

	if (IS_SKYLAKE(dev_priv))
		csr->fw_path = I915_CSR_SKL;
	else if (IS_BROXTON(dev_priv))
		csr->fw_path = I915_CSR_BXT;
	else {
		DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
		return;
	}

	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);

	/*
	 * Obtain a runtime pm reference, until CSR is loaded,
	 * to avoid entering runtime-suspend.
	 */
	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);

	schedule_work(&dev_priv->csr.work);
}

/**
 * intel_csr_ucode_fini() - unload the CSR firmware.
 * @dev_priv: i915 drm device.
 *
 * Firmmware unloading includes freeing the internal momory and reset the
 * firmware loading status.
 */
void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
{
	if (!HAS_CSR(dev_priv))
		return;

	flush_work(&dev_priv->csr.work);

	kfree(dev_priv->csr.dmc_payload);
}
Commit	Line	Data
eb805623 DV	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24	#include <linux/firmware.h>
	25	#include "i915_drv.h"
	26	#include "i915_reg.h"
	27
aa9145c4 AM	28	/**
	29	* DOC: csr support for dmc
	30	*
	31	* Display Context Save and Restore (CSR) firmware support added from gen9
	32	* onwards to drive newly added DMC (Display microcontroller) in display
	33	* engine to save and restore the state of display engine when it enter into
	34	* low-power state and comes back to normal.
	35	*
	36	* Firmware loading status will be one of the below states: FW_UNINITIALIZED,
	37	* FW_LOADED, FW_FAILED.
	38	*
	39	* Once the firmware is written into the registers status will be moved from
	40	* FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
	41	* be moved to FW_FAILED.
	42	*/
	43
bf546f81	44	#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
18c237c0	45	#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
eb805623 DV	46
eb805623 DV	47	MODULE_FIRMWARE(I915_CSR_SKL);
18c237c0	48	MODULE_FIRMWARE(I915_CSR_BXT);
eb805623	49
9c5308ea MK	50	#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
9c5308ea MK	51
eb805623 DV	52	#define CSR_MAX_FW_SIZE 0x2FFF
eb805623 DV	53	#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
eb805623 DV	54
	55	struct intel_css_header {
	56	/* 0x09 for DMC */
	57	uint32_t module_type;
	58
	59	/* Includes the DMC specific header in dwords */
	60	uint32_t header_len;
	61
	62	/* always value would be 0x10000 */
	63	uint32_t header_ver;
	64
	65	/* Not used */
	66	uint32_t module_id;
	67
	68	/* Not used */
	69	uint32_t module_vendor;
	70
	71	/* in YYYYMMDD format */
	72	uint32_t date;
	73
	74	/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
	75	uint32_t size;
	76
	77	/* Not used */
	78	uint32_t key_size;
	79
	80	/* Not used */
	81	uint32_t modulus_size;
	82
	83	/* Not used */
	84	uint32_t exponent_size;
	85
	86	/* Not used */
	87	uint32_t reserved1[12];
	88
	89	/* Major Minor */
	90	uint32_t version;
	91
	92	/* Not used */
	93	uint32_t reserved2[8];
	94
	95	/* Not used */
	96	uint32_t kernel_header_info;
	97	} __packed;
	98
	99	struct intel_fw_info {
	100	uint16_t reserved1;
	101
	102	/* Stepping (A, B, C, ..., ). is a wildcard */
	103	char stepping;
	104
	105	/* Sub-stepping (0, 1, ..., ). is a wildcard */
	106	char substepping;
	107
	108	uint32_t offset;
	109	uint32_t reserved2;
	110	} __packed;
	111
	112	struct intel_package_header {
	113	/* DMC container header length in dwords */
	114	unsigned char header_len;
	115
	116	/* always value would be 0x01 */
	117	unsigned char header_ver;
118
119	unsigned char reserved[10];
120
121	/* Number of valid entries in the FWInfo array below */
122	uint32_t num_entries;
123
124	struct intel_fw_info fw_info[20];
125	} __packed;
126
127	struct intel_dmc_header {
128	/* always value would be 0x40403E3E */
129	uint32_t signature;
130
131	/* DMC binary header length */
132	unsigned char header_len;
133
134	/* 0x01 */
135	unsigned char header_ver;
136
137	/* Reserved */
138	uint16_t dmcc_ver;
139
140	/* Major, Minor */
141	uint32_t project;
142
143	/* Firmware program size (excluding header) in dwords */
144	uint32_t fw_size;
145
146	/* Major Minor version */
147	uint32_t fw_version;
148
149	/* Number of valid MMIO cycles present. */
150	uint32_t mmio_count;
151
152	/* MMIO address */
153	uint32_t mmioaddr[8];
154
155	/* MMIO data */
156	uint32_t mmiodata[8];
157
158	/* FW filename */
159	unsigned char dfile[32];
160
161	uint32_t reserved1[2];
162	} __packed;
163
164	struct stepping_info {
165	char stepping;
166	char substepping;
167	};
168
a25c9f00 RV	169	/*
	170	* Kabylake derivated from Skylake H0, so SKL H0
	171	* is the right firmware for KBL A0 (revid 0).
	172	*/
	173	static const struct stepping_info kbl_stepping_info[] = {
	174	{'H', '0'}, {'I', '0'}
	175	};
	176
eb805623	177	static const struct stepping_info skl_stepping_info[] = {
84cb00ec JN	178	{'A', '0'}, {'B', '0'}, {'C', '0'},
	179	{'D', '0'}, {'E', '0'}, {'F', '0'},
	180	{'G', '0'}, {'H', '0'}, {'I', '0'}
eb805623 DV	181	};
eb805623 DV	182
b9cd5bfd	183	static const struct stepping_info bxt_stepping_info[] = {
cff765fb AM	184	{'A', '0'}, {'A', '1'}, {'A', '2'},
	185	{'B', '0'}, {'B', '1'}, {'B', '2'}
	186	};
	187
b1a14c6e	188	static const struct stepping_info intel_get_stepping_info(struct drm_device dev)
eb805623	189	{
b1a14c6e JN	190	const struct stepping_info *si;
	191	unsigned int size;
	192
a25c9f00 RV	193	if (IS_KABYLAKE(dev)) {
	194	size = ARRAY_SIZE(kbl_stepping_info);
	195	si = kbl_stepping_info;
	196	} else if (IS_SKYLAKE(dev)) {
b1a14c6e JN	197	size = ARRAY_SIZE(skl_stepping_info);
	198	si = skl_stepping_info;
	199	} else if (IS_BROXTON(dev)) {
	200	size = ARRAY_SIZE(bxt_stepping_info);
	201	si = bxt_stepping_info;
	202	} else {
	203	return NULL;
	204	}
eb805623	205
b1a14c6e JN	206	if (INTEL_REVID(dev) < size)
	207	return si + INTEL_REVID(dev);
	208
	209	return NULL;
eb805623 DV	210	}
eb805623 DV	211
aa9145c4 AM	212	/**
aa9145c4 AM	213	* intel_csr_load_program() - write the firmware from memory to register.
f4448375	214	* @dev_priv: i915 drm device.
aa9145c4 AM	215	*
	216	* CSR firmware is read from a .bin file and kept in internal memory one time.
	217	* Everytime display comes back from low power state this function is called to
	218	* copy the firmware from internal memory to registers.
	219	*/
f4448375	220	void intel_csr_load_program(struct drm_i915_private *dev_priv)
eb805623	221	{
a7f749f9	222	u32 *payload = dev_priv->csr.dmc_payload;
eb805623 DV	223	uint32_t i, fw_size;
eb805623 DV	224
f4448375	225	if (!IS_GEN9(dev_priv)) {
eb805623 DV	226	DRM_ERROR("No CSR support available for this platform\n");
	227	return;
	228	}
	229
fc131bf2 PJ	230	if (!dev_priv->csr.dmc_payload) {
fc131bf2 PJ	231	DRM_ERROR("Tried to program CSR with empty payload\n");
4b7ab5fc	232	return;
fc131bf2	233	}
4b7ab5fc	234
eb805623 DV	235	fw_size = dev_priv->csr.dmc_fw_size;
eb805623 DV	236	for (i = 0; i < fw_size; i++)
d2aa5ae8	237	I915_WRITE(CSR_PROGRAM(i), payload[i]);
eb805623 DV	238
	239	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
	240	I915_WRITE(dev_priv->csr.mmioaddr[i],
f98f70d9	241	dev_priv->csr.mmiodata[i]);
eb805623	242	}
9b6f2098 PJ	243
9b6f2098 PJ	244	dev_priv->csr.dc_state = 0;
eb805623 DV	245	}
eb805623 DV	246
6a6582bf DV	247	static uint32_t parse_csr_fw(struct drm_i915_private dev_priv,
6a6582bf DV	248	const struct firmware *fw)
eb805623	249	{
eb805623 DV	250	struct drm_device *dev = dev_priv->dev;
	251	struct intel_css_header *css_header;
	252	struct intel_package_header *package_header;
	253	struct intel_dmc_header *dmc_header;
	254	struct intel_csr *csr = &dev_priv->csr;
b1a14c6e JN	255	const struct stepping_info *stepping_info = intel_get_stepping_info(dev);
b1a14c6e JN	256	char stepping, substepping;
eb805623 DV	257	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
eb805623 DV	258	uint32_t i;
a7f749f9	259	uint32_t *dmc_payload;
eb805623	260
9c5308ea	261	if (!fw)
6a6582bf	262	return NULL;
eb805623	263
b1a14c6e	264	if (!stepping_info) {
eb805623	265	DRM_ERROR("Unknown stepping info, firmware loading failed\n");
6a6582bf	266	return NULL;
eb805623 DV	267	}
eb805623 DV	268
b1a14c6e JN	269	stepping = stepping_info->stepping;
	270	substepping = stepping_info->substepping;
	271
eb805623 DV	272	/* Extract CSS Header information*/
	273	css_header = (struct intel_css_header *)fw->data;
	274	if (sizeof(struct intel_css_header) !=
f98f70d9	275	(css_header->header_len * 4)) {
eb805623	276	DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
f98f70d9	277	(css_header->header_len * 4));
6a6582bf	278	return NULL;
eb805623	279	}
b6e7d894 DL	280
	281	csr->version = css_header->version;
	282
9c5308ea MK	283	if (IS_SKYLAKE(dev) && csr->version < SKL_CSR_VERSION_REQUIRED) {
	284	DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
	285	" please upgrade to v%u.%u or later"
	286	" [https://01.org/linuxgraphics/intel-linux-graphics-firmwares].\n",
	287	CSR_VERSION_MAJOR(csr->version),
	288	CSR_VERSION_MINOR(csr->version),
	289	CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
	290	CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
6a6582bf	291	return NULL;
9c5308ea MK	292	}
9c5308ea MK	293
eb805623 DV	294	readcount += sizeof(struct intel_css_header);
	295
	296	/* Extract Package Header information*/
	297	package_header = (struct intel_package_header *)
f98f70d9	298	&fw->data[readcount];
eb805623	299	if (sizeof(struct intel_package_header) !=
f98f70d9	300	(package_header->header_len * 4)) {
eb805623	301	DRM_ERROR("Firmware has wrong package header length %u bytes\n",
f98f70d9	302	(package_header->header_len * 4));
6a6582bf	303	return NULL;
eb805623 DV	304	}
	305	readcount += sizeof(struct intel_package_header);
	306
	307	/* Search for dmc_offset to find firware binary. */
	308	for (i = 0; i < package_header->num_entries; i++) {
	309	if (package_header->fw_info[i].substepping == '*' &&
f98f70d9	310	stepping == package_header->fw_info[i].stepping) {
eb805623 DV	311	dmc_offset = package_header->fw_info[i].offset;
	312	break;
	313	} else if (stepping == package_header->fw_info[i].stepping &&
	314	substepping == package_header->fw_info[i].substepping) {
	315	dmc_offset = package_header->fw_info[i].offset;
	316	break;
	317	} else if (package_header->fw_info[i].stepping == '*' &&
f98f70d9	318	package_header->fw_info[i].substepping == '*')
eb805623 DV	319	dmc_offset = package_header->fw_info[i].offset;
	320	}
	321	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
	322	DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
6a6582bf	323	return NULL;
eb805623 DV	324	}
	325	readcount += dmc_offset;
	326
	327	/* Extract dmc_header information. */
	328	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
	329	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
	330	DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
f98f70d9	331	(dmc_header->header_len));
6a6582bf	332	return NULL;
eb805623 DV	333	}
	334	readcount += sizeof(struct intel_dmc_header);
	335
	336	/* Cache the dmc header info. */
	337	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
	338	DRM_ERROR("Firmware has wrong mmio count %u\n",
f98f70d9	339	dmc_header->mmio_count);
6a6582bf	340	return NULL;
eb805623 DV	341	}
	342	csr->mmio_count = dmc_header->mmio_count;
	343	for (i = 0; i < dmc_header->mmio_count; i++) {
982b0b2d	344	if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE \|\|
f98f70d9	345	dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
eb805623	346	DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
f98f70d9	347	dmc_header->mmioaddr[i]);
6a6582bf	348	return NULL;
eb805623	349	}
f0f59a00	350	csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
eb805623 DV	351	csr->mmiodata[i] = dmc_header->mmiodata[i];
	352	}
	353
	354	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
	355	nbytes = dmc_header->fw_size * 4;
	356	if (nbytes > CSR_MAX_FW_SIZE) {
	357	DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
6a6582bf	358	return NULL;
eb805623 DV	359	}
	360	csr->dmc_fw_size = dmc_header->fw_size;
	361
6a6582bf DV	362	dmc_payload = kmalloc(nbytes, GFP_KERNEL);
6a6582bf DV	363	if (!dmc_payload) {
eb805623	364	DRM_ERROR("Memory allocation failed for dmc payload\n");
6a6582bf	365	return NULL;
eb805623 DV	366	}
eb805623 DV	367
a7f749f9	368	memcpy(dmc_payload, &fw->data[readcount], nbytes);
eb805623	369
6a6582bf DV	370	return dmc_payload;
	371	}
	372
8144ac59	373	static void csr_load_work_fn(struct work_struct *work)
6a6582bf	374	{
8144ac59 DV	375	struct drm_i915_private *dev_priv;
	376	struct intel_csr *csr;
	377	const struct firmware *fw;
	378	int ret;
	379
	380	dev_priv = container_of(work, typeof(*dev_priv), csr.work);
	381	csr = &dev_priv->csr;
6a6582bf	382
8144ac59 DV	383	ret = request_firmware(&fw, dev_priv->csr.fw_path,
8144ac59 DV	384	&dev_priv->dev->pdev->dev);
6a6582bf DV	385	if (!fw)
	386	goto out;
	387
	388	dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
	389	if (!dev_priv->csr.dmc_payload)
	390	goto out;
	391
eb805623	392	/* load csr program during system boot, as needed for DC states */
f4448375	393	intel_csr_load_program(dev_priv);
dc174300	394
eb805623	395	out:
6a6582bf	396	if (dev_priv->csr.dmc_payload) {
01a6908c	397	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
9c5308ea MK	398
	399	DRM_INFO("Finished loading %s (v%u.%u)\n",
	400	dev_priv->csr.fw_path,
	401	CSR_VERSION_MAJOR(csr->version),
	402	CSR_VERSION_MINOR(csr->version));
	403	} else {
c729ed88	404	DRM_ERROR("Failed to load DMC firmware, disabling rpm\n");
9c5308ea MK	405	}
9c5308ea MK	406
eb805623 DV	407	release_firmware(fw);
	408	}
	409
aa9145c4 AM	410	/**
aa9145c4 AM	411	* intel_csr_ucode_init() - initialize the firmware loading.
f4448375	412	* @dev_priv: i915 drm device.
aa9145c4 AM	413	*
	414	* This function is called at the time of loading the display driver to read
	415	* firmware from a .bin file and copied into a internal memory.
	416	*/
f4448375	417	void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
eb805623	418	{
eb805623	419	struct intel_csr *csr = &dev_priv->csr;
8144ac59 DV	420
8144ac59 DV	421	INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
eb805623	422
f4448375	423	if (!HAS_CSR(dev_priv))
eb805623 DV	424	return;
eb805623 DV	425
f4448375	426	if (IS_SKYLAKE(dev_priv))
eb805623	427	csr->fw_path = I915_CSR_SKL;
18c237c0 AM	428	else if (IS_BROXTON(dev_priv))
18c237c0 AM	429	csr->fw_path = I915_CSR_BXT;
eb805623 DV	430	else {
	431	DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
	432	return;
	433	}
	434
abd41dc9 DL	435	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
abd41dc9 DL	436
dc174300 SS	437	/*
	438	* Obtain a runtime pm reference, until CSR is loaded,
	439	* to avoid entering runtime-suspend.
	440	*/
01a6908c	441	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
dc174300	442
8144ac59	443	schedule_work(&dev_priv->csr.work);
eb805623 DV	444	}
eb805623 DV	445
aa9145c4 AM	446	/**
aa9145c4 AM	447	* intel_csr_ucode_fini() - unload the CSR firmware.
f4448375	448	* @dev_priv: i915 drm device.
aa9145c4 AM	449	*
	450	* Firmmware unloading includes freeing the internal momory and reset the
	451	* firmware loading status.
	452	*/
f4448375	453	void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
eb805623	454	{
f4448375	455	if (!HAS_CSR(dev_priv))
eb805623 DV	456	return;
eb805623 DV	457
15e72c1f AM	458	flush_work(&dev_priv->csr.work);
15e72c1f AM	459
eb805623 DV	460	kfree(dev_priv->csr.dmc_payload);
eb805623 DV	461	}