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drm/i915: Enable querying offset of UV plane with intel_plane_obj_offset
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
5f8b2531 131/* Skylake H and S */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 146 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d
DW		 147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
5f8b2531
RV		 149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost level 0x1 */
150 { 0x0000201B, 0x0000009D, 0x0 },
f8896f5d
DW		 151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
155};
156
5f8b2531
RV		 157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
5f8b2531 162 { 0x80009010, 0x000000C7, 0x3 }, /* Uses I_boost level 0x3 */
f8896f5d
DW		 163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
168};
169
170/*
5f8b2531 171 * Skylake H and S
f8896f5d
DW		 172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d 204/*
5f8b2531 205 * Skylake Y
f8896f5d
DW		 206 * eDP 1.4 low vswing translation parameters
207 */
5f8b2531 208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
5f8b2531 221/* Skylake U, H and S */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
234};
235
5f8b2531
RV		 236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
5f8b2531 247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */
f8896f5d 248 { 0x00000018, 0x000000C7, 0x0 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
259/* BSpec does not define separate vswing/pre-emphasis values for eDP.
260 * Using DP values for eDP as well.
261 */
262static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
263 /* Idx NT mV diff db */
fe4c63c8
ID		 264 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
265 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
266 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
267 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
268 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
269 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
270 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
271 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
272 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 273 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 274};
275
276/* BSpec has 2 recommended values - entries 0 and 8.
277 * Using the entry with higher vswing.
278 */
279static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
280 /* Idx NT mV diff db */
fe4c63c8
ID		 281 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
282 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
283 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
284 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
285 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
286 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
287 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
288 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
289 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 290 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
291};
292
f8896f5d
DW		 293static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
294 enum port port, int type);
295
a1e6ad66
ID		 296static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
297 struct intel_digital_port **dig_port,
298 enum port *port)
fc914639 299{
0bdee30e 300 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 301 int type = intel_encoder->type;
302
0e32b39c 303 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 304 *dig_port = enc_to_mst(encoder)->primary;
305 *port = (*dig_port)->port;
0e32b39c 306 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 307 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 308 *dig_port = enc_to_dig_port(encoder);
309 *port = (*dig_port)->port;
fc914639 310 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 311 *dig_port = NULL;
312 *port = PORT_E;
fc914639
PZ		 313 } else {
314 DRM_ERROR("Invalid DDI encoder type %d\n", type);
315 BUG();
316 }
317}
318
a1e6ad66
ID		 319enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
320{
321 struct intel_digital_port *dig_port;
322 enum port port;
323
324 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
325
326 return port;
327}
328
ce3b7e9b
DL		 329static bool
330intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
331{
332 return intel_dig_port->hdmi.hdmi_reg;
333}
334
f8896f5d
DW		 335static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
336 int *n_entries)
337{
f8896f5d 338 const struct ddi_buf_trans *ddi_translations;
f8896f5d 339
5f8b2531
RV		 340 if (IS_SKL_ULX(dev)) {
341 ddi_translations = skl_y_ddi_translations_dp;
342 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
f8896f5d
DW		 343 } else if (IS_SKL_ULT(dev)) {
344 ddi_translations = skl_u_ddi_translations_dp;
345 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
346 } else {
347 ddi_translations = skl_ddi_translations_dp;
348 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
349 }
350
351 return ddi_translations;
352}
353
354static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
355 int *n_entries)
356{
357 struct drm_i915_private *dev_priv = dev->dev_private;
358 const struct ddi_buf_trans *ddi_translations;
f8896f5d 359
5f8b2531 360 if (IS_SKL_ULX(dev)) {
f8896f5d 361 if (dev_priv->edp_low_vswing) {
5f8b2531
RV		 362 ddi_translations = skl_y_ddi_translations_edp;
363 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
f8896f5d 364 } else {
5f8b2531
RV		 365 ddi_translations = skl_y_ddi_translations_dp;
366 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
f8896f5d
DW		 367 }
368 } else if (IS_SKL_ULT(dev)) {
369 if (dev_priv->edp_low_vswing) {
370 ddi_translations = skl_u_ddi_translations_edp;
371 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
372 } else {
373 ddi_translations = skl_u_ddi_translations_dp;
374 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
375 }
376 } else {
377 if (dev_priv->edp_low_vswing) {
378 ddi_translations = skl_ddi_translations_edp;
379 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
380 } else {
381 ddi_translations = skl_ddi_translations_dp;
382 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
383 }
384 }
385
386 return ddi_translations;
387}
388
389static const struct ddi_buf_trans *
390skl_get_buf_trans_hdmi(struct drm_device *dev,
391 int *n_entries)
392{
f8896f5d 393 const struct ddi_buf_trans *ddi_translations;
f8896f5d 394
5f8b2531
RV		 395 if (IS_SKL_ULX(dev)) {
396 ddi_translations = skl_y_ddi_translations_hdmi;
397 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
f8896f5d
DW		 398 } else {
399 ddi_translations = skl_ddi_translations_hdmi;
400 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
401 }
402
403 return ddi_translations;
404}
405
e58623cb
AR		 406/*
407 * Starting with Haswell, DDI port buffers must be programmed with correct
408 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 409 * but the HDMI/DVI fields are shared among those. So we program the DDI
410 * in either FDI or DP modes only, as HDMI connections will work with both
411 * of those
412 */
faa0cdbe
ID		 413static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
414 bool supports_hdmi)
45244b87
ED		 415{
416 struct drm_i915_private *dev_priv = dev->dev_private;
75067dde 417 u32 iboost_bit = 0;
7ff44670 418 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 419 size;
6acab15a 420 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 421 const struct ddi_buf_trans *ddi_translations_fdi;
422 const struct ddi_buf_trans *ddi_translations_dp;
423 const struct ddi_buf_trans *ddi_translations_edp;
424 const struct ddi_buf_trans *ddi_translations_hdmi;
425 const struct ddi_buf_trans *ddi_translations;
e58623cb 426
96fb9f9b 427 if (IS_BROXTON(dev)) {
faa0cdbe 428 if (!supports_hdmi)
96fb9f9b
VK		 429 return;
430
431 /* Vswing programming for HDMI */
432 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
433 INTEL_OUTPUT_HDMI);
434 return;
435 } else if (IS_SKYLAKE(dev)) {
c30400fc 436 ddi_translations_fdi = NULL;
f8896f5d
DW		 437 ddi_translations_dp =
438 skl_get_buf_trans_dp(dev, &n_dp_entries);
439 ddi_translations_edp =
440 skl_get_buf_trans_edp(dev, &n_edp_entries);
441 ddi_translations_hdmi =
442 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
443 hdmi_default_entry = 8;
75067dde
AK		 444 /* If we're boosting the current, set bit 31 of trans1 */
445 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
446 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
447 iboost_bit = 1<<31;
7f88e3af 448 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 449 ddi_translations_fdi = bdw_ddi_translations_fdi;
450 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 451 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 452 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 453 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
454 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 455 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 456 hdmi_default_entry = 7;
e58623cb
AR		 457 } else if (IS_HASWELL(dev)) {
458 ddi_translations_fdi = hsw_ddi_translations_fdi;
459 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 460 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 461 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 462 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 463 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 464 hdmi_default_entry = 6;
e58623cb
AR		 465 } else {
466 WARN(1, "ddi translation table missing\n");
300644c7 467 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 468 ddi_translations_fdi = bdw_ddi_translations_fdi;
469 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 470 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 471 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
472 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 473 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 474 hdmi_default_entry = 7;
e58623cb
AR		 475 }
476
300644c7
PZ		 477 switch (port) {
478 case PORT_A:
479 ddi_translations = ddi_translations_edp;
7ad14a29 480 size = n_edp_entries;
300644c7
PZ		 481 break;
482 case PORT_B:
483 case PORT_C:
300644c7 484 ddi_translations = ddi_translations_dp;
7ad14a29 485 size = n_dp_entries;
300644c7 486 break;
77d8d009 487 case PORT_D:
7ad14a29 488 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 489 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 490 size = n_edp_entries;
491 } else {
77d8d009 492 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 493 size = n_dp_entries;
494 }
77d8d009 495 break;
300644c7 496 case PORT_E:
7f88e3af
DL		 497 if (ddi_translations_fdi)
498 ddi_translations = ddi_translations_fdi;
499 else
500 ddi_translations = ddi_translations_dp;
7ad14a29 501 size = n_dp_entries;
300644c7
PZ		 502 break;
503 default:
504 BUG();
505 }
45244b87 506
9712e688
VS		 507 for (i = 0; i < size; i++) {
508 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
509 ddi_translations[i].trans1 | iboost_bit);
510 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
511 ddi_translations[i].trans2);
45244b87 512 }
ce4dd49e 513
faa0cdbe 514 if (!supports_hdmi)
ce3b7e9b
DL		 515 return;
516
ce4dd49e
DL		 517 /* Choose a good default if VBT is badly populated */
518 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
519 hdmi_level >= n_hdmi_entries)
7ff44670 520 hdmi_level = hdmi_default_entry;
ce4dd49e 521
6acab15a 522 /* Entry 9 is for HDMI: */
9712e688
VS		 523 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
524 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
525 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
526 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 527}
528
529/* Program DDI buffers translations for DP. By default, program ports A-D in DP
530 * mode and port E for FDI.
531 */
532void intel_prepare_ddi(struct drm_device *dev)
533{
faa0cdbe 534 struct intel_encoder *intel_encoder;
b403745c 535 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 536
0d536cb4
PZ		 537 if (!HAS_DDI(dev))
538 return;
45244b87 539
faa0cdbe
ID		 540 for_each_intel_encoder(dev, intel_encoder) {
541 struct intel_digital_port *intel_dig_port;
542 enum port port;
543 bool supports_hdmi;
544
545 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
546
547 if (visited[port])
b403745c
DL		 548 continue;
549
faa0cdbe
ID		 550 supports_hdmi = intel_dig_port &&
551 intel_dig_port_supports_hdmi(intel_dig_port);
552
553 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
554 visited[port] = true;
b403745c 555 }
45244b87 556}
c82e4d26 557
248138b5
PZ		 558static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
559 enum port port)
560{
561 uint32_t reg = DDI_BUF_CTL(port);
562 int i;
563
3449ca85 564 for (i = 0; i < 16; i++) {
248138b5
PZ		 565 udelay(1);
566 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
567 return;
568 }
569 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
570}
c82e4d26
ED		 571
572/* Starting with Haswell, different DDI ports can work in FDI mode for
573 * connection to the PCH-located connectors. For this, it is necessary to train
574 * both the DDI port and PCH receiver for the desired DDI buffer settings.
575 *
576 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
577 * please note that when FDI mode is active on DDI E, it shares 2 lines with
578 * DDI A (which is used for eDP)
579 */
580
581void hsw_fdi_link_train(struct drm_crtc *crtc)
582{
583 struct drm_device *dev = crtc->dev;
584 struct drm_i915_private *dev_priv = dev->dev_private;
585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 586 u32 temp, i, rx_ctl_val;
c82e4d26 587
04945641
PZ		 588 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
589 * mode set "sequence for CRT port" document:
590 * - TP1 to TP2 time with the default value
591 * - FDI delay to 90h
8693a824
DL		 592 *
593 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 594 */
595 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
596 FDI_RX_PWRDN_LANE0_VAL(2) |
597 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
598
599 /* Enable the PCH Receiver FDI PLL */
3e68320e 600 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 601 FDI_RX_PLL_ENABLE |
6e3c9717 602 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 603 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
604 POSTING_READ(_FDI_RXA_CTL);
605 udelay(220);
606
607 /* Switch from Rawclk to PCDclk */
608 rx_ctl_val |= FDI_PCDCLK;
609 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
610
611 /* Configure Port Clock Select */
6e3c9717
ACO		 612 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
613 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 614
615 /* Start the training iterating through available voltages and emphasis,
616 * testing each value twice. */
10122051 617 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 618 /* Configure DP_TP_CTL with auto-training */
619 I915_WRITE(DP_TP_CTL(PORT_E),
620 DP_TP_CTL_FDI_AUTOTRAIN |
621 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
622 DP_TP_CTL_LINK_TRAIN_PAT1 |
623 DP_TP_CTL_ENABLE);
624
876a8cdf
DL		 625 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
626 * DDI E does not support port reversal, the functionality is
627 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
628 * port reversal bit */
c82e4d26 629 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 630 DDI_BUF_CTL_ENABLE |
6e3c9717 631 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 632 DDI_BUF_TRANS_SELECT(i / 2));
04945641 633 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 634
635 udelay(600);
636
04945641
PZ		 637 /* Program PCH FDI Receiver TU */
638 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
639
640 /* Enable PCH FDI Receiver with auto-training */
641 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
642 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
643 POSTING_READ(_FDI_RXA_CTL);
644
645 /* Wait for FDI receiver lane calibration */
646 udelay(30);
647
648 /* Unset FDI_RX_MISC pwrdn lanes */
649 temp = I915_READ(_FDI_RXA_MISC);
650 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
651 I915_WRITE(_FDI_RXA_MISC, temp);
652 POSTING_READ(_FDI_RXA_MISC);
653
654 /* Wait for FDI auto training time */
655 udelay(5);
c82e4d26
ED		 656
657 temp = I915_READ(DP_TP_STATUS(PORT_E));
658 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 659 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 660
661 /* Enable normal pixel sending for FDI */
662 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 663 DP_TP_CTL_FDI_AUTOTRAIN |
664 DP_TP_CTL_LINK_TRAIN_NORMAL |
665 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
666 DP_TP_CTL_ENABLE);
c82e4d26 667
04945641 668 return;
c82e4d26 669 }
04945641 670
248138b5
PZ		 671 temp = I915_READ(DDI_BUF_CTL(PORT_E));
672 temp &= ~DDI_BUF_CTL_ENABLE;
673 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
674 POSTING_READ(DDI_BUF_CTL(PORT_E));
675
04945641 676 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 677 temp = I915_READ(DP_TP_CTL(PORT_E));
678 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
679 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
680 I915_WRITE(DP_TP_CTL(PORT_E), temp);
681 POSTING_READ(DP_TP_CTL(PORT_E));
682
683 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 684
685 rx_ctl_val &= ~FDI_RX_ENABLE;
686 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 687 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 688
689 /* Reset FDI_RX_MISC pwrdn lanes */
690 temp = I915_READ(_FDI_RXA_MISC);
691 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
692 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
693 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 694 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 695 }
696
04945641 697 DRM_ERROR("FDI link training failed!\n");
c82e4d26 698}
0e72a5b5 699
44905a27
DA		 700void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
701{
702 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
703 struct intel_digital_port *intel_dig_port =
704 enc_to_dig_port(&encoder->base);
705
706 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 707 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 708 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 709}
710
8d9ddbcb
PZ		 711static struct intel_encoder *
712intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
713{
714 struct drm_device *dev = crtc->dev;
715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
716 struct intel_encoder *intel_encoder, *ret = NULL;
717 int num_encoders = 0;
718
719 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
720 ret = intel_encoder;
721 num_encoders++;
722 }
723
724 if (num_encoders != 1)
84f44ce7
VS		 725 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
726 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 727
728 BUG_ON(ret == NULL);
729 return ret;
730}
731
bcddf610 732struct intel_encoder *
3165c074 733intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 734{
3165c074
ACO		 735 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
736 struct intel_encoder *ret = NULL;
737 struct drm_atomic_state *state;
da3ced29
ACO		 738 struct drm_connector *connector;
739 struct drm_connector_state *connector_state;
d0737e1d 740 int num_encoders = 0;
3165c074 741 int i;
d0737e1d 742
3165c074
ACO		 743 state = crtc_state->base.state;
744
da3ced29
ACO		 745 for_each_connector_in_state(state, connector, connector_state, i) {
746 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 747 continue;
748
da3ced29 749 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 750 num_encoders++;
d0737e1d
ACO		 751 }
752
753 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
754 pipe_name(crtc->pipe));
755
756 BUG_ON(ret == NULL);
757 return ret;
758}
759
1c0b85c5 760#define LC_FREQ 2700
27893390 761#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 762
763#define P_MIN 2
764#define P_MAX 64
765#define P_INC 2
766
767/* Constraints for PLL good behavior */
768#define REF_MIN 48
769#define REF_MAX 400
770#define VCO_MIN 2400
771#define VCO_MAX 4800
772
27893390
DL		 773#define abs_diff(a, b) ({ \
774 typeof(a) __a = (a); \
775 typeof(b) __b = (b); \
776 (void) (&__a == &__b); \
777 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 778
63582983 779struct hsw_wrpll_rnp {
1c0b85c5
DL		 780 unsigned p, n2, r2;
781};
782
63582983 783static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 784{
1c0b85c5
DL		 785 unsigned budget;
786
787 switch (clock) {
788 case 25175000:
789 case 25200000:
790 case 27000000:
791 case 27027000:
792 case 37762500:
793 case 37800000:
794 case 40500000:
795 case 40541000:
796 case 54000000:
797 case 54054000:
798 case 59341000:
799 case 59400000:
800 case 72000000:
801 case 74176000:
802 case 74250000:
803 case 81000000:
804 case 81081000:
805 case 89012000:
806 case 89100000:
807 case 108000000:
808 case 108108000:
809 case 111264000:
810 case 111375000:
811 case 148352000:
812 case 148500000:
813 case 162000000:
814 case 162162000:
815 case 222525000:
816 case 222750000:
817 case 296703000:
818 case 297000000:
819 budget = 0;
820 break;
821 case 233500000:
822 case 245250000:
823 case 247750000:
824 case 253250000:
825 case 298000000:
826 budget = 1500;
827 break;
828 case 169128000:
829 case 169500000:
830 case 179500000:
831 case 202000000:
832 budget = 2000;
833 break;
834 case 256250000:
835 case 262500000:
836 case 270000000:
837 case 272500000:
838 case 273750000:
839 case 280750000:
840 case 281250000:
841 case 286000000:
842 case 291750000:
843 budget = 4000;
844 break;
845 case 267250000:
846 case 268500000:
847 budget = 5000;
848 break;
849 default:
850 budget = 1000;
851 break;
852 }
6441ab5f 853
1c0b85c5
DL		 854 return budget;
855}
856
63582983
DL		 857static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
858 unsigned r2, unsigned n2, unsigned p,
859 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 860{
861 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 862
1c0b85c5
DL		 863 /* No best (r,n,p) yet */
864 if (best->p == 0) {
865 best->p = p;
866 best->n2 = n2;
867 best->r2 = r2;
868 return;
869 }
6441ab5f 870
1c0b85c5
DL		 871 /*
872 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
873 * freq2k.
874 *
875 * delta = 1e6 *
876 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
877 * freq2k;
878 *
879 * and we would like delta <= budget.
880 *
881 * If the discrepancy is above the PPM-based budget, always prefer to
882 * improve upon the previous solution. However, if you're within the
883 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
884 */
885 a = freq2k * budget * p * r2;
886 b = freq2k * budget * best->p * best->r2;
27893390
DL		 887 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
888 diff_best = abs_diff(freq2k * best->p * best->r2,
889 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 890 c = 1000000 * diff;
891 d = 1000000 * diff_best;
892
893 if (a < c && b < d) {
894 /* If both are above the budget, pick the closer */
895 if (best->p * best->r2 * diff < p * r2 * diff_best) {
896 best->p = p;
897 best->n2 = n2;
898 best->r2 = r2;
899 }
900 } else if (a >= c && b < d) {
901 /* If A is below the threshold but B is above it? Update. */
902 best->p = p;
903 best->n2 = n2;
904 best->r2 = r2;
905 } else if (a >= c && b >= d) {
906 /* Both are below the limit, so pick the higher n2/(r2*r2) */
907 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
908 best->p = p;
909 best->n2 = n2;
910 best->r2 = r2;
911 }
912 }
913 /* Otherwise a < c && b >= d, do nothing */
914}
915
63582983 916static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
11578553
JB		 917{
918 int refclk = LC_FREQ;
919 int n, p, r;
920 u32 wrpll;
921
922 wrpll = I915_READ(reg);
114fe488
DV		 923 switch (wrpll & WRPLL_PLL_REF_MASK) {
924 case WRPLL_PLL_SSC:
925 case WRPLL_PLL_NON_SSC:
11578553
JB		 926 /*
927 * We could calculate spread here, but our checking
928 * code only cares about 5% accuracy, and spread is a max of
929 * 0.5% downspread.
930 */
931 refclk = 135;
932 break;
114fe488 933 case WRPLL_PLL_LCPLL:
11578553
JB		 934 refclk = LC_FREQ;
935 break;
936 default:
937 WARN(1, "bad wrpll refclk\n");
938 return 0;
939 }
940
941 r = wrpll & WRPLL_DIVIDER_REF_MASK;
942 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
943 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
944
20f0ec16
JB		 945 /* Convert to KHz, p & r have a fixed point portion */
946 return (refclk * n * 100) / (p * r);
11578553
JB		 947}
948
540e732c
S		 949static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
950 uint32_t dpll)
951{
952 uint32_t cfgcr1_reg, cfgcr2_reg;
953 uint32_t cfgcr1_val, cfgcr2_val;
954 uint32_t p0, p1, p2, dco_freq;
955
956 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
957 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
958
959 cfgcr1_val = I915_READ(cfgcr1_reg);
960 cfgcr2_val = I915_READ(cfgcr2_reg);
961
962 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
963 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
964
965 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
966 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
967 else
968 p1 = 1;
969
970
971 switch (p0) {
972 case DPLL_CFGCR2_PDIV_1:
973 p0 = 1;
974 break;
975 case DPLL_CFGCR2_PDIV_2:
976 p0 = 2;
977 break;
978 case DPLL_CFGCR2_PDIV_3:
979 p0 = 3;
980 break;
981 case DPLL_CFGCR2_PDIV_7:
982 p0 = 7;
983 break;
984 }
985
986 switch (p2) {
987 case DPLL_CFGCR2_KDIV_5:
988 p2 = 5;
989 break;
990 case DPLL_CFGCR2_KDIV_2:
991 p2 = 2;
992 break;
993 case DPLL_CFGCR2_KDIV_3:
994 p2 = 3;
995 break;
996 case DPLL_CFGCR2_KDIV_1:
997 p2 = 1;
998 break;
999 }
1000
1001 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1002
1003 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1004 1000) / 0x8000;
1005
1006 return dco_freq / (p0 * p1 * p2 * 5);
1007}
1008
398a017e
VS		 1009static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1010{
1011 int dotclock;
1012
1013 if (pipe_config->has_pch_encoder)
1014 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1015 &pipe_config->fdi_m_n);
1016 else if (pipe_config->has_dp_encoder)
1017 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1018 &pipe_config->dp_m_n);
1019 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1020 dotclock = pipe_config->port_clock * 2 / 3;
1021 else
1022 dotclock = pipe_config->port_clock;
1023
1024 if (pipe_config->pixel_multiplier)
1025 dotclock /= pipe_config->pixel_multiplier;
1026
1027 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1028}
540e732c
S		 1029
1030static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1031 struct intel_crtc_state *pipe_config)
540e732c
S		 1032{
1033 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1034 int link_clock = 0;
1035 uint32_t dpll_ctl1, dpll;
1036
134ffa44 1037 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1038
1039 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1040
1041 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1042 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1043 } else {
71cd8423
DL		 1044 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1045 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1046
1047 switch (link_clock) {
71cd8423 1048 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1049 link_clock = 81000;
1050 break;
71cd8423 1051 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1052 link_clock = 108000;
1053 break;
71cd8423 1054 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1055 link_clock = 135000;
1056 break;
71cd8423 1057 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1058 link_clock = 162000;
1059 break;
71cd8423 1060 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1061 link_clock = 216000;
1062 break;
71cd8423 1063 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1064 link_clock = 270000;
1065 break;
1066 default:
1067 WARN(1, "Unsupported link rate\n");
1068 break;
1069 }
1070 link_clock *= 2;
1071 }
1072
1073 pipe_config->port_clock = link_clock;
1074
398a017e 1075 ddi_dotclock_get(pipe_config);
540e732c
S		 1076}
1077
3d51278a 1078static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1079 struct intel_crtc_state *pipe_config)
11578553
JB		 1080{
1081 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1082 int link_clock = 0;
1083 u32 val, pll;
1084
26804afd 1085 val = pipe_config->ddi_pll_sel;
11578553
JB		 1086 switch (val & PORT_CLK_SEL_MASK) {
1087 case PORT_CLK_SEL_LCPLL_810:
1088 link_clock = 81000;
1089 break;
1090 case PORT_CLK_SEL_LCPLL_1350:
1091 link_clock = 135000;
1092 break;
1093 case PORT_CLK_SEL_LCPLL_2700:
1094 link_clock = 270000;
1095 break;
1096 case PORT_CLK_SEL_WRPLL1:
63582983 1097 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
11578553
JB		 1098 break;
1099 case PORT_CLK_SEL_WRPLL2:
63582983 1100 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
11578553
JB		 1101 break;
1102 case PORT_CLK_SEL_SPLL:
1103 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1104 if (pll == SPLL_PLL_FREQ_810MHz)
1105 link_clock = 81000;
1106 else if (pll == SPLL_PLL_FREQ_1350MHz)
1107 link_clock = 135000;
1108 else if (pll == SPLL_PLL_FREQ_2700MHz)
1109 link_clock = 270000;
1110 else {
1111 WARN(1, "bad spll freq\n");
1112 return;
1113 }
1114 break;
1115 default:
1116 WARN(1, "bad port clock sel\n");
1117 return;
1118 }
1119
1120 pipe_config->port_clock = link_clock * 2;
1121
398a017e 1122 ddi_dotclock_get(pipe_config);
11578553
JB		 1123}
1124
977bb38d
S		 1125static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1126 enum intel_dpll_id dpll)
1127{
aa610dcb
ID		 1128 struct intel_shared_dpll *pll;
1129 struct intel_dpll_hw_state *state;
1130 intel_clock_t clock;
1131
1132 /* For DDI ports we always use a shared PLL. */
1133 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1134 return 0;
1135
1136 pll = &dev_priv->shared_dplls[dpll];
1137 state = &pll->config.hw_state;
1138
1139 clock.m1 = 2;
1140 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1141 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1142 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1143 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1144 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1145 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1146
1147 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1148}
1149
1150static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1151 struct intel_crtc_state *pipe_config)
1152{
1153 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1154 enum port port = intel_ddi_get_encoder_port(encoder);
1155 uint32_t dpll = port;
1156
398a017e 1157 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1158
398a017e 1159 ddi_dotclock_get(pipe_config);
977bb38d
S		 1160}
1161
3d51278a 1162void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1163 struct intel_crtc_state *pipe_config)
3d51278a 1164{
22606a18
DL		 1165 struct drm_device *dev = encoder->base.dev;
1166
1167 if (INTEL_INFO(dev)->gen <= 8)
1168 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1169 else if (IS_SKYLAKE(dev))
22606a18 1170 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1171 else if (IS_BROXTON(dev))
1172 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1173}
1174
1c0b85c5 1175static void
d664c0ce
DL		 1176hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1177 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1178{
1179 uint64_t freq2k;
1180 unsigned p, n2, r2;
63582983 1181 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1182 unsigned budget;
1183
1184 freq2k = clock / 100;
1185
63582983 1186 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1187
1188 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1189 * and directly pass the LC PLL to it. */
1190 if (freq2k == 5400000) {
1191 *n2_out = 2;
1192 *p_out = 1;
1193 *r2_out = 2;
1194 return;
1195 }
1196
1197 /*
1198 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1199 * the WR PLL.
1200 *
1201 * We want R so that REF_MIN <= Ref <= REF_MAX.
1202 * Injecting R2 = 2 * R gives:
1203 * REF_MAX * r2 > LC_FREQ * 2 and
1204 * REF_MIN * r2 < LC_FREQ * 2
1205 *
1206 * Which means the desired boundaries for r2 are:
1207 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1208 *
1209 */
1210 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1211 r2 <= LC_FREQ * 2 / REF_MIN;
1212 r2++) {
1213
1214 /*
1215 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1216 *
1217 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1218 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1219 * VCO_MAX * r2 > n2 * LC_FREQ and
1220 * VCO_MIN * r2 < n2 * LC_FREQ)
1221 *
1222 * Which means the desired boundaries for n2 are:
1223 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1224 */
1225 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1226 n2 <= VCO_MAX * r2 / LC_FREQ;
1227 n2++) {
1228
1229 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1230 hsw_wrpll_update_rnp(freq2k, budget,
1231 r2, n2, p, &best);
1c0b85c5
DL		 1232 }
1233 }
6441ab5f 1234
1c0b85c5
DL		 1235 *n2_out = best.n2;
1236 *p_out = best.p;
1237 *r2_out = best.r2;
6441ab5f
PZ		 1238}
1239
0220ab6e 1240static bool
d664c0ce 1241hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1242 struct intel_crtc_state *crtc_state,
96f3f1f9 1243 struct intel_encoder *intel_encoder)
6441ab5f 1244{
96f3f1f9
VS		 1245 int clock = crtc_state->port_clock;
1246
d664c0ce 1247 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1248 struct intel_shared_dpll *pll;
716c2e55 1249 uint32_t val;
1c0b85c5 1250 unsigned p, n2, r2;
6441ab5f 1251
d664c0ce 1252 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1253
114fe488 1254 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1255 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1256 WRPLL_DIVIDER_POST(p);
1257
dd3cd74a
ACO		 1258 memset(&crtc_state->dpll_hw_state, 0,
1259 sizeof(crtc_state->dpll_hw_state));
1260
190f68c5 1261 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1262
190f68c5 1263 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1264 if (pll == NULL) {
1265 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1266 pipe_name(intel_crtc->pipe));
1267 return false;
0694001b 1268 }
d452c5b6 1269
190f68c5 1270 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1271 }
1272
6441ab5f
PZ		 1273 return true;
1274}
1275
dc253813
DL		 1276struct skl_wrpll_context {
1277 uint64_t min_deviation; /* current minimal deviation */
1278 uint64_t central_freq; /* chosen central freq */
1279 uint64_t dco_freq; /* chosen dco freq */
1280 unsigned int p; /* chosen divider */
1281};
1282
1283static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1284{
1285 memset(ctx, 0, sizeof(*ctx));
1286
1287 ctx->min_deviation = U64_MAX;
1288}
1289
1290/* DCO freq must be within +1%/-6% of the DCO central freq */
1291#define SKL_DCO_MAX_PDEVIATION 100
1292#define SKL_DCO_MAX_NDEVIATION 600
1293
1294static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1295 uint64_t central_freq,
1296 uint64_t dco_freq,
1297 unsigned int divider)
1298{
1299 uint64_t deviation;
1300
1301 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1302 central_freq);
1303
1304 /* positive deviation */
1305 if (dco_freq >= central_freq) {
1306 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1307 deviation < ctx->min_deviation) {
1308 ctx->min_deviation = deviation;
1309 ctx->central_freq = central_freq;
1310 ctx->dco_freq = dco_freq;
1311 ctx->p = divider;
1312 }
1313 /* negative deviation */
1314 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1315 deviation < ctx->min_deviation) {
1316 ctx->min_deviation = deviation;
1317 ctx->central_freq = central_freq;
1318 ctx->dco_freq = dco_freq;
1319 ctx->p = divider;
1320 }
dc253813
DL		 1321}
1322
1323static void skl_wrpll_get_multipliers(unsigned int p,
1324 unsigned int *p0 /* out */,
1325 unsigned int *p1 /* out */,
1326 unsigned int *p2 /* out */)
1327{
1328 /* even dividers */
1329 if (p % 2 == 0) {
1330 unsigned int half = p / 2;
1331
1332 if (half == 1 || half == 2 || half == 3 || half == 5) {
1333 *p0 = 2;
1334 *p1 = 1;
1335 *p2 = half;
1336 } else if (half % 2 == 0) {
1337 *p0 = 2;
1338 *p1 = half / 2;
1339 *p2 = 2;
1340 } else if (half % 3 == 0) {
1341 *p0 = 3;
1342 *p1 = half / 3;
1343 *p2 = 2;
1344 } else if (half % 7 == 0) {
1345 *p0 = 7;
1346 *p1 = half / 7;
1347 *p2 = 2;
1348 }
1349 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1350 *p0 = 3;
1351 *p1 = 1;
1352 *p2 = p / 3;
1353 } else if (p == 5 || p == 7) {
1354 *p0 = p;
1355 *p1 = 1;
1356 *p2 = 1;
1357 } else if (p == 15) {
1358 *p0 = 3;
1359 *p1 = 1;
1360 *p2 = 5;
1361 } else if (p == 21) {
1362 *p0 = 7;
1363 *p1 = 1;
1364 *p2 = 3;
1365 } else if (p == 35) {
1366 *p0 = 7;
1367 *p1 = 1;
1368 *p2 = 5;
1369 }
1370}
1371
82d35437
S		 1372struct skl_wrpll_params {
1373 uint32_t dco_fraction;
1374 uint32_t dco_integer;
1375 uint32_t qdiv_ratio;
1376 uint32_t qdiv_mode;
1377 uint32_t kdiv;
1378 uint32_t pdiv;
1379 uint32_t central_freq;
1380};
1381
76516fbc
DL		 1382static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1383 uint64_t afe_clock,
1384 uint64_t central_freq,
1385 uint32_t p0, uint32_t p1, uint32_t p2)
1386{
1387 uint64_t dco_freq;
1388
76516fbc
DL		 1389 switch (central_freq) {
1390 case 9600000000ULL:
1391 params->central_freq = 0;
1392 break;
1393 case 9000000000ULL:
1394 params->central_freq = 1;
1395 break;
1396 case 8400000000ULL:
1397 params->central_freq = 3;
1398 }
1399
1400 switch (p0) {
1401 case 1:
1402 params->pdiv = 0;
1403 break;
1404 case 2:
1405 params->pdiv = 1;
1406 break;
1407 case 3:
1408 params->pdiv = 2;
1409 break;
1410 case 7:
1411 params->pdiv = 4;
1412 break;
1413 default:
1414 WARN(1, "Incorrect PDiv\n");
1415 }
1416
1417 switch (p2) {
1418 case 5:
1419 params->kdiv = 0;
1420 break;
1421 case 2:
1422 params->kdiv = 1;
1423 break;
1424 case 3:
1425 params->kdiv = 2;
1426 break;
1427 case 1:
1428 params->kdiv = 3;
1429 break;
1430 default:
1431 WARN(1, "Incorrect KDiv\n");
1432 }
1433
1434 params->qdiv_ratio = p1;
1435 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1436
1437 dco_freq = p0 * p1 * p2 * afe_clock;
1438
1439 /*
1440 * Intermediate values are in Hz.
1441 * Divide by MHz to match bsepc
1442 */
30a7862d 1443 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1444 params->dco_fraction =
30a7862d
DL		 1445 div_u64((div_u64(dco_freq, 24) -
1446 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1447}
1448
318bd821 1449static bool
82d35437
S		 1450skl_ddi_calculate_wrpll(int clock /* in Hz */,
1451 struct skl_wrpll_params *wrpll_params)
1452{
1453 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1454 uint64_t dco_central_freq[3] = {8400000000ULL,
1455 9000000000ULL,
1456 9600000000ULL};
dc253813
DL		 1457 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1458 24, 28, 30, 32, 36, 40, 42, 44,
1459 48, 52, 54, 56, 60, 64, 66, 68,
1460 70, 72, 76, 78, 80, 84, 88, 90,
1461 92, 96, 98 };
1462 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1463 static const struct {
1464 const int *list;
1465 int n_dividers;
1466 } dividers[] = {
1467 { even_dividers, ARRAY_SIZE(even_dividers) },
1468 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1469 };
1470 struct skl_wrpll_context ctx;
1471 unsigned int dco, d, i;
1472 unsigned int p0, p1, p2;
1473
1474 skl_wrpll_context_init(&ctx);
1475
1476 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1477 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1478 for (i = 0; i < dividers[d].n_dividers; i++) {
1479 unsigned int p = dividers[d].list[i];
1480 uint64_t dco_freq = p * afe_clock;
1481
1482 skl_wrpll_try_divider(&ctx,
1483 dco_central_freq[dco],
1484 dco_freq,
1485 p);
e7ad9878
DL		 1486 /*
1487 * Skip the remaining dividers if we're sure to
1488 * have found the definitive divider, we can't
1489 * improve a 0 deviation.
1490 */
1491 if (ctx.min_deviation == 0)
1492 goto skip_remaining_dividers;
82d35437
S		 1493 }
1494 }
267db663 1495
e7ad9878 1496skip_remaining_dividers:
267db663
DL		 1497 /*
1498 * If a solution is found with an even divider, prefer
1499 * this one.
1500 */
1501 if (d == 0 && ctx.p)
1502 break;
82d35437
S		 1503 }
1504
dc253813
DL		 1505 if (!ctx.p) {
1506 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1507 return false;
dc253813 1508 }
82d35437 1509
dc253813
DL		 1510 /*
1511 * gcc incorrectly analyses that these can be used without being
1512 * initialized. To be fair, it's hard to guess.
1513 */
1514 p0 = p1 = p2 = 0;
1515 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1516 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1517 p0, p1, p2);
318bd821
DL		 1518
1519 return true;
82d35437
S		 1520}
1521
82d35437
S		 1522static bool
1523skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1524 struct intel_crtc_state *crtc_state,
96f3f1f9 1525 struct intel_encoder *intel_encoder)
82d35437
S		 1526{
1527 struct intel_shared_dpll *pll;
1528 uint32_t ctrl1, cfgcr1, cfgcr2;
96f3f1f9 1529 int clock = crtc_state->port_clock;
82d35437
S		 1530
1531 /*
1532 * See comment in intel_dpll_hw_state to understand why we always use 0
1533 * as the DPLL id in this function.
1534 */
1535
1536 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1537
1538 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1539 struct skl_wrpll_params wrpll_params = { 0, };
1540
1541 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1542
318bd821
DL		 1543 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1544 return false;
82d35437
S		 1545
1546 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1547 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1548 wrpll_params.dco_integer;
1549
1550 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1551 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1552 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1553 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1554 wrpll_params.central_freq;
1555 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
840b32b7
VS		 1556 switch (crtc_state->port_clock / 2) {
1557 case 81000:
71cd8423 1558 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437 1559 break;
840b32b7 1560 case 135000:
71cd8423 1561 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437 1562 break;
840b32b7 1563 case 270000:
71cd8423 1564 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1565 break;
1566 }
1567
1568 cfgcr1 = cfgcr2 = 0;
1569 } else /* eDP */
1570 return true;
1571
dd3cd74a
ACO		 1572 memset(&crtc_state->dpll_hw_state, 0,
1573 sizeof(crtc_state->dpll_hw_state));
1574
190f68c5
ACO		 1575 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1576 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1577 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1578
190f68c5 1579 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1580 if (pll == NULL) {
1581 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1582 pipe_name(intel_crtc->pipe));
1583 return false;
1584 }
1585
1586 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1587 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1588
1589 return true;
1590}
0220ab6e 1591
d683f3bc
S		 1592/* bxt clock parameters */
1593struct bxt_clk_div {
64987fc5 1594 int clock;
d683f3bc
S		 1595 uint32_t p1;
1596 uint32_t p2;
1597 uint32_t m2_int;
1598 uint32_t m2_frac;
1599 bool m2_frac_en;
1600 uint32_t n;
d683f3bc
S		 1601};
1602
1603/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1604static const struct bxt_clk_div bxt_dp_clk_val[] = {
1605 {162000, 4, 2, 32, 1677722, 1, 1},
1606 {270000, 4, 1, 27, 0, 0, 1},
1607 {540000, 2, 1, 27, 0, 0, 1},
1608 {216000, 3, 2, 32, 1677722, 1, 1},
1609 {243000, 4, 1, 24, 1258291, 1, 1},
1610 {324000, 4, 1, 32, 1677722, 1, 1},
1611 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1612};
1613
1614static bool
1615bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1616 struct intel_crtc_state *crtc_state,
96f3f1f9 1617 struct intel_encoder *intel_encoder)
d683f3bc
S		 1618{
1619 struct intel_shared_dpll *pll;
1620 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1621 int vco = 0;
1622 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e6292556 1623 uint32_t lanestagger;
96f3f1f9 1624 int clock = crtc_state->port_clock;
d683f3bc
S		 1625
1626 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1627 intel_clock_t best_clock;
1628
1629 /* Calculate HDMI div */
1630 /*
1631 * FIXME: tie the following calculation into
1632 * i9xx_crtc_compute_clock
1633 */
1634 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1635 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1636 clock, pipe_name(intel_crtc->pipe));
1637 return false;
1638 }
1639
1640 clk_div.p1 = best_clock.p1;
1641 clk_div.p2 = best_clock.p2;
1642 WARN_ON(best_clock.m1 != 2);
1643 clk_div.n = best_clock.n;
1644 clk_div.m2_int = best_clock.m2 >> 22;
1645 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1646 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1647
b6dc71f3 1648 vco = best_clock.vco;
d683f3bc
S		 1649 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1650 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1651 int i;
d683f3bc 1652
64987fc5
SJ		 1653 clk_div = bxt_dp_clk_val[0];
1654 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1655 if (bxt_dp_clk_val[i].clock == clock) {
1656 clk_div = bxt_dp_clk_val[i];
1657 break;
1658 }
d683f3bc 1659 }
b6dc71f3
VK		 1660 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1661 }
1662
e6292556 1663 if (vco >= 6200000 && vco <= 6700000) {
b6dc71f3
VK		 1664 prop_coef = 4;
1665 int_coef = 9;
1666 gain_ctl = 3;
1667 targ_cnt = 8;
1668 } else if ((vco > 5400000 && vco < 6200000) ||
1669 (vco >= 4800000 && vco < 5400000)) {
1670 prop_coef = 5;
1671 int_coef = 11;
1672 gain_ctl = 3;
1673 targ_cnt = 9;
b6dc71f3
VK		 1674 } else if (vco == 5400000) {
1675 prop_coef = 3;
1676 int_coef = 8;
1677 gain_ctl = 1;
1678 targ_cnt = 9;
1679 } else {
1680 DRM_ERROR("Invalid VCO\n");
1681 return false;
d683f3bc
S		 1682 }
1683
dd3cd74a
ACO		 1684 memset(&crtc_state->dpll_hw_state, 0,
1685 sizeof(crtc_state->dpll_hw_state));
1686
e0681e38
VK		 1687 if (clock > 270000)
1688 lanestagger = 0x18;
1689 else if (clock > 135000)
1690 lanestagger = 0x0d;
1691 else if (clock > 67000)
1692 lanestagger = 0x07;
1693 else if (clock > 33000)
1694 lanestagger = 0x04;
1695 else
1696 lanestagger = 0x02;
1697
d683f3bc
S		 1698 crtc_state->dpll_hw_state.ebb0 =
1699 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1700 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1701 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1702 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1703
1704 if (clk_div.m2_frac_en)
1705 crtc_state->dpll_hw_state.pll3 =
1706 PORT_PLL_M2_FRAC_ENABLE;
1707
1708 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1709 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1710 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1711 PORT_PLL_GAIN_CTL(gain_ctl);
1712
1713 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1714
05712c15
ID		 1715 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1716
e6292556
VK		 1717 crtc_state->dpll_hw_state.pll10 =
1718 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1719 | PORT_PLL_DCO_AMP_OVR_EN_H;
d683f3bc 1720
05712c15
ID		 1721 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1722
d683f3bc 1723 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1724 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1725
1726 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1727 if (pll == NULL) {
1728 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1729 pipe_name(intel_crtc->pipe));
1730 return false;
1731 }
1732
1733 /* shared DPLL id 0 is DPLL A */
1734 crtc_state->ddi_pll_sel = pll->id;
1735
1736 return true;
1737}
1738
0220ab6e
DL		 1739/*
1740 * Tries to find a *shared* PLL for the CRTC and store it in
1741 * intel_crtc->ddi_pll_sel.
1742 *
1743 * For private DPLLs, compute_config() should do the selection for us. This
1744 * function should be folded into compute_config() eventually.
1745 */
190f68c5
ACO		 1746bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1747 struct intel_crtc_state *crtc_state)
0220ab6e 1748{
82d35437 1749 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1750 struct intel_encoder *intel_encoder =
3165c074 1751 intel_ddi_get_crtc_new_encoder(crtc_state);
0220ab6e 1752
82d35437 1753 if (IS_SKYLAKE(dev))
190f68c5 1754 return skl_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1755 intel_encoder);
d683f3bc
S		 1756 else if (IS_BROXTON(dev))
1757 return bxt_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1758 intel_encoder);
82d35437 1759 else
190f68c5 1760 return hsw_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1761 intel_encoder);
0220ab6e
DL		 1762}
1763
dae84799
PZ		 1764void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1765{
1766 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1768 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1769 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1770 int type = intel_encoder->type;
1771 uint32_t temp;
1772
0e32b39c 1773 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1774 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1775 switch (intel_crtc->config->pipe_bpp) {
dae84799 1776 case 18:
c9809791 1777 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1778 break;
1779 case 24:
c9809791 1780 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1781 break;
1782 case 30:
c9809791 1783 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1784 break;
1785 case 36:
c9809791 1786 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1787 break;
1788 default:
4e53c2e0 1789 BUG();
dae84799 1790 }
c9809791 1791 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1792 }
1793}
1794
0e32b39c
DA		 1795void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1796{
1797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1798 struct drm_device *dev = crtc->dev;
1799 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1800 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1801 uint32_t temp;
1802 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1803 if (state == true)
1804 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1805 else
1806 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1807 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1808}
1809
8228c251 1810void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1811{
1812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1813 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1814 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1815 struct drm_device *dev = crtc->dev;
1816 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1817 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1818 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1819 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1820 int type = intel_encoder->type;
8d9ddbcb
PZ		 1821 uint32_t temp;
1822
ad80a810
PZ		 1823 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1824 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1825 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1826
6e3c9717 1827 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1828 case 18:
ad80a810 1829 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1830 break;
1831 case 24:
ad80a810 1832 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1833 break;
1834 case 30:
ad80a810 1835 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1836 break;
1837 case 36:
ad80a810 1838 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1839 break;
1840 default:
4e53c2e0 1841 BUG();
dfcef252 1842 }
72662e10 1843
6e3c9717 1844 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1845 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1846 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1847 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1848
e6f0bfc4
PZ		 1849 if (cpu_transcoder == TRANSCODER_EDP) {
1850 switch (pipe) {
1851 case PIPE_A:
c7670b10
PZ		 1852 /* On Haswell, can only use the always-on power well for
1853 * eDP when not using the panel fitter, and when not
1854 * using motion blur mitigation (which we don't
1855 * support). */
fabf6e51 1856 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1857 (intel_crtc->config->pch_pfit.enabled ||
1858 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1859 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1860 else
1861 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1862 break;
1863 case PIPE_B:
1864 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1865 break;
1866 case PIPE_C:
1867 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1868 break;
1869 default:
1870 BUG();
1871 break;
1872 }
1873 }
1874
7739c33b 1875 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1876 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1877 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1878 else
ad80a810 1879 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1880
7739c33b 1881 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1882 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1883 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1884
1885 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1886 type == INTEL_OUTPUT_EDP) {
1887 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1888
0e32b39c
DA		 1889 if (intel_dp->is_mst) {
1890 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1891 } else
1892 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1893
90a6b7b0 1894 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
0e32b39c
DA		 1895 } else if (type == INTEL_OUTPUT_DP_MST) {
1896 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1897
1898 if (intel_dp->is_mst) {
1899 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1900 } else
1901 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1902
90a6b7b0 1903 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
8d9ddbcb 1904 } else {
84f44ce7
VS		 1905 WARN(1, "Invalid encoder type %d for pipe %c\n",
1906 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1907 }
1908
ad80a810 1909 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1910}
72662e10 1911
ad80a810
PZ		 1912void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1913 enum transcoder cpu_transcoder)
8d9ddbcb 1914{
ad80a810 1915 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1916 uint32_t val = I915_READ(reg);
1917
0e32b39c 1918 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1919 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1920 I915_WRITE(reg, val);
72662e10
ED		 1921}
1922
bcbc889b
PZ		 1923bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1924{
1925 struct drm_device *dev = intel_connector->base.dev;
1926 struct drm_i915_private *dev_priv = dev->dev_private;
1927 struct intel_encoder *intel_encoder = intel_connector->encoder;
1928 int type = intel_connector->base.connector_type;
1929 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1930 enum pipe pipe = 0;
1931 enum transcoder cpu_transcoder;
882244a3 1932 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1933 uint32_t tmp;
1934
882244a3 1935 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1936 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1937 return false;
1938
bcbc889b
PZ		 1939 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1940 return false;
1941
1942 if (port == PORT_A)
1943 cpu_transcoder = TRANSCODER_EDP;
1944 else
1a240d4d 1945 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1946
1947 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1948
1949 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1950 case TRANS_DDI_MODE_SELECT_HDMI:
1951 case TRANS_DDI_MODE_SELECT_DVI:
1952 return (type == DRM_MODE_CONNECTOR_HDMIA);
1953
1954 case TRANS_DDI_MODE_SELECT_DP_SST:
1955 if (type == DRM_MODE_CONNECTOR_eDP)
1956 return true;
bcbc889b 1957 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1958 case TRANS_DDI_MODE_SELECT_DP_MST:
1959 /* if the transcoder is in MST state then
1960 * connector isn't connected */
1961 return false;
bcbc889b
PZ		 1962
1963 case TRANS_DDI_MODE_SELECT_FDI:
1964 return (type == DRM_MODE_CONNECTOR_VGA);
1965
1966 default:
1967 return false;
1968 }
1969}
1970
85234cdc
DV		 1971bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1972 enum pipe *pipe)
1973{
1974 struct drm_device *dev = encoder->base.dev;
1975 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1976 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1977 enum intel_display_power_domain power_domain;
85234cdc
DV		 1978 u32 tmp;
1979 int i;
1980
6d129bea 1981 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1982 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1983 return false;
1984
fe43d3f5 1985 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1986
1987 if (!(tmp & DDI_BUF_CTL_ENABLE))
1988 return false;
1989
ad80a810
PZ		 1990 if (port == PORT_A) {
1991 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1992
ad80a810
PZ		 1993 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1994 case TRANS_DDI_EDP_INPUT_A_ON:
1995 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1996 *pipe = PIPE_A;
1997 break;
1998 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1999 *pipe = PIPE_B;
2000 break;
2001 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2002 *pipe = PIPE_C;
2003 break;
2004 }
2005
2006 return true;
2007 } else {
2008 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2009 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2010
2011 if ((tmp & TRANS_DDI_PORT_MASK)
2012 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 2013 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2014 return false;
2015
ad80a810
PZ		 2016 *pipe = i;
2017 return true;
2018 }
85234cdc
DV		 2019 }
2020 }
2021
84f44ce7 2022 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2023
22f9fe50 2024 return false;
85234cdc
DV		 2025}
2026
fc914639
PZ		 2027void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2028{
2029 struct drm_crtc *crtc = &intel_crtc->base;
2030 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2031 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2032 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2033 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2034
bb523fc0
PZ		 2035 if (cpu_transcoder != TRANSCODER_EDP)
2036 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2037 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2038}
2039
2040void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2041{
2042 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2043 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2044
bb523fc0
PZ		 2045 if (cpu_transcoder != TRANSCODER_EDP)
2046 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2047 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2048}
2049
f8896f5d
DW		 2050static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2051 enum port port, int type)
2052{
2053 struct drm_i915_private *dev_priv = dev->dev_private;
2054 const struct ddi_buf_trans *ddi_translations;
2055 uint8_t iboost;
75067dde 2056 uint8_t dp_iboost, hdmi_iboost;
f8896f5d
DW		 2057 int n_entries;
2058 u32 reg;
2059
75067dde
AK		 2060 /* VBT may override standard boost values */
2061 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2062 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2063
f8896f5d 2064 if (type == INTEL_OUTPUT_DISPLAYPORT) {
75067dde
AK		 2065 if (dp_iboost) {
2066 iboost = dp_iboost;
2067 } else {
2068 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2069 iboost = ddi_translations[port].i_boost;
2070 }
f8896f5d 2071 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 2072 if (dp_iboost) {
2073 iboost = dp_iboost;
2074 } else {
2075 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2076 iboost = ddi_translations[port].i_boost;
2077 }
f8896f5d 2078 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 2079 if (hdmi_iboost) {
2080 iboost = hdmi_iboost;
2081 } else {
2082 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2083 iboost = ddi_translations[port].i_boost;
2084 }
f8896f5d
DW		 2085 } else {
2086 return;
2087 }
2088
2089 /* Make sure that the requested I_boost is valid */
2090 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2091 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2092 return;
2093 }
2094
2095 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2096 reg &= ~BALANCE_LEG_MASK(port);
2097 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2098
2099 if (iboost)
2100 reg |= iboost << BALANCE_LEG_SHIFT(port);
2101 else
2102 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2103
2104 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2105}
2106
2107static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2108 enum port port, int type)
96fb9f9b
VK		 2109{
2110 struct drm_i915_private *dev_priv = dev->dev_private;
2111 const struct bxt_ddi_buf_trans *ddi_translations;
2112 u32 n_entries, i;
2113 uint32_t val;
2114
2115 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2116 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2117 ddi_translations = bxt_ddi_translations_dp;
2118 } else if (type == INTEL_OUTPUT_HDMI) {
2119 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2120 ddi_translations = bxt_ddi_translations_hdmi;
2121 } else {
2122 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2123 type);
2124 return;
2125 }
2126
2127 /* Check if default value has to be used */
2128 if (level >= n_entries ||
2129 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2130 for (i = 0; i < n_entries; i++) {
2131 if (ddi_translations[i].default_index) {
2132 level = i;
2133 break;
2134 }
2135 }
2136 }
2137
2138 /*
2139 * While we write to the group register to program all lanes at once we
2140 * can read only lane registers and we pick lanes 0/1 for that.
2141 */
2142 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2143 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2144 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2145
2146 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2147 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2148 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2149 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2150 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2151
2152 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2153 val &= ~UNIQE_TRANGE_EN_METHOD;
2154 if (ddi_translations[level].enable)
2155 val |= UNIQE_TRANGE_EN_METHOD;
2156 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2157
2158 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2159 val &= ~DE_EMPHASIS;
2160 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2161 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2162
2163 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2164 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2165 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2166}
2167
f8896f5d
DW		 2168static uint32_t translate_signal_level(int signal_levels)
2169{
2170 uint32_t level;
2171
2172 switch (signal_levels) {
2173 default:
2174 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2175 signal_levels);
2176 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2177 level = 0;
2178 break;
2179 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2180 level = 1;
2181 break;
2182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2183 level = 2;
2184 break;
2185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2186 level = 3;
2187 break;
2188
2189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2190 level = 4;
2191 break;
2192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2193 level = 5;
2194 break;
2195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2196 level = 6;
2197 break;
2198
2199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2200 level = 7;
2201 break;
2202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2203 level = 8;
2204 break;
2205
2206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2207 level = 9;
2208 break;
2209 }
2210
2211 return level;
2212}
2213
2214uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2215{
2216 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2217 struct drm_device *dev = dport->base.base.dev;
2218 struct intel_encoder *encoder = &dport->base;
2219 uint8_t train_set = intel_dp->train_set[0];
2220 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2221 DP_TRAIN_PRE_EMPHASIS_MASK);
2222 enum port port = dport->port;
2223 uint32_t level;
2224
2225 level = translate_signal_level(signal_levels);
2226
2227 if (IS_SKYLAKE(dev))
2228 skl_ddi_set_iboost(dev, level, port, encoder->type);
2229 else if (IS_BROXTON(dev))
2230 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2231
2232 return DDI_BUF_TRANS_SELECT(level);
2233}
2234
00c09d70 2235static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 2236{
c19b0669 2237 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2238 struct drm_device *dev = encoder->dev;
2239 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 2240 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 2241 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2242 int type = intel_encoder->type;
96fb9f9b 2243 int hdmi_level;
6441ab5f 2244
82a4d9c0
PZ		 2245 if (type == INTEL_OUTPUT_EDP) {
2246 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 2247 intel_edp_panel_on(intel_dp);
82a4d9c0 2248 }
6441ab5f 2249
efa80add 2250 if (IS_SKYLAKE(dev)) {
6e3c9717 2251 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 2252 uint32_t val;
2253
5416d871
DL		 2254 /*
2255 * DPLL0 is used for eDP and is the only "private" DPLL (as
2256 * opposed to shared) on SKL
2257 */
2258 if (type == INTEL_OUTPUT_EDP) {
2259 WARN_ON(dpll != SKL_DPLL0);
2260
2261 val = I915_READ(DPLL_CTRL1);
2262
2263 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2264 DPLL_CTRL1_SSC(dpll) |
71cd8423 2265 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 2266 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2267
2268 I915_WRITE(DPLL_CTRL1, val);
2269 POSTING_READ(DPLL_CTRL1);
2270 }
2271
2272 /* DDI -> PLL mapping */
efa80add
S		 2273 val = I915_READ(DPLL_CTRL2);
2274
2275 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2276 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2277 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2278 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2279
2280 I915_WRITE(DPLL_CTRL2, val);
5416d871 2281
1ab23380 2282 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 2283 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2284 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 2285 }
c19b0669 2286
82a4d9c0 2287 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2288 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2289
901c2daf
VS		 2290 intel_dp_set_link_params(intel_dp, crtc->config);
2291
44905a27 2292 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2293
2294 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2295 intel_dp_start_link_train(intel_dp);
2296 intel_dp_complete_link_train(intel_dp);
23f08d83 2297 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 2298 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2299 } else if (type == INTEL_OUTPUT_HDMI) {
2300 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2301
96fb9f9b
VK		 2302 if (IS_BROXTON(dev)) {
2303 hdmi_level = dev_priv->vbt.
2304 ddi_port_info[port].hdmi_level_shift;
2305 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2306 INTEL_OUTPUT_HDMI);
2307 }
30cf6db8 2308 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2309 crtc->config->has_hdmi_sink,
2310 &crtc->config->base.adjusted_mode);
c19b0669 2311 }
6441ab5f
PZ		 2312}
2313
00c09d70 2314static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2315{
2316 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2317 struct drm_device *dev = encoder->dev;
2318 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2319 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2320 int type = intel_encoder->type;
2886e93f 2321 uint32_t val;
a836bdf9 2322 bool wait = false;
2886e93f
PZ		 2323
2324 val = I915_READ(DDI_BUF_CTL(port));
2325 if (val & DDI_BUF_CTL_ENABLE) {
2326 val &= ~DDI_BUF_CTL_ENABLE;
2327 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2328 wait = true;
2886e93f 2329 }
6441ab5f 2330
a836bdf9
PZ		 2331 val = I915_READ(DP_TP_CTL(port));
2332 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2333 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2334 I915_WRITE(DP_TP_CTL(port), val);
2335
2336 if (wait)
2337 intel_wait_ddi_buf_idle(dev_priv, port);
2338
76bb80ed 2339 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2340 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2341 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2342 intel_edp_panel_vdd_on(intel_dp);
4be73780 2343 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2344 }
2345
efa80add
S		 2346 if (IS_SKYLAKE(dev))
2347 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2348 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2349 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2350 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2351}
2352
00c09d70 2353static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2354{
6547fef8 2355 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2356 struct drm_crtc *crtc = encoder->crtc;
2357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2358 struct drm_device *dev = encoder->dev;
72662e10 2359 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2360 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2361 int type = intel_encoder->type;
72662e10 2362
6547fef8 2363 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2364 struct intel_digital_port *intel_dig_port =
2365 enc_to_dig_port(encoder);
2366
6547fef8
PZ		 2367 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2368 * are ignored so nothing special needs to be done besides
2369 * enabling the port.
2370 */
876a8cdf 2371 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2372 intel_dig_port->saved_port_bits |
2373 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2374 } else if (type == INTEL_OUTPUT_EDP) {
2375 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2376
23f08d83 2377 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2378 intel_dp_stop_link_train(intel_dp);
2379
4be73780 2380 intel_edp_backlight_on(intel_dp);
0bc12bcb 2381 intel_psr_enable(intel_dp);
c395578e 2382 intel_edp_drrs_enable(intel_dp);
6547fef8 2383 }
7b9f35a6 2384
6e3c9717 2385 if (intel_crtc->config->has_audio) {
d45a0bf5 2386 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2387 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2388 }
5ab432ef
DV		 2389}
2390
00c09d70 2391static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2392{
d6c50ff8 2393 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2394 struct drm_crtc *crtc = encoder->crtc;
2395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2396 int type = intel_encoder->type;
7b9f35a6
WX		 2397 struct drm_device *dev = encoder->dev;
2398 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2399
6e3c9717 2400 if (intel_crtc->config->has_audio) {
69bfe1a9 2401 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2402 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2403 }
2831d842 2404
d6c50ff8
PZ		 2405 if (type == INTEL_OUTPUT_EDP) {
2406 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2407
c395578e 2408 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2409 intel_psr_disable(intel_dp);
4be73780 2410 intel_edp_backlight_off(intel_dp);
d6c50ff8 2411 }
72662e10 2412}
79f689aa 2413
e0b01be4
DV		 2414static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2415 struct intel_shared_dpll *pll)
2416{
3e369b76 2417 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2418 POSTING_READ(WRPLL_CTL(pll->id));
2419 udelay(20);
2420}
2421
12030431
DV		 2422static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2423 struct intel_shared_dpll *pll)
2424{
2425 uint32_t val;
2426
2427 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2428 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2429 POSTING_READ(WRPLL_CTL(pll->id));
2430}
2431
d452c5b6
DV		 2432static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2433 struct intel_shared_dpll *pll,
2434 struct intel_dpll_hw_state *hw_state)
2435{
2436 uint32_t val;
2437
f458ebbc 2438 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2439 return false;
2440
2441 val = I915_READ(WRPLL_CTL(pll->id));
2442 hw_state->wrpll = val;
2443
2444 return val & WRPLL_PLL_ENABLE;
2445}
2446
ca1381b5 2447static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2448 "WRPLL 1",
2449 "WRPLL 2",
2450};
2451
143b307c 2452static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2453{
9cd86933
DV		 2454 int i;
2455
716c2e55 2456 dev_priv->num_shared_dpll = 2;
9cd86933 2457
716c2e55 2458 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2459 dev_priv->shared_dplls[i].id = i;
2460 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2461 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2462 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2463 dev_priv->shared_dplls[i].get_hw_state =
2464 hsw_ddi_pll_get_hw_state;
9cd86933 2465 }
143b307c
DL		 2466}
2467
d1a2dc78
S		 2468static const char * const skl_ddi_pll_names[] = {
2469 "DPLL 1",
2470 "DPLL 2",
2471 "DPLL 3",
2472};
2473
2474struct skl_dpll_regs {
2475 u32 ctl, cfgcr1, cfgcr2;
2476};
2477
2478/* this array is indexed by the *shared* pll id */
2479static const struct skl_dpll_regs skl_dpll_regs[3] = {
2480 {
2481 /* DPLL 1 */
2482 .ctl = LCPLL2_CTL,
2483 .cfgcr1 = DPLL1_CFGCR1,
2484 .cfgcr2 = DPLL1_CFGCR2,
2485 },
2486 {
2487 /* DPLL 2 */
2488 .ctl = WRPLL_CTL1,
2489 .cfgcr1 = DPLL2_CFGCR1,
2490 .cfgcr2 = DPLL2_CFGCR2,
2491 },
2492 {
2493 /* DPLL 3 */
2494 .ctl = WRPLL_CTL2,
2495 .cfgcr1 = DPLL3_CFGCR1,
2496 .cfgcr2 = DPLL3_CFGCR2,
2497 },
2498};
2499
2500static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2501 struct intel_shared_dpll *pll)
2502{
2503 uint32_t val;
2504 unsigned int dpll;
2505 const struct skl_dpll_regs *regs = skl_dpll_regs;
2506
2507 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2508 dpll = pll->id + 1;
2509
2510 val = I915_READ(DPLL_CTRL1);
2511
2512 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2513 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2514 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2515
2516 I915_WRITE(DPLL_CTRL1, val);
2517 POSTING_READ(DPLL_CTRL1);
2518
2519 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2520 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2521 POSTING_READ(regs[pll->id].cfgcr1);
2522 POSTING_READ(regs[pll->id].cfgcr2);
2523
2524 /* the enable bit is always bit 31 */
2525 I915_WRITE(regs[pll->id].ctl,
2526 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2527
2528 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2529 DRM_ERROR("DPLL %d not locked\n", dpll);
2530}
2531
2532static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2533 struct intel_shared_dpll *pll)
2534{
2535 const struct skl_dpll_regs *regs = skl_dpll_regs;
2536
2537 /* the enable bit is always bit 31 */
2538 I915_WRITE(regs[pll->id].ctl,
2539 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2540 POSTING_READ(regs[pll->id].ctl);
2541}
2542
2543static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2544 struct intel_shared_dpll *pll,
2545 struct intel_dpll_hw_state *hw_state)
2546{
2547 uint32_t val;
2548 unsigned int dpll;
2549 const struct skl_dpll_regs *regs = skl_dpll_regs;
2550
2551 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2552 return false;
2553
2554 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2555 dpll = pll->id + 1;
2556
2557 val = I915_READ(regs[pll->id].ctl);
2558 if (!(val & LCPLL_PLL_ENABLE))
2559 return false;
2560
2561 val = I915_READ(DPLL_CTRL1);
2562 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2563
2564 /* avoid reading back stale values if HDMI mode is not enabled */
2565 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2566 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2567 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2568 }
2569
2570 return true;
2571}
2572
2573static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2574{
2575 int i;
2576
2577 dev_priv->num_shared_dpll = 3;
2578
2579 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2580 dev_priv->shared_dplls[i].id = i;
2581 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2582 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2583 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2584 dev_priv->shared_dplls[i].get_hw_state =
2585 skl_ddi_pll_get_hw_state;
2586 }
2587}
2588
5c6706e5
VK		 2589static void broxton_phy_init(struct drm_i915_private *dev_priv,
2590 enum dpio_phy phy)
2591{
2592 enum port port;
2593 uint32_t val;
2594
2595 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2596 val |= GT_DISPLAY_POWER_ON(phy);
2597 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2598
2599 /* Considering 10ms timeout until BSpec is updated */
2600 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2601 DRM_ERROR("timeout during PHY%d power on\n", phy);
2602
2603 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2604 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2605 int lane;
2606
2607 for (lane = 0; lane < 4; lane++) {
2608 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2609 /*
2610 * Note that on CHV this flag is called UPAR, but has
2611 * the same function.
2612 */
2613 val &= ~LATENCY_OPTIM;
2614 if (lane != 1)
2615 val |= LATENCY_OPTIM;
2616
2617 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2618 }
2619 }
2620
2621 /* Program PLL Rcomp code offset */
2622 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2623 val &= ~IREF0RC_OFFSET_MASK;
2624 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2625 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2626
2627 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2628 val &= ~IREF1RC_OFFSET_MASK;
2629 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2630 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2631
2632 /* Program power gating */
2633 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2634 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2635 SUS_CLK_CONFIG;
2636 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2637
2638 if (phy == DPIO_PHY0) {
2639 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2640 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2641 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2642 }
2643
2644 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2645 val &= ~OCL2_LDOFUSE_PWR_DIS;
2646 /*
2647 * On PHY1 disable power on the second channel, since no port is
2648 * connected there. On PHY0 both channels have a port, so leave it
2649 * enabled.
2650 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2651 * power down the second channel on PHY0 as well.
2652 */
2653 if (phy == DPIO_PHY1)
2654 val |= OCL2_LDOFUSE_PWR_DIS;
2655 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2656
2657 if (phy == DPIO_PHY0) {
2658 uint32_t grc_code;
2659 /*
2660 * PHY0 isn't connected to an RCOMP resistor so copy over
2661 * the corresponding calibrated value from PHY1, and disable
2662 * the automatic calibration on PHY0.
2663 */
2664 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2665 10))
2666 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2667
2668 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2669 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2670 grc_code = val << GRC_CODE_FAST_SHIFT |
2671 val << GRC_CODE_SLOW_SHIFT |
2672 val;
2673 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2674
2675 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2676 val |= GRC_DIS | GRC_RDY_OVRD;
2677 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2678 }
2679
2680 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2681 val |= COMMON_RESET_DIS;
2682 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2683}
2684
2685void broxton_ddi_phy_init(struct drm_device *dev)
2686{
2687 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2688 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2689 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2690}
2691
2692static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2693 enum dpio_phy phy)
2694{
2695 uint32_t val;
2696
2697 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2698 val &= ~COMMON_RESET_DIS;
2699 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2700}
2701
2702void broxton_ddi_phy_uninit(struct drm_device *dev)
2703{
2704 struct drm_i915_private *dev_priv = dev->dev_private;
2705
2706 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2707 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2708
2709 /* FIXME: do this in broxton_phy_uninit per phy */
2710 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2711}
2712
dfb82408
S		 2713static const char * const bxt_ddi_pll_names[] = {
2714 "PORT PLL A",
2715 "PORT PLL B",
2716 "PORT PLL C",
2717};
2718
2719static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2720 struct intel_shared_dpll *pll)
2721{
2722 uint32_t temp;
2723 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2724
2725 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2726 temp &= ~PORT_PLL_REF_SEL;
2727 /* Non-SSC reference */
2728 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2729
2730 /* Disable 10 bit clock */
2731 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2732 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2733 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2734
2735 /* Write P1 & P2 */
2736 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2737 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2738 temp |= pll->config.hw_state.ebb0;
2739 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2740
2741 /* Write M2 integer */
2742 temp = I915_READ(BXT_PORT_PLL(port, 0));
2743 temp &= ~PORT_PLL_M2_MASK;
2744 temp |= pll->config.hw_state.pll0;
2745 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2746
2747 /* Write N */
2748 temp = I915_READ(BXT_PORT_PLL(port, 1));
2749 temp &= ~PORT_PLL_N_MASK;
2750 temp |= pll->config.hw_state.pll1;
2751 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2752
2753 /* Write M2 fraction */
2754 temp = I915_READ(BXT_PORT_PLL(port, 2));
2755 temp &= ~PORT_PLL_M2_FRAC_MASK;
2756 temp |= pll->config.hw_state.pll2;
2757 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2758
2759 /* Write M2 fraction enable */
2760 temp = I915_READ(BXT_PORT_PLL(port, 3));
2761 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2762 temp |= pll->config.hw_state.pll3;
2763 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2764
2765 /* Write coeff */
2766 temp = I915_READ(BXT_PORT_PLL(port, 6));
2767 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2768 temp &= ~PORT_PLL_INT_COEFF_MASK;
2769 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2770 temp |= pll->config.hw_state.pll6;
2771 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2772
2773 /* Write calibration val */
2774 temp = I915_READ(BXT_PORT_PLL(port, 8));
2775 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2776 temp |= pll->config.hw_state.pll8;
2777 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2778
b6dc71f3
VK		 2779 temp = I915_READ(BXT_PORT_PLL(port, 9));
2780 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
05712c15 2781 temp |= pll->config.hw_state.pll9;
b6dc71f3
VK		 2782 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2783
2784 temp = I915_READ(BXT_PORT_PLL(port, 10));
2785 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2786 temp &= ~PORT_PLL_DCO_AMP_MASK;
2787 temp |= pll->config.hw_state.pll10;
2788 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2789
2790 /* Recalibrate with new settings */
2791 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2792 temp |= PORT_PLL_RECALIBRATE;
2793 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
05712c15
ID		 2794 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2795 temp |= pll->config.hw_state.ebb4;
dfb82408
S		 2796 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2797
2798 /* Enable PLL */
2799 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2800 temp |= PORT_PLL_ENABLE;
2801 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2802 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2803
2804 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2805 PORT_PLL_LOCK), 200))
2806 DRM_ERROR("PLL %d not locked\n", port);
2807
2808 /*
2809 * While we write to the group register to program all lanes at once we
2810 * can read only lane registers and we pick lanes 0/1 for that.
2811 */
2812 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2813 temp &= ~LANE_STAGGER_MASK;
2814 temp &= ~LANESTAGGER_STRAP_OVRD;
2815 temp |= pll->config.hw_state.pcsdw12;
2816 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2817}
2818
2819static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2820 struct intel_shared_dpll *pll)
2821{
2822 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2823 uint32_t temp;
2824
2825 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2826 temp &= ~PORT_PLL_ENABLE;
2827 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2828 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2829}
2830
2831static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2832 struct intel_shared_dpll *pll,
2833 struct intel_dpll_hw_state *hw_state)
2834{
2835 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2836 uint32_t val;
2837
2838 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2839 return false;
2840
2841 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2842 if (!(val & PORT_PLL_ENABLE))
2843 return false;
2844
2845 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
793dfa59
ID		 2846 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2847
05712c15
ID		 2848 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2849 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2850
dfb82408 2851 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
793dfa59
ID		 2852 hw_state->pll0 &= PORT_PLL_M2_MASK;
2853
dfb82408 2854 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
793dfa59
ID		 2855 hw_state->pll1 &= PORT_PLL_N_MASK;
2856
dfb82408 2857 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
793dfa59
ID		 2858 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2859
dfb82408 2860 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
793dfa59
ID		 2861 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2862
dfb82408 2863 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
793dfa59
ID		 2864 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2865 PORT_PLL_INT_COEFF_MASK |
2866 PORT_PLL_GAIN_CTL_MASK;
2867
dfb82408 2868 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
793dfa59
ID		 2869 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2870
05712c15
ID		 2871 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2872 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2873
b6dc71f3 2874 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
793dfa59
ID		 2875 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2876 PORT_PLL_DCO_AMP_MASK;
2877
dfb82408
S		 2878 /*
2879 * While we write to the group register to program all lanes at once we
2880 * can read only lane registers. We configure all lanes the same way, so
2881 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2882 */
2883 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
b5dada82 2884 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
dfb82408
S		 2885 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2886 hw_state->pcsdw12,
2887 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
793dfa59 2888 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
dfb82408
S		 2889
2890 return true;
2891}
2892
2893static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2894{
2895 int i;
2896
2897 dev_priv->num_shared_dpll = 3;
2898
2899 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2900 dev_priv->shared_dplls[i].id = i;
2901 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2902 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2903 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2904 dev_priv->shared_dplls[i].get_hw_state =
2905 bxt_ddi_pll_get_hw_state;
2906 }
2907}
2908
143b307c
DL		 2909void intel_ddi_pll_init(struct drm_device *dev)
2910{
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912 uint32_t val = I915_READ(LCPLL_CTL);
2913
d1a2dc78
S		 2914 if (IS_SKYLAKE(dev))
2915 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2916 else if (IS_BROXTON(dev))
2917 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2918 else
2919 hsw_shared_dplls_init(dev_priv);
79f689aa 2920
121643c2 2921 if (IS_SKYLAKE(dev)) {
d9062ae5
DL		 2922 int cdclk_freq;
2923
2924 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 2925 dev_priv->skl_boot_cdclk = cdclk_freq;
121643c2
S		 2926 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2927 DRM_ERROR("LCPLL1 is disabled\n");
5d96d8af
DL		 2928 else
2929 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2930 } else if (IS_BROXTON(dev)) {
2931 broxton_init_cdclk(dev);
5c6706e5 2932 broxton_ddi_phy_init(dev);
121643c2
S		 2933 } else {
2934 /*
2935 * The LCPLL register should be turned on by the BIOS. For now
2936 * let's just check its state and print errors in case
2937 * something is wrong. Don't even try to turn it on.
2938 */
2939
2940 if (val & LCPLL_CD_SOURCE_FCLK)
2941 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2942
121643c2
S		 2943 if (val & LCPLL_PLL_DISABLE)
2944 DRM_ERROR("LCPLL is disabled\n");
2945 }
79f689aa 2946}
c19b0669
PZ		 2947
2948void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2949{
174edf1f
PZ		 2950 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2951 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2952 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2953 enum port port = intel_dig_port->port;
c19b0669 2954 uint32_t val;
f3e227df 2955 bool wait = false;
c19b0669
PZ		 2956
2957 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2958 val = I915_READ(DDI_BUF_CTL(port));
2959 if (val & DDI_BUF_CTL_ENABLE) {
2960 val &= ~DDI_BUF_CTL_ENABLE;
2961 I915_WRITE(DDI_BUF_CTL(port), val);
2962 wait = true;
2963 }
2964
2965 val = I915_READ(DP_TP_CTL(port));
2966 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2967 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2968 I915_WRITE(DP_TP_CTL(port), val);
2969 POSTING_READ(DP_TP_CTL(port));
2970
2971 if (wait)
2972 intel_wait_ddi_buf_idle(dev_priv, port);
2973 }
2974
0e32b39c 2975 val = DP_TP_CTL_ENABLE |
c19b0669 2976 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2977 if (intel_dp->is_mst)
2978 val |= DP_TP_CTL_MODE_MST;
2979 else {
2980 val |= DP_TP_CTL_MODE_SST;
2981 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2982 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2983 }
c19b0669
PZ		 2984 I915_WRITE(DP_TP_CTL(port), val);
2985 POSTING_READ(DP_TP_CTL(port));
2986
2987 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2988 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2989 POSTING_READ(DDI_BUF_CTL(port));
2990
2991 udelay(600);
2992}
00c09d70 2993
1ad960f2
PZ		 2994void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2995{
2996 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2997 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2998 uint32_t val;
2999
3000 intel_ddi_post_disable(intel_encoder);
3001
3002 val = I915_READ(_FDI_RXA_CTL);
3003 val &= ~FDI_RX_ENABLE;
3004 I915_WRITE(_FDI_RXA_CTL, val);
3005
3006 val = I915_READ(_FDI_RXA_MISC);
3007 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3008 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3009 I915_WRITE(_FDI_RXA_MISC, val);
3010
3011 val = I915_READ(_FDI_RXA_CTL);
3012 val &= ~FDI_PCDCLK;
3013 I915_WRITE(_FDI_RXA_CTL, val);
3014
3015 val = I915_READ(_FDI_RXA_CTL);
3016 val &= ~FDI_RX_PLL_ENABLE;
3017 I915_WRITE(_FDI_RXA_CTL, val);
3018}
3019
6801c18c 3020void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3021 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 3022{
3023 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3024 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 3025 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 3026 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 3027 u32 temp, flags = 0;
3028
3029 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3030 if (temp & TRANS_DDI_PHSYNC)
3031 flags |= DRM_MODE_FLAG_PHSYNC;
3032 else
3033 flags |= DRM_MODE_FLAG_NHSYNC;
3034 if (temp & TRANS_DDI_PVSYNC)
3035 flags |= DRM_MODE_FLAG_PVSYNC;
3036 else
3037 flags |= DRM_MODE_FLAG_NVSYNC;
3038
2d112de7 3039 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3040
3041 switch (temp & TRANS_DDI_BPC_MASK) {
3042 case TRANS_DDI_BPC_6:
3043 pipe_config->pipe_bpp = 18;
3044 break;
3045 case TRANS_DDI_BPC_8:
3046 pipe_config->pipe_bpp = 24;
3047 break;
3048 case TRANS_DDI_BPC_10:
3049 pipe_config->pipe_bpp = 30;
3050 break;
3051 case TRANS_DDI_BPC_12:
3052 pipe_config->pipe_bpp = 36;
3053 break;
3054 default:
3055 break;
3056 }
eb14cb74
VS		 3057
3058 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3059 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3060 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 3061 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3062
3063 if (intel_hdmi->infoframe_enabled(&encoder->base))
3064 pipe_config->has_infoframe = true;
cbc572a9 3065 break;
eb14cb74
VS		 3066 case TRANS_DDI_MODE_SELECT_DVI:
3067 case TRANS_DDI_MODE_SELECT_FDI:
3068 break;
3069 case TRANS_DDI_MODE_SELECT_DP_SST:
3070 case TRANS_DDI_MODE_SELECT_DP_MST:
3071 pipe_config->has_dp_encoder = true;
90a6b7b0
VS		 3072 pipe_config->lane_count =
3073 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3074 intel_dp_get_m_n(intel_crtc, pipe_config);
3075 break;
3076 default:
3077 break;
3078 }
10214420 3079
f458ebbc 3080 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 3081 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 3082 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 3083 pipe_config->has_audio = true;
3084 }
9ed109a7 3085
10214420
DV		 3086 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3087 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3088 /*
3089 * This is a big fat ugly hack.
3090 *
3091 * Some machines in UEFI boot mode provide us a VBT that has 18
3092 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3093 * unknown we fail to light up. Yet the same BIOS boots up with
3094 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3095 * max, not what it tells us to use.
3096 *
3097 * Note: This will still be broken if the eDP panel is not lit
3098 * up by the BIOS, and thus we can't get the mode at module
3099 * load.
3100 */
3101 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3102 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3103 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3104 }
11578553 3105
22606a18 3106 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 3107}
3108
00c09d70
PZ		 3109static void intel_ddi_destroy(struct drm_encoder *encoder)
3110{
3111 /* HDMI has nothing special to destroy, so we can go with this. */
3112 intel_dp_encoder_destroy(encoder);
3113}
3114
5bfe2ac0 3115static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 3116 struct intel_crtc_state *pipe_config)
00c09d70 3117{
5bfe2ac0 3118 int type = encoder->type;
eccb140b 3119 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 3120
5bfe2ac0 3121 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 3122
eccb140b
DV		 3123 if (port == PORT_A)
3124 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3125
00c09d70 3126 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 3127 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 3128 else
5bfe2ac0 3129 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 3130}
3131
3132static const struct drm_encoder_funcs intel_ddi_funcs = {
3133 .destroy = intel_ddi_destroy,
3134};
3135
4a28ae58
PZ		 3136static struct intel_connector *
3137intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3138{
3139 struct intel_connector *connector;
3140 enum port port = intel_dig_port->port;
3141
9bdbd0b9 3142 connector = intel_connector_alloc();
4a28ae58
PZ		 3143 if (!connector)
3144 return NULL;
3145
3146 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3147 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3148 kfree(connector);
3149 return NULL;
3150 }
3151
3152 return connector;
3153}
3154
3155static struct intel_connector *
3156intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3157{
3158 struct intel_connector *connector;
3159 enum port port = intel_dig_port->port;
3160
9bdbd0b9 3161 connector = intel_connector_alloc();
4a28ae58
PZ		 3162 if (!connector)
3163 return NULL;
3164
3165 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3166 intel_hdmi_init_connector(intel_dig_port, connector);
3167
3168 return connector;
3169}
3170
00c09d70
PZ		 3171void intel_ddi_init(struct drm_device *dev, enum port port)
3172{
876a8cdf 3173 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 3174 struct intel_digital_port *intel_dig_port;
3175 struct intel_encoder *intel_encoder;
3176 struct drm_encoder *encoder;
311a2094
PZ		 3177 bool init_hdmi, init_dp;
3178
3179 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3180 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3181 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3182 if (!init_dp && !init_hdmi) {
500ea70d 3183 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 3184 port_name(port));
500ea70d 3185 return;
311a2094 3186 }
00c09d70 3187
b14c5679 3188 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3189 if (!intel_dig_port)
3190 return;
3191
00c09d70
PZ		 3192 intel_encoder = &intel_dig_port->base;
3193 encoder = &intel_encoder->base;
3194
3195 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3196 DRM_MODE_ENCODER_TMDS);
00c09d70 3197
5bfe2ac0 3198 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 3199 intel_encoder->enable = intel_enable_ddi;
3200 intel_encoder->pre_enable = intel_ddi_pre_enable;
3201 intel_encoder->disable = intel_disable_ddi;
3202 intel_encoder->post_disable = intel_ddi_post_disable;
3203 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3204 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 3205
3206 intel_dig_port->port = port;
bcf53de4
SM		 3207 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3208 (DDI_BUF_PORT_REVERSAL |
3209 DDI_A_4_LANES);
00c09d70
PZ		 3210
3211 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 3212 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3213 intel_encoder->cloneable = 0;
00c09d70 3214
f68d697e
CW		 3215 if (init_dp) {
3216 if (!intel_ddi_init_dp_connector(intel_dig_port))
3217 goto err;
13cf5504 3218
f68d697e 3219 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
cf1d5883
SJ		 3220 /*
3221 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3222 * interrupts to check the external panel connection.
3223 */
3224 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)
3225 && port == PORT_B)
3226 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3227 else
3228 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3229 }
21a8e6a4 3230
311a2094
PZ		 3231 /* In theory we don't need the encoder->type check, but leave it just in
3232 * case we have some really bad VBTs... */
f68d697e
CW		 3233 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3234 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3235 goto err;
21a8e6a4 3236 }
f68d697e
CW		 3237
3238 return;
3239
3240err:
3241 drm_encoder_cleanup(encoder);
3242 kfree(intel_dig_port);
00c09d70 3243}
Linux kernel - Deliverables
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