Commit | Line | Data |
---|---|---|
45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
32 | * them for both DP and FDI transports, allowing those ports to | |
33 | * automatically adapt to HDMI connections as well | |
34 | */ | |
35 | static const u32 hsw_ddi_translations_dp[] = { | |
36 | 0x00FFFFFF, 0x0006000E, /* DP parameters */ | |
37 | 0x00D75FFF, 0x0005000A, | |
38 | 0x00C30FFF, 0x00040006, | |
39 | 0x80AAAFFF, 0x000B0000, | |
40 | 0x00FFFFFF, 0x0005000A, | |
41 | 0x00D75FFF, 0x000C0004, | |
42 | 0x80C30FFF, 0x000B0000, | |
43 | 0x00FFFFFF, 0x00040006, | |
44 | 0x80D75FFF, 0x000B0000, | |
45 | 0x00FFFFFF, 0x00040006 /* HDMI parameters */ | |
46 | }; | |
47 | ||
48 | static const u32 hsw_ddi_translations_fdi[] = { | |
49 | 0x00FFFFFF, 0x0007000E, /* FDI parameters */ | |
50 | 0x00D75FFF, 0x000F000A, | |
51 | 0x00C30FFF, 0x00060006, | |
52 | 0x00AAAFFF, 0x001E0000, | |
53 | 0x00FFFFFF, 0x000F000A, | |
54 | 0x00D75FFF, 0x00160004, | |
55 | 0x00C30FFF, 0x001E0000, | |
56 | 0x00FFFFFF, 0x00060006, | |
57 | 0x00D75FFF, 0x001E0000, | |
58 | 0x00FFFFFF, 0x00040006 /* HDMI parameters */ | |
59 | }; | |
60 | ||
fc914639 PZ |
61 | static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
62 | { | |
0bdee30e | 63 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
64 | int type = intel_encoder->type; |
65 | ||
174edf1f | 66 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || |
00c09d70 | 67 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
174edf1f PZ |
68 | struct intel_digital_port *intel_dig_port = |
69 | enc_to_dig_port(encoder); | |
70 | return intel_dig_port->port; | |
0bdee30e | 71 | |
fc914639 PZ |
72 | } else if (type == INTEL_OUTPUT_ANALOG) { |
73 | return PORT_E; | |
0bdee30e | 74 | |
fc914639 PZ |
75 | } else { |
76 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
77 | BUG(); | |
78 | } | |
79 | } | |
80 | ||
45244b87 ED |
81 | /* On Haswell, DDI port buffers must be programmed with correct values |
82 | * in advance. The buffer values are different for FDI and DP modes, | |
83 | * but the HDMI/DVI fields are shared among those. So we program the DDI | |
84 | * in either FDI or DP modes only, as HDMI connections will work with both | |
85 | * of those | |
86 | */ | |
c1f63f9d PZ |
87 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, |
88 | bool use_fdi_mode) | |
45244b87 ED |
89 | { |
90 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91 | u32 reg; | |
92 | int i; | |
93 | const u32 *ddi_translations = ((use_fdi_mode) ? | |
94 | hsw_ddi_translations_fdi : | |
95 | hsw_ddi_translations_dp); | |
96 | ||
97 | DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n", | |
98 | port_name(port), | |
99 | use_fdi_mode ? "FDI" : "DP"); | |
100 | ||
101 | WARN((use_fdi_mode && (port != PORT_E)), | |
102 | "Programming port %c in FDI mode, this probably will not work.\n", | |
103 | port_name(port)); | |
104 | ||
105 | for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
106 | I915_WRITE(reg, ddi_translations[i]); | |
107 | reg += 4; | |
108 | } | |
109 | } | |
110 | ||
111 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
112 | * mode and port E for FDI. | |
113 | */ | |
114 | void intel_prepare_ddi(struct drm_device *dev) | |
115 | { | |
116 | int port; | |
117 | ||
0d536cb4 PZ |
118 | if (!HAS_DDI(dev)) |
119 | return; | |
45244b87 | 120 | |
0d536cb4 PZ |
121 | for (port = PORT_A; port < PORT_E; port++) |
122 | intel_prepare_ddi_buffers(dev, port, false); | |
123 | ||
124 | /* DDI E is the suggested one to work in FDI mode, so program is as such | |
125 | * by default. It will have to be re-programmed in case a digital DP | |
126 | * output will be detected on it | |
127 | */ | |
128 | intel_prepare_ddi_buffers(dev, PORT_E, true); | |
45244b87 | 129 | } |
c82e4d26 ED |
130 | |
131 | static const long hsw_ddi_buf_ctl_values[] = { | |
132 | DDI_BUF_EMP_400MV_0DB_HSW, | |
133 | DDI_BUF_EMP_400MV_3_5DB_HSW, | |
134 | DDI_BUF_EMP_400MV_6DB_HSW, | |
135 | DDI_BUF_EMP_400MV_9_5DB_HSW, | |
136 | DDI_BUF_EMP_600MV_0DB_HSW, | |
137 | DDI_BUF_EMP_600MV_3_5DB_HSW, | |
138 | DDI_BUF_EMP_600MV_6DB_HSW, | |
139 | DDI_BUF_EMP_800MV_0DB_HSW, | |
140 | DDI_BUF_EMP_800MV_3_5DB_HSW | |
141 | }; | |
142 | ||
248138b5 PZ |
143 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
144 | enum port port) | |
145 | { | |
146 | uint32_t reg = DDI_BUF_CTL(port); | |
147 | int i; | |
148 | ||
149 | for (i = 0; i < 8; i++) { | |
150 | udelay(1); | |
151 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
152 | return; | |
153 | } | |
154 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
155 | } | |
c82e4d26 ED |
156 | |
157 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
158 | * connection to the PCH-located connectors. For this, it is necessary to train | |
159 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
160 | * | |
161 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
162 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
163 | * DDI A (which is used for eDP) | |
164 | */ | |
165 | ||
166 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
167 | { | |
168 | struct drm_device *dev = crtc->dev; | |
169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
170 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
04945641 | 171 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 172 | |
04945641 PZ |
173 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
174 | * mode set "sequence for CRT port" document: | |
175 | * - TP1 to TP2 time with the default value | |
176 | * - FDI delay to 90h | |
8693a824 DL |
177 | * |
178 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 PZ |
179 | */ |
180 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
181 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
182 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
183 | ||
184 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 185 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 186 | FDI_RX_PLL_ENABLE | |
627eb5a3 | 187 | FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
04945641 PZ |
188 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
189 | POSTING_READ(_FDI_RXA_CTL); | |
190 | udelay(220); | |
191 | ||
192 | /* Switch from Rawclk to PCDclk */ | |
193 | rx_ctl_val |= FDI_PCDCLK; | |
194 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
195 | ||
196 | /* Configure Port Clock Select */ | |
197 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel); | |
198 | ||
199 | /* Start the training iterating through available voltages and emphasis, | |
200 | * testing each value twice. */ | |
201 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { | |
c82e4d26 ED |
202 | /* Configure DP_TP_CTL with auto-training */ |
203 | I915_WRITE(DP_TP_CTL(PORT_E), | |
204 | DP_TP_CTL_FDI_AUTOTRAIN | | |
205 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
206 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
207 | DP_TP_CTL_ENABLE); | |
208 | ||
876a8cdf DL |
209 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
210 | * DDI E does not support port reversal, the functionality is | |
211 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
212 | * port reversal bit */ | |
c82e4d26 | 213 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 214 | DDI_BUF_CTL_ENABLE | |
33d29b14 | 215 | ((intel_crtc->config.fdi_lanes - 1) << 1) | |
04945641 PZ |
216 | hsw_ddi_buf_ctl_values[i / 2]); |
217 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
c82e4d26 ED |
218 | |
219 | udelay(600); | |
220 | ||
04945641 PZ |
221 | /* Program PCH FDI Receiver TU */ |
222 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
223 | ||
224 | /* Enable PCH FDI Receiver with auto-training */ | |
225 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
226 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
227 | POSTING_READ(_FDI_RXA_CTL); | |
228 | ||
229 | /* Wait for FDI receiver lane calibration */ | |
230 | udelay(30); | |
231 | ||
232 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
233 | temp = I915_READ(_FDI_RXA_MISC); | |
234 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
235 | I915_WRITE(_FDI_RXA_MISC, temp); | |
236 | POSTING_READ(_FDI_RXA_MISC); | |
237 | ||
238 | /* Wait for FDI auto training time */ | |
239 | udelay(5); | |
c82e4d26 ED |
240 | |
241 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
242 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 243 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
c82e4d26 ED |
244 | |
245 | /* Enable normal pixel sending for FDI */ | |
246 | I915_WRITE(DP_TP_CTL(PORT_E), | |
04945641 PZ |
247 | DP_TP_CTL_FDI_AUTOTRAIN | |
248 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
249 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
250 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 251 | |
04945641 | 252 | return; |
c82e4d26 | 253 | } |
04945641 | 254 | |
248138b5 PZ |
255 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
256 | temp &= ~DDI_BUF_CTL_ENABLE; | |
257 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
258 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
259 | ||
04945641 | 260 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
261 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
262 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
263 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
264 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
265 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
266 | ||
267 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
268 | |
269 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
270 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
248138b5 | 271 | POSTING_READ(_FDI_RXA_CTL); |
04945641 PZ |
272 | |
273 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
274 | temp = I915_READ(_FDI_RXA_MISC); | |
275 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
276 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
277 | I915_WRITE(_FDI_RXA_MISC, temp); | |
248138b5 | 278 | POSTING_READ(_FDI_RXA_MISC); |
c82e4d26 ED |
279 | } |
280 | ||
04945641 | 281 | DRM_ERROR("FDI link training failed!\n"); |
c82e4d26 | 282 | } |
0e72a5b5 | 283 | |
c7d8be30 | 284 | static void intel_ddi_mode_set(struct intel_encoder *encoder) |
72662e10 | 285 | { |
c7d8be30 DV |
286 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
287 | int port = intel_ddi_get_encoder_port(encoder); | |
288 | int pipe = crtc->pipe; | |
289 | int type = encoder->type; | |
290 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
72662e10 | 291 | |
bf98a726 | 292 | DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n", |
247d89f6 | 293 | port_name(port), pipe_name(pipe)); |
72662e10 | 294 | |
c7d8be30 | 295 | crtc->eld_vld = false; |
247d89f6 | 296 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c7d8be30 | 297 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
876a8cdf | 298 | struct intel_digital_port *intel_dig_port = |
c7d8be30 | 299 | enc_to_dig_port(&encoder->base); |
4f07854d | 300 | |
bcf53de4 | 301 | intel_dp->DP = intel_dig_port->saved_port_bits | |
876a8cdf | 302 | DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; |
17aa6be9 | 303 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
247d89f6 | 304 | |
8fed6193 TI |
305 | if (intel_dp->has_audio) { |
306 | DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n", | |
c7d8be30 | 307 | pipe_name(crtc->pipe)); |
8fed6193 TI |
308 | |
309 | /* write eld */ | |
310 | DRM_DEBUG_DRIVER("DP audio: write eld information\n"); | |
c7d8be30 | 311 | intel_write_eld(&encoder->base, adjusted_mode); |
8fed6193 TI |
312 | } |
313 | ||
247d89f6 PZ |
314 | intel_dp_init_link_config(intel_dp); |
315 | ||
316 | } else if (type == INTEL_OUTPUT_HDMI) { | |
c7d8be30 | 317 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
247d89f6 PZ |
318 | |
319 | if (intel_hdmi->has_audio) { | |
320 | /* Proper support for digital audio needs a new logic | |
321 | * and a new set of registers, so we leave it for future | |
322 | * patch bombing. | |
323 | */ | |
324 | DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n", | |
c7d8be30 | 325 | pipe_name(crtc->pipe)); |
247d89f6 PZ |
326 | |
327 | /* write eld */ | |
328 | DRM_DEBUG_DRIVER("HDMI audio: write eld information\n"); | |
c7d8be30 | 329 | intel_write_eld(&encoder->base, adjusted_mode); |
247d89f6 | 330 | } |
72662e10 | 331 | |
c7d8be30 | 332 | intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); |
247d89f6 | 333 | } |
8d9ddbcb PZ |
334 | } |
335 | ||
336 | static struct intel_encoder * | |
337 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
338 | { | |
339 | struct drm_device *dev = crtc->dev; | |
340 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
341 | struct intel_encoder *intel_encoder, *ret = NULL; | |
342 | int num_encoders = 0; | |
343 | ||
344 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
345 | ret = intel_encoder; | |
346 | num_encoders++; | |
347 | } | |
348 | ||
349 | if (num_encoders != 1) | |
84f44ce7 VS |
350 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
351 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
352 | |
353 | BUG_ON(ret == NULL); | |
354 | return ret; | |
355 | } | |
356 | ||
6441ab5f PZ |
357 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) |
358 | { | |
359 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
360 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
361 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
362 | uint32_t val; | |
363 | ||
364 | switch (intel_crtc->ddi_pll_sel) { | |
365 | case PORT_CLK_SEL_SPLL: | |
366 | plls->spll_refcount--; | |
367 | if (plls->spll_refcount == 0) { | |
368 | DRM_DEBUG_KMS("Disabling SPLL\n"); | |
369 | val = I915_READ(SPLL_CTL); | |
370 | WARN_ON(!(val & SPLL_PLL_ENABLE)); | |
371 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | |
372 | POSTING_READ(SPLL_CTL); | |
373 | } | |
374 | break; | |
375 | case PORT_CLK_SEL_WRPLL1: | |
376 | plls->wrpll1_refcount--; | |
377 | if (plls->wrpll1_refcount == 0) { | |
378 | DRM_DEBUG_KMS("Disabling WRPLL 1\n"); | |
379 | val = I915_READ(WRPLL_CTL1); | |
380 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
381 | I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); | |
382 | POSTING_READ(WRPLL_CTL1); | |
383 | } | |
384 | break; | |
385 | case PORT_CLK_SEL_WRPLL2: | |
386 | plls->wrpll2_refcount--; | |
387 | if (plls->wrpll2_refcount == 0) { | |
388 | DRM_DEBUG_KMS("Disabling WRPLL 2\n"); | |
389 | val = I915_READ(WRPLL_CTL2); | |
390 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
391 | I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); | |
392 | POSTING_READ(WRPLL_CTL2); | |
393 | } | |
394 | break; | |
395 | } | |
396 | ||
397 | WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n"); | |
398 | WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n"); | |
399 | WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n"); | |
400 | ||
401 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE; | |
402 | } | |
403 | ||
1c0b85c5 DL |
404 | #define LC_FREQ 2700 |
405 | #define LC_FREQ_2K (LC_FREQ * 2000) | |
406 | ||
407 | #define P_MIN 2 | |
408 | #define P_MAX 64 | |
409 | #define P_INC 2 | |
410 | ||
411 | /* Constraints for PLL good behavior */ | |
412 | #define REF_MIN 48 | |
413 | #define REF_MAX 400 | |
414 | #define VCO_MIN 2400 | |
415 | #define VCO_MAX 4800 | |
416 | ||
417 | #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a)) | |
418 | ||
419 | struct wrpll_rnp { | |
420 | unsigned p, n2, r2; | |
421 | }; | |
422 | ||
423 | static unsigned wrpll_get_budget_for_freq(int clock) | |
6441ab5f | 424 | { |
1c0b85c5 DL |
425 | unsigned budget; |
426 | ||
427 | switch (clock) { | |
428 | case 25175000: | |
429 | case 25200000: | |
430 | case 27000000: | |
431 | case 27027000: | |
432 | case 37762500: | |
433 | case 37800000: | |
434 | case 40500000: | |
435 | case 40541000: | |
436 | case 54000000: | |
437 | case 54054000: | |
438 | case 59341000: | |
439 | case 59400000: | |
440 | case 72000000: | |
441 | case 74176000: | |
442 | case 74250000: | |
443 | case 81000000: | |
444 | case 81081000: | |
445 | case 89012000: | |
446 | case 89100000: | |
447 | case 108000000: | |
448 | case 108108000: | |
449 | case 111264000: | |
450 | case 111375000: | |
451 | case 148352000: | |
452 | case 148500000: | |
453 | case 162000000: | |
454 | case 162162000: | |
455 | case 222525000: | |
456 | case 222750000: | |
457 | case 296703000: | |
458 | case 297000000: | |
459 | budget = 0; | |
460 | break; | |
461 | case 233500000: | |
462 | case 245250000: | |
463 | case 247750000: | |
464 | case 253250000: | |
465 | case 298000000: | |
466 | budget = 1500; | |
467 | break; | |
468 | case 169128000: | |
469 | case 169500000: | |
470 | case 179500000: | |
471 | case 202000000: | |
472 | budget = 2000; | |
473 | break; | |
474 | case 256250000: | |
475 | case 262500000: | |
476 | case 270000000: | |
477 | case 272500000: | |
478 | case 273750000: | |
479 | case 280750000: | |
480 | case 281250000: | |
481 | case 286000000: | |
482 | case 291750000: | |
483 | budget = 4000; | |
484 | break; | |
485 | case 267250000: | |
486 | case 268500000: | |
487 | budget = 5000; | |
488 | break; | |
489 | default: | |
490 | budget = 1000; | |
491 | break; | |
492 | } | |
6441ab5f | 493 | |
1c0b85c5 DL |
494 | return budget; |
495 | } | |
496 | ||
497 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
498 | unsigned r2, unsigned n2, unsigned p, | |
499 | struct wrpll_rnp *best) | |
500 | { | |
501 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 502 | |
1c0b85c5 DL |
503 | /* No best (r,n,p) yet */ |
504 | if (best->p == 0) { | |
505 | best->p = p; | |
506 | best->n2 = n2; | |
507 | best->r2 = r2; | |
508 | return; | |
509 | } | |
6441ab5f | 510 | |
1c0b85c5 DL |
511 | /* |
512 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
513 | * freq2k. | |
514 | * | |
515 | * delta = 1e6 * | |
516 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
517 | * freq2k; | |
518 | * | |
519 | * and we would like delta <= budget. | |
520 | * | |
521 | * If the discrepancy is above the PPM-based budget, always prefer to | |
522 | * improve upon the previous solution. However, if you're within the | |
523 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
524 | */ | |
525 | a = freq2k * budget * p * r2; | |
526 | b = freq2k * budget * best->p * best->r2; | |
527 | diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2)); | |
528 | diff_best = ABS_DIFF((freq2k * best->p * best->r2), | |
529 | (LC_FREQ_2K * best->n2)); | |
530 | c = 1000000 * diff; | |
531 | d = 1000000 * diff_best; | |
532 | ||
533 | if (a < c && b < d) { | |
534 | /* If both are above the budget, pick the closer */ | |
535 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
536 | best->p = p; | |
537 | best->n2 = n2; | |
538 | best->r2 = r2; | |
539 | } | |
540 | } else if (a >= c && b < d) { | |
541 | /* If A is below the threshold but B is above it? Update. */ | |
542 | best->p = p; | |
543 | best->n2 = n2; | |
544 | best->r2 = r2; | |
545 | } else if (a >= c && b >= d) { | |
546 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
547 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
548 | best->p = p; | |
549 | best->n2 = n2; | |
550 | best->r2 = r2; | |
551 | } | |
552 | } | |
553 | /* Otherwise a < c && b >= d, do nothing */ | |
554 | } | |
555 | ||
556 | static void | |
557 | intel_ddi_calculate_wrpll(int clock /* in Hz */, | |
558 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
559 | { | |
560 | uint64_t freq2k; | |
561 | unsigned p, n2, r2; | |
562 | struct wrpll_rnp best = { 0, 0, 0 }; | |
563 | unsigned budget; | |
564 | ||
565 | freq2k = clock / 100; | |
566 | ||
567 | budget = wrpll_get_budget_for_freq(clock); | |
568 | ||
569 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
570 | * and directly pass the LC PLL to it. */ | |
571 | if (freq2k == 5400000) { | |
572 | *n2_out = 2; | |
573 | *p_out = 1; | |
574 | *r2_out = 2; | |
575 | return; | |
576 | } | |
577 | ||
578 | /* | |
579 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
580 | * the WR PLL. | |
581 | * | |
582 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
583 | * Injecting R2 = 2 * R gives: | |
584 | * REF_MAX * r2 > LC_FREQ * 2 and | |
585 | * REF_MIN * r2 < LC_FREQ * 2 | |
586 | * | |
587 | * Which means the desired boundaries for r2 are: | |
588 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
589 | * | |
590 | */ | |
591 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
592 | r2 <= LC_FREQ * 2 / REF_MIN; | |
593 | r2++) { | |
594 | ||
595 | /* | |
596 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
597 | * | |
598 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
599 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
600 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
601 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
602 | * | |
603 | * Which means the desired boundaries for n2 are: | |
604 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
605 | */ | |
606 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
607 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
608 | n2++) { | |
609 | ||
610 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
611 | wrpll_update_rnp(freq2k, budget, | |
612 | r2, n2, p, &best); | |
613 | } | |
614 | } | |
6441ab5f | 615 | |
1c0b85c5 DL |
616 | *n2_out = best.n2; |
617 | *p_out = best.p; | |
618 | *r2_out = best.r2; | |
6441ab5f | 619 | |
1c0b85c5 DL |
620 | DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n", |
621 | clock, *p_out, *n2_out, *r2_out); | |
6441ab5f PZ |
622 | } |
623 | ||
ff9a6750 | 624 | bool intel_ddi_pll_mode_set(struct drm_crtc *crtc) |
6441ab5f PZ |
625 | { |
626 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
627 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
068759bd | 628 | struct drm_encoder *encoder = &intel_encoder->base; |
6441ab5f PZ |
629 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
630 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
631 | int type = intel_encoder->type; | |
632 | enum pipe pipe = intel_crtc->pipe; | |
633 | uint32_t reg, val; | |
ff9a6750 | 634 | int clock = intel_crtc->config.port_clock; |
6441ab5f PZ |
635 | |
636 | /* TODO: reuse PLLs when possible (compare values) */ | |
637 | ||
638 | intel_ddi_put_crtc_pll(crtc); | |
639 | ||
068759bd PZ |
640 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
641 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
642 | ||
643 | switch (intel_dp->link_bw) { | |
644 | case DP_LINK_BW_1_62: | |
645 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; | |
646 | break; | |
647 | case DP_LINK_BW_2_7: | |
648 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; | |
649 | break; | |
650 | case DP_LINK_BW_5_4: | |
651 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; | |
652 | break; | |
653 | default: | |
654 | DRM_ERROR("Link bandwidth %d unsupported\n", | |
655 | intel_dp->link_bw); | |
656 | return false; | |
657 | } | |
658 | ||
659 | /* We don't need to turn any PLL on because we'll use LCPLL. */ | |
660 | return true; | |
661 | ||
662 | } else if (type == INTEL_OUTPUT_HDMI) { | |
1c0b85c5 | 663 | unsigned p, n2, r2; |
6441ab5f PZ |
664 | |
665 | if (plls->wrpll1_refcount == 0) { | |
666 | DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", | |
667 | pipe_name(pipe)); | |
668 | plls->wrpll1_refcount++; | |
669 | reg = WRPLL_CTL1; | |
670 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1; | |
671 | } else if (plls->wrpll2_refcount == 0) { | |
672 | DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", | |
673 | pipe_name(pipe)); | |
674 | plls->wrpll2_refcount++; | |
675 | reg = WRPLL_CTL2; | |
676 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2; | |
677 | } else { | |
678 | DRM_ERROR("No WRPLLs available!\n"); | |
679 | return false; | |
680 | } | |
681 | ||
682 | WARN(I915_READ(reg) & WRPLL_PLL_ENABLE, | |
683 | "WRPLL already enabled\n"); | |
684 | ||
1c0b85c5 | 685 | intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
6441ab5f PZ |
686 | |
687 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | | |
688 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | | |
689 | WRPLL_DIVIDER_POST(p); | |
690 | ||
691 | } else if (type == INTEL_OUTPUT_ANALOG) { | |
692 | if (plls->spll_refcount == 0) { | |
693 | DRM_DEBUG_KMS("Using SPLL on pipe %c\n", | |
694 | pipe_name(pipe)); | |
695 | plls->spll_refcount++; | |
696 | reg = SPLL_CTL; | |
697 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; | |
00037c2e DL |
698 | } else { |
699 | DRM_ERROR("SPLL already in use\n"); | |
700 | return false; | |
6441ab5f PZ |
701 | } |
702 | ||
703 | WARN(I915_READ(reg) & SPLL_PLL_ENABLE, | |
704 | "SPLL already enabled\n"); | |
705 | ||
39bc66c9 | 706 | val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; |
6441ab5f PZ |
707 | |
708 | } else { | |
709 | WARN(1, "Invalid DDI encoder type %d\n", type); | |
710 | return false; | |
711 | } | |
712 | ||
713 | I915_WRITE(reg, val); | |
714 | udelay(20); | |
715 | ||
716 | return true; | |
717 | } | |
718 | ||
dae84799 PZ |
719 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
720 | { | |
721 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
723 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
3b117c8f | 724 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
dae84799 PZ |
725 | int type = intel_encoder->type; |
726 | uint32_t temp; | |
727 | ||
728 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | |
729 | ||
c9809791 | 730 | temp = TRANS_MSA_SYNC_CLK; |
965e0c48 | 731 | switch (intel_crtc->config.pipe_bpp) { |
dae84799 | 732 | case 18: |
c9809791 | 733 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
734 | break; |
735 | case 24: | |
c9809791 | 736 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
737 | break; |
738 | case 30: | |
c9809791 | 739 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
740 | break; |
741 | case 36: | |
c9809791 | 742 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
743 | break; |
744 | default: | |
4e53c2e0 | 745 | BUG(); |
dae84799 | 746 | } |
c9809791 | 747 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
748 | } |
749 | } | |
750 | ||
8228c251 | 751 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
752 | { |
753 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
754 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 755 | struct drm_encoder *encoder = &intel_encoder->base; |
8d9ddbcb PZ |
756 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
757 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 758 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
174edf1f | 759 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 760 | int type = intel_encoder->type; |
8d9ddbcb PZ |
761 | uint32_t temp; |
762 | ||
ad80a810 PZ |
763 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
764 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 765 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 766 | |
965e0c48 | 767 | switch (intel_crtc->config.pipe_bpp) { |
dfcef252 | 768 | case 18: |
ad80a810 | 769 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
770 | break; |
771 | case 24: | |
ad80a810 | 772 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
773 | break; |
774 | case 30: | |
ad80a810 | 775 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
776 | break; |
777 | case 36: | |
ad80a810 | 778 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
779 | break; |
780 | default: | |
4e53c2e0 | 781 | BUG(); |
dfcef252 | 782 | } |
72662e10 | 783 | |
8d9ddbcb | 784 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 785 | temp |= TRANS_DDI_PVSYNC; |
8d9ddbcb | 786 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 787 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 788 | |
e6f0bfc4 PZ |
789 | if (cpu_transcoder == TRANSCODER_EDP) { |
790 | switch (pipe) { | |
791 | case PIPE_A: | |
d6dd9eb1 DV |
792 | /* Can only use the always-on power well for eDP when |
793 | * not using the panel fitter, and when not using motion | |
794 | * blur mitigation (which we don't support). */ | |
b074cec8 | 795 | if (intel_crtc->config.pch_pfit.size) |
d6dd9eb1 DV |
796 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
797 | else | |
798 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
799 | break; |
800 | case PIPE_B: | |
801 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
802 | break; | |
803 | case PIPE_C: | |
804 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
805 | break; | |
806 | default: | |
807 | BUG(); | |
808 | break; | |
809 | } | |
810 | } | |
811 | ||
7739c33b PZ |
812 | if (type == INTEL_OUTPUT_HDMI) { |
813 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
8d9ddbcb PZ |
814 | |
815 | if (intel_hdmi->has_hdmi_sink) | |
ad80a810 | 816 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 817 | else |
ad80a810 | 818 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 819 | |
7739c33b | 820 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 821 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
33d29b14 | 822 | temp |= (intel_crtc->config.fdi_lanes - 1) << 1; |
7739c33b PZ |
823 | |
824 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
825 | type == INTEL_OUTPUT_EDP) { | |
826 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
827 | ||
ad80a810 | 828 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
7739c33b | 829 | |
17aa6be9 | 830 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
8d9ddbcb | 831 | } else { |
84f44ce7 VS |
832 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
833 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
834 | } |
835 | ||
ad80a810 | 836 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 837 | } |
72662e10 | 838 | |
ad80a810 PZ |
839 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
840 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 841 | { |
ad80a810 | 842 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
843 | uint32_t val = I915_READ(reg); |
844 | ||
ad80a810 PZ |
845 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); |
846 | val |= TRANS_DDI_PORT_NONE; | |
8d9ddbcb | 847 | I915_WRITE(reg, val); |
72662e10 ED |
848 | } |
849 | ||
bcbc889b PZ |
850 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
851 | { | |
852 | struct drm_device *dev = intel_connector->base.dev; | |
853 | struct drm_i915_private *dev_priv = dev->dev_private; | |
854 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
855 | int type = intel_connector->base.connector_type; | |
856 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
857 | enum pipe pipe = 0; | |
858 | enum transcoder cpu_transcoder; | |
859 | uint32_t tmp; | |
860 | ||
861 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) | |
862 | return false; | |
863 | ||
864 | if (port == PORT_A) | |
865 | cpu_transcoder = TRANSCODER_EDP; | |
866 | else | |
1a240d4d | 867 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
868 | |
869 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
870 | ||
871 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
872 | case TRANS_DDI_MODE_SELECT_HDMI: | |
873 | case TRANS_DDI_MODE_SELECT_DVI: | |
874 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
875 | ||
876 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
877 | if (type == DRM_MODE_CONNECTOR_eDP) | |
878 | return true; | |
879 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
880 | return (type == DRM_MODE_CONNECTOR_DisplayPort); | |
881 | ||
882 | case TRANS_DDI_MODE_SELECT_FDI: | |
883 | return (type == DRM_MODE_CONNECTOR_VGA); | |
884 | ||
885 | default: | |
886 | return false; | |
887 | } | |
888 | } | |
889 | ||
85234cdc DV |
890 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
891 | enum pipe *pipe) | |
892 | { | |
893 | struct drm_device *dev = encoder->base.dev; | |
894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 895 | enum port port = intel_ddi_get_encoder_port(encoder); |
85234cdc DV |
896 | u32 tmp; |
897 | int i; | |
898 | ||
fe43d3f5 | 899 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
900 | |
901 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
902 | return false; | |
903 | ||
ad80a810 PZ |
904 | if (port == PORT_A) { |
905 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 906 | |
ad80a810 PZ |
907 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
908 | case TRANS_DDI_EDP_INPUT_A_ON: | |
909 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
910 | *pipe = PIPE_A; | |
911 | break; | |
912 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
913 | *pipe = PIPE_B; | |
914 | break; | |
915 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
916 | *pipe = PIPE_C; | |
917 | break; | |
918 | } | |
919 | ||
920 | return true; | |
921 | } else { | |
922 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
923 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
924 | ||
925 | if ((tmp & TRANS_DDI_PORT_MASK) | |
926 | == TRANS_DDI_SELECT_PORT(port)) { | |
927 | *pipe = i; | |
928 | return true; | |
929 | } | |
85234cdc DV |
930 | } |
931 | } | |
932 | ||
84f44ce7 | 933 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 934 | |
22f9fe50 | 935 | return false; |
85234cdc DV |
936 | } |
937 | ||
6441ab5f PZ |
938 | static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, |
939 | enum pipe pipe) | |
940 | { | |
941 | uint32_t temp, ret; | |
a42f704b | 942 | enum port port = I915_MAX_PORTS; |
ad80a810 PZ |
943 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
944 | pipe); | |
6441ab5f PZ |
945 | int i; |
946 | ||
ad80a810 PZ |
947 | if (cpu_transcoder == TRANSCODER_EDP) { |
948 | port = PORT_A; | |
949 | } else { | |
950 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
951 | temp &= TRANS_DDI_PORT_MASK; | |
952 | ||
953 | for (i = PORT_B; i <= PORT_E; i++) | |
954 | if (temp == TRANS_DDI_SELECT_PORT(i)) | |
955 | port = i; | |
956 | } | |
6441ab5f | 957 | |
a42f704b DL |
958 | if (port == I915_MAX_PORTS) { |
959 | WARN(1, "Pipe %c enabled on an unknown port\n", | |
960 | pipe_name(pipe)); | |
961 | ret = PORT_CLK_SEL_NONE; | |
962 | } else { | |
963 | ret = I915_READ(PORT_CLK_SEL(port)); | |
964 | DRM_DEBUG_KMS("Pipe %c connected to port %c using clock " | |
965 | "0x%08x\n", pipe_name(pipe), port_name(port), | |
966 | ret); | |
967 | } | |
6441ab5f PZ |
968 | |
969 | return ret; | |
970 | } | |
971 | ||
972 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev) | |
973 | { | |
974 | struct drm_i915_private *dev_priv = dev->dev_private; | |
975 | enum pipe pipe; | |
976 | struct intel_crtc *intel_crtc; | |
977 | ||
978 | for_each_pipe(pipe) { | |
979 | intel_crtc = | |
980 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
981 | ||
982 | if (!intel_crtc->active) | |
983 | continue; | |
984 | ||
985 | intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv, | |
986 | pipe); | |
987 | ||
988 | switch (intel_crtc->ddi_pll_sel) { | |
989 | case PORT_CLK_SEL_SPLL: | |
990 | dev_priv->ddi_plls.spll_refcount++; | |
991 | break; | |
992 | case PORT_CLK_SEL_WRPLL1: | |
993 | dev_priv->ddi_plls.wrpll1_refcount++; | |
994 | break; | |
995 | case PORT_CLK_SEL_WRPLL2: | |
996 | dev_priv->ddi_plls.wrpll2_refcount++; | |
997 | break; | |
998 | } | |
999 | } | |
1000 | } | |
1001 | ||
fc914639 PZ |
1002 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1003 | { | |
1004 | struct drm_crtc *crtc = &intel_crtc->base; | |
1005 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1006 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1007 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
3b117c8f | 1008 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1009 | |
bb523fc0 PZ |
1010 | if (cpu_transcoder != TRANSCODER_EDP) |
1011 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1012 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1013 | } |
1014 | ||
1015 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1016 | { | |
1017 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3b117c8f | 1018 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1019 | |
bb523fc0 PZ |
1020 | if (cpu_transcoder != TRANSCODER_EDP) |
1021 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1022 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1023 | } |
1024 | ||
00c09d70 | 1025 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
6441ab5f | 1026 | { |
c19b0669 PZ |
1027 | struct drm_encoder *encoder = &intel_encoder->base; |
1028 | struct drm_crtc *crtc = encoder->crtc; | |
1029 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
6441ab5f PZ |
1030 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1031 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1032 | int type = intel_encoder->type; |
6441ab5f | 1033 | |
82a4d9c0 PZ |
1034 | if (type == INTEL_OUTPUT_EDP) { |
1035 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1036 | ironlake_edp_panel_vdd_on(intel_dp); | |
1037 | ironlake_edp_panel_on(intel_dp); | |
1038 | ironlake_edp_panel_vdd_off(intel_dp, true); | |
1039 | } | |
6441ab5f | 1040 | |
82a4d9c0 | 1041 | WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE); |
6441ab5f | 1042 | I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel); |
c19b0669 | 1043 | |
82a4d9c0 | 1044 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 PZ |
1045 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1046 | ||
1047 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1048 | intel_dp_start_link_train(intel_dp); | |
1049 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 ID |
1050 | if (port != PORT_A) |
1051 | intel_dp_stop_link_train(intel_dp); | |
c19b0669 | 1052 | } |
6441ab5f PZ |
1053 | } |
1054 | ||
00c09d70 | 1055 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
1056 | { |
1057 | struct drm_encoder *encoder = &intel_encoder->base; | |
1058 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1059 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1060 | int type = intel_encoder->type; |
2886e93f | 1061 | uint32_t val; |
a836bdf9 | 1062 | bool wait = false; |
2886e93f PZ |
1063 | |
1064 | val = I915_READ(DDI_BUF_CTL(port)); | |
1065 | if (val & DDI_BUF_CTL_ENABLE) { | |
1066 | val &= ~DDI_BUF_CTL_ENABLE; | |
1067 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1068 | wait = true; |
2886e93f | 1069 | } |
6441ab5f | 1070 | |
a836bdf9 PZ |
1071 | val = I915_READ(DP_TP_CTL(port)); |
1072 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1073 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1074 | I915_WRITE(DP_TP_CTL(port), val); | |
1075 | ||
1076 | if (wait) | |
1077 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1078 | ||
82a4d9c0 PZ |
1079 | if (type == INTEL_OUTPUT_EDP) { |
1080 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1081 | ironlake_edp_panel_vdd_on(intel_dp); | |
1082 | ironlake_edp_panel_off(intel_dp); | |
1083 | } | |
1084 | ||
6441ab5f PZ |
1085 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
1086 | } | |
1087 | ||
00c09d70 | 1088 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1089 | { |
6547fef8 | 1090 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1091 | struct drm_crtc *crtc = encoder->crtc; |
1092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1093 | int pipe = intel_crtc->pipe; | |
6547fef8 | 1094 | struct drm_device *dev = encoder->dev; |
72662e10 | 1095 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1096 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1097 | int type = intel_encoder->type; | |
7b9f35a6 | 1098 | uint32_t tmp; |
72662e10 | 1099 | |
6547fef8 | 1100 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1101 | struct intel_digital_port *intel_dig_port = |
1102 | enc_to_dig_port(encoder); | |
1103 | ||
6547fef8 PZ |
1104 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1105 | * are ignored so nothing special needs to be done besides | |
1106 | * enabling the port. | |
1107 | */ | |
876a8cdf | 1108 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1109 | intel_dig_port->saved_port_bits | |
1110 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1111 | } else if (type == INTEL_OUTPUT_EDP) { |
1112 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1113 | ||
3ab9c637 ID |
1114 | if (port == PORT_A) |
1115 | intel_dp_stop_link_train(intel_dp); | |
1116 | ||
d6c50ff8 | 1117 | ironlake_edp_backlight_on(intel_dp); |
4906557e | 1118 | intel_edp_psr_enable(intel_dp); |
6547fef8 | 1119 | } |
7b9f35a6 | 1120 | |
c77bf565 | 1121 | if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) { |
7b9f35a6 WX |
1122 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
1123 | tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); | |
1124 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1125 | } | |
5ab432ef DV |
1126 | } |
1127 | ||
00c09d70 | 1128 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1129 | { |
d6c50ff8 | 1130 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1131 | struct drm_crtc *crtc = encoder->crtc; |
1132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1133 | int pipe = intel_crtc->pipe; | |
d6c50ff8 | 1134 | int type = intel_encoder->type; |
7b9f35a6 WX |
1135 | struct drm_device *dev = encoder->dev; |
1136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1137 | uint32_t tmp; | |
d6c50ff8 | 1138 | |
c77bf565 PZ |
1139 | if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) { |
1140 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1141 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << | |
1142 | (pipe * 4)); | |
1143 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1144 | } | |
2831d842 | 1145 | |
d6c50ff8 PZ |
1146 | if (type == INTEL_OUTPUT_EDP) { |
1147 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1148 | ||
4906557e | 1149 | intel_edp_psr_disable(intel_dp); |
d6c50ff8 PZ |
1150 | ironlake_edp_backlight_off(intel_dp); |
1151 | } | |
72662e10 | 1152 | } |
79f689aa | 1153 | |
b8fc2f6a | 1154 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
79f689aa PZ |
1155 | { |
1156 | if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
b2b877ff | 1157 | return 450000; |
79f689aa PZ |
1158 | else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) == |
1159 | LCPLL_CLK_FREQ_450) | |
b2b877ff | 1160 | return 450000; |
d567b07f | 1161 | else if (IS_ULT(dev_priv->dev)) |
b2b877ff | 1162 | return 337500; |
79f689aa | 1163 | else |
b2b877ff | 1164 | return 540000; |
79f689aa PZ |
1165 | } |
1166 | ||
1167 | void intel_ddi_pll_init(struct drm_device *dev) | |
1168 | { | |
1169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1170 | uint32_t val = I915_READ(LCPLL_CTL); | |
1171 | ||
1172 | /* The LCPLL register should be turned on by the BIOS. For now let's | |
1173 | * just check its state and print errors in case something is wrong. | |
1174 | * Don't even try to turn it on. | |
1175 | */ | |
1176 | ||
b2b877ff | 1177 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
79f689aa PZ |
1178 | intel_ddi_get_cdclk_freq(dev_priv)); |
1179 | ||
1180 | if (val & LCPLL_CD_SOURCE_FCLK) | |
1181 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
1182 | ||
1183 | if (val & LCPLL_PLL_DISABLE) | |
1184 | DRM_ERROR("LCPLL is disabled\n"); | |
1185 | } | |
c19b0669 PZ |
1186 | |
1187 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
1188 | { | |
174edf1f PZ |
1189 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
1190 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 1191 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 1192 | enum port port = intel_dig_port->port; |
c19b0669 | 1193 | uint32_t val; |
f3e227df | 1194 | bool wait = false; |
c19b0669 PZ |
1195 | |
1196 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1197 | val = I915_READ(DDI_BUF_CTL(port)); | |
1198 | if (val & DDI_BUF_CTL_ENABLE) { | |
1199 | val &= ~DDI_BUF_CTL_ENABLE; | |
1200 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1201 | wait = true; | |
1202 | } | |
1203 | ||
1204 | val = I915_READ(DP_TP_CTL(port)); | |
1205 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1206 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1207 | I915_WRITE(DP_TP_CTL(port), val); | |
1208 | POSTING_READ(DP_TP_CTL(port)); | |
1209 | ||
1210 | if (wait) | |
1211 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1212 | } | |
1213 | ||
1214 | val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | | |
1215 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; | |
1216 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) | |
1217 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
1218 | I915_WRITE(DP_TP_CTL(port), val); | |
1219 | POSTING_READ(DP_TP_CTL(port)); | |
1220 | ||
1221 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1222 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1223 | POSTING_READ(DDI_BUF_CTL(port)); | |
1224 | ||
1225 | udelay(600); | |
1226 | } | |
00c09d70 | 1227 | |
1ad960f2 PZ |
1228 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
1229 | { | |
1230 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1231 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1232 | uint32_t val; | |
1233 | ||
1234 | intel_ddi_post_disable(intel_encoder); | |
1235 | ||
1236 | val = I915_READ(_FDI_RXA_CTL); | |
1237 | val &= ~FDI_RX_ENABLE; | |
1238 | I915_WRITE(_FDI_RXA_CTL, val); | |
1239 | ||
1240 | val = I915_READ(_FDI_RXA_MISC); | |
1241 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1242 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1243 | I915_WRITE(_FDI_RXA_MISC, val); | |
1244 | ||
1245 | val = I915_READ(_FDI_RXA_CTL); | |
1246 | val &= ~FDI_PCDCLK; | |
1247 | I915_WRITE(_FDI_RXA_CTL, val); | |
1248 | ||
1249 | val = I915_READ(_FDI_RXA_CTL); | |
1250 | val &= ~FDI_RX_PLL_ENABLE; | |
1251 | I915_WRITE(_FDI_RXA_CTL, val); | |
1252 | } | |
1253 | ||
00c09d70 PZ |
1254 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
1255 | { | |
1256 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
1257 | int type = intel_encoder->type; | |
1258 | ||
1259 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) | |
1260 | intel_dp_check_link_status(intel_dp); | |
1261 | } | |
1262 | ||
045ac3b5 JB |
1263 | static void intel_ddi_get_config(struct intel_encoder *encoder, |
1264 | struct intel_crtc_config *pipe_config) | |
1265 | { | |
1266 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1267 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1268 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
1269 | u32 temp, flags = 0; | |
1270 | ||
1271 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1272 | if (temp & TRANS_DDI_PHSYNC) | |
1273 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1274 | else | |
1275 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1276 | if (temp & TRANS_DDI_PVSYNC) | |
1277 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1278 | else | |
1279 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1280 | ||
1281 | pipe_config->adjusted_mode.flags |= flags; | |
045ac3b5 JB |
1282 | } |
1283 | ||
00c09d70 PZ |
1284 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
1285 | { | |
1286 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
1287 | intel_dp_encoder_destroy(encoder); | |
1288 | } | |
1289 | ||
5bfe2ac0 DV |
1290 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
1291 | struct intel_crtc_config *pipe_config) | |
00c09d70 | 1292 | { |
5bfe2ac0 | 1293 | int type = encoder->type; |
eccb140b | 1294 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 1295 | |
5bfe2ac0 | 1296 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 1297 | |
eccb140b DV |
1298 | if (port == PORT_A) |
1299 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
1300 | ||
00c09d70 | 1301 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 1302 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 1303 | else |
5bfe2ac0 | 1304 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
1305 | } |
1306 | ||
1307 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
1308 | .destroy = intel_ddi_destroy, | |
1309 | }; | |
1310 | ||
00c09d70 PZ |
1311 | void intel_ddi_init(struct drm_device *dev, enum port port) |
1312 | { | |
876a8cdf | 1313 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
1314 | struct intel_digital_port *intel_dig_port; |
1315 | struct intel_encoder *intel_encoder; | |
1316 | struct drm_encoder *encoder; | |
1317 | struct intel_connector *hdmi_connector = NULL; | |
1318 | struct intel_connector *dp_connector = NULL; | |
1319 | ||
1320 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); | |
1321 | if (!intel_dig_port) | |
1322 | return; | |
1323 | ||
1324 | dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
1325 | if (!dp_connector) { | |
1326 | kfree(intel_dig_port); | |
1327 | return; | |
1328 | } | |
1329 | ||
00c09d70 PZ |
1330 | intel_encoder = &intel_dig_port->base; |
1331 | encoder = &intel_encoder->base; | |
1332 | ||
1333 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
1334 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1335 | |
5bfe2ac0 | 1336 | intel_encoder->compute_config = intel_ddi_compute_config; |
c7d8be30 | 1337 | intel_encoder->mode_set = intel_ddi_mode_set; |
00c09d70 PZ |
1338 | intel_encoder->enable = intel_enable_ddi; |
1339 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
1340 | intel_encoder->disable = intel_disable_ddi; | |
1341 | intel_encoder->post_disable = intel_ddi_post_disable; | |
1342 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 1343 | intel_encoder->get_config = intel_ddi_get_config; |
00c09d70 PZ |
1344 | |
1345 | intel_dig_port->port = port; | |
bcf53de4 SM |
1346 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
1347 | (DDI_BUF_PORT_REVERSAL | | |
1348 | DDI_A_4_LANES); | |
00c09d70 PZ |
1349 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); |
1350 | ||
1351 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
1352 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1353 | intel_encoder->cloneable = false; | |
1354 | intel_encoder->hot_plug = intel_ddi_hot_plug; | |
1355 | ||
b2f246a8 | 1356 | if (!intel_dp_init_connector(intel_dig_port, dp_connector)) { |
15b1d171 PZ |
1357 | drm_encoder_cleanup(encoder); |
1358 | kfree(intel_dig_port); | |
b2f246a8 | 1359 | kfree(dp_connector); |
16c25533 | 1360 | return; |
b2f246a8 | 1361 | } |
21a8e6a4 DV |
1362 | |
1363 | if (intel_encoder->type != INTEL_OUTPUT_EDP) { | |
1364 | hdmi_connector = kzalloc(sizeof(struct intel_connector), | |
1365 | GFP_KERNEL); | |
1366 | if (!hdmi_connector) { | |
1367 | return; | |
1368 | } | |
1369 | ||
1370 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
1371 | intel_hdmi_init_connector(intel_dig_port, hdmi_connector); | |
1372 | } | |
00c09d70 | 1373 | } |