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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
10122051 JN |
31 | struct ddi_buf_trans { |
32 | u32 trans1; /* balance leg enable, de-emph level */ | |
33 | u32 trans2; /* vref sel, vswing */ | |
f8896f5d | 34 | u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ |
10122051 JN |
35 | }; |
36 | ||
45244b87 ED |
37 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
38 | * them for both DP and FDI transports, allowing those ports to | |
39 | * automatically adapt to HDMI connections as well | |
40 | */ | |
10122051 | 41 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
f8896f5d DW |
42 | { 0x00FFFFFF, 0x0006000E, 0x0 }, |
43 | { 0x00D75FFF, 0x0005000A, 0x0 }, | |
44 | { 0x00C30FFF, 0x00040006, 0x0 }, | |
45 | { 0x80AAAFFF, 0x000B0000, 0x0 }, | |
46 | { 0x00FFFFFF, 0x0005000A, 0x0 }, | |
47 | { 0x00D75FFF, 0x000C0004, 0x0 }, | |
48 | { 0x80C30FFF, 0x000B0000, 0x0 }, | |
49 | { 0x00FFFFFF, 0x00040006, 0x0 }, | |
50 | { 0x80D75FFF, 0x000B0000, 0x0 }, | |
45244b87 ED |
51 | }; |
52 | ||
10122051 | 53 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { |
f8896f5d DW |
54 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
55 | { 0x00D75FFF, 0x000F000A, 0x0 }, | |
56 | { 0x00C30FFF, 0x00060006, 0x0 }, | |
57 | { 0x00AAAFFF, 0x001E0000, 0x0 }, | |
58 | { 0x00FFFFFF, 0x000F000A, 0x0 }, | |
59 | { 0x00D75FFF, 0x00160004, 0x0 }, | |
60 | { 0x00C30FFF, 0x001E0000, 0x0 }, | |
61 | { 0x00FFFFFF, 0x00060006, 0x0 }, | |
62 | { 0x00D75FFF, 0x001E0000, 0x0 }, | |
6acab15a PZ |
63 | }; |
64 | ||
10122051 JN |
65 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
66 | /* Idx NT mV d T mV d db */ | |
f8896f5d DW |
67 | { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ |
68 | { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ | |
69 | { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ | |
70 | { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ | |
71 | { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ | |
72 | { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ | |
73 | { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ | |
74 | { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ | |
75 | { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ | |
76 | { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ | |
77 | { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ | |
78 | { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ | |
45244b87 ED |
79 | }; |
80 | ||
10122051 | 81 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
f8896f5d DW |
82 | { 0x00FFFFFF, 0x00000012, 0x0 }, |
83 | { 0x00EBAFFF, 0x00020011, 0x0 }, | |
84 | { 0x00C71FFF, 0x0006000F, 0x0 }, | |
85 | { 0x00AAAFFF, 0x000E000A, 0x0 }, | |
86 | { 0x00FFFFFF, 0x00020011, 0x0 }, | |
87 | { 0x00DB6FFF, 0x0005000F, 0x0 }, | |
88 | { 0x00BEEFFF, 0x000A000C, 0x0 }, | |
89 | { 0x00FFFFFF, 0x0005000F, 0x0 }, | |
90 | { 0x00DB6FFF, 0x000A000C, 0x0 }, | |
300644c7 PZ |
91 | }; |
92 | ||
10122051 | 93 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
f8896f5d DW |
94 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
95 | { 0x00D75FFF, 0x000E000A, 0x0 }, | |
96 | { 0x00BEFFFF, 0x00140006, 0x0 }, | |
97 | { 0x80B2CFFF, 0x001B0002, 0x0 }, | |
98 | { 0x00FFFFFF, 0x000E000A, 0x0 }, | |
99 | { 0x00DB6FFF, 0x00160005, 0x0 }, | |
100 | { 0x80C71FFF, 0x001A0002, 0x0 }, | |
101 | { 0x00F7DFFF, 0x00180004, 0x0 }, | |
102 | { 0x80D75FFF, 0x001B0002, 0x0 }, | |
e58623cb AR |
103 | }; |
104 | ||
10122051 | 105 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
f8896f5d DW |
106 | { 0x00FFFFFF, 0x0001000E, 0x0 }, |
107 | { 0x00D75FFF, 0x0004000A, 0x0 }, | |
108 | { 0x00C30FFF, 0x00070006, 0x0 }, | |
109 | { 0x00AAAFFF, 0x000C0000, 0x0 }, | |
110 | { 0x00FFFFFF, 0x0004000A, 0x0 }, | |
111 | { 0x00D75FFF, 0x00090004, 0x0 }, | |
112 | { 0x00C30FFF, 0x000C0000, 0x0 }, | |
113 | { 0x00FFFFFF, 0x00070006, 0x0 }, | |
114 | { 0x00D75FFF, 0x000C0000, 0x0 }, | |
e58623cb AR |
115 | }; |
116 | ||
10122051 JN |
117 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
118 | /* Idx NT mV d T mV df db */ | |
f8896f5d DW |
119 | { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ |
120 | { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ | |
121 | { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ | |
122 | { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ | |
123 | { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ | |
124 | { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ | |
125 | { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ | |
126 | { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ | |
127 | { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ | |
128 | { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ | |
a26aa8ba DL |
129 | }; |
130 | ||
5f8b2531 | 131 | /* Skylake H and S */ |
7f88e3af | 132 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
f8896f5d DW |
133 | { 0x00002016, 0x000000A0, 0x0 }, |
134 | { 0x00005012, 0x0000009B, 0x0 }, | |
135 | { 0x00007011, 0x00000088, 0x0 }, | |
d7097cff | 136 | { 0x80009010, 0x000000C0, 0x1 }, |
f8896f5d DW |
137 | { 0x00002016, 0x0000009B, 0x0 }, |
138 | { 0x00005012, 0x00000088, 0x0 }, | |
d7097cff | 139 | { 0x80007011, 0x000000C0, 0x1 }, |
f8896f5d | 140 | { 0x00002016, 0x000000DF, 0x0 }, |
d7097cff | 141 | { 0x80005012, 0x000000C0, 0x1 }, |
7f88e3af DL |
142 | }; |
143 | ||
f8896f5d DW |
144 | /* Skylake U */ |
145 | static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { | |
5f8b2531 | 146 | { 0x0000201B, 0x000000A2, 0x0 }, |
f8896f5d | 147 | { 0x00005012, 0x00000088, 0x0 }, |
63ebce1f | 148 | { 0x80007011, 0x000000CD, 0x0 }, |
d7097cff | 149 | { 0x80009010, 0x000000C0, 0x1 }, |
5f8b2531 | 150 | { 0x0000201B, 0x0000009D, 0x0 }, |
d7097cff RV |
151 | { 0x80005012, 0x000000C0, 0x1 }, |
152 | { 0x80007011, 0x000000C0, 0x1 }, | |
f8896f5d | 153 | { 0x00002016, 0x00000088, 0x0 }, |
d7097cff | 154 | { 0x80005012, 0x000000C0, 0x1 }, |
f8896f5d DW |
155 | }; |
156 | ||
5f8b2531 RV |
157 | /* Skylake Y */ |
158 | static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { | |
f8896f5d DW |
159 | { 0x00000018, 0x000000A2, 0x0 }, |
160 | { 0x00005012, 0x00000088, 0x0 }, | |
63ebce1f | 161 | { 0x80007011, 0x000000CD, 0x0 }, |
d7097cff | 162 | { 0x80009010, 0x000000C0, 0x3 }, |
f8896f5d | 163 | { 0x00000018, 0x0000009D, 0x0 }, |
d7097cff RV |
164 | { 0x80005012, 0x000000C0, 0x3 }, |
165 | { 0x80007011, 0x000000C0, 0x3 }, | |
f8896f5d | 166 | { 0x00000018, 0x00000088, 0x0 }, |
d7097cff | 167 | { 0x80005012, 0x000000C0, 0x3 }, |
f8896f5d DW |
168 | }; |
169 | ||
170 | /* | |
5f8b2531 | 171 | * Skylake H and S |
f8896f5d DW |
172 | * eDP 1.4 low vswing translation parameters |
173 | */ | |
7ad14a29 | 174 | static const struct ddi_buf_trans skl_ddi_translations_edp[] = { |
f8896f5d DW |
175 | { 0x00000018, 0x000000A8, 0x0 }, |
176 | { 0x00004013, 0x000000A9, 0x0 }, | |
177 | { 0x00007011, 0x000000A2, 0x0 }, | |
178 | { 0x00009010, 0x0000009C, 0x0 }, | |
179 | { 0x00000018, 0x000000A9, 0x0 }, | |
180 | { 0x00006013, 0x000000A2, 0x0 }, | |
181 | { 0x00007011, 0x000000A6, 0x0 }, | |
182 | { 0x00000018, 0x000000AB, 0x0 }, | |
183 | { 0x00007013, 0x0000009F, 0x0 }, | |
184 | { 0x00000018, 0x000000DF, 0x0 }, | |
185 | }; | |
186 | ||
187 | /* | |
188 | * Skylake U | |
189 | * eDP 1.4 low vswing translation parameters | |
190 | */ | |
191 | static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { | |
192 | { 0x00000018, 0x000000A8, 0x0 }, | |
193 | { 0x00004013, 0x000000A9, 0x0 }, | |
194 | { 0x00007011, 0x000000A2, 0x0 }, | |
195 | { 0x00009010, 0x0000009C, 0x0 }, | |
196 | { 0x00000018, 0x000000A9, 0x0 }, | |
197 | { 0x00006013, 0x000000A2, 0x0 }, | |
198 | { 0x00007011, 0x000000A6, 0x0 }, | |
199 | { 0x00002016, 0x000000AB, 0x0 }, | |
200 | { 0x00005013, 0x0000009F, 0x0 }, | |
201 | { 0x00000018, 0x000000DF, 0x0 }, | |
7ad14a29 SJ |
202 | }; |
203 | ||
f8896f5d | 204 | /* |
5f8b2531 | 205 | * Skylake Y |
f8896f5d DW |
206 | * eDP 1.4 low vswing translation parameters |
207 | */ | |
5f8b2531 | 208 | static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { |
f8896f5d DW |
209 | { 0x00000018, 0x000000A8, 0x0 }, |
210 | { 0x00004013, 0x000000AB, 0x0 }, | |
211 | { 0x00007011, 0x000000A4, 0x0 }, | |
212 | { 0x00009010, 0x000000DF, 0x0 }, | |
213 | { 0x00000018, 0x000000AA, 0x0 }, | |
214 | { 0x00006013, 0x000000A4, 0x0 }, | |
215 | { 0x00007011, 0x0000009D, 0x0 }, | |
216 | { 0x00000018, 0x000000A0, 0x0 }, | |
217 | { 0x00006012, 0x000000DF, 0x0 }, | |
218 | { 0x00000018, 0x0000008A, 0x0 }, | |
219 | }; | |
7ad14a29 | 220 | |
5f8b2531 | 221 | /* Skylake U, H and S */ |
7f88e3af | 222 | static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { |
f8896f5d DW |
223 | { 0x00000018, 0x000000AC, 0x0 }, |
224 | { 0x00005012, 0x0000009D, 0x0 }, | |
225 | { 0x00007011, 0x00000088, 0x0 }, | |
226 | { 0x00000018, 0x000000A1, 0x0 }, | |
227 | { 0x00000018, 0x00000098, 0x0 }, | |
228 | { 0x00004013, 0x00000088, 0x0 }, | |
2e78416e | 229 | { 0x80006012, 0x000000CD, 0x1 }, |
f8896f5d | 230 | { 0x00000018, 0x000000DF, 0x0 }, |
2e78416e RV |
231 | { 0x80003015, 0x000000CD, 0x1 }, /* Default */ |
232 | { 0x80003015, 0x000000C0, 0x1 }, | |
233 | { 0x80000018, 0x000000C0, 0x1 }, | |
f8896f5d DW |
234 | }; |
235 | ||
5f8b2531 RV |
236 | /* Skylake Y */ |
237 | static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { | |
f8896f5d DW |
238 | { 0x00000018, 0x000000A1, 0x0 }, |
239 | { 0x00005012, 0x000000DF, 0x0 }, | |
2e78416e | 240 | { 0x80007011, 0x000000CB, 0x3 }, |
f8896f5d DW |
241 | { 0x00000018, 0x000000A4, 0x0 }, |
242 | { 0x00000018, 0x0000009D, 0x0 }, | |
243 | { 0x00004013, 0x00000080, 0x0 }, | |
2e78416e | 244 | { 0x80006013, 0x000000C0, 0x3 }, |
f8896f5d | 245 | { 0x00000018, 0x0000008A, 0x0 }, |
2e78416e RV |
246 | { 0x80003015, 0x000000C0, 0x3 }, /* Default */ |
247 | { 0x80003015, 0x000000C0, 0x3 }, | |
248 | { 0x80000018, 0x000000C0, 0x3 }, | |
7f88e3af DL |
249 | }; |
250 | ||
96fb9f9b VK |
251 | struct bxt_ddi_buf_trans { |
252 | u32 margin; /* swing value */ | |
253 | u32 scale; /* scale value */ | |
254 | u32 enable; /* scale enable */ | |
255 | u32 deemphasis; | |
256 | bool default_index; /* true if the entry represents default value */ | |
257 | }; | |
258 | ||
96fb9f9b VK |
259 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { |
260 | /* Idx NT mV diff db */ | |
fe4c63c8 ID |
261 | { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ |
262 | { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ | |
263 | { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ | |
264 | { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ | |
265 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ | |
266 | { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ | |
267 | { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ | |
268 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ | |
269 | { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ | |
f8896f5d | 270 | { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ |
96fb9f9b VK |
271 | }; |
272 | ||
d9d7000d SJ |
273 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { |
274 | /* Idx NT mV diff db */ | |
275 | { 26, 0, 0, 128, false }, /* 0: 200 0 */ | |
276 | { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ | |
277 | { 48, 0, 0, 96, false }, /* 2: 200 4 */ | |
278 | { 54, 0, 0, 69, false }, /* 3: 200 6 */ | |
279 | { 32, 0, 0, 128, false }, /* 4: 250 0 */ | |
280 | { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ | |
281 | { 54, 0, 0, 85, false }, /* 6: 250 4 */ | |
282 | { 43, 0, 0, 128, false }, /* 7: 300 0 */ | |
283 | { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ | |
284 | { 48, 0, 0, 128, false }, /* 9: 300 0 */ | |
285 | }; | |
286 | ||
96fb9f9b VK |
287 | /* BSpec has 2 recommended values - entries 0 and 8. |
288 | * Using the entry with higher vswing. | |
289 | */ | |
290 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { | |
291 | /* Idx NT mV diff db */ | |
fe4c63c8 ID |
292 | { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ |
293 | { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ | |
294 | { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ | |
295 | { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ | |
296 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ | |
297 | { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ | |
298 | { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ | |
299 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ | |
300 | { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ | |
96fb9f9b VK |
301 | { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ |
302 | }; | |
303 | ||
78ab0bae VS |
304 | static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, |
305 | u32 level, enum port port, int type); | |
f8896f5d | 306 | |
a1e6ad66 ID |
307 | static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, |
308 | struct intel_digital_port **dig_port, | |
309 | enum port *port) | |
fc914639 | 310 | { |
0bdee30e | 311 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 | 312 | |
8cd21b7f JN |
313 | switch (intel_encoder->type) { |
314 | case INTEL_OUTPUT_DP_MST: | |
a1e6ad66 ID |
315 | *dig_port = enc_to_mst(encoder)->primary; |
316 | *port = (*dig_port)->port; | |
8cd21b7f JN |
317 | break; |
318 | case INTEL_OUTPUT_DISPLAYPORT: | |
319 | case INTEL_OUTPUT_EDP: | |
320 | case INTEL_OUTPUT_HDMI: | |
321 | case INTEL_OUTPUT_UNKNOWN: | |
a1e6ad66 ID |
322 | *dig_port = enc_to_dig_port(encoder); |
323 | *port = (*dig_port)->port; | |
8cd21b7f JN |
324 | break; |
325 | case INTEL_OUTPUT_ANALOG: | |
a1e6ad66 ID |
326 | *dig_port = NULL; |
327 | *port = PORT_E; | |
8cd21b7f JN |
328 | break; |
329 | default: | |
330 | WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type); | |
331 | break; | |
fc914639 PZ |
332 | } |
333 | } | |
334 | ||
a1e6ad66 ID |
335 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
336 | { | |
337 | struct intel_digital_port *dig_port; | |
338 | enum port port; | |
339 | ||
340 | ddi_get_encoder_port(intel_encoder, &dig_port, &port); | |
341 | ||
342 | return port; | |
343 | } | |
344 | ||
acee2998 | 345 | static const struct ddi_buf_trans * |
78ab0bae | 346 | skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 347 | { |
78ab0bae | 348 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
5f8b2531 | 349 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
acee2998 | 350 | return skl_y_ddi_translations_dp; |
78ab0bae | 351 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { |
f8896f5d | 352 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
acee2998 | 353 | return skl_u_ddi_translations_dp; |
f8896f5d | 354 | } else { |
f8896f5d | 355 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
acee2998 | 356 | return skl_ddi_translations_dp; |
f8896f5d | 357 | } |
f8896f5d DW |
358 | } |
359 | ||
acee2998 | 360 | static const struct ddi_buf_trans * |
78ab0bae | 361 | skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 362 | { |
cd1101cb | 363 | if (dev_priv->edp_low_vswing) { |
78ab0bae | 364 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
5f8b2531 | 365 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); |
acee2998 | 366 | return skl_y_ddi_translations_edp; |
78ab0bae | 367 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { |
f8896f5d | 368 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); |
acee2998 | 369 | return skl_u_ddi_translations_edp; |
f8896f5d | 370 | } else { |
f8896f5d | 371 | *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); |
acee2998 | 372 | return skl_ddi_translations_edp; |
f8896f5d DW |
373 | } |
374 | } | |
cd1101cb | 375 | |
78ab0bae | 376 | return skl_get_buf_trans_dp(dev_priv, n_entries); |
f8896f5d DW |
377 | } |
378 | ||
379 | static const struct ddi_buf_trans * | |
78ab0bae | 380 | skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 381 | { |
78ab0bae | 382 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
5f8b2531 | 383 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); |
acee2998 | 384 | return skl_y_ddi_translations_hdmi; |
f8896f5d | 385 | } else { |
f8896f5d | 386 | *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); |
acee2998 | 387 | return skl_ddi_translations_hdmi; |
f8896f5d | 388 | } |
f8896f5d DW |
389 | } |
390 | ||
e58623cb AR |
391 | /* |
392 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
393 | * values in advance. The buffer values are different for FDI and DP modes, | |
45244b87 ED |
394 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
395 | * in either FDI or DP modes only, as HDMI connections will work with both | |
396 | * of those | |
397 | */ | |
6a7e4f99 | 398 | void intel_prepare_ddi_buffer(struct intel_encoder *encoder) |
45244b87 | 399 | { |
6a7e4f99 | 400 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
75067dde | 401 | u32 iboost_bit = 0; |
7ff44670 | 402 | int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, |
7ad14a29 | 403 | size; |
6a7e4f99 VS |
404 | int hdmi_level; |
405 | enum port port; | |
10122051 JN |
406 | const struct ddi_buf_trans *ddi_translations_fdi; |
407 | const struct ddi_buf_trans *ddi_translations_dp; | |
408 | const struct ddi_buf_trans *ddi_translations_edp; | |
409 | const struct ddi_buf_trans *ddi_translations_hdmi; | |
410 | const struct ddi_buf_trans *ddi_translations; | |
e58623cb | 411 | |
6a7e4f99 VS |
412 | port = intel_ddi_get_encoder_port(encoder); |
413 | hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; | |
414 | ||
78ab0bae | 415 | if (IS_BROXTON(dev_priv)) { |
6a7e4f99 | 416 | if (encoder->type != INTEL_OUTPUT_HDMI) |
96fb9f9b VK |
417 | return; |
418 | ||
419 | /* Vswing programming for HDMI */ | |
78ab0bae | 420 | bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port, |
96fb9f9b VK |
421 | INTEL_OUTPUT_HDMI); |
422 | return; | |
6a7e4f99 VS |
423 | } |
424 | ||
425 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { | |
c30400fc | 426 | ddi_translations_fdi = NULL; |
f8896f5d | 427 | ddi_translations_dp = |
78ab0bae | 428 | skl_get_buf_trans_dp(dev_priv, &n_dp_entries); |
f8896f5d | 429 | ddi_translations_edp = |
78ab0bae | 430 | skl_get_buf_trans_edp(dev_priv, &n_edp_entries); |
f8896f5d | 431 | ddi_translations_hdmi = |
78ab0bae | 432 | skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); |
f8896f5d | 433 | hdmi_default_entry = 8; |
75067dde AK |
434 | /* If we're boosting the current, set bit 31 of trans1 */ |
435 | if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level || | |
436 | dev_priv->vbt.ddi_port_info[port].dp_boost_level) | |
437 | iboost_bit = 1<<31; | |
10afa0b6 | 438 | |
ceccad59 VS |
439 | if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP && |
440 | port != PORT_A && port != PORT_E && | |
441 | n_edp_entries > 9)) | |
10afa0b6 | 442 | n_edp_entries = 9; |
78ab0bae | 443 | } else if (IS_BROADWELL(dev_priv)) { |
e58623cb AR |
444 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
445 | ddi_translations_dp = bdw_ddi_translations_dp; | |
992e7a41 MK |
446 | |
447 | if (dev_priv->edp_low_vswing) { | |
448 | ddi_translations_edp = bdw_ddi_translations_edp; | |
449 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); | |
450 | } else { | |
451 | ddi_translations_edp = bdw_ddi_translations_dp; | |
452 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
453 | } | |
454 | ||
a26aa8ba | 455 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
992e7a41 | 456 | |
7ad14a29 | 457 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
10122051 | 458 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
7ff44670 | 459 | hdmi_default_entry = 7; |
78ab0bae | 460 | } else if (IS_HASWELL(dev_priv)) { |
e58623cb AR |
461 | ddi_translations_fdi = hsw_ddi_translations_fdi; |
462 | ddi_translations_dp = hsw_ddi_translations_dp; | |
300644c7 | 463 | ddi_translations_edp = hsw_ddi_translations_dp; |
a26aa8ba | 464 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; |
7ad14a29 | 465 | n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); |
10122051 | 466 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); |
7ff44670 | 467 | hdmi_default_entry = 6; |
e58623cb AR |
468 | } else { |
469 | WARN(1, "ddi translation table missing\n"); | |
300644c7 | 470 | ddi_translations_edp = bdw_ddi_translations_dp; |
e58623cb AR |
471 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
472 | ddi_translations_dp = bdw_ddi_translations_dp; | |
a26aa8ba | 473 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
7ad14a29 SJ |
474 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
475 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
10122051 | 476 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
7ff44670 | 477 | hdmi_default_entry = 7; |
e58623cb AR |
478 | } |
479 | ||
6a7e4f99 VS |
480 | switch (encoder->type) { |
481 | case INTEL_OUTPUT_EDP: | |
300644c7 | 482 | ddi_translations = ddi_translations_edp; |
7ad14a29 | 483 | size = n_edp_entries; |
300644c7 | 484 | break; |
6a7e4f99 VS |
485 | case INTEL_OUTPUT_DISPLAYPORT: |
486 | case INTEL_OUTPUT_HDMI: | |
300644c7 | 487 | ddi_translations = ddi_translations_dp; |
7ad14a29 | 488 | size = n_dp_entries; |
300644c7 | 489 | break; |
6a7e4f99 VS |
490 | case INTEL_OUTPUT_ANALOG: |
491 | ddi_translations = ddi_translations_fdi; | |
7ad14a29 | 492 | size = n_dp_entries; |
300644c7 PZ |
493 | break; |
494 | default: | |
495 | BUG(); | |
496 | } | |
45244b87 | 497 | |
9712e688 VS |
498 | for (i = 0; i < size; i++) { |
499 | I915_WRITE(DDI_BUF_TRANS_LO(port, i), | |
500 | ddi_translations[i].trans1 | iboost_bit); | |
501 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), | |
502 | ddi_translations[i].trans2); | |
45244b87 | 503 | } |
ce4dd49e | 504 | |
6a7e4f99 | 505 | if (encoder->type != INTEL_OUTPUT_HDMI) |
ce3b7e9b DL |
506 | return; |
507 | ||
ce4dd49e DL |
508 | /* Choose a good default if VBT is badly populated */ |
509 | if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || | |
510 | hdmi_level >= n_hdmi_entries) | |
7ff44670 | 511 | hdmi_level = hdmi_default_entry; |
ce4dd49e | 512 | |
6acab15a | 513 | /* Entry 9 is for HDMI: */ |
9712e688 VS |
514 | I915_WRITE(DDI_BUF_TRANS_LO(port, i), |
515 | ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); | |
516 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), | |
517 | ddi_translations_hdmi[hdmi_level].trans2); | |
45244b87 ED |
518 | } |
519 | ||
248138b5 PZ |
520 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
521 | enum port port) | |
522 | { | |
f0f59a00 | 523 | i915_reg_t reg = DDI_BUF_CTL(port); |
248138b5 PZ |
524 | int i; |
525 | ||
3449ca85 | 526 | for (i = 0; i < 16; i++) { |
248138b5 PZ |
527 | udelay(1); |
528 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
529 | return; | |
530 | } | |
531 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
532 | } | |
c82e4d26 ED |
533 | |
534 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
535 | * connection to the PCH-located connectors. For this, it is necessary to train | |
536 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
537 | * | |
538 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
539 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
540 | * DDI A (which is used for eDP) | |
541 | */ | |
542 | ||
543 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
544 | { | |
545 | struct drm_device *dev = crtc->dev; | |
546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
547 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6a7e4f99 | 548 | struct intel_encoder *encoder; |
04945641 | 549 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 550 | |
6a7e4f99 VS |
551 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
552 | WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); | |
553 | intel_prepare_ddi_buffer(encoder); | |
554 | } | |
555 | ||
04945641 PZ |
556 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
557 | * mode set "sequence for CRT port" document: | |
558 | * - TP1 to TP2 time with the default value | |
559 | * - FDI delay to 90h | |
8693a824 DL |
560 | * |
561 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 | 562 | */ |
eede3b53 | 563 | I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | |
04945641 PZ |
564 | FDI_RX_PWRDN_LANE0_VAL(2) | |
565 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
566 | ||
567 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 568 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 569 | FDI_RX_PLL_ENABLE | |
6e3c9717 | 570 | FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
eede3b53 VS |
571 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
572 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
573 | udelay(220); |
574 | ||
575 | /* Switch from Rawclk to PCDclk */ | |
576 | rx_ctl_val |= FDI_PCDCLK; | |
eede3b53 | 577 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
04945641 PZ |
578 | |
579 | /* Configure Port Clock Select */ | |
6e3c9717 ACO |
580 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); |
581 | WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
04945641 PZ |
582 | |
583 | /* Start the training iterating through available voltages and emphasis, | |
584 | * testing each value twice. */ | |
10122051 | 585 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
c82e4d26 ED |
586 | /* Configure DP_TP_CTL with auto-training */ |
587 | I915_WRITE(DP_TP_CTL(PORT_E), | |
588 | DP_TP_CTL_FDI_AUTOTRAIN | | |
589 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
590 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
591 | DP_TP_CTL_ENABLE); | |
592 | ||
876a8cdf DL |
593 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
594 | * DDI E does not support port reversal, the functionality is | |
595 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
596 | * port reversal bit */ | |
c82e4d26 | 597 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 598 | DDI_BUF_CTL_ENABLE | |
6e3c9717 | 599 | ((intel_crtc->config->fdi_lanes - 1) << 1) | |
c5fe6a06 | 600 | DDI_BUF_TRANS_SELECT(i / 2)); |
04945641 | 601 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
c82e4d26 ED |
602 | |
603 | udelay(600); | |
604 | ||
04945641 | 605 | /* Program PCH FDI Receiver TU */ |
eede3b53 | 606 | I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); |
04945641 PZ |
607 | |
608 | /* Enable PCH FDI Receiver with auto-training */ | |
609 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
eede3b53 VS |
610 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
611 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
612 | |
613 | /* Wait for FDI receiver lane calibration */ | |
614 | udelay(30); | |
615 | ||
616 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
eede3b53 | 617 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
04945641 | 618 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
eede3b53 VS |
619 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
620 | POSTING_READ(FDI_RX_MISC(PIPE_A)); | |
04945641 PZ |
621 | |
622 | /* Wait for FDI auto training time */ | |
623 | udelay(5); | |
c82e4d26 ED |
624 | |
625 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
626 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 627 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
a308ccb3 VS |
628 | break; |
629 | } | |
c82e4d26 | 630 | |
a308ccb3 VS |
631 | /* |
632 | * Leave things enabled even if we failed to train FDI. | |
633 | * Results in less fireworks from the state checker. | |
634 | */ | |
635 | if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { | |
636 | DRM_ERROR("FDI link training failed!\n"); | |
637 | break; | |
c82e4d26 | 638 | } |
04945641 | 639 | |
248138b5 PZ |
640 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
641 | temp &= ~DDI_BUF_CTL_ENABLE; | |
642 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
643 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
644 | ||
04945641 | 645 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
646 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
647 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
648 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
649 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
650 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
651 | ||
652 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
653 | |
654 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
eede3b53 VS |
655 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
656 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
657 | |
658 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
eede3b53 | 659 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
04945641 PZ |
660 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
661 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
eede3b53 VS |
662 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
663 | POSTING_READ(FDI_RX_MISC(PIPE_A)); | |
c82e4d26 ED |
664 | } |
665 | ||
a308ccb3 VS |
666 | /* Enable normal pixel sending for FDI */ |
667 | I915_WRITE(DP_TP_CTL(PORT_E), | |
668 | DP_TP_CTL_FDI_AUTOTRAIN | | |
669 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
670 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
671 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 672 | } |
0e72a5b5 | 673 | |
44905a27 DA |
674 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
675 | { | |
676 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
677 | struct intel_digital_port *intel_dig_port = | |
678 | enc_to_dig_port(&encoder->base); | |
679 | ||
680 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
c5fe6a06 | 681 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
901c2daf | 682 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
44905a27 DA |
683 | } |
684 | ||
8d9ddbcb PZ |
685 | static struct intel_encoder * |
686 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
687 | { | |
688 | struct drm_device *dev = crtc->dev; | |
689 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
690 | struct intel_encoder *intel_encoder, *ret = NULL; | |
691 | int num_encoders = 0; | |
692 | ||
693 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
694 | ret = intel_encoder; | |
695 | num_encoders++; | |
696 | } | |
697 | ||
698 | if (num_encoders != 1) | |
84f44ce7 VS |
699 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
700 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
701 | |
702 | BUG_ON(ret == NULL); | |
703 | return ret; | |
704 | } | |
705 | ||
bcddf610 | 706 | struct intel_encoder * |
3165c074 | 707 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) |
d0737e1d | 708 | { |
3165c074 ACO |
709 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
710 | struct intel_encoder *ret = NULL; | |
711 | struct drm_atomic_state *state; | |
da3ced29 ACO |
712 | struct drm_connector *connector; |
713 | struct drm_connector_state *connector_state; | |
d0737e1d | 714 | int num_encoders = 0; |
3165c074 | 715 | int i; |
d0737e1d | 716 | |
3165c074 ACO |
717 | state = crtc_state->base.state; |
718 | ||
da3ced29 ACO |
719 | for_each_connector_in_state(state, connector, connector_state, i) { |
720 | if (connector_state->crtc != crtc_state->base.crtc) | |
3165c074 ACO |
721 | continue; |
722 | ||
da3ced29 | 723 | ret = to_intel_encoder(connector_state->best_encoder); |
3165c074 | 724 | num_encoders++; |
d0737e1d ACO |
725 | } |
726 | ||
727 | WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, | |
728 | pipe_name(crtc->pipe)); | |
729 | ||
730 | BUG_ON(ret == NULL); | |
731 | return ret; | |
732 | } | |
733 | ||
1c0b85c5 | 734 | #define LC_FREQ 2700 |
27893390 | 735 | #define LC_FREQ_2K U64_C(LC_FREQ * 2000) |
1c0b85c5 DL |
736 | |
737 | #define P_MIN 2 | |
738 | #define P_MAX 64 | |
739 | #define P_INC 2 | |
740 | ||
741 | /* Constraints for PLL good behavior */ | |
742 | #define REF_MIN 48 | |
743 | #define REF_MAX 400 | |
744 | #define VCO_MIN 2400 | |
745 | #define VCO_MAX 4800 | |
746 | ||
27893390 DL |
747 | #define abs_diff(a, b) ({ \ |
748 | typeof(a) __a = (a); \ | |
749 | typeof(b) __b = (b); \ | |
750 | (void) (&__a == &__b); \ | |
751 | __a > __b ? (__a - __b) : (__b - __a); }) | |
1c0b85c5 | 752 | |
63582983 | 753 | struct hsw_wrpll_rnp { |
1c0b85c5 DL |
754 | unsigned p, n2, r2; |
755 | }; | |
756 | ||
63582983 | 757 | static unsigned hsw_wrpll_get_budget_for_freq(int clock) |
6441ab5f | 758 | { |
1c0b85c5 DL |
759 | unsigned budget; |
760 | ||
761 | switch (clock) { | |
762 | case 25175000: | |
763 | case 25200000: | |
764 | case 27000000: | |
765 | case 27027000: | |
766 | case 37762500: | |
767 | case 37800000: | |
768 | case 40500000: | |
769 | case 40541000: | |
770 | case 54000000: | |
771 | case 54054000: | |
772 | case 59341000: | |
773 | case 59400000: | |
774 | case 72000000: | |
775 | case 74176000: | |
776 | case 74250000: | |
777 | case 81000000: | |
778 | case 81081000: | |
779 | case 89012000: | |
780 | case 89100000: | |
781 | case 108000000: | |
782 | case 108108000: | |
783 | case 111264000: | |
784 | case 111375000: | |
785 | case 148352000: | |
786 | case 148500000: | |
787 | case 162000000: | |
788 | case 162162000: | |
789 | case 222525000: | |
790 | case 222750000: | |
791 | case 296703000: | |
792 | case 297000000: | |
793 | budget = 0; | |
794 | break; | |
795 | case 233500000: | |
796 | case 245250000: | |
797 | case 247750000: | |
798 | case 253250000: | |
799 | case 298000000: | |
800 | budget = 1500; | |
801 | break; | |
802 | case 169128000: | |
803 | case 169500000: | |
804 | case 179500000: | |
805 | case 202000000: | |
806 | budget = 2000; | |
807 | break; | |
808 | case 256250000: | |
809 | case 262500000: | |
810 | case 270000000: | |
811 | case 272500000: | |
812 | case 273750000: | |
813 | case 280750000: | |
814 | case 281250000: | |
815 | case 286000000: | |
816 | case 291750000: | |
817 | budget = 4000; | |
818 | break; | |
819 | case 267250000: | |
820 | case 268500000: | |
821 | budget = 5000; | |
822 | break; | |
823 | default: | |
824 | budget = 1000; | |
825 | break; | |
826 | } | |
6441ab5f | 827 | |
1c0b85c5 DL |
828 | return budget; |
829 | } | |
830 | ||
63582983 DL |
831 | static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget, |
832 | unsigned r2, unsigned n2, unsigned p, | |
833 | struct hsw_wrpll_rnp *best) | |
1c0b85c5 DL |
834 | { |
835 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 836 | |
1c0b85c5 DL |
837 | /* No best (r,n,p) yet */ |
838 | if (best->p == 0) { | |
839 | best->p = p; | |
840 | best->n2 = n2; | |
841 | best->r2 = r2; | |
842 | return; | |
843 | } | |
6441ab5f | 844 | |
1c0b85c5 DL |
845 | /* |
846 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
847 | * freq2k. | |
848 | * | |
849 | * delta = 1e6 * | |
850 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
851 | * freq2k; | |
852 | * | |
853 | * and we would like delta <= budget. | |
854 | * | |
855 | * If the discrepancy is above the PPM-based budget, always prefer to | |
856 | * improve upon the previous solution. However, if you're within the | |
857 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
858 | */ | |
859 | a = freq2k * budget * p * r2; | |
860 | b = freq2k * budget * best->p * best->r2; | |
27893390 DL |
861 | diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); |
862 | diff_best = abs_diff(freq2k * best->p * best->r2, | |
863 | LC_FREQ_2K * best->n2); | |
1c0b85c5 DL |
864 | c = 1000000 * diff; |
865 | d = 1000000 * diff_best; | |
866 | ||
867 | if (a < c && b < d) { | |
868 | /* If both are above the budget, pick the closer */ | |
869 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
870 | best->p = p; | |
871 | best->n2 = n2; | |
872 | best->r2 = r2; | |
873 | } | |
874 | } else if (a >= c && b < d) { | |
875 | /* If A is below the threshold but B is above it? Update. */ | |
876 | best->p = p; | |
877 | best->n2 = n2; | |
878 | best->r2 = r2; | |
879 | } else if (a >= c && b >= d) { | |
880 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
881 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
882 | best->p = p; | |
883 | best->n2 = n2; | |
884 | best->r2 = r2; | |
885 | } | |
886 | } | |
887 | /* Otherwise a < c && b >= d, do nothing */ | |
888 | } | |
889 | ||
f0f59a00 VS |
890 | static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
891 | i915_reg_t reg) | |
11578553 JB |
892 | { |
893 | int refclk = LC_FREQ; | |
894 | int n, p, r; | |
895 | u32 wrpll; | |
896 | ||
897 | wrpll = I915_READ(reg); | |
114fe488 DV |
898 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
899 | case WRPLL_PLL_SSC: | |
900 | case WRPLL_PLL_NON_SSC: | |
11578553 JB |
901 | /* |
902 | * We could calculate spread here, but our checking | |
903 | * code only cares about 5% accuracy, and spread is a max of | |
904 | * 0.5% downspread. | |
905 | */ | |
906 | refclk = 135; | |
907 | break; | |
114fe488 | 908 | case WRPLL_PLL_LCPLL: |
11578553 JB |
909 | refclk = LC_FREQ; |
910 | break; | |
911 | default: | |
912 | WARN(1, "bad wrpll refclk\n"); | |
913 | return 0; | |
914 | } | |
915 | ||
916 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
917 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
918 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
919 | ||
20f0ec16 JB |
920 | /* Convert to KHz, p & r have a fixed point portion */ |
921 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
922 | } |
923 | ||
540e732c S |
924 | static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
925 | uint32_t dpll) | |
926 | { | |
f0f59a00 | 927 | i915_reg_t cfgcr1_reg, cfgcr2_reg; |
540e732c S |
928 | uint32_t cfgcr1_val, cfgcr2_val; |
929 | uint32_t p0, p1, p2, dco_freq; | |
930 | ||
923c1241 VS |
931 | cfgcr1_reg = DPLL_CFGCR1(dpll); |
932 | cfgcr2_reg = DPLL_CFGCR2(dpll); | |
540e732c S |
933 | |
934 | cfgcr1_val = I915_READ(cfgcr1_reg); | |
935 | cfgcr2_val = I915_READ(cfgcr2_reg); | |
936 | ||
937 | p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; | |
938 | p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; | |
939 | ||
940 | if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) | |
941 | p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; | |
942 | else | |
943 | p1 = 1; | |
944 | ||
945 | ||
946 | switch (p0) { | |
947 | case DPLL_CFGCR2_PDIV_1: | |
948 | p0 = 1; | |
949 | break; | |
950 | case DPLL_CFGCR2_PDIV_2: | |
951 | p0 = 2; | |
952 | break; | |
953 | case DPLL_CFGCR2_PDIV_3: | |
954 | p0 = 3; | |
955 | break; | |
956 | case DPLL_CFGCR2_PDIV_7: | |
957 | p0 = 7; | |
958 | break; | |
959 | } | |
960 | ||
961 | switch (p2) { | |
962 | case DPLL_CFGCR2_KDIV_5: | |
963 | p2 = 5; | |
964 | break; | |
965 | case DPLL_CFGCR2_KDIV_2: | |
966 | p2 = 2; | |
967 | break; | |
968 | case DPLL_CFGCR2_KDIV_3: | |
969 | p2 = 3; | |
970 | break; | |
971 | case DPLL_CFGCR2_KDIV_1: | |
972 | p2 = 1; | |
973 | break; | |
974 | } | |
975 | ||
976 | dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; | |
977 | ||
978 | dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * | |
979 | 1000) / 0x8000; | |
980 | ||
981 | return dco_freq / (p0 * p1 * p2 * 5); | |
982 | } | |
983 | ||
398a017e VS |
984 | static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) |
985 | { | |
986 | int dotclock; | |
987 | ||
988 | if (pipe_config->has_pch_encoder) | |
989 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
990 | &pipe_config->fdi_m_n); | |
991 | else if (pipe_config->has_dp_encoder) | |
992 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
993 | &pipe_config->dp_m_n); | |
994 | else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) | |
995 | dotclock = pipe_config->port_clock * 2 / 3; | |
996 | else | |
997 | dotclock = pipe_config->port_clock; | |
998 | ||
999 | if (pipe_config->pixel_multiplier) | |
1000 | dotclock /= pipe_config->pixel_multiplier; | |
1001 | ||
1002 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; | |
1003 | } | |
540e732c S |
1004 | |
1005 | static void skl_ddi_clock_get(struct intel_encoder *encoder, | |
5cec258b | 1006 | struct intel_crtc_state *pipe_config) |
540e732c S |
1007 | { |
1008 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
540e732c S |
1009 | int link_clock = 0; |
1010 | uint32_t dpll_ctl1, dpll; | |
1011 | ||
134ffa44 | 1012 | dpll = pipe_config->ddi_pll_sel; |
540e732c S |
1013 | |
1014 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
1015 | ||
1016 | if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { | |
1017 | link_clock = skl_calc_wrpll_link(dev_priv, dpll); | |
1018 | } else { | |
71cd8423 DL |
1019 | link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); |
1020 | link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); | |
540e732c S |
1021 | |
1022 | switch (link_clock) { | |
71cd8423 | 1023 | case DPLL_CTRL1_LINK_RATE_810: |
540e732c S |
1024 | link_clock = 81000; |
1025 | break; | |
71cd8423 | 1026 | case DPLL_CTRL1_LINK_RATE_1080: |
a8f3ef61 SJ |
1027 | link_clock = 108000; |
1028 | break; | |
71cd8423 | 1029 | case DPLL_CTRL1_LINK_RATE_1350: |
540e732c S |
1030 | link_clock = 135000; |
1031 | break; | |
71cd8423 | 1032 | case DPLL_CTRL1_LINK_RATE_1620: |
a8f3ef61 SJ |
1033 | link_clock = 162000; |
1034 | break; | |
71cd8423 | 1035 | case DPLL_CTRL1_LINK_RATE_2160: |
a8f3ef61 SJ |
1036 | link_clock = 216000; |
1037 | break; | |
71cd8423 | 1038 | case DPLL_CTRL1_LINK_RATE_2700: |
540e732c S |
1039 | link_clock = 270000; |
1040 | break; | |
1041 | default: | |
1042 | WARN(1, "Unsupported link rate\n"); | |
1043 | break; | |
1044 | } | |
1045 | link_clock *= 2; | |
1046 | } | |
1047 | ||
1048 | pipe_config->port_clock = link_clock; | |
1049 | ||
398a017e | 1050 | ddi_dotclock_get(pipe_config); |
540e732c S |
1051 | } |
1052 | ||
3d51278a | 1053 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1054 | struct intel_crtc_state *pipe_config) |
11578553 JB |
1055 | { |
1056 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
11578553 JB |
1057 | int link_clock = 0; |
1058 | u32 val, pll; | |
1059 | ||
26804afd | 1060 | val = pipe_config->ddi_pll_sel; |
11578553 JB |
1061 | switch (val & PORT_CLK_SEL_MASK) { |
1062 | case PORT_CLK_SEL_LCPLL_810: | |
1063 | link_clock = 81000; | |
1064 | break; | |
1065 | case PORT_CLK_SEL_LCPLL_1350: | |
1066 | link_clock = 135000; | |
1067 | break; | |
1068 | case PORT_CLK_SEL_LCPLL_2700: | |
1069 | link_clock = 270000; | |
1070 | break; | |
1071 | case PORT_CLK_SEL_WRPLL1: | |
01403de3 | 1072 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); |
11578553 JB |
1073 | break; |
1074 | case PORT_CLK_SEL_WRPLL2: | |
01403de3 | 1075 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); |
11578553 JB |
1076 | break; |
1077 | case PORT_CLK_SEL_SPLL: | |
1078 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
1079 | if (pll == SPLL_PLL_FREQ_810MHz) | |
1080 | link_clock = 81000; | |
1081 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
1082 | link_clock = 135000; | |
1083 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
1084 | link_clock = 270000; | |
1085 | else { | |
1086 | WARN(1, "bad spll freq\n"); | |
1087 | return; | |
1088 | } | |
1089 | break; | |
1090 | default: | |
1091 | WARN(1, "bad port clock sel\n"); | |
1092 | return; | |
1093 | } | |
1094 | ||
1095 | pipe_config->port_clock = link_clock * 2; | |
1096 | ||
398a017e | 1097 | ddi_dotclock_get(pipe_config); |
11578553 JB |
1098 | } |
1099 | ||
977bb38d S |
1100 | static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, |
1101 | enum intel_dpll_id dpll) | |
1102 | { | |
aa610dcb ID |
1103 | struct intel_shared_dpll *pll; |
1104 | struct intel_dpll_hw_state *state; | |
1105 | intel_clock_t clock; | |
1106 | ||
1107 | /* For DDI ports we always use a shared PLL. */ | |
1108 | if (WARN_ON(dpll == DPLL_ID_PRIVATE)) | |
1109 | return 0; | |
1110 | ||
1111 | pll = &dev_priv->shared_dplls[dpll]; | |
1112 | state = &pll->config.hw_state; | |
1113 | ||
1114 | clock.m1 = 2; | |
1115 | clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; | |
1116 | if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) | |
1117 | clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; | |
1118 | clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; | |
1119 | clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; | |
1120 | clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; | |
1121 | ||
1122 | return chv_calc_dpll_params(100000, &clock); | |
977bb38d S |
1123 | } |
1124 | ||
1125 | static void bxt_ddi_clock_get(struct intel_encoder *encoder, | |
1126 | struct intel_crtc_state *pipe_config) | |
1127 | { | |
1128 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1129 | enum port port = intel_ddi_get_encoder_port(encoder); | |
1130 | uint32_t dpll = port; | |
1131 | ||
398a017e | 1132 | pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); |
977bb38d | 1133 | |
398a017e | 1134 | ddi_dotclock_get(pipe_config); |
977bb38d S |
1135 | } |
1136 | ||
3d51278a | 1137 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1138 | struct intel_crtc_state *pipe_config) |
3d51278a | 1139 | { |
22606a18 DL |
1140 | struct drm_device *dev = encoder->base.dev; |
1141 | ||
1142 | if (INTEL_INFO(dev)->gen <= 8) | |
1143 | hsw_ddi_clock_get(encoder, pipe_config); | |
ef11bdb3 | 1144 | else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
22606a18 | 1145 | skl_ddi_clock_get(encoder, pipe_config); |
977bb38d S |
1146 | else if (IS_BROXTON(dev)) |
1147 | bxt_ddi_clock_get(encoder, pipe_config); | |
3d51278a DV |
1148 | } |
1149 | ||
1c0b85c5 | 1150 | static void |
d664c0ce DL |
1151 | hsw_ddi_calculate_wrpll(int clock /* in Hz */, |
1152 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
1c0b85c5 DL |
1153 | { |
1154 | uint64_t freq2k; | |
1155 | unsigned p, n2, r2; | |
63582983 | 1156 | struct hsw_wrpll_rnp best = { 0, 0, 0 }; |
1c0b85c5 DL |
1157 | unsigned budget; |
1158 | ||
1159 | freq2k = clock / 100; | |
1160 | ||
63582983 | 1161 | budget = hsw_wrpll_get_budget_for_freq(clock); |
1c0b85c5 DL |
1162 | |
1163 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
1164 | * and directly pass the LC PLL to it. */ | |
1165 | if (freq2k == 5400000) { | |
1166 | *n2_out = 2; | |
1167 | *p_out = 1; | |
1168 | *r2_out = 2; | |
1169 | return; | |
1170 | } | |
1171 | ||
1172 | /* | |
1173 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
1174 | * the WR PLL. | |
1175 | * | |
1176 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
1177 | * Injecting R2 = 2 * R gives: | |
1178 | * REF_MAX * r2 > LC_FREQ * 2 and | |
1179 | * REF_MIN * r2 < LC_FREQ * 2 | |
1180 | * | |
1181 | * Which means the desired boundaries for r2 are: | |
1182 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
1183 | * | |
1184 | */ | |
1185 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
1186 | r2 <= LC_FREQ * 2 / REF_MIN; | |
1187 | r2++) { | |
1188 | ||
1189 | /* | |
1190 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
1191 | * | |
1192 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
1193 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
1194 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
1195 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
1196 | * | |
1197 | * Which means the desired boundaries for n2 are: | |
1198 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
1199 | */ | |
1200 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
1201 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
1202 | n2++) { | |
1203 | ||
1204 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
63582983 DL |
1205 | hsw_wrpll_update_rnp(freq2k, budget, |
1206 | r2, n2, p, &best); | |
1c0b85c5 DL |
1207 | } |
1208 | } | |
6441ab5f | 1209 | |
1c0b85c5 DL |
1210 | *n2_out = best.n2; |
1211 | *p_out = best.p; | |
1212 | *r2_out = best.r2; | |
6441ab5f PZ |
1213 | } |
1214 | ||
0220ab6e | 1215 | static bool |
d664c0ce | 1216 | hsw_ddi_pll_select(struct intel_crtc *intel_crtc, |
190f68c5 | 1217 | struct intel_crtc_state *crtc_state, |
96f3f1f9 | 1218 | struct intel_encoder *intel_encoder) |
6441ab5f | 1219 | { |
96f3f1f9 VS |
1220 | int clock = crtc_state->port_clock; |
1221 | ||
d664c0ce | 1222 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
e0b01be4 | 1223 | struct intel_shared_dpll *pll; |
716c2e55 | 1224 | uint32_t val; |
1c0b85c5 | 1225 | unsigned p, n2, r2; |
6441ab5f | 1226 | |
d664c0ce | 1227 | hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
0694001b | 1228 | |
114fe488 | 1229 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
0694001b PZ |
1230 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
1231 | WRPLL_DIVIDER_POST(p); | |
1232 | ||
dd3cd74a ACO |
1233 | memset(&crtc_state->dpll_hw_state, 0, |
1234 | sizeof(crtc_state->dpll_hw_state)); | |
1235 | ||
190f68c5 | 1236 | crtc_state->dpll_hw_state.wrpll = val; |
6441ab5f | 1237 | |
190f68c5 | 1238 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
716c2e55 DV |
1239 | if (pll == NULL) { |
1240 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1241 | pipe_name(intel_crtc->pipe)); | |
1242 | return false; | |
0694001b | 1243 | } |
d452c5b6 | 1244 | |
190f68c5 | 1245 | crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); |
00490c22 ML |
1246 | } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) { |
1247 | struct drm_atomic_state *state = crtc_state->base.state; | |
1248 | struct intel_shared_dpll_config *spll = | |
1249 | &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL]; | |
1250 | ||
1251 | if (spll->crtc_mask && | |
1252 | WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll)) | |
1253 | return false; | |
1254 | ||
1255 | crtc_state->shared_dpll = DPLL_ID_SPLL; | |
1256 | spll->hw_state.spll = crtc_state->dpll_hw_state.spll; | |
1257 | spll->crtc_mask |= 1 << intel_crtc->pipe; | |
6441ab5f PZ |
1258 | } |
1259 | ||
6441ab5f PZ |
1260 | return true; |
1261 | } | |
1262 | ||
dc253813 DL |
1263 | struct skl_wrpll_context { |
1264 | uint64_t min_deviation; /* current minimal deviation */ | |
1265 | uint64_t central_freq; /* chosen central freq */ | |
1266 | uint64_t dco_freq; /* chosen dco freq */ | |
1267 | unsigned int p; /* chosen divider */ | |
1268 | }; | |
1269 | ||
1270 | static void skl_wrpll_context_init(struct skl_wrpll_context *ctx) | |
1271 | { | |
1272 | memset(ctx, 0, sizeof(*ctx)); | |
1273 | ||
1274 | ctx->min_deviation = U64_MAX; | |
1275 | } | |
1276 | ||
1277 | /* DCO freq must be within +1%/-6% of the DCO central freq */ | |
1278 | #define SKL_DCO_MAX_PDEVIATION 100 | |
1279 | #define SKL_DCO_MAX_NDEVIATION 600 | |
1280 | ||
1281 | static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, | |
1282 | uint64_t central_freq, | |
1283 | uint64_t dco_freq, | |
1284 | unsigned int divider) | |
1285 | { | |
1286 | uint64_t deviation; | |
1287 | ||
1288 | deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq), | |
1289 | central_freq); | |
1290 | ||
1291 | /* positive deviation */ | |
1292 | if (dco_freq >= central_freq) { | |
1293 | if (deviation < SKL_DCO_MAX_PDEVIATION && | |
1294 | deviation < ctx->min_deviation) { | |
1295 | ctx->min_deviation = deviation; | |
1296 | ctx->central_freq = central_freq; | |
1297 | ctx->dco_freq = dco_freq; | |
1298 | ctx->p = divider; | |
1299 | } | |
1300 | /* negative deviation */ | |
1301 | } else if (deviation < SKL_DCO_MAX_NDEVIATION && | |
1302 | deviation < ctx->min_deviation) { | |
1303 | ctx->min_deviation = deviation; | |
1304 | ctx->central_freq = central_freq; | |
1305 | ctx->dco_freq = dco_freq; | |
1306 | ctx->p = divider; | |
1307 | } | |
dc253813 DL |
1308 | } |
1309 | ||
1310 | static void skl_wrpll_get_multipliers(unsigned int p, | |
1311 | unsigned int *p0 /* out */, | |
1312 | unsigned int *p1 /* out */, | |
1313 | unsigned int *p2 /* out */) | |
1314 | { | |
1315 | /* even dividers */ | |
1316 | if (p % 2 == 0) { | |
1317 | unsigned int half = p / 2; | |
1318 | ||
1319 | if (half == 1 || half == 2 || half == 3 || half == 5) { | |
1320 | *p0 = 2; | |
1321 | *p1 = 1; | |
1322 | *p2 = half; | |
1323 | } else if (half % 2 == 0) { | |
1324 | *p0 = 2; | |
1325 | *p1 = half / 2; | |
1326 | *p2 = 2; | |
1327 | } else if (half % 3 == 0) { | |
1328 | *p0 = 3; | |
1329 | *p1 = half / 3; | |
1330 | *p2 = 2; | |
1331 | } else if (half % 7 == 0) { | |
1332 | *p0 = 7; | |
1333 | *p1 = half / 7; | |
1334 | *p2 = 2; | |
1335 | } | |
1336 | } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ | |
1337 | *p0 = 3; | |
1338 | *p1 = 1; | |
1339 | *p2 = p / 3; | |
1340 | } else if (p == 5 || p == 7) { | |
1341 | *p0 = p; | |
1342 | *p1 = 1; | |
1343 | *p2 = 1; | |
1344 | } else if (p == 15) { | |
1345 | *p0 = 3; | |
1346 | *p1 = 1; | |
1347 | *p2 = 5; | |
1348 | } else if (p == 21) { | |
1349 | *p0 = 7; | |
1350 | *p1 = 1; | |
1351 | *p2 = 3; | |
1352 | } else if (p == 35) { | |
1353 | *p0 = 7; | |
1354 | *p1 = 1; | |
1355 | *p2 = 5; | |
1356 | } | |
1357 | } | |
1358 | ||
82d35437 S |
1359 | struct skl_wrpll_params { |
1360 | uint32_t dco_fraction; | |
1361 | uint32_t dco_integer; | |
1362 | uint32_t qdiv_ratio; | |
1363 | uint32_t qdiv_mode; | |
1364 | uint32_t kdiv; | |
1365 | uint32_t pdiv; | |
1366 | uint32_t central_freq; | |
1367 | }; | |
1368 | ||
76516fbc DL |
1369 | static void skl_wrpll_params_populate(struct skl_wrpll_params *params, |
1370 | uint64_t afe_clock, | |
1371 | uint64_t central_freq, | |
1372 | uint32_t p0, uint32_t p1, uint32_t p2) | |
1373 | { | |
1374 | uint64_t dco_freq; | |
1375 | ||
76516fbc DL |
1376 | switch (central_freq) { |
1377 | case 9600000000ULL: | |
1378 | params->central_freq = 0; | |
1379 | break; | |
1380 | case 9000000000ULL: | |
1381 | params->central_freq = 1; | |
1382 | break; | |
1383 | case 8400000000ULL: | |
1384 | params->central_freq = 3; | |
1385 | } | |
1386 | ||
1387 | switch (p0) { | |
1388 | case 1: | |
1389 | params->pdiv = 0; | |
1390 | break; | |
1391 | case 2: | |
1392 | params->pdiv = 1; | |
1393 | break; | |
1394 | case 3: | |
1395 | params->pdiv = 2; | |
1396 | break; | |
1397 | case 7: | |
1398 | params->pdiv = 4; | |
1399 | break; | |
1400 | default: | |
1401 | WARN(1, "Incorrect PDiv\n"); | |
1402 | } | |
1403 | ||
1404 | switch (p2) { | |
1405 | case 5: | |
1406 | params->kdiv = 0; | |
1407 | break; | |
1408 | case 2: | |
1409 | params->kdiv = 1; | |
1410 | break; | |
1411 | case 3: | |
1412 | params->kdiv = 2; | |
1413 | break; | |
1414 | case 1: | |
1415 | params->kdiv = 3; | |
1416 | break; | |
1417 | default: | |
1418 | WARN(1, "Incorrect KDiv\n"); | |
1419 | } | |
1420 | ||
1421 | params->qdiv_ratio = p1; | |
1422 | params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; | |
1423 | ||
1424 | dco_freq = p0 * p1 * p2 * afe_clock; | |
1425 | ||
1426 | /* | |
1427 | * Intermediate values are in Hz. | |
1428 | * Divide by MHz to match bsepc | |
1429 | */ | |
30a7862d | 1430 | params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); |
76516fbc | 1431 | params->dco_fraction = |
30a7862d DL |
1432 | div_u64((div_u64(dco_freq, 24) - |
1433 | params->dco_integer * MHz(1)) * 0x8000, MHz(1)); | |
76516fbc DL |
1434 | } |
1435 | ||
318bd821 | 1436 | static bool |
82d35437 S |
1437 | skl_ddi_calculate_wrpll(int clock /* in Hz */, |
1438 | struct skl_wrpll_params *wrpll_params) | |
1439 | { | |
1440 | uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ | |
21318cce DL |
1441 | uint64_t dco_central_freq[3] = {8400000000ULL, |
1442 | 9000000000ULL, | |
1443 | 9600000000ULL}; | |
dc253813 DL |
1444 | static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, |
1445 | 24, 28, 30, 32, 36, 40, 42, 44, | |
1446 | 48, 52, 54, 56, 60, 64, 66, 68, | |
1447 | 70, 72, 76, 78, 80, 84, 88, 90, | |
1448 | 92, 96, 98 }; | |
1449 | static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; | |
1450 | static const struct { | |
1451 | const int *list; | |
1452 | int n_dividers; | |
1453 | } dividers[] = { | |
1454 | { even_dividers, ARRAY_SIZE(even_dividers) }, | |
1455 | { odd_dividers, ARRAY_SIZE(odd_dividers) }, | |
1456 | }; | |
1457 | struct skl_wrpll_context ctx; | |
1458 | unsigned int dco, d, i; | |
1459 | unsigned int p0, p1, p2; | |
1460 | ||
1461 | skl_wrpll_context_init(&ctx); | |
1462 | ||
1463 | for (d = 0; d < ARRAY_SIZE(dividers); d++) { | |
1464 | for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { | |
1465 | for (i = 0; i < dividers[d].n_dividers; i++) { | |
1466 | unsigned int p = dividers[d].list[i]; | |
1467 | uint64_t dco_freq = p * afe_clock; | |
1468 | ||
1469 | skl_wrpll_try_divider(&ctx, | |
1470 | dco_central_freq[dco], | |
1471 | dco_freq, | |
1472 | p); | |
e7ad9878 DL |
1473 | /* |
1474 | * Skip the remaining dividers if we're sure to | |
1475 | * have found the definitive divider, we can't | |
1476 | * improve a 0 deviation. | |
1477 | */ | |
1478 | if (ctx.min_deviation == 0) | |
1479 | goto skip_remaining_dividers; | |
82d35437 S |
1480 | } |
1481 | } | |
267db663 | 1482 | |
e7ad9878 | 1483 | skip_remaining_dividers: |
267db663 DL |
1484 | /* |
1485 | * If a solution is found with an even divider, prefer | |
1486 | * this one. | |
1487 | */ | |
1488 | if (d == 0 && ctx.p) | |
1489 | break; | |
82d35437 S |
1490 | } |
1491 | ||
dc253813 DL |
1492 | if (!ctx.p) { |
1493 | DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock); | |
318bd821 | 1494 | return false; |
dc253813 | 1495 | } |
82d35437 | 1496 | |
dc253813 DL |
1497 | /* |
1498 | * gcc incorrectly analyses that these can be used without being | |
1499 | * initialized. To be fair, it's hard to guess. | |
1500 | */ | |
1501 | p0 = p1 = p2 = 0; | |
1502 | skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); | |
1503 | skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq, | |
1504 | p0, p1, p2); | |
318bd821 DL |
1505 | |
1506 | return true; | |
82d35437 S |
1507 | } |
1508 | ||
82d35437 S |
1509 | static bool |
1510 | skl_ddi_pll_select(struct intel_crtc *intel_crtc, | |
190f68c5 | 1511 | struct intel_crtc_state *crtc_state, |
96f3f1f9 | 1512 | struct intel_encoder *intel_encoder) |
82d35437 S |
1513 | { |
1514 | struct intel_shared_dpll *pll; | |
1515 | uint32_t ctrl1, cfgcr1, cfgcr2; | |
96f3f1f9 | 1516 | int clock = crtc_state->port_clock; |
82d35437 S |
1517 | |
1518 | /* | |
1519 | * See comment in intel_dpll_hw_state to understand why we always use 0 | |
1520 | * as the DPLL id in this function. | |
1521 | */ | |
1522 | ||
1523 | ctrl1 = DPLL_CTRL1_OVERRIDE(0); | |
1524 | ||
1525 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
1526 | struct skl_wrpll_params wrpll_params = { 0, }; | |
1527 | ||
1528 | ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); | |
1529 | ||
318bd821 DL |
1530 | if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params)) |
1531 | return false; | |
82d35437 S |
1532 | |
1533 | cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | | |
1534 | DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | | |
1535 | wrpll_params.dco_integer; | |
1536 | ||
1537 | cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | | |
1538 | DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | | |
1539 | DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | | |
1540 | DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | | |
1541 | wrpll_params.central_freq; | |
78385cb3 L |
1542 | } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
1543 | intel_encoder->type == INTEL_OUTPUT_DP_MST) { | |
840b32b7 VS |
1544 | switch (crtc_state->port_clock / 2) { |
1545 | case 81000: | |
71cd8423 | 1546 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); |
82d35437 | 1547 | break; |
840b32b7 | 1548 | case 135000: |
71cd8423 | 1549 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); |
82d35437 | 1550 | break; |
840b32b7 | 1551 | case 270000: |
71cd8423 | 1552 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); |
82d35437 S |
1553 | break; |
1554 | } | |
1555 | ||
1556 | cfgcr1 = cfgcr2 = 0; | |
5a01d5b6 | 1557 | } else if (intel_encoder->type == INTEL_OUTPUT_EDP) { |
82d35437 | 1558 | return true; |
5a01d5b6 L |
1559 | } else |
1560 | return false; | |
82d35437 | 1561 | |
dd3cd74a ACO |
1562 | memset(&crtc_state->dpll_hw_state, 0, |
1563 | sizeof(crtc_state->dpll_hw_state)); | |
1564 | ||
190f68c5 ACO |
1565 | crtc_state->dpll_hw_state.ctrl1 = ctrl1; |
1566 | crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; | |
1567 | crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; | |
82d35437 | 1568 | |
190f68c5 | 1569 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
82d35437 S |
1570 | if (pll == NULL) { |
1571 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1572 | pipe_name(intel_crtc->pipe)); | |
1573 | return false; | |
1574 | } | |
1575 | ||
1576 | /* shared DPLL id 0 is DPLL 1 */ | |
190f68c5 | 1577 | crtc_state->ddi_pll_sel = pll->id + 1; |
82d35437 S |
1578 | |
1579 | return true; | |
1580 | } | |
0220ab6e | 1581 | |
d683f3bc S |
1582 | /* bxt clock parameters */ |
1583 | struct bxt_clk_div { | |
64987fc5 | 1584 | int clock; |
d683f3bc S |
1585 | uint32_t p1; |
1586 | uint32_t p2; | |
1587 | uint32_t m2_int; | |
1588 | uint32_t m2_frac; | |
1589 | bool m2_frac_en; | |
1590 | uint32_t n; | |
d683f3bc S |
1591 | }; |
1592 | ||
1593 | /* pre-calculated values for DP linkrates */ | |
64987fc5 SJ |
1594 | static const struct bxt_clk_div bxt_dp_clk_val[] = { |
1595 | {162000, 4, 2, 32, 1677722, 1, 1}, | |
1596 | {270000, 4, 1, 27, 0, 0, 1}, | |
1597 | {540000, 2, 1, 27, 0, 0, 1}, | |
1598 | {216000, 3, 2, 32, 1677722, 1, 1}, | |
1599 | {243000, 4, 1, 24, 1258291, 1, 1}, | |
1600 | {324000, 4, 1, 32, 1677722, 1, 1}, | |
1601 | {432000, 3, 1, 32, 1677722, 1, 1} | |
d683f3bc S |
1602 | }; |
1603 | ||
1604 | static bool | |
1605 | bxt_ddi_pll_select(struct intel_crtc *intel_crtc, | |
1606 | struct intel_crtc_state *crtc_state, | |
96f3f1f9 | 1607 | struct intel_encoder *intel_encoder) |
d683f3bc S |
1608 | { |
1609 | struct intel_shared_dpll *pll; | |
1610 | struct bxt_clk_div clk_div = {0}; | |
b6dc71f3 VK |
1611 | int vco = 0; |
1612 | uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; | |
e6292556 | 1613 | uint32_t lanestagger; |
96f3f1f9 | 1614 | int clock = crtc_state->port_clock; |
d683f3bc S |
1615 | |
1616 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
1617 | intel_clock_t best_clock; | |
1618 | ||
1619 | /* Calculate HDMI div */ | |
1620 | /* | |
1621 | * FIXME: tie the following calculation into | |
1622 | * i9xx_crtc_compute_clock | |
1623 | */ | |
1624 | if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { | |
1625 | DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", | |
1626 | clock, pipe_name(intel_crtc->pipe)); | |
1627 | return false; | |
1628 | } | |
1629 | ||
1630 | clk_div.p1 = best_clock.p1; | |
1631 | clk_div.p2 = best_clock.p2; | |
1632 | WARN_ON(best_clock.m1 != 2); | |
1633 | clk_div.n = best_clock.n; | |
1634 | clk_div.m2_int = best_clock.m2 >> 22; | |
1635 | clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); | |
1636 | clk_div.m2_frac_en = clk_div.m2_frac != 0; | |
1637 | ||
b6dc71f3 | 1638 | vco = best_clock.vco; |
d683f3bc S |
1639 | } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
1640 | intel_encoder->type == INTEL_OUTPUT_EDP) { | |
64987fc5 | 1641 | int i; |
d683f3bc | 1642 | |
64987fc5 SJ |
1643 | clk_div = bxt_dp_clk_val[0]; |
1644 | for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { | |
1645 | if (bxt_dp_clk_val[i].clock == clock) { | |
1646 | clk_div = bxt_dp_clk_val[i]; | |
1647 | break; | |
1648 | } | |
d683f3bc | 1649 | } |
b6dc71f3 VK |
1650 | vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; |
1651 | } | |
1652 | ||
e6292556 | 1653 | if (vco >= 6200000 && vco <= 6700000) { |
b6dc71f3 VK |
1654 | prop_coef = 4; |
1655 | int_coef = 9; | |
1656 | gain_ctl = 3; | |
1657 | targ_cnt = 8; | |
1658 | } else if ((vco > 5400000 && vco < 6200000) || | |
1659 | (vco >= 4800000 && vco < 5400000)) { | |
1660 | prop_coef = 5; | |
1661 | int_coef = 11; | |
1662 | gain_ctl = 3; | |
1663 | targ_cnt = 9; | |
b6dc71f3 VK |
1664 | } else if (vco == 5400000) { |
1665 | prop_coef = 3; | |
1666 | int_coef = 8; | |
1667 | gain_ctl = 1; | |
1668 | targ_cnt = 9; | |
1669 | } else { | |
1670 | DRM_ERROR("Invalid VCO\n"); | |
1671 | return false; | |
d683f3bc S |
1672 | } |
1673 | ||
dd3cd74a ACO |
1674 | memset(&crtc_state->dpll_hw_state, 0, |
1675 | sizeof(crtc_state->dpll_hw_state)); | |
1676 | ||
e0681e38 VK |
1677 | if (clock > 270000) |
1678 | lanestagger = 0x18; | |
1679 | else if (clock > 135000) | |
1680 | lanestagger = 0x0d; | |
1681 | else if (clock > 67000) | |
1682 | lanestagger = 0x07; | |
1683 | else if (clock > 33000) | |
1684 | lanestagger = 0x04; | |
1685 | else | |
1686 | lanestagger = 0x02; | |
1687 | ||
d683f3bc S |
1688 | crtc_state->dpll_hw_state.ebb0 = |
1689 | PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); | |
1690 | crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; | |
1691 | crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); | |
1692 | crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; | |
1693 | ||
1694 | if (clk_div.m2_frac_en) | |
1695 | crtc_state->dpll_hw_state.pll3 = | |
1696 | PORT_PLL_M2_FRAC_ENABLE; | |
1697 | ||
1698 | crtc_state->dpll_hw_state.pll6 = | |
b6dc71f3 | 1699 | prop_coef | PORT_PLL_INT_COEFF(int_coef); |
d683f3bc | 1700 | crtc_state->dpll_hw_state.pll6 |= |
b6dc71f3 VK |
1701 | PORT_PLL_GAIN_CTL(gain_ctl); |
1702 | ||
1703 | crtc_state->dpll_hw_state.pll8 = targ_cnt; | |
d683f3bc | 1704 | |
05712c15 ID |
1705 | crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; |
1706 | ||
e6292556 VK |
1707 | crtc_state->dpll_hw_state.pll10 = |
1708 | PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) | |
1709 | | PORT_PLL_DCO_AMP_OVR_EN_H; | |
d683f3bc | 1710 | |
05712c15 ID |
1711 | crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE; |
1712 | ||
d683f3bc | 1713 | crtc_state->dpll_hw_state.pcsdw12 = |
e0681e38 | 1714 | LANESTAGGER_STRAP_OVRD | lanestagger; |
d683f3bc S |
1715 | |
1716 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); | |
1717 | if (pll == NULL) { | |
1718 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1719 | pipe_name(intel_crtc->pipe)); | |
1720 | return false; | |
1721 | } | |
1722 | ||
1723 | /* shared DPLL id 0 is DPLL A */ | |
1724 | crtc_state->ddi_pll_sel = pll->id; | |
1725 | ||
1726 | return true; | |
1727 | } | |
1728 | ||
0220ab6e DL |
1729 | /* |
1730 | * Tries to find a *shared* PLL for the CRTC and store it in | |
1731 | * intel_crtc->ddi_pll_sel. | |
1732 | * | |
1733 | * For private DPLLs, compute_config() should do the selection for us. This | |
1734 | * function should be folded into compute_config() eventually. | |
1735 | */ | |
190f68c5 ACO |
1736 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, |
1737 | struct intel_crtc_state *crtc_state) | |
0220ab6e | 1738 | { |
82d35437 | 1739 | struct drm_device *dev = intel_crtc->base.dev; |
d0737e1d | 1740 | struct intel_encoder *intel_encoder = |
3165c074 | 1741 | intel_ddi_get_crtc_new_encoder(crtc_state); |
0220ab6e | 1742 | |
ef11bdb3 | 1743 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
190f68c5 | 1744 | return skl_ddi_pll_select(intel_crtc, crtc_state, |
96f3f1f9 | 1745 | intel_encoder); |
d683f3bc S |
1746 | else if (IS_BROXTON(dev)) |
1747 | return bxt_ddi_pll_select(intel_crtc, crtc_state, | |
96f3f1f9 | 1748 | intel_encoder); |
82d35437 | 1749 | else |
190f68c5 | 1750 | return hsw_ddi_pll_select(intel_crtc, crtc_state, |
96f3f1f9 | 1751 | intel_encoder); |
0220ab6e DL |
1752 | } |
1753 | ||
dae84799 PZ |
1754 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
1755 | { | |
1756 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1757 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1758 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
6e3c9717 | 1759 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
dae84799 PZ |
1760 | int type = intel_encoder->type; |
1761 | uint32_t temp; | |
1762 | ||
0e32b39c | 1763 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
c9809791 | 1764 | temp = TRANS_MSA_SYNC_CLK; |
6e3c9717 | 1765 | switch (intel_crtc->config->pipe_bpp) { |
dae84799 | 1766 | case 18: |
c9809791 | 1767 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
1768 | break; |
1769 | case 24: | |
c9809791 | 1770 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
1771 | break; |
1772 | case 30: | |
c9809791 | 1773 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
1774 | break; |
1775 | case 36: | |
c9809791 | 1776 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
1777 | break; |
1778 | default: | |
4e53c2e0 | 1779 | BUG(); |
dae84799 | 1780 | } |
c9809791 | 1781 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
1782 | } |
1783 | } | |
1784 | ||
0e32b39c DA |
1785 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) |
1786 | { | |
1787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1788 | struct drm_device *dev = crtc->dev; | |
1789 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 1790 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
0e32b39c DA |
1791 | uint32_t temp; |
1792 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1793 | if (state == true) | |
1794 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1795 | else | |
1796 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1797 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
1798 | } | |
1799 | ||
8228c251 | 1800 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
1801 | { |
1802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1803 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 1804 | struct drm_encoder *encoder = &intel_encoder->base; |
c7670b10 PZ |
1805 | struct drm_device *dev = crtc->dev; |
1806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8d9ddbcb | 1807 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 1808 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
174edf1f | 1809 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 1810 | int type = intel_encoder->type; |
8d9ddbcb PZ |
1811 | uint32_t temp; |
1812 | ||
ad80a810 PZ |
1813 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
1814 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 1815 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 1816 | |
6e3c9717 | 1817 | switch (intel_crtc->config->pipe_bpp) { |
dfcef252 | 1818 | case 18: |
ad80a810 | 1819 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
1820 | break; |
1821 | case 24: | |
ad80a810 | 1822 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
1823 | break; |
1824 | case 30: | |
ad80a810 | 1825 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
1826 | break; |
1827 | case 36: | |
ad80a810 | 1828 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
1829 | break; |
1830 | default: | |
4e53c2e0 | 1831 | BUG(); |
dfcef252 | 1832 | } |
72662e10 | 1833 | |
6e3c9717 | 1834 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 1835 | temp |= TRANS_DDI_PVSYNC; |
6e3c9717 | 1836 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 1837 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 1838 | |
e6f0bfc4 PZ |
1839 | if (cpu_transcoder == TRANSCODER_EDP) { |
1840 | switch (pipe) { | |
1841 | case PIPE_A: | |
c7670b10 PZ |
1842 | /* On Haswell, can only use the always-on power well for |
1843 | * eDP when not using the panel fitter, and when not | |
1844 | * using motion blur mitigation (which we don't | |
1845 | * support). */ | |
fabf6e51 | 1846 | if (IS_HASWELL(dev) && |
6e3c9717 ACO |
1847 | (intel_crtc->config->pch_pfit.enabled || |
1848 | intel_crtc->config->pch_pfit.force_thru)) | |
d6dd9eb1 DV |
1849 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
1850 | else | |
1851 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
1852 | break; |
1853 | case PIPE_B: | |
1854 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
1855 | break; | |
1856 | case PIPE_C: | |
1857 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
1858 | break; | |
1859 | default: | |
1860 | BUG(); | |
1861 | break; | |
1862 | } | |
1863 | } | |
1864 | ||
7739c33b | 1865 | if (type == INTEL_OUTPUT_HDMI) { |
6e3c9717 | 1866 | if (intel_crtc->config->has_hdmi_sink) |
ad80a810 | 1867 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 1868 | else |
ad80a810 | 1869 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 1870 | |
7739c33b | 1871 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 1872 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
6e3c9717 | 1873 | temp |= (intel_crtc->config->fdi_lanes - 1) << 1; |
7739c33b PZ |
1874 | |
1875 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
1876 | type == INTEL_OUTPUT_EDP) { | |
1877 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1878 | ||
0e32b39c DA |
1879 | if (intel_dp->is_mst) { |
1880 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; | |
1881 | } else | |
1882 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; | |
1883 | ||
90a6b7b0 | 1884 | temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); |
0e32b39c DA |
1885 | } else if (type == INTEL_OUTPUT_DP_MST) { |
1886 | struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; | |
1887 | ||
1888 | if (intel_dp->is_mst) { | |
1889 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; | |
1890 | } else | |
1891 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; | |
7739c33b | 1892 | |
90a6b7b0 | 1893 | temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); |
8d9ddbcb | 1894 | } else { |
84f44ce7 VS |
1895 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
1896 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
1897 | } |
1898 | ||
ad80a810 | 1899 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 1900 | } |
72662e10 | 1901 | |
ad80a810 PZ |
1902 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
1903 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 1904 | { |
f0f59a00 | 1905 | i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
1906 | uint32_t val = I915_READ(reg); |
1907 | ||
0e32b39c | 1908 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
ad80a810 | 1909 | val |= TRANS_DDI_PORT_NONE; |
8d9ddbcb | 1910 | I915_WRITE(reg, val); |
72662e10 ED |
1911 | } |
1912 | ||
bcbc889b PZ |
1913 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
1914 | { | |
1915 | struct drm_device *dev = intel_connector->base.dev; | |
1916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1917 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
1918 | int type = intel_connector->base.connector_type; | |
1919 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
1920 | enum pipe pipe = 0; | |
1921 | enum transcoder cpu_transcoder; | |
882244a3 | 1922 | enum intel_display_power_domain power_domain; |
bcbc889b | 1923 | uint32_t tmp; |
e27daab4 | 1924 | bool ret; |
bcbc889b | 1925 | |
882244a3 | 1926 | power_domain = intel_display_port_power_domain(intel_encoder); |
e27daab4 | 1927 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
882244a3 PZ |
1928 | return false; |
1929 | ||
e27daab4 ID |
1930 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) { |
1931 | ret = false; | |
1932 | goto out; | |
1933 | } | |
bcbc889b PZ |
1934 | |
1935 | if (port == PORT_A) | |
1936 | cpu_transcoder = TRANSCODER_EDP; | |
1937 | else | |
1a240d4d | 1938 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
1939 | |
1940 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1941 | ||
1942 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
1943 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1944 | case TRANS_DDI_MODE_SELECT_DVI: | |
e27daab4 ID |
1945 | ret = type == DRM_MODE_CONNECTOR_HDMIA; |
1946 | break; | |
bcbc889b PZ |
1947 | |
1948 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
e27daab4 ID |
1949 | ret = type == DRM_MODE_CONNECTOR_eDP || |
1950 | type == DRM_MODE_CONNECTOR_DisplayPort; | |
1951 | break; | |
1952 | ||
0e32b39c DA |
1953 | case TRANS_DDI_MODE_SELECT_DP_MST: |
1954 | /* if the transcoder is in MST state then | |
1955 | * connector isn't connected */ | |
e27daab4 ID |
1956 | ret = false; |
1957 | break; | |
bcbc889b PZ |
1958 | |
1959 | case TRANS_DDI_MODE_SELECT_FDI: | |
e27daab4 ID |
1960 | ret = type == DRM_MODE_CONNECTOR_VGA; |
1961 | break; | |
bcbc889b PZ |
1962 | |
1963 | default: | |
e27daab4 ID |
1964 | ret = false; |
1965 | break; | |
bcbc889b | 1966 | } |
e27daab4 ID |
1967 | |
1968 | out: | |
1969 | intel_display_power_put(dev_priv, power_domain); | |
1970 | ||
1971 | return ret; | |
bcbc889b PZ |
1972 | } |
1973 | ||
85234cdc DV |
1974 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
1975 | enum pipe *pipe) | |
1976 | { | |
1977 | struct drm_device *dev = encoder->base.dev; | |
1978 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 1979 | enum port port = intel_ddi_get_encoder_port(encoder); |
6d129bea | 1980 | enum intel_display_power_domain power_domain; |
85234cdc DV |
1981 | u32 tmp; |
1982 | int i; | |
e27daab4 | 1983 | bool ret; |
85234cdc | 1984 | |
6d129bea | 1985 | power_domain = intel_display_port_power_domain(encoder); |
e27daab4 | 1986 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
1987 | return false; |
1988 | ||
e27daab4 ID |
1989 | ret = false; |
1990 | ||
fe43d3f5 | 1991 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
1992 | |
1993 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
e27daab4 | 1994 | goto out; |
85234cdc | 1995 | |
ad80a810 PZ |
1996 | if (port == PORT_A) { |
1997 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 1998 | |
ad80a810 PZ |
1999 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
2000 | case TRANS_DDI_EDP_INPUT_A_ON: | |
2001 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
2002 | *pipe = PIPE_A; | |
2003 | break; | |
2004 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
2005 | *pipe = PIPE_B; | |
2006 | break; | |
2007 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
2008 | *pipe = PIPE_C; | |
2009 | break; | |
2010 | } | |
2011 | ||
e27daab4 | 2012 | ret = true; |
ad80a810 | 2013 | |
e27daab4 ID |
2014 | goto out; |
2015 | } | |
0e32b39c | 2016 | |
e27daab4 ID |
2017 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { |
2018 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
2019 | ||
2020 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { | |
2021 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == | |
2022 | TRANS_DDI_MODE_SELECT_DP_MST) | |
2023 | goto out; | |
2024 | ||
2025 | *pipe = i; | |
2026 | ret = true; | |
2027 | ||
2028 | goto out; | |
85234cdc DV |
2029 | } |
2030 | } | |
2031 | ||
84f44ce7 | 2032 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 2033 | |
e27daab4 ID |
2034 | out: |
2035 | intel_display_power_put(dev_priv, power_domain); | |
2036 | ||
2037 | return ret; | |
85234cdc DV |
2038 | } |
2039 | ||
fc914639 PZ |
2040 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
2041 | { | |
2042 | struct drm_crtc *crtc = &intel_crtc->base; | |
7d4aefd0 SS |
2043 | struct drm_device *dev = crtc->dev; |
2044 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fc914639 PZ |
2045 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
2046 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
6e3c9717 | 2047 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
fc914639 | 2048 | |
bb523fc0 PZ |
2049 | if (cpu_transcoder != TRANSCODER_EDP) |
2050 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
2051 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
2052 | } |
2053 | ||
2054 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
2055 | { | |
2056 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
6e3c9717 | 2057 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
fc914639 | 2058 | |
bb523fc0 PZ |
2059 | if (cpu_transcoder != TRANSCODER_EDP) |
2060 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
2061 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
2062 | } |
2063 | ||
78ab0bae VS |
2064 | static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv, |
2065 | u32 level, enum port port, int type) | |
f8896f5d | 2066 | { |
f8896f5d DW |
2067 | const struct ddi_buf_trans *ddi_translations; |
2068 | uint8_t iboost; | |
75067dde | 2069 | uint8_t dp_iboost, hdmi_iboost; |
f8896f5d DW |
2070 | int n_entries; |
2071 | u32 reg; | |
2072 | ||
75067dde AK |
2073 | /* VBT may override standard boost values */ |
2074 | dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; | |
2075 | hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; | |
2076 | ||
f8896f5d | 2077 | if (type == INTEL_OUTPUT_DISPLAYPORT) { |
75067dde AK |
2078 | if (dp_iboost) { |
2079 | iboost = dp_iboost; | |
2080 | } else { | |
78ab0bae | 2081 | ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries); |
e4d4c05b | 2082 | iboost = ddi_translations[level].i_boost; |
75067dde | 2083 | } |
f8896f5d | 2084 | } else if (type == INTEL_OUTPUT_EDP) { |
75067dde AK |
2085 | if (dp_iboost) { |
2086 | iboost = dp_iboost; | |
2087 | } else { | |
78ab0bae | 2088 | ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries); |
10afa0b6 VS |
2089 | |
2090 | if (WARN_ON(port != PORT_A && | |
2091 | port != PORT_E && n_entries > 9)) | |
2092 | n_entries = 9; | |
2093 | ||
e4d4c05b | 2094 | iboost = ddi_translations[level].i_boost; |
75067dde | 2095 | } |
f8896f5d | 2096 | } else if (type == INTEL_OUTPUT_HDMI) { |
75067dde AK |
2097 | if (hdmi_iboost) { |
2098 | iboost = hdmi_iboost; | |
2099 | } else { | |
78ab0bae | 2100 | ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries); |
e4d4c05b | 2101 | iboost = ddi_translations[level].i_boost; |
75067dde | 2102 | } |
f8896f5d DW |
2103 | } else { |
2104 | return; | |
2105 | } | |
2106 | ||
2107 | /* Make sure that the requested I_boost is valid */ | |
2108 | if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { | |
2109 | DRM_ERROR("Invalid I_boost value %u\n", iboost); | |
2110 | return; | |
2111 | } | |
2112 | ||
2113 | reg = I915_READ(DISPIO_CR_TX_BMU_CR0); | |
2114 | reg &= ~BALANCE_LEG_MASK(port); | |
2115 | reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port)); | |
2116 | ||
2117 | if (iboost) | |
2118 | reg |= iboost << BALANCE_LEG_SHIFT(port); | |
2119 | else | |
2120 | reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port); | |
2121 | ||
2122 | I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg); | |
2123 | } | |
2124 | ||
78ab0bae VS |
2125 | static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, |
2126 | u32 level, enum port port, int type) | |
96fb9f9b | 2127 | { |
96fb9f9b VK |
2128 | const struct bxt_ddi_buf_trans *ddi_translations; |
2129 | u32 n_entries, i; | |
2130 | uint32_t val; | |
2131 | ||
d9d7000d SJ |
2132 | if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) { |
2133 | n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); | |
2134 | ddi_translations = bxt_ddi_translations_edp; | |
2135 | } else if (type == INTEL_OUTPUT_DISPLAYPORT | |
2136 | || type == INTEL_OUTPUT_EDP) { | |
96fb9f9b VK |
2137 | n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); |
2138 | ddi_translations = bxt_ddi_translations_dp; | |
2139 | } else if (type == INTEL_OUTPUT_HDMI) { | |
2140 | n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); | |
2141 | ddi_translations = bxt_ddi_translations_hdmi; | |
2142 | } else { | |
2143 | DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", | |
2144 | type); | |
2145 | return; | |
2146 | } | |
2147 | ||
2148 | /* Check if default value has to be used */ | |
2149 | if (level >= n_entries || | |
2150 | (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { | |
2151 | for (i = 0; i < n_entries; i++) { | |
2152 | if (ddi_translations[i].default_index) { | |
2153 | level = i; | |
2154 | break; | |
2155 | } | |
2156 | } | |
2157 | } | |
2158 | ||
2159 | /* | |
2160 | * While we write to the group register to program all lanes at once we | |
2161 | * can read only lane registers and we pick lanes 0/1 for that. | |
2162 | */ | |
2163 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); | |
2164 | val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); | |
2165 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); | |
2166 | ||
2167 | val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); | |
2168 | val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); | |
2169 | val |= ddi_translations[level].margin << MARGIN_000_SHIFT | | |
2170 | ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; | |
2171 | I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); | |
2172 | ||
2173 | val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); | |
9c58a049 | 2174 | val &= ~SCALE_DCOMP_METHOD; |
96fb9f9b | 2175 | if (ddi_translations[level].enable) |
9c58a049 SJ |
2176 | val |= SCALE_DCOMP_METHOD; |
2177 | ||
2178 | if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) | |
2179 | DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); | |
2180 | ||
96fb9f9b VK |
2181 | I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); |
2182 | ||
2183 | val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); | |
2184 | val &= ~DE_EMPHASIS; | |
2185 | val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; | |
2186 | I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); | |
2187 | ||
2188 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); | |
2189 | val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; | |
2190 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); | |
2191 | } | |
2192 | ||
f8896f5d DW |
2193 | static uint32_t translate_signal_level(int signal_levels) |
2194 | { | |
2195 | uint32_t level; | |
2196 | ||
2197 | switch (signal_levels) { | |
2198 | default: | |
2199 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n", | |
2200 | signal_levels); | |
2201 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
2202 | level = 0; | |
2203 | break; | |
2204 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
2205 | level = 1; | |
2206 | break; | |
2207 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
2208 | level = 2; | |
2209 | break; | |
2210 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: | |
2211 | level = 3; | |
2212 | break; | |
2213 | ||
2214 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
2215 | level = 4; | |
2216 | break; | |
2217 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
2218 | level = 5; | |
2219 | break; | |
2220 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
2221 | level = 6; | |
2222 | break; | |
2223 | ||
2224 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
2225 | level = 7; | |
2226 | break; | |
2227 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
2228 | level = 8; | |
2229 | break; | |
2230 | ||
2231 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
2232 | level = 9; | |
2233 | break; | |
2234 | } | |
2235 | ||
2236 | return level; | |
2237 | } | |
2238 | ||
2239 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp) | |
2240 | { | |
2241 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
78ab0bae | 2242 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); |
f8896f5d DW |
2243 | struct intel_encoder *encoder = &dport->base; |
2244 | uint8_t train_set = intel_dp->train_set[0]; | |
2245 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
2246 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2247 | enum port port = dport->port; | |
2248 | uint32_t level; | |
2249 | ||
2250 | level = translate_signal_level(signal_levels); | |
2251 | ||
78ab0bae VS |
2252 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
2253 | skl_ddi_set_iboost(dev_priv, level, port, encoder->type); | |
2254 | else if (IS_BROXTON(dev_priv)) | |
2255 | bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); | |
f8896f5d DW |
2256 | |
2257 | return DDI_BUF_TRANS_SELECT(level); | |
2258 | } | |
2259 | ||
e404ba8d VS |
2260 | void intel_ddi_clk_select(struct intel_encoder *encoder, |
2261 | const struct intel_crtc_state *pipe_config) | |
6441ab5f | 2262 | { |
e404ba8d VS |
2263 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2264 | enum port port = intel_ddi_get_encoder_port(encoder); | |
6441ab5f | 2265 | |
e404ba8d VS |
2266 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
2267 | uint32_t dpll = pipe_config->ddi_pll_sel; | |
efa80add S |
2268 | uint32_t val; |
2269 | ||
5416d871 DL |
2270 | /* |
2271 | * DPLL0 is used for eDP and is the only "private" DPLL (as | |
2272 | * opposed to shared) on SKL | |
2273 | */ | |
e404ba8d | 2274 | if (encoder->type == INTEL_OUTPUT_EDP) { |
5416d871 DL |
2275 | WARN_ON(dpll != SKL_DPLL0); |
2276 | ||
2277 | val = I915_READ(DPLL_CTRL1); | |
2278 | ||
2279 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | | |
2280 | DPLL_CTRL1_SSC(dpll) | | |
71cd8423 | 2281 | DPLL_CTRL1_LINK_RATE_MASK(dpll)); |
e404ba8d | 2282 | val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6); |
5416d871 DL |
2283 | |
2284 | I915_WRITE(DPLL_CTRL1, val); | |
2285 | POSTING_READ(DPLL_CTRL1); | |
2286 | } | |
2287 | ||
2288 | /* DDI -> PLL mapping */ | |
efa80add S |
2289 | val = I915_READ(DPLL_CTRL2); |
2290 | ||
2291 | val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | | |
2292 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); | |
2293 | val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | | |
2294 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); | |
2295 | ||
2296 | I915_WRITE(DPLL_CTRL2, val); | |
5416d871 | 2297 | |
e404ba8d VS |
2298 | } else if (INTEL_INFO(dev_priv)->gen < 9) { |
2299 | WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE); | |
2300 | I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel); | |
efa80add | 2301 | } |
e404ba8d VS |
2302 | } |
2303 | ||
2304 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) | |
2305 | { | |
2306 | struct drm_encoder *encoder = &intel_encoder->base; | |
6a7e4f99 | 2307 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
e404ba8d VS |
2308 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
2309 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
2310 | int type = intel_encoder->type; | |
6a7e4f99 VS |
2311 | |
2312 | intel_prepare_ddi_buffer(intel_encoder); | |
e404ba8d VS |
2313 | |
2314 | if (type == INTEL_OUTPUT_EDP) { | |
2315 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2316 | intel_edp_panel_on(intel_dp); | |
2317 | } | |
2318 | ||
2319 | intel_ddi_clk_select(intel_encoder, crtc->config); | |
c19b0669 | 2320 | |
82a4d9c0 | 2321 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 | 2322 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
30cf6db8 | 2323 | |
901c2daf VS |
2324 | intel_dp_set_link_params(intel_dp, crtc->config); |
2325 | ||
44905a27 | 2326 | intel_ddi_init_dp_buf_reg(intel_encoder); |
c19b0669 PZ |
2327 | |
2328 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
2329 | intel_dp_start_link_train(intel_dp); | |
6a7e4f99 | 2330 | if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9) |
3ab9c637 | 2331 | intel_dp_stop_link_train(intel_dp); |
30cf6db8 DV |
2332 | } else if (type == INTEL_OUTPUT_HDMI) { |
2333 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
2334 | ||
2335 | intel_hdmi->set_infoframes(encoder, | |
6e3c9717 ACO |
2336 | crtc->config->has_hdmi_sink, |
2337 | &crtc->config->base.adjusted_mode); | |
c19b0669 | 2338 | } |
6441ab5f PZ |
2339 | } |
2340 | ||
00c09d70 | 2341 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
2342 | { |
2343 | struct drm_encoder *encoder = &intel_encoder->base; | |
efa80add S |
2344 | struct drm_device *dev = encoder->dev; |
2345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6441ab5f | 2346 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 2347 | int type = intel_encoder->type; |
2886e93f | 2348 | uint32_t val; |
a836bdf9 | 2349 | bool wait = false; |
2886e93f PZ |
2350 | |
2351 | val = I915_READ(DDI_BUF_CTL(port)); | |
2352 | if (val & DDI_BUF_CTL_ENABLE) { | |
2353 | val &= ~DDI_BUF_CTL_ENABLE; | |
2354 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 2355 | wait = true; |
2886e93f | 2356 | } |
6441ab5f | 2357 | |
a836bdf9 PZ |
2358 | val = I915_READ(DP_TP_CTL(port)); |
2359 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
2360 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2361 | I915_WRITE(DP_TP_CTL(port), val); | |
2362 | ||
2363 | if (wait) | |
2364 | intel_wait_ddi_buf_idle(dev_priv, port); | |
2365 | ||
76bb80ed | 2366 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
82a4d9c0 | 2367 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
76bb80ed | 2368 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
24f3e092 | 2369 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 2370 | intel_edp_panel_off(intel_dp); |
82a4d9c0 PZ |
2371 | } |
2372 | ||
ef11bdb3 | 2373 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
efa80add S |
2374 | I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | |
2375 | DPLL_CTRL2_DDI_CLK_OFF(port))); | |
1ab23380 | 2376 | else if (INTEL_INFO(dev)->gen < 9) |
efa80add | 2377 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
6441ab5f PZ |
2378 | } |
2379 | ||
00c09d70 | 2380 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 2381 | { |
6547fef8 | 2382 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
2383 | struct drm_crtc *crtc = encoder->crtc; |
2384 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6547fef8 | 2385 | struct drm_device *dev = encoder->dev; |
72662e10 | 2386 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
2387 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
2388 | int type = intel_encoder->type; | |
72662e10 | 2389 | |
6547fef8 | 2390 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
2391 | struct intel_digital_port *intel_dig_port = |
2392 | enc_to_dig_port(encoder); | |
2393 | ||
6547fef8 PZ |
2394 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
2395 | * are ignored so nothing special needs to be done besides | |
2396 | * enabling the port. | |
2397 | */ | |
876a8cdf | 2398 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
2399 | intel_dig_port->saved_port_bits | |
2400 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
2401 | } else if (type == INTEL_OUTPUT_EDP) { |
2402 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2403 | ||
23f08d83 | 2404 | if (port == PORT_A && INTEL_INFO(dev)->gen < 9) |
3ab9c637 ID |
2405 | intel_dp_stop_link_train(intel_dp); |
2406 | ||
4be73780 | 2407 | intel_edp_backlight_on(intel_dp); |
0bc12bcb | 2408 | intel_psr_enable(intel_dp); |
c395578e | 2409 | intel_edp_drrs_enable(intel_dp); |
6547fef8 | 2410 | } |
7b9f35a6 | 2411 | |
6e3c9717 | 2412 | if (intel_crtc->config->has_audio) { |
d45a0bf5 | 2413 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
69bfe1a9 | 2414 | intel_audio_codec_enable(intel_encoder); |
7b9f35a6 | 2415 | } |
5ab432ef DV |
2416 | } |
2417 | ||
00c09d70 | 2418 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 2419 | { |
d6c50ff8 | 2420 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
2421 | struct drm_crtc *crtc = encoder->crtc; |
2422 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d6c50ff8 | 2423 | int type = intel_encoder->type; |
7b9f35a6 WX |
2424 | struct drm_device *dev = encoder->dev; |
2425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6c50ff8 | 2426 | |
6e3c9717 | 2427 | if (intel_crtc->config->has_audio) { |
69bfe1a9 | 2428 | intel_audio_codec_disable(intel_encoder); |
d45a0bf5 PZ |
2429 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
2430 | } | |
2831d842 | 2431 | |
d6c50ff8 PZ |
2432 | if (type == INTEL_OUTPUT_EDP) { |
2433 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2434 | ||
c395578e | 2435 | intel_edp_drrs_disable(intel_dp); |
0bc12bcb | 2436 | intel_psr_disable(intel_dp); |
4be73780 | 2437 | intel_edp_backlight_off(intel_dp); |
d6c50ff8 | 2438 | } |
72662e10 | 2439 | } |
79f689aa | 2440 | |
00490c22 | 2441 | static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, |
e0b01be4 DV |
2442 | struct intel_shared_dpll *pll) |
2443 | { | |
3e369b76 | 2444 | I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); |
e0b01be4 DV |
2445 | POSTING_READ(WRPLL_CTL(pll->id)); |
2446 | udelay(20); | |
2447 | } | |
2448 | ||
00490c22 | 2449 | static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, |
12030431 | 2450 | struct intel_shared_dpll *pll) |
00490c22 ML |
2451 | { |
2452 | I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); | |
2453 | POSTING_READ(SPLL_CTL); | |
2454 | udelay(20); | |
2455 | } | |
2456 | ||
2457 | static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, | |
2458 | struct intel_shared_dpll *pll) | |
12030431 DV |
2459 | { |
2460 | uint32_t val; | |
2461 | ||
2462 | val = I915_READ(WRPLL_CTL(pll->id)); | |
12030431 DV |
2463 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); |
2464 | POSTING_READ(WRPLL_CTL(pll->id)); | |
2465 | } | |
2466 | ||
00490c22 ML |
2467 | static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, |
2468 | struct intel_shared_dpll *pll) | |
2469 | { | |
2470 | uint32_t val; | |
2471 | ||
2472 | val = I915_READ(SPLL_CTL); | |
2473 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | |
2474 | POSTING_READ(SPLL_CTL); | |
2475 | } | |
2476 | ||
2477 | static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, | |
2478 | struct intel_shared_dpll *pll, | |
2479 | struct intel_dpll_hw_state *hw_state) | |
d452c5b6 DV |
2480 | { |
2481 | uint32_t val; | |
2482 | ||
e27daab4 | 2483 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
d452c5b6 DV |
2484 | return false; |
2485 | ||
2486 | val = I915_READ(WRPLL_CTL(pll->id)); | |
2487 | hw_state->wrpll = val; | |
2488 | ||
e27daab4 ID |
2489 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
2490 | ||
d452c5b6 DV |
2491 | return val & WRPLL_PLL_ENABLE; |
2492 | } | |
2493 | ||
00490c22 ML |
2494 | static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, |
2495 | struct intel_shared_dpll *pll, | |
2496 | struct intel_dpll_hw_state *hw_state) | |
2497 | { | |
2498 | uint32_t val; | |
2499 | ||
e27daab4 | 2500 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
00490c22 ML |
2501 | return false; |
2502 | ||
2503 | val = I915_READ(SPLL_CTL); | |
2504 | hw_state->spll = val; | |
2505 | ||
e27daab4 ID |
2506 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
2507 | ||
00490c22 ML |
2508 | return val & SPLL_PLL_ENABLE; |
2509 | } | |
2510 | ||
2511 | ||
ca1381b5 | 2512 | static const char * const hsw_ddi_pll_names[] = { |
9cd86933 DV |
2513 | "WRPLL 1", |
2514 | "WRPLL 2", | |
00490c22 | 2515 | "SPLL" |
9cd86933 DV |
2516 | }; |
2517 | ||
143b307c | 2518 | static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) |
79f689aa | 2519 | { |
9cd86933 DV |
2520 | int i; |
2521 | ||
00490c22 | 2522 | dev_priv->num_shared_dpll = 3; |
9cd86933 | 2523 | |
00490c22 | 2524 | for (i = 0; i < 2; i++) { |
9cd86933 DV |
2525 | dev_priv->shared_dplls[i].id = i; |
2526 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; | |
00490c22 ML |
2527 | dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable; |
2528 | dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable; | |
d452c5b6 | 2529 | dev_priv->shared_dplls[i].get_hw_state = |
00490c22 | 2530 | hsw_ddi_wrpll_get_hw_state; |
9cd86933 | 2531 | } |
00490c22 ML |
2532 | |
2533 | /* SPLL is special, but needs to be initialized anyway.. */ | |
2534 | dev_priv->shared_dplls[i].id = i; | |
2535 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; | |
2536 | dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable; | |
2537 | dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable; | |
2538 | dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state; | |
2539 | ||
143b307c DL |
2540 | } |
2541 | ||
d1a2dc78 S |
2542 | static const char * const skl_ddi_pll_names[] = { |
2543 | "DPLL 1", | |
2544 | "DPLL 2", | |
2545 | "DPLL 3", | |
2546 | }; | |
2547 | ||
2548 | struct skl_dpll_regs { | |
f0f59a00 | 2549 | i915_reg_t ctl, cfgcr1, cfgcr2; |
d1a2dc78 S |
2550 | }; |
2551 | ||
2552 | /* this array is indexed by the *shared* pll id */ | |
2553 | static const struct skl_dpll_regs skl_dpll_regs[3] = { | |
2554 | { | |
2555 | /* DPLL 1 */ | |
2556 | .ctl = LCPLL2_CTL, | |
923c1241 VS |
2557 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), |
2558 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), | |
d1a2dc78 S |
2559 | }, |
2560 | { | |
2561 | /* DPLL 2 */ | |
01403de3 | 2562 | .ctl = WRPLL_CTL(0), |
923c1241 VS |
2563 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), |
2564 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), | |
d1a2dc78 S |
2565 | }, |
2566 | { | |
2567 | /* DPLL 3 */ | |
01403de3 | 2568 | .ctl = WRPLL_CTL(1), |
923c1241 VS |
2569 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), |
2570 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), | |
d1a2dc78 S |
2571 | }, |
2572 | }; | |
2573 | ||
2574 | static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, | |
2575 | struct intel_shared_dpll *pll) | |
2576 | { | |
2577 | uint32_t val; | |
2578 | unsigned int dpll; | |
2579 | const struct skl_dpll_regs *regs = skl_dpll_regs; | |
2580 | ||
2581 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ | |
2582 | dpll = pll->id + 1; | |
2583 | ||
2584 | val = I915_READ(DPLL_CTRL1); | |
2585 | ||
2586 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | | |
71cd8423 | 2587 | DPLL_CTRL1_LINK_RATE_MASK(dpll)); |
d1a2dc78 S |
2588 | val |= pll->config.hw_state.ctrl1 << (dpll * 6); |
2589 | ||
2590 | I915_WRITE(DPLL_CTRL1, val); | |
2591 | POSTING_READ(DPLL_CTRL1); | |
2592 | ||
2593 | I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); | |
2594 | I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); | |
2595 | POSTING_READ(regs[pll->id].cfgcr1); | |
2596 | POSTING_READ(regs[pll->id].cfgcr2); | |
2597 | ||
2598 | /* the enable bit is always bit 31 */ | |
2599 | I915_WRITE(regs[pll->id].ctl, | |
2600 | I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); | |
2601 | ||
2602 | if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) | |
2603 | DRM_ERROR("DPLL %d not locked\n", dpll); | |
2604 | } | |
2605 | ||
2606 | static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, | |
2607 | struct intel_shared_dpll *pll) | |
2608 | { | |
2609 | const struct skl_dpll_regs *regs = skl_dpll_regs; | |
2610 | ||
2611 | /* the enable bit is always bit 31 */ | |
2612 | I915_WRITE(regs[pll->id].ctl, | |
2613 | I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); | |
2614 | POSTING_READ(regs[pll->id].ctl); | |
2615 | } | |
2616 | ||
2617 | static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, | |
2618 | struct intel_shared_dpll *pll, | |
2619 | struct intel_dpll_hw_state *hw_state) | |
2620 | { | |
2621 | uint32_t val; | |
2622 | unsigned int dpll; | |
2623 | const struct skl_dpll_regs *regs = skl_dpll_regs; | |
e27daab4 | 2624 | bool ret; |
d1a2dc78 | 2625 | |
e27daab4 | 2626 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
d1a2dc78 S |
2627 | return false; |
2628 | ||
e27daab4 ID |
2629 | ret = false; |
2630 | ||
d1a2dc78 S |
2631 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ |
2632 | dpll = pll->id + 1; | |
2633 | ||
2634 | val = I915_READ(regs[pll->id].ctl); | |
2635 | if (!(val & LCPLL_PLL_ENABLE)) | |
e27daab4 | 2636 | goto out; |
d1a2dc78 S |
2637 | |
2638 | val = I915_READ(DPLL_CTRL1); | |
2639 | hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; | |
2640 | ||
2641 | /* avoid reading back stale values if HDMI mode is not enabled */ | |
2642 | if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { | |
2643 | hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); | |
2644 | hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); | |
2645 | } | |
e27daab4 | 2646 | ret = true; |
d1a2dc78 | 2647 | |
e27daab4 ID |
2648 | out: |
2649 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
2650 | ||
2651 | return ret; | |
d1a2dc78 S |
2652 | } |
2653 | ||
2654 | static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) | |
2655 | { | |
2656 | int i; | |
2657 | ||
2658 | dev_priv->num_shared_dpll = 3; | |
2659 | ||
2660 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
2661 | dev_priv->shared_dplls[i].id = i; | |
2662 | dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; | |
2663 | dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; | |
2664 | dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; | |
2665 | dev_priv->shared_dplls[i].get_hw_state = | |
2666 | skl_ddi_pll_get_hw_state; | |
2667 | } | |
2668 | } | |
2669 | ||
5c6706e5 VK |
2670 | static void broxton_phy_init(struct drm_i915_private *dev_priv, |
2671 | enum dpio_phy phy) | |
2672 | { | |
2673 | enum port port; | |
2674 | uint32_t val; | |
2675 | ||
2676 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
2677 | val |= GT_DISPLAY_POWER_ON(phy); | |
2678 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); | |
2679 | ||
2680 | /* Considering 10ms timeout until BSpec is updated */ | |
2681 | if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) | |
2682 | DRM_ERROR("timeout during PHY%d power on\n", phy); | |
2683 | ||
2684 | for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); | |
2685 | port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { | |
2686 | int lane; | |
2687 | ||
2688 | for (lane = 0; lane < 4; lane++) { | |
2689 | val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); | |
2690 | /* | |
2691 | * Note that on CHV this flag is called UPAR, but has | |
2692 | * the same function. | |
2693 | */ | |
2694 | val &= ~LATENCY_OPTIM; | |
2695 | if (lane != 1) | |
2696 | val |= LATENCY_OPTIM; | |
2697 | ||
2698 | I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); | |
2699 | } | |
2700 | } | |
2701 | ||
2702 | /* Program PLL Rcomp code offset */ | |
2703 | val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); | |
2704 | val &= ~IREF0RC_OFFSET_MASK; | |
2705 | val |= 0xE4 << IREF0RC_OFFSET_SHIFT; | |
2706 | I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); | |
2707 | ||
2708 | val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); | |
2709 | val &= ~IREF1RC_OFFSET_MASK; | |
2710 | val |= 0xE4 << IREF1RC_OFFSET_SHIFT; | |
2711 | I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); | |
2712 | ||
2713 | /* Program power gating */ | |
2714 | val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); | |
2715 | val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | | |
2716 | SUS_CLK_CONFIG; | |
2717 | I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); | |
2718 | ||
2719 | if (phy == DPIO_PHY0) { | |
2720 | val = I915_READ(BXT_PORT_CL2CM_DW6_BC); | |
2721 | val |= DW6_OLDO_DYN_PWR_DOWN_EN; | |
2722 | I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); | |
2723 | } | |
2724 | ||
2725 | val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); | |
2726 | val &= ~OCL2_LDOFUSE_PWR_DIS; | |
2727 | /* | |
2728 | * On PHY1 disable power on the second channel, since no port is | |
2729 | * connected there. On PHY0 both channels have a port, so leave it | |
2730 | * enabled. | |
2731 | * TODO: port C is only connected on BXT-P, so on BXT0/1 we should | |
2732 | * power down the second channel on PHY0 as well. | |
2733 | */ | |
2734 | if (phy == DPIO_PHY1) | |
2735 | val |= OCL2_LDOFUSE_PWR_DIS; | |
2736 | I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); | |
2737 | ||
2738 | if (phy == DPIO_PHY0) { | |
2739 | uint32_t grc_code; | |
2740 | /* | |
2741 | * PHY0 isn't connected to an RCOMP resistor so copy over | |
2742 | * the corresponding calibrated value from PHY1, and disable | |
2743 | * the automatic calibration on PHY0. | |
2744 | */ | |
2745 | if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, | |
2746 | 10)) | |
2747 | DRM_ERROR("timeout waiting for PHY1 GRC\n"); | |
2748 | ||
2749 | val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); | |
2750 | val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; | |
2751 | grc_code = val << GRC_CODE_FAST_SHIFT | | |
2752 | val << GRC_CODE_SLOW_SHIFT | | |
2753 | val; | |
2754 | I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); | |
2755 | ||
2756 | val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); | |
2757 | val |= GRC_DIS | GRC_RDY_OVRD; | |
2758 | I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); | |
2759 | } | |
2760 | ||
2761 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); | |
2762 | val |= COMMON_RESET_DIS; | |
2763 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
2764 | } | |
2765 | ||
2766 | void broxton_ddi_phy_init(struct drm_device *dev) | |
2767 | { | |
2768 | /* Enable PHY1 first since it provides Rcomp for PHY0 */ | |
2769 | broxton_phy_init(dev->dev_private, DPIO_PHY1); | |
2770 | broxton_phy_init(dev->dev_private, DPIO_PHY0); | |
2771 | } | |
2772 | ||
2773 | static void broxton_phy_uninit(struct drm_i915_private *dev_priv, | |
2774 | enum dpio_phy phy) | |
2775 | { | |
2776 | uint32_t val; | |
2777 | ||
2778 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); | |
2779 | val &= ~COMMON_RESET_DIS; | |
2780 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
2781 | } | |
2782 | ||
2783 | void broxton_ddi_phy_uninit(struct drm_device *dev) | |
2784 | { | |
2785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2786 | ||
2787 | broxton_phy_uninit(dev_priv, DPIO_PHY1); | |
2788 | broxton_phy_uninit(dev_priv, DPIO_PHY0); | |
2789 | ||
2790 | /* FIXME: do this in broxton_phy_uninit per phy */ | |
2791 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); | |
2792 | } | |
2793 | ||
dfb82408 S |
2794 | static const char * const bxt_ddi_pll_names[] = { |
2795 | "PORT PLL A", | |
2796 | "PORT PLL B", | |
2797 | "PORT PLL C", | |
2798 | }; | |
2799 | ||
2800 | static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, | |
2801 | struct intel_shared_dpll *pll) | |
2802 | { | |
2803 | uint32_t temp; | |
2804 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ | |
2805 | ||
2806 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
2807 | temp &= ~PORT_PLL_REF_SEL; | |
2808 | /* Non-SSC reference */ | |
2809 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); | |
2810 | ||
2811 | /* Disable 10 bit clock */ | |
2812 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); | |
2813 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; | |
2814 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); | |
2815 | ||
2816 | /* Write P1 & P2 */ | |
2817 | temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); | |
2818 | temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); | |
2819 | temp |= pll->config.hw_state.ebb0; | |
2820 | I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); | |
2821 | ||
2822 | /* Write M2 integer */ | |
2823 | temp = I915_READ(BXT_PORT_PLL(port, 0)); | |
2824 | temp &= ~PORT_PLL_M2_MASK; | |
2825 | temp |= pll->config.hw_state.pll0; | |
2826 | I915_WRITE(BXT_PORT_PLL(port, 0), temp); | |
2827 | ||
2828 | /* Write N */ | |
2829 | temp = I915_READ(BXT_PORT_PLL(port, 1)); | |
2830 | temp &= ~PORT_PLL_N_MASK; | |
2831 | temp |= pll->config.hw_state.pll1; | |
2832 | I915_WRITE(BXT_PORT_PLL(port, 1), temp); | |
2833 | ||
2834 | /* Write M2 fraction */ | |
2835 | temp = I915_READ(BXT_PORT_PLL(port, 2)); | |
2836 | temp &= ~PORT_PLL_M2_FRAC_MASK; | |
2837 | temp |= pll->config.hw_state.pll2; | |
2838 | I915_WRITE(BXT_PORT_PLL(port, 2), temp); | |
2839 | ||
2840 | /* Write M2 fraction enable */ | |
2841 | temp = I915_READ(BXT_PORT_PLL(port, 3)); | |
2842 | temp &= ~PORT_PLL_M2_FRAC_ENABLE; | |
2843 | temp |= pll->config.hw_state.pll3; | |
2844 | I915_WRITE(BXT_PORT_PLL(port, 3), temp); | |
2845 | ||
2846 | /* Write coeff */ | |
2847 | temp = I915_READ(BXT_PORT_PLL(port, 6)); | |
2848 | temp &= ~PORT_PLL_PROP_COEFF_MASK; | |
2849 | temp &= ~PORT_PLL_INT_COEFF_MASK; | |
2850 | temp &= ~PORT_PLL_GAIN_CTL_MASK; | |
2851 | temp |= pll->config.hw_state.pll6; | |
2852 | I915_WRITE(BXT_PORT_PLL(port, 6), temp); | |
2853 | ||
2854 | /* Write calibration val */ | |
2855 | temp = I915_READ(BXT_PORT_PLL(port, 8)); | |
2856 | temp &= ~PORT_PLL_TARGET_CNT_MASK; | |
2857 | temp |= pll->config.hw_state.pll8; | |
2858 | I915_WRITE(BXT_PORT_PLL(port, 8), temp); | |
2859 | ||
b6dc71f3 VK |
2860 | temp = I915_READ(BXT_PORT_PLL(port, 9)); |
2861 | temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; | |
05712c15 | 2862 | temp |= pll->config.hw_state.pll9; |
b6dc71f3 VK |
2863 | I915_WRITE(BXT_PORT_PLL(port, 9), temp); |
2864 | ||
2865 | temp = I915_READ(BXT_PORT_PLL(port, 10)); | |
2866 | temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; | |
2867 | temp &= ~PORT_PLL_DCO_AMP_MASK; | |
2868 | temp |= pll->config.hw_state.pll10; | |
2869 | I915_WRITE(BXT_PORT_PLL(port, 10), temp); | |
dfb82408 S |
2870 | |
2871 | /* Recalibrate with new settings */ | |
2872 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); | |
2873 | temp |= PORT_PLL_RECALIBRATE; | |
2874 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); | |
05712c15 ID |
2875 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; |
2876 | temp |= pll->config.hw_state.ebb4; | |
dfb82408 S |
2877 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); |
2878 | ||
2879 | /* Enable PLL */ | |
2880 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
2881 | temp |= PORT_PLL_ENABLE; | |
2882 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); | |
2883 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); | |
2884 | ||
2885 | if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & | |
2886 | PORT_PLL_LOCK), 200)) | |
2887 | DRM_ERROR("PLL %d not locked\n", port); | |
2888 | ||
2889 | /* | |
2890 | * While we write to the group register to program all lanes at once we | |
2891 | * can read only lane registers and we pick lanes 0/1 for that. | |
2892 | */ | |
2893 | temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); | |
2894 | temp &= ~LANE_STAGGER_MASK; | |
2895 | temp &= ~LANESTAGGER_STRAP_OVRD; | |
2896 | temp |= pll->config.hw_state.pcsdw12; | |
2897 | I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); | |
2898 | } | |
2899 | ||
2900 | static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, | |
2901 | struct intel_shared_dpll *pll) | |
2902 | { | |
2903 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ | |
2904 | uint32_t temp; | |
2905 | ||
2906 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
2907 | temp &= ~PORT_PLL_ENABLE; | |
2908 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); | |
2909 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); | |
2910 | } | |
2911 | ||
2912 | static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, | |
2913 | struct intel_shared_dpll *pll, | |
2914 | struct intel_dpll_hw_state *hw_state) | |
2915 | { | |
2916 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ | |
2917 | uint32_t val; | |
e27daab4 | 2918 | bool ret; |
dfb82408 | 2919 | |
e27daab4 | 2920 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
dfb82408 S |
2921 | return false; |
2922 | ||
e27daab4 ID |
2923 | ret = false; |
2924 | ||
dfb82408 S |
2925 | val = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
2926 | if (!(val & PORT_PLL_ENABLE)) | |
e27daab4 | 2927 | goto out; |
dfb82408 S |
2928 | |
2929 | hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); | |
793dfa59 ID |
2930 | hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; |
2931 | ||
05712c15 ID |
2932 | hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); |
2933 | hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; | |
2934 | ||
dfb82408 | 2935 | hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); |
793dfa59 ID |
2936 | hw_state->pll0 &= PORT_PLL_M2_MASK; |
2937 | ||
dfb82408 | 2938 | hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); |
793dfa59 ID |
2939 | hw_state->pll1 &= PORT_PLL_N_MASK; |
2940 | ||
dfb82408 | 2941 | hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); |
793dfa59 ID |
2942 | hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; |
2943 | ||
dfb82408 | 2944 | hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); |
793dfa59 ID |
2945 | hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; |
2946 | ||
dfb82408 | 2947 | hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); |
793dfa59 ID |
2948 | hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | |
2949 | PORT_PLL_INT_COEFF_MASK | | |
2950 | PORT_PLL_GAIN_CTL_MASK; | |
2951 | ||
dfb82408 | 2952 | hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); |
793dfa59 ID |
2953 | hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; |
2954 | ||
05712c15 ID |
2955 | hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); |
2956 | hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; | |
2957 | ||
b6dc71f3 | 2958 | hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); |
793dfa59 ID |
2959 | hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | |
2960 | PORT_PLL_DCO_AMP_MASK; | |
2961 | ||
dfb82408 S |
2962 | /* |
2963 | * While we write to the group register to program all lanes at once we | |
2964 | * can read only lane registers. We configure all lanes the same way, so | |
2965 | * here just read out lanes 0/1 and output a note if lanes 2/3 differ. | |
2966 | */ | |
2967 | hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); | |
b5dada82 | 2968 | if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12) |
dfb82408 S |
2969 | DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", |
2970 | hw_state->pcsdw12, | |
2971 | I915_READ(BXT_PORT_PCS_DW12_LN23(port))); | |
793dfa59 | 2972 | hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; |
dfb82408 | 2973 | |
e27daab4 ID |
2974 | ret = true; |
2975 | ||
2976 | out: | |
2977 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
2978 | ||
2979 | return ret; | |
dfb82408 S |
2980 | } |
2981 | ||
2982 | static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) | |
2983 | { | |
2984 | int i; | |
2985 | ||
2986 | dev_priv->num_shared_dpll = 3; | |
2987 | ||
2988 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
2989 | dev_priv->shared_dplls[i].id = i; | |
2990 | dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; | |
2991 | dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; | |
2992 | dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; | |
2993 | dev_priv->shared_dplls[i].get_hw_state = | |
2994 | bxt_ddi_pll_get_hw_state; | |
2995 | } | |
2996 | } | |
2997 | ||
143b307c DL |
2998 | void intel_ddi_pll_init(struct drm_device *dev) |
2999 | { | |
3000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3001 | uint32_t val = I915_READ(LCPLL_CTL); | |
3002 | ||
ef11bdb3 | 3003 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
d1a2dc78 | 3004 | skl_shared_dplls_init(dev_priv); |
dfb82408 S |
3005 | else if (IS_BROXTON(dev)) |
3006 | bxt_shared_dplls_init(dev_priv); | |
d1a2dc78 S |
3007 | else |
3008 | hsw_shared_dplls_init(dev_priv); | |
79f689aa | 3009 | |
ef11bdb3 | 3010 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
d9062ae5 DL |
3011 | int cdclk_freq; |
3012 | ||
3013 | cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5d96d8af | 3014 | dev_priv->skl_boot_cdclk = cdclk_freq; |
c73666f3 SK |
3015 | if (skl_sanitize_cdclk(dev_priv)) |
3016 | DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); | |
2f693e28 DL |
3017 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) |
3018 | DRM_ERROR("LCPLL1 is disabled\n"); | |
f8437dd1 VK |
3019 | } else if (IS_BROXTON(dev)) { |
3020 | broxton_init_cdclk(dev); | |
5c6706e5 | 3021 | broxton_ddi_phy_init(dev); |
121643c2 S |
3022 | } else { |
3023 | /* | |
3024 | * The LCPLL register should be turned on by the BIOS. For now | |
3025 | * let's just check its state and print errors in case | |
3026 | * something is wrong. Don't even try to turn it on. | |
3027 | */ | |
3028 | ||
3029 | if (val & LCPLL_CD_SOURCE_FCLK) | |
3030 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
79f689aa | 3031 | |
121643c2 S |
3032 | if (val & LCPLL_PLL_DISABLE) |
3033 | DRM_ERROR("LCPLL is disabled\n"); | |
3034 | } | |
79f689aa | 3035 | } |
c19b0669 | 3036 | |
ad64217b | 3037 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) |
c19b0669 | 3038 | { |
ad64217b ACO |
3039 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3040 | struct drm_i915_private *dev_priv = | |
3041 | to_i915(intel_dig_port->base.base.dev); | |
174edf1f | 3042 | enum port port = intel_dig_port->port; |
c19b0669 | 3043 | uint32_t val; |
f3e227df | 3044 | bool wait = false; |
c19b0669 PZ |
3045 | |
3046 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
3047 | val = I915_READ(DDI_BUF_CTL(port)); | |
3048 | if (val & DDI_BUF_CTL_ENABLE) { | |
3049 | val &= ~DDI_BUF_CTL_ENABLE; | |
3050 | I915_WRITE(DDI_BUF_CTL(port), val); | |
3051 | wait = true; | |
3052 | } | |
3053 | ||
3054 | val = I915_READ(DP_TP_CTL(port)); | |
3055 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
3056 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
3057 | I915_WRITE(DP_TP_CTL(port), val); | |
3058 | POSTING_READ(DP_TP_CTL(port)); | |
3059 | ||
3060 | if (wait) | |
3061 | intel_wait_ddi_buf_idle(dev_priv, port); | |
3062 | } | |
3063 | ||
0e32b39c | 3064 | val = DP_TP_CTL_ENABLE | |
c19b0669 | 3065 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
0e32b39c DA |
3066 | if (intel_dp->is_mst) |
3067 | val |= DP_TP_CTL_MODE_MST; | |
3068 | else { | |
3069 | val |= DP_TP_CTL_MODE_SST; | |
3070 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
3071 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
3072 | } | |
c19b0669 PZ |
3073 | I915_WRITE(DP_TP_CTL(port), val); |
3074 | POSTING_READ(DP_TP_CTL(port)); | |
3075 | ||
3076 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
3077 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
3078 | POSTING_READ(DDI_BUF_CTL(port)); | |
3079 | ||
3080 | udelay(600); | |
3081 | } | |
00c09d70 | 3082 | |
1ad960f2 PZ |
3083 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
3084 | { | |
3085 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
3086 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
3087 | uint32_t val; | |
3088 | ||
3089 | intel_ddi_post_disable(intel_encoder); | |
3090 | ||
eede3b53 | 3091 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
1ad960f2 | 3092 | val &= ~FDI_RX_ENABLE; |
eede3b53 | 3093 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
1ad960f2 | 3094 | |
eede3b53 | 3095 | val = I915_READ(FDI_RX_MISC(PIPE_A)); |
1ad960f2 PZ |
3096 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
3097 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
eede3b53 | 3098 | I915_WRITE(FDI_RX_MISC(PIPE_A), val); |
1ad960f2 | 3099 | |
eede3b53 | 3100 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
1ad960f2 | 3101 | val &= ~FDI_PCDCLK; |
eede3b53 | 3102 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
1ad960f2 | 3103 | |
eede3b53 | 3104 | val = I915_READ(FDI_RX_CTL(PIPE_A)); |
1ad960f2 | 3105 | val &= ~FDI_RX_PLL_ENABLE; |
eede3b53 | 3106 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); |
1ad960f2 PZ |
3107 | } |
3108 | ||
6801c18c | 3109 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 3110 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
3111 | { |
3112 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
3113 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
0cb09a97 | 3114 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
bbd440fb | 3115 | struct intel_hdmi *intel_hdmi; |
045ac3b5 JB |
3116 | u32 temp, flags = 0; |
3117 | ||
3118 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
3119 | if (temp & TRANS_DDI_PHSYNC) | |
3120 | flags |= DRM_MODE_FLAG_PHSYNC; | |
3121 | else | |
3122 | flags |= DRM_MODE_FLAG_NHSYNC; | |
3123 | if (temp & TRANS_DDI_PVSYNC) | |
3124 | flags |= DRM_MODE_FLAG_PVSYNC; | |
3125 | else | |
3126 | flags |= DRM_MODE_FLAG_NVSYNC; | |
3127 | ||
2d112de7 | 3128 | pipe_config->base.adjusted_mode.flags |= flags; |
42571aef VS |
3129 | |
3130 | switch (temp & TRANS_DDI_BPC_MASK) { | |
3131 | case TRANS_DDI_BPC_6: | |
3132 | pipe_config->pipe_bpp = 18; | |
3133 | break; | |
3134 | case TRANS_DDI_BPC_8: | |
3135 | pipe_config->pipe_bpp = 24; | |
3136 | break; | |
3137 | case TRANS_DDI_BPC_10: | |
3138 | pipe_config->pipe_bpp = 30; | |
3139 | break; | |
3140 | case TRANS_DDI_BPC_12: | |
3141 | pipe_config->pipe_bpp = 36; | |
3142 | break; | |
3143 | default: | |
3144 | break; | |
3145 | } | |
eb14cb74 VS |
3146 | |
3147 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
3148 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 3149 | pipe_config->has_hdmi_sink = true; |
bbd440fb DV |
3150 | intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
3151 | ||
cda0aaaf | 3152 | if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) |
bbd440fb | 3153 | pipe_config->has_infoframe = true; |
cbc572a9 | 3154 | break; |
eb14cb74 VS |
3155 | case TRANS_DDI_MODE_SELECT_DVI: |
3156 | case TRANS_DDI_MODE_SELECT_FDI: | |
3157 | break; | |
3158 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
3159 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
3160 | pipe_config->has_dp_encoder = true; | |
90a6b7b0 VS |
3161 | pipe_config->lane_count = |
3162 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; | |
eb14cb74 VS |
3163 | intel_dp_get_m_n(intel_crtc, pipe_config); |
3164 | break; | |
3165 | default: | |
3166 | break; | |
3167 | } | |
10214420 | 3168 | |
26792526 L |
3169 | if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
3170 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
3171 | if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) | |
3172 | pipe_config->has_audio = true; | |
3173 | } | |
9ed109a7 | 3174 | |
10214420 DV |
3175 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && |
3176 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
3177 | /* | |
3178 | * This is a big fat ugly hack. | |
3179 | * | |
3180 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
3181 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
3182 | * unknown we fail to light up. Yet the same BIOS boots up with | |
3183 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
3184 | * max, not what it tells us to use. | |
3185 | * | |
3186 | * Note: This will still be broken if the eDP panel is not lit | |
3187 | * up by the BIOS, and thus we can't get the mode at module | |
3188 | * load. | |
3189 | */ | |
3190 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
3191 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
3192 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
3193 | } | |
11578553 | 3194 | |
22606a18 | 3195 | intel_ddi_clock_get(encoder, pipe_config); |
045ac3b5 JB |
3196 | } |
3197 | ||
5bfe2ac0 | 3198 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
5cec258b | 3199 | struct intel_crtc_state *pipe_config) |
00c09d70 | 3200 | { |
5bfe2ac0 | 3201 | int type = encoder->type; |
eccb140b | 3202 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 3203 | |
5bfe2ac0 | 3204 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 3205 | |
eccb140b DV |
3206 | if (port == PORT_A) |
3207 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
3208 | ||
00c09d70 | 3209 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 3210 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 3211 | else |
5bfe2ac0 | 3212 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
3213 | } |
3214 | ||
3215 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
5eaa60c7 ID |
3216 | .reset = intel_dp_encoder_reset, |
3217 | .destroy = intel_dp_encoder_destroy, | |
00c09d70 PZ |
3218 | }; |
3219 | ||
4a28ae58 PZ |
3220 | static struct intel_connector * |
3221 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
3222 | { | |
3223 | struct intel_connector *connector; | |
3224 | enum port port = intel_dig_port->port; | |
3225 | ||
9bdbd0b9 | 3226 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
3227 | if (!connector) |
3228 | return NULL; | |
3229 | ||
3230 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
3231 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
3232 | kfree(connector); | |
3233 | return NULL; | |
3234 | } | |
3235 | ||
3236 | return connector; | |
3237 | } | |
3238 | ||
3239 | static struct intel_connector * | |
3240 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
3241 | { | |
3242 | struct intel_connector *connector; | |
3243 | enum port port = intel_dig_port->port; | |
3244 | ||
9bdbd0b9 | 3245 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
3246 | if (!connector) |
3247 | return NULL; | |
3248 | ||
3249 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
3250 | intel_hdmi_init_connector(intel_dig_port, connector); | |
3251 | ||
3252 | return connector; | |
3253 | } | |
3254 | ||
00c09d70 PZ |
3255 | void intel_ddi_init(struct drm_device *dev, enum port port) |
3256 | { | |
876a8cdf | 3257 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
3258 | struct intel_digital_port *intel_dig_port; |
3259 | struct intel_encoder *intel_encoder; | |
3260 | struct drm_encoder *encoder; | |
311a2094 | 3261 | bool init_hdmi, init_dp; |
10e7bec3 VS |
3262 | int max_lanes; |
3263 | ||
3264 | if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { | |
3265 | switch (port) { | |
3266 | case PORT_A: | |
3267 | max_lanes = 4; | |
3268 | break; | |
3269 | case PORT_E: | |
3270 | max_lanes = 0; | |
3271 | break; | |
3272 | default: | |
3273 | max_lanes = 4; | |
3274 | break; | |
3275 | } | |
3276 | } else { | |
3277 | switch (port) { | |
3278 | case PORT_A: | |
3279 | max_lanes = 2; | |
3280 | break; | |
3281 | case PORT_E: | |
3282 | max_lanes = 2; | |
3283 | break; | |
3284 | default: | |
3285 | max_lanes = 4; | |
3286 | break; | |
3287 | } | |
3288 | } | |
311a2094 PZ |
3289 | |
3290 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
3291 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
3292 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
3293 | if (!init_dp && !init_hdmi) { | |
500ea70d | 3294 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", |
311a2094 | 3295 | port_name(port)); |
500ea70d | 3296 | return; |
311a2094 | 3297 | } |
00c09d70 | 3298 | |
b14c5679 | 3299 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
3300 | if (!intel_dig_port) |
3301 | return; | |
3302 | ||
00c09d70 PZ |
3303 | intel_encoder = &intel_dig_port->base; |
3304 | encoder = &intel_encoder->base; | |
3305 | ||
3306 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
13a3d91f | 3307 | DRM_MODE_ENCODER_TMDS, NULL); |
00c09d70 | 3308 | |
5bfe2ac0 | 3309 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 PZ |
3310 | intel_encoder->enable = intel_enable_ddi; |
3311 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
3312 | intel_encoder->disable = intel_disable_ddi; | |
3313 | intel_encoder->post_disable = intel_ddi_post_disable; | |
3314 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 3315 | intel_encoder->get_config = intel_ddi_get_config; |
5eaa60c7 | 3316 | intel_encoder->suspend = intel_dp_encoder_suspend; |
00c09d70 PZ |
3317 | |
3318 | intel_dig_port->port = port; | |
bcf53de4 SM |
3319 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
3320 | (DDI_BUF_PORT_REVERSAL | | |
3321 | DDI_A_4_LANES); | |
00c09d70 | 3322 | |
6c566dc9 MR |
3323 | /* |
3324 | * Bspec says that DDI_A_4_LANES is the only supported configuration | |
3325 | * for Broxton. Yet some BIOS fail to set this bit on port A if eDP | |
3326 | * wasn't lit up at boot. Force this bit on in our internal | |
3327 | * configuration so that we use the proper lane count for our | |
3328 | * calculations. | |
3329 | */ | |
3330 | if (IS_BROXTON(dev) && port == PORT_A) { | |
3331 | if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { | |
3332 | DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); | |
3333 | intel_dig_port->saved_port_bits |= DDI_A_4_LANES; | |
ed8d60f4 | 3334 | max_lanes = 4; |
6c566dc9 MR |
3335 | } |
3336 | } | |
3337 | ||
ed8d60f4 MR |
3338 | intel_dig_port->max_lanes = max_lanes; |
3339 | ||
00c09d70 | 3340 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |
f68d697e | 3341 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
bc079e8b | 3342 | intel_encoder->cloneable = 0; |
00c09d70 | 3343 | |
f68d697e CW |
3344 | if (init_dp) { |
3345 | if (!intel_ddi_init_dp_connector(intel_dig_port)) | |
3346 | goto err; | |
13cf5504 | 3347 | |
f68d697e | 3348 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
cf1d5883 SJ |
3349 | /* |
3350 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and | |
3351 | * interrupts to check the external panel connection. | |
3352 | */ | |
e87a005d | 3353 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B) |
cf1d5883 SJ |
3354 | dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; |
3355 | else | |
3356 | dev_priv->hotplug.irq_port[port] = intel_dig_port; | |
f68d697e | 3357 | } |
21a8e6a4 | 3358 | |
311a2094 PZ |
3359 | /* In theory we don't need the encoder->type check, but leave it just in |
3360 | * case we have some really bad VBTs... */ | |
f68d697e CW |
3361 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
3362 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) | |
3363 | goto err; | |
21a8e6a4 | 3364 | } |
f68d697e CW |
3365 | |
3366 | return; | |
3367 | ||
3368 | err: | |
3369 | drm_encoder_cleanup(encoder); | |
3370 | kfree(intel_dig_port); | |
00c09d70 | 3371 | } |