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drm/i915: Make for_each_sprite() take dev_priv as argument
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
45244b87
ED		 36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
10122051
JN		 40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
45244b87
ED		 50};
51
10122051
JN		 52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
6acab15a
PZ		 62};
63
10122051
JN		 64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
45244b87
ED		 78};
79
10122051
JN		 80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
300644c7
PZ		 90};
91
10122051
JN		 92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
17b523ba 98 { 0x00DB6FFF, 0x00160005 },
6805b2a7 99 { 0x80C71FFF, 0x001A0002 },
10122051
JN		 100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
e58623cb
AR		 102};
103
10122051
JN		 104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
e58623cb
AR		 114};
115
10122051
JN		 116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
a26aa8ba
DL		 128};
129
7f88e3af 130static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6c930688
DL		 131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
7f88e3af 133 { 0x00006012, 0x00000088 },
6c930688
DL		 134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
7f88e3af 136 { 0x00004014, 0x00000088 },
6c930688 137 { 0x00006012, 0x00000087 },
7f88e3af 138 { 0x00000018, 0x00000088 },
6c930688 139 { 0x00004014, 0x00000087 },
7f88e3af
DL		 140};
141
7ad14a29
SJ		 142/* eDP 1.4 low vswing translation parameters */
143static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
154};
155
156
7f88e3af
DL		 157static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
158 /* Idx NT mV T mV db */
159 { 0x00000018, 0x000000a0 }, /* 0: 400 400 0 */
160 { 0x00004014, 0x00000098 }, /* 1: 400 600 3.5 */
161 { 0x00006012, 0x00000088 }, /* 2: 400 800 6 */
162 { 0x00000018, 0x0000003c }, /* 3: 450 450 0 */
163 { 0x00000018, 0x00000098 }, /* 4: 600 600 0 */
164 { 0x00003015, 0x00000088 }, /* 5: 600 800 2.5 */
165 { 0x00005013, 0x00000080 }, /* 6: 600 1000 4.5 */
166 { 0x00000018, 0x00000088 }, /* 7: 800 800 0 */
167 { 0x00000096, 0x00000080 }, /* 8: 800 1000 2 */
168 { 0x00000018, 0x00000080 }, /* 9: 1200 1200 0 */
169};
170
20f4dbe4 171enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
fc914639 172{
0bdee30e 173 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 174 int type = intel_encoder->type;
175
0e32b39c
DA		 176 if (type == INTEL_OUTPUT_DP_MST) {
177 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
178 return intel_dig_port->port;
179 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 180 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
174edf1f
PZ		 181 struct intel_digital_port *intel_dig_port =
182 enc_to_dig_port(encoder);
183 return intel_dig_port->port;
0bdee30e 184
fc914639
PZ		 185 } else if (type == INTEL_OUTPUT_ANALOG) {
186 return PORT_E;
0bdee30e 187
fc914639
PZ		 188 } else {
189 DRM_ERROR("Invalid DDI encoder type %d\n", type);
190 BUG();
191 }
192}
193
e58623cb
AR		 194/*
195 * Starting with Haswell, DDI port buffers must be programmed with correct
196 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 197 * but the HDMI/DVI fields are shared among those. So we program the DDI
198 * in either FDI or DP modes only, as HDMI connections will work with both
199 * of those
200 */
ad8d270c 201static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
45244b87
ED		 202{
203 struct drm_i915_private *dev_priv = dev->dev_private;
204 u32 reg;
7ad14a29
SJ		 205 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_800mV_0dB,
206 size;
6acab15a 207 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 208 const struct ddi_buf_trans *ddi_translations_fdi;
209 const struct ddi_buf_trans *ddi_translations_dp;
210 const struct ddi_buf_trans *ddi_translations_edp;
211 const struct ddi_buf_trans *ddi_translations_hdmi;
212 const struct ddi_buf_trans *ddi_translations;
e58623cb 213
7f88e3af
DL		 214 if (IS_SKYLAKE(dev)) {
215 ddi_translations_fdi = NULL;
216 ddi_translations_dp = skl_ddi_translations_dp;
7ad14a29
SJ		 217 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
218 if (dev_priv->vbt.edp_low_vswing) {
219 ddi_translations_edp = skl_ddi_translations_edp;
220 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
221 } else {
222 ddi_translations_edp = skl_ddi_translations_dp;
223 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
224 }
225
7f88e3af
DL		 226 ddi_translations_hdmi = skl_ddi_translations_hdmi;
227 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
228 hdmi_800mV_0dB = 7;
229 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 230 ddi_translations_fdi = bdw_ddi_translations_fdi;
231 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 232 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 233 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 234 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
235 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 236 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
a26aa8ba 237 hdmi_800mV_0dB = 7;
e58623cb
AR		 238 } else if (IS_HASWELL(dev)) {
239 ddi_translations_fdi = hsw_ddi_translations_fdi;
240 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 241 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 242 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 243 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 244 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
ce4dd49e 245 hdmi_800mV_0dB = 6;
e58623cb
AR		 246 } else {
247 WARN(1, "ddi translation table missing\n");
300644c7 248 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 249 ddi_translations_fdi = bdw_ddi_translations_fdi;
250 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 251 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 252 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
253 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 254 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
a26aa8ba 255 hdmi_800mV_0dB = 7;
e58623cb
AR		 256 }
257
300644c7
PZ		 258 switch (port) {
259 case PORT_A:
260 ddi_translations = ddi_translations_edp;
7ad14a29 261 size = n_edp_entries;
300644c7
PZ		 262 break;
263 case PORT_B:
264 case PORT_C:
300644c7 265 ddi_translations = ddi_translations_dp;
7ad14a29 266 size = n_dp_entries;
300644c7 267 break;
77d8d009 268 case PORT_D:
7ad14a29 269 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 270 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 271 size = n_edp_entries;
272 } else {
77d8d009 273 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 274 size = n_dp_entries;
275 }
77d8d009 276 break;
300644c7 277 case PORT_E:
7f88e3af
DL		 278 if (ddi_translations_fdi)
279 ddi_translations = ddi_translations_fdi;
280 else
281 ddi_translations = ddi_translations_dp;
7ad14a29 282 size = n_dp_entries;
300644c7
PZ		 283 break;
284 default:
285 BUG();
286 }
45244b87 287
7ad14a29 288 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
10122051
JN		 289 I915_WRITE(reg, ddi_translations[i].trans1);
290 reg += 4;
291 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 292 reg += 4;
293 }
ce4dd49e
DL		 294
295 /* Choose a good default if VBT is badly populated */
296 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
297 hdmi_level >= n_hdmi_entries)
298 hdmi_level = hdmi_800mV_0dB;
299
6acab15a 300 /* Entry 9 is for HDMI: */
10122051
JN		 301 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
302 reg += 4;
303 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
304 reg += 4;
45244b87
ED		 305}
306
307/* Program DDI buffers translations for DP. By default, program ports A-D in DP
308 * mode and port E for FDI.
309 */
310void intel_prepare_ddi(struct drm_device *dev)
311{
312 int port;
313
0d536cb4
PZ		 314 if (!HAS_DDI(dev))
315 return;
45244b87 316
ad8d270c
PZ		 317 for (port = PORT_A; port <= PORT_E; port++)
318 intel_prepare_ddi_buffers(dev, port);
45244b87 319}
c82e4d26 320
248138b5
PZ		 321static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
322 enum port port)
323{
324 uint32_t reg = DDI_BUF_CTL(port);
325 int i;
326
327 for (i = 0; i < 8; i++) {
328 udelay(1);
329 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
330 return;
331 }
332 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
333}
c82e4d26
ED		 334
335/* Starting with Haswell, different DDI ports can work in FDI mode for
336 * connection to the PCH-located connectors. For this, it is necessary to train
337 * both the DDI port and PCH receiver for the desired DDI buffer settings.
338 *
339 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
340 * please note that when FDI mode is active on DDI E, it shares 2 lines with
341 * DDI A (which is used for eDP)
342 */
343
344void hsw_fdi_link_train(struct drm_crtc *crtc)
345{
346 struct drm_device *dev = crtc->dev;
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 349 u32 temp, i, rx_ctl_val;
c82e4d26 350
04945641
PZ		 351 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
352 * mode set "sequence for CRT port" document:
353 * - TP1 to TP2 time with the default value
354 * - FDI delay to 90h
8693a824
DL		 355 *
356 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 357 */
358 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
359 FDI_RX_PWRDN_LANE0_VAL(2) |
360 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
361
362 /* Enable the PCH Receiver FDI PLL */
3e68320e 363 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 364 FDI_RX_PLL_ENABLE |
6e3c9717 365 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 366 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
367 POSTING_READ(_FDI_RXA_CTL);
368 udelay(220);
369
370 /* Switch from Rawclk to PCDclk */
371 rx_ctl_val |= FDI_PCDCLK;
372 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
373
374 /* Configure Port Clock Select */
6e3c9717
ACO		 375 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
376 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 377
378 /* Start the training iterating through available voltages and emphasis,
379 * testing each value twice. */
10122051 380 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 381 /* Configure DP_TP_CTL with auto-training */
382 I915_WRITE(DP_TP_CTL(PORT_E),
383 DP_TP_CTL_FDI_AUTOTRAIN |
384 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
385 DP_TP_CTL_LINK_TRAIN_PAT1 |
386 DP_TP_CTL_ENABLE);
387
876a8cdf
DL		 388 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
389 * DDI E does not support port reversal, the functionality is
390 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
391 * port reversal bit */
c82e4d26 392 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 393 DDI_BUF_CTL_ENABLE |
6e3c9717 394 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 395 DDI_BUF_TRANS_SELECT(i / 2));
04945641 396 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 397
398 udelay(600);
399
04945641
PZ		 400 /* Program PCH FDI Receiver TU */
401 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
402
403 /* Enable PCH FDI Receiver with auto-training */
404 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
405 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
406 POSTING_READ(_FDI_RXA_CTL);
407
408 /* Wait for FDI receiver lane calibration */
409 udelay(30);
410
411 /* Unset FDI_RX_MISC pwrdn lanes */
412 temp = I915_READ(_FDI_RXA_MISC);
413 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
414 I915_WRITE(_FDI_RXA_MISC, temp);
415 POSTING_READ(_FDI_RXA_MISC);
416
417 /* Wait for FDI auto training time */
418 udelay(5);
c82e4d26
ED		 419
420 temp = I915_READ(DP_TP_STATUS(PORT_E));
421 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 422 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 423
424 /* Enable normal pixel sending for FDI */
425 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 426 DP_TP_CTL_FDI_AUTOTRAIN |
427 DP_TP_CTL_LINK_TRAIN_NORMAL |
428 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
429 DP_TP_CTL_ENABLE);
c82e4d26 430
04945641 431 return;
c82e4d26 432 }
04945641 433
248138b5
PZ		 434 temp = I915_READ(DDI_BUF_CTL(PORT_E));
435 temp &= ~DDI_BUF_CTL_ENABLE;
436 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
437 POSTING_READ(DDI_BUF_CTL(PORT_E));
438
04945641 439 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 440 temp = I915_READ(DP_TP_CTL(PORT_E));
441 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
442 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
443 I915_WRITE(DP_TP_CTL(PORT_E), temp);
444 POSTING_READ(DP_TP_CTL(PORT_E));
445
446 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 447
448 rx_ctl_val &= ~FDI_RX_ENABLE;
449 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 450 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 451
452 /* Reset FDI_RX_MISC pwrdn lanes */
453 temp = I915_READ(_FDI_RXA_MISC);
454 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
455 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
456 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 457 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 458 }
459
04945641 460 DRM_ERROR("FDI link training failed!\n");
c82e4d26 461}
0e72a5b5 462
44905a27
DA		 463void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
464{
465 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
466 struct intel_digital_port *intel_dig_port =
467 enc_to_dig_port(&encoder->base);
468
469 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 470 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 471 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
472
473}
474
8d9ddbcb
PZ		 475static struct intel_encoder *
476intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
477{
478 struct drm_device *dev = crtc->dev;
479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
480 struct intel_encoder *intel_encoder, *ret = NULL;
481 int num_encoders = 0;
482
483 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
484 ret = intel_encoder;
485 num_encoders++;
486 }
487
488 if (num_encoders != 1)
84f44ce7
VS		 489 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
490 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 491
492 BUG_ON(ret == NULL);
493 return ret;
494}
495
d0737e1d
ACO		 496static struct intel_encoder *
497intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
498{
499 struct drm_device *dev = crtc->base.dev;
500 struct intel_encoder *intel_encoder, *ret = NULL;
501 int num_encoders = 0;
502
503 for_each_intel_encoder(dev, intel_encoder) {
504 if (intel_encoder->new_crtc == crtc) {
505 ret = intel_encoder;
506 num_encoders++;
507 }
508 }
509
510 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
511 pipe_name(crtc->pipe));
512
513 BUG_ON(ret == NULL);
514 return ret;
515}
516
1c0b85c5 517#define LC_FREQ 2700
27893390 518#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 519
520#define P_MIN 2
521#define P_MAX 64
522#define P_INC 2
523
524/* Constraints for PLL good behavior */
525#define REF_MIN 48
526#define REF_MAX 400
527#define VCO_MIN 2400
528#define VCO_MAX 4800
529
27893390
DL		 530#define abs_diff(a, b) ({ \
531 typeof(a) __a = (a); \
532 typeof(b) __b = (b); \
533 (void) (&__a == &__b); \
534 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5
DL		 535
536struct wrpll_rnp {
537 unsigned p, n2, r2;
538};
539
540static unsigned wrpll_get_budget_for_freq(int clock)
6441ab5f 541{
1c0b85c5
DL		 542 unsigned budget;
543
544 switch (clock) {
545 case 25175000:
546 case 25200000:
547 case 27000000:
548 case 27027000:
549 case 37762500:
550 case 37800000:
551 case 40500000:
552 case 40541000:
553 case 54000000:
554 case 54054000:
555 case 59341000:
556 case 59400000:
557 case 72000000:
558 case 74176000:
559 case 74250000:
560 case 81000000:
561 case 81081000:
562 case 89012000:
563 case 89100000:
564 case 108000000:
565 case 108108000:
566 case 111264000:
567 case 111375000:
568 case 148352000:
569 case 148500000:
570 case 162000000:
571 case 162162000:
572 case 222525000:
573 case 222750000:
574 case 296703000:
575 case 297000000:
576 budget = 0;
577 break;
578 case 233500000:
579 case 245250000:
580 case 247750000:
581 case 253250000:
582 case 298000000:
583 budget = 1500;
584 break;
585 case 169128000:
586 case 169500000:
587 case 179500000:
588 case 202000000:
589 budget = 2000;
590 break;
591 case 256250000:
592 case 262500000:
593 case 270000000:
594 case 272500000:
595 case 273750000:
596 case 280750000:
597 case 281250000:
598 case 286000000:
599 case 291750000:
600 budget = 4000;
601 break;
602 case 267250000:
603 case 268500000:
604 budget = 5000;
605 break;
606 default:
607 budget = 1000;
608 break;
609 }
6441ab5f 610
1c0b85c5
DL		 611 return budget;
612}
613
614static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
615 unsigned r2, unsigned n2, unsigned p,
616 struct wrpll_rnp *best)
617{
618 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 619
1c0b85c5
DL		 620 /* No best (r,n,p) yet */
621 if (best->p == 0) {
622 best->p = p;
623 best->n2 = n2;
624 best->r2 = r2;
625 return;
626 }
6441ab5f 627
1c0b85c5
DL		 628 /*
629 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
630 * freq2k.
631 *
632 * delta = 1e6 *
633 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
634 * freq2k;
635 *
636 * and we would like delta <= budget.
637 *
638 * If the discrepancy is above the PPM-based budget, always prefer to
639 * improve upon the previous solution. However, if you're within the
640 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
641 */
642 a = freq2k * budget * p * r2;
643 b = freq2k * budget * best->p * best->r2;
27893390
DL		 644 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
645 diff_best = abs_diff(freq2k * best->p * best->r2,
646 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 647 c = 1000000 * diff;
648 d = 1000000 * diff_best;
649
650 if (a < c && b < d) {
651 /* If both are above the budget, pick the closer */
652 if (best->p * best->r2 * diff < p * r2 * diff_best) {
653 best->p = p;
654 best->n2 = n2;
655 best->r2 = r2;
656 }
657 } else if (a >= c && b < d) {
658 /* If A is below the threshold but B is above it? Update. */
659 best->p = p;
660 best->n2 = n2;
661 best->r2 = r2;
662 } else if (a >= c && b >= d) {
663 /* Both are below the limit, so pick the higher n2/(r2*r2) */
664 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
665 best->p = p;
666 best->n2 = n2;
667 best->r2 = r2;
668 }
669 }
670 /* Otherwise a < c && b >= d, do nothing */
671}
672
11578553
JB		 673static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
674 int reg)
675{
676 int refclk = LC_FREQ;
677 int n, p, r;
678 u32 wrpll;
679
680 wrpll = I915_READ(reg);
114fe488
DV		 681 switch (wrpll & WRPLL_PLL_REF_MASK) {
682 case WRPLL_PLL_SSC:
683 case WRPLL_PLL_NON_SSC:
11578553
JB		 684 /*
685 * We could calculate spread here, but our checking
686 * code only cares about 5% accuracy, and spread is a max of
687 * 0.5% downspread.
688 */
689 refclk = 135;
690 break;
114fe488 691 case WRPLL_PLL_LCPLL:
11578553
JB		 692 refclk = LC_FREQ;
693 break;
694 default:
695 WARN(1, "bad wrpll refclk\n");
696 return 0;
697 }
698
699 r = wrpll & WRPLL_DIVIDER_REF_MASK;
700 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
701 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
702
20f0ec16
JB		 703 /* Convert to KHz, p & r have a fixed point portion */
704 return (refclk * n * 100) / (p * r);
11578553
JB		 705}
706
540e732c
S		 707static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
708 uint32_t dpll)
709{
710 uint32_t cfgcr1_reg, cfgcr2_reg;
711 uint32_t cfgcr1_val, cfgcr2_val;
712 uint32_t p0, p1, p2, dco_freq;
713
714 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
715 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
716
717 cfgcr1_val = I915_READ(cfgcr1_reg);
718 cfgcr2_val = I915_READ(cfgcr2_reg);
719
720 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
721 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
722
723 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
724 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
725 else
726 p1 = 1;
727
728
729 switch (p0) {
730 case DPLL_CFGCR2_PDIV_1:
731 p0 = 1;
732 break;
733 case DPLL_CFGCR2_PDIV_2:
734 p0 = 2;
735 break;
736 case DPLL_CFGCR2_PDIV_3:
737 p0 = 3;
738 break;
739 case DPLL_CFGCR2_PDIV_7:
740 p0 = 7;
741 break;
742 }
743
744 switch (p2) {
745 case DPLL_CFGCR2_KDIV_5:
746 p2 = 5;
747 break;
748 case DPLL_CFGCR2_KDIV_2:
749 p2 = 2;
750 break;
751 case DPLL_CFGCR2_KDIV_3:
752 p2 = 3;
753 break;
754 case DPLL_CFGCR2_KDIV_1:
755 p2 = 1;
756 break;
757 }
758
759 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
760
761 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
762 1000) / 0x8000;
763
764 return dco_freq / (p0 * p1 * p2 * 5);
765}
766
767
768static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 769 struct intel_crtc_state *pipe_config)
540e732c
S		 770{
771 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 772 int link_clock = 0;
773 uint32_t dpll_ctl1, dpll;
774
134ffa44 775 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 776
777 dpll_ctl1 = I915_READ(DPLL_CTRL1);
778
779 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
780 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
781 } else {
782 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
783 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
784
785 switch (link_clock) {
786 case DPLL_CRTL1_LINK_RATE_810:
787 link_clock = 81000;
788 break;
789 case DPLL_CRTL1_LINK_RATE_1350:
790 link_clock = 135000;
791 break;
792 case DPLL_CRTL1_LINK_RATE_2700:
793 link_clock = 270000;
794 break;
795 default:
796 WARN(1, "Unsupported link rate\n");
797 break;
798 }
799 link_clock *= 2;
800 }
801
802 pipe_config->port_clock = link_clock;
803
804 if (pipe_config->has_dp_encoder)
2d112de7 805 pipe_config->base.adjusted_mode.crtc_clock =
540e732c
S		 806 intel_dotclock_calculate(pipe_config->port_clock,
807 &pipe_config->dp_m_n);
808 else
2d112de7 809 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
540e732c
S		 810}
811
3d51278a 812static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 813 struct intel_crtc_state *pipe_config)
11578553
JB		 814{
815 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 816 int link_clock = 0;
817 u32 val, pll;
818
26804afd 819 val = pipe_config->ddi_pll_sel;
11578553
JB		 820 switch (val & PORT_CLK_SEL_MASK) {
821 case PORT_CLK_SEL_LCPLL_810:
822 link_clock = 81000;
823 break;
824 case PORT_CLK_SEL_LCPLL_1350:
825 link_clock = 135000;
826 break;
827 case PORT_CLK_SEL_LCPLL_2700:
828 link_clock = 270000;
829 break;
830 case PORT_CLK_SEL_WRPLL1:
831 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
832 break;
833 case PORT_CLK_SEL_WRPLL2:
834 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
835 break;
836 case PORT_CLK_SEL_SPLL:
837 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
838 if (pll == SPLL_PLL_FREQ_810MHz)
839 link_clock = 81000;
840 else if (pll == SPLL_PLL_FREQ_1350MHz)
841 link_clock = 135000;
842 else if (pll == SPLL_PLL_FREQ_2700MHz)
843 link_clock = 270000;
844 else {
845 WARN(1, "bad spll freq\n");
846 return;
847 }
848 break;
849 default:
850 WARN(1, "bad port clock sel\n");
851 return;
852 }
853
854 pipe_config->port_clock = link_clock * 2;
855
856 if (pipe_config->has_pch_encoder)
2d112de7 857 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 858 intel_dotclock_calculate(pipe_config->port_clock,
859 &pipe_config->fdi_m_n);
860 else if (pipe_config->has_dp_encoder)
2d112de7 861 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 862 intel_dotclock_calculate(pipe_config->port_clock,
863 &pipe_config->dp_m_n);
864 else
2d112de7 865 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
11578553
JB		 866}
867
3d51278a 868void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 869 struct intel_crtc_state *pipe_config)
3d51278a 870{
22606a18
DL		 871 struct drm_device *dev = encoder->base.dev;
872
873 if (INTEL_INFO(dev)->gen <= 8)
874 hsw_ddi_clock_get(encoder, pipe_config);
875 else
876 skl_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 877}
878
1c0b85c5 879static void
d664c0ce
DL		 880hsw_ddi_calculate_wrpll(int clock /* in Hz */,
881 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 882{
883 uint64_t freq2k;
884 unsigned p, n2, r2;
885 struct wrpll_rnp best = { 0, 0, 0 };
886 unsigned budget;
887
888 freq2k = clock / 100;
889
890 budget = wrpll_get_budget_for_freq(clock);
891
892 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
893 * and directly pass the LC PLL to it. */
894 if (freq2k == 5400000) {
895 *n2_out = 2;
896 *p_out = 1;
897 *r2_out = 2;
898 return;
899 }
900
901 /*
902 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
903 * the WR PLL.
904 *
905 * We want R so that REF_MIN <= Ref <= REF_MAX.
906 * Injecting R2 = 2 * R gives:
907 * REF_MAX * r2 > LC_FREQ * 2 and
908 * REF_MIN * r2 < LC_FREQ * 2
909 *
910 * Which means the desired boundaries for r2 are:
911 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
912 *
913 */
914 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
915 r2 <= LC_FREQ * 2 / REF_MIN;
916 r2++) {
917
918 /*
919 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
920 *
921 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
922 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
923 * VCO_MAX * r2 > n2 * LC_FREQ and
924 * VCO_MIN * r2 < n2 * LC_FREQ)
925 *
926 * Which means the desired boundaries for n2 are:
927 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
928 */
929 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
930 n2 <= VCO_MAX * r2 / LC_FREQ;
931 n2++) {
932
933 for (p = P_MIN; p <= P_MAX; p += P_INC)
934 wrpll_update_rnp(freq2k, budget,
935 r2, n2, p, &best);
936 }
937 }
6441ab5f 938
1c0b85c5
DL		 939 *n2_out = best.n2;
940 *p_out = best.p;
941 *r2_out = best.r2;
6441ab5f
PZ		 942}
943
0220ab6e 944static bool
d664c0ce 945hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 946 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 947 struct intel_encoder *intel_encoder,
948 int clock)
6441ab5f 949{
d664c0ce 950 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 951 struct intel_shared_dpll *pll;
716c2e55 952 uint32_t val;
1c0b85c5 953 unsigned p, n2, r2;
6441ab5f 954
d664c0ce 955 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 956
114fe488 957 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 958 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
959 WRPLL_DIVIDER_POST(p);
960
190f68c5 961 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 962
190f68c5 963 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 964 if (pll == NULL) {
965 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
966 pipe_name(intel_crtc->pipe));
967 return false;
0694001b 968 }
d452c5b6 969
190f68c5 970 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 971 }
972
6441ab5f
PZ		 973 return true;
974}
975
82d35437
S		 976struct skl_wrpll_params {
977 uint32_t dco_fraction;
978 uint32_t dco_integer;
979 uint32_t qdiv_ratio;
980 uint32_t qdiv_mode;
981 uint32_t kdiv;
982 uint32_t pdiv;
983 uint32_t central_freq;
984};
985
986static void
987skl_ddi_calculate_wrpll(int clock /* in Hz */,
988 struct skl_wrpll_params *wrpll_params)
989{
990 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 991 uint64_t dco_central_freq[3] = {8400000000ULL,
992 9000000000ULL,
993 9600000000ULL};
82d35437
S		 994 uint32_t min_dco_deviation = 400;
995 uint32_t min_dco_index = 3;
996 uint32_t P0[4] = {1, 2, 3, 7};
997 uint32_t P2[4] = {1, 2, 3, 5};
998 bool found = false;
999 uint32_t candidate_p = 0;
1000 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
1001 uint32_t candidate_p2[3] = {0};
1002 uint32_t dco_central_freq_deviation[3];
1003 uint32_t i, P1, k, dco_count;
1004 bool retry_with_odd = false;
1005 uint64_t dco_freq;
1006
1007 /* Determine P0, P1 or P2 */
1008 for (dco_count = 0; dco_count < 3; dco_count++) {
1009 found = false;
1010 candidate_p =
1011 div64_u64(dco_central_freq[dco_count], afe_clock);
1012 if (retry_with_odd == false)
1013 candidate_p = (candidate_p % 2 == 0 ?
1014 candidate_p : candidate_p + 1);
1015
1016 for (P1 = 1; P1 < candidate_p; P1++) {
1017 for (i = 0; i < 4; i++) {
1018 if (!(P0[i] != 1 || P1 == 1))
1019 continue;
1020
1021 for (k = 0; k < 4; k++) {
1022 if (P1 != 1 && P2[k] != 2)
1023 continue;
1024
1025 if (candidate_p == P0[i] * P1 * P2[k]) {
1026 /* Found possible P0, P1, P2 */
1027 found = true;
1028 candidate_p0[dco_count] = P0[i];
1029 candidate_p1[dco_count] = P1;
1030 candidate_p2[dco_count] = P2[k];
1031 goto found;
1032 }
1033
1034 }
1035 }
1036 }
1037
1038found:
1039 if (found) {
1040 dco_central_freq_deviation[dco_count] =
1041 div64_u64(10000 *
1042 abs_diff((candidate_p * afe_clock),
1043 dco_central_freq[dco_count]),
1044 dco_central_freq[dco_count]);
1045
1046 if (dco_central_freq_deviation[dco_count] <
1047 min_dco_deviation) {
1048 min_dco_deviation =
1049 dco_central_freq_deviation[dco_count];
1050 min_dco_index = dco_count;
1051 }
1052 }
1053
1054 if (min_dco_index > 2 && dco_count == 2) {
1055 retry_with_odd = true;
1056 dco_count = 0;
1057 }
1058 }
1059
1060 if (min_dco_index > 2) {
1061 WARN(1, "No valid values found for the given pixel clock\n");
1062 } else {
1063 wrpll_params->central_freq = dco_central_freq[min_dco_index];
1064
1065 switch (dco_central_freq[min_dco_index]) {
21318cce 1066 case 9600000000ULL:
82d35437
S		 1067 wrpll_params->central_freq = 0;
1068 break;
21318cce 1069 case 9000000000ULL:
82d35437
S		 1070 wrpll_params->central_freq = 1;
1071 break;
21318cce 1072 case 8400000000ULL:
82d35437
S		 1073 wrpll_params->central_freq = 3;
1074 }
1075
1076 switch (candidate_p0[min_dco_index]) {
1077 case 1:
1078 wrpll_params->pdiv = 0;
1079 break;
1080 case 2:
1081 wrpll_params->pdiv = 1;
1082 break;
1083 case 3:
1084 wrpll_params->pdiv = 2;
1085 break;
1086 case 7:
1087 wrpll_params->pdiv = 4;
1088 break;
1089 default:
1090 WARN(1, "Incorrect PDiv\n");
1091 }
1092
1093 switch (candidate_p2[min_dco_index]) {
1094 case 5:
1095 wrpll_params->kdiv = 0;
1096 break;
1097 case 2:
1098 wrpll_params->kdiv = 1;
1099 break;
1100 case 3:
1101 wrpll_params->kdiv = 2;
1102 break;
1103 case 1:
1104 wrpll_params->kdiv = 3;
1105 break;
1106 default:
1107 WARN(1, "Incorrect KDiv\n");
1108 }
1109
1110 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
1111 wrpll_params->qdiv_mode =
1112 (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
1113
1114 dco_freq = candidate_p0[min_dco_index] *
1115 candidate_p1[min_dco_index] *
1116 candidate_p2[min_dco_index] * afe_clock;
1117
1118 /*
1119 * Intermediate values are in Hz.
1120 * Divide by MHz to match bsepc
1121 */
1122 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
1123 wrpll_params->dco_fraction =
1124 div_u64(((div_u64(dco_freq, 24) -
1125 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
1126
1127 }
1128}
1129
1130
1131static bool
1132skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1133 struct intel_crtc_state *crtc_state,
82d35437
S		 1134 struct intel_encoder *intel_encoder,
1135 int clock)
1136{
1137 struct intel_shared_dpll *pll;
1138 uint32_t ctrl1, cfgcr1, cfgcr2;
1139
1140 /*
1141 * See comment in intel_dpll_hw_state to understand why we always use 0
1142 * as the DPLL id in this function.
1143 */
1144
1145 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1146
1147 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1148 struct skl_wrpll_params wrpll_params = { 0, };
1149
1150 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1151
1152 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
1153
1154 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1155 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1156 wrpll_params.dco_integer;
1157
1158 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1159 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1160 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1161 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1162 wrpll_params.central_freq;
1163 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1164 struct drm_encoder *encoder = &intel_encoder->base;
1165 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1166
1167 switch (intel_dp->link_bw) {
1168 case DP_LINK_BW_1_62:
1169 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
1170 break;
1171 case DP_LINK_BW_2_7:
1172 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
1173 break;
1174 case DP_LINK_BW_5_4:
1175 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
1176 break;
1177 }
1178
1179 cfgcr1 = cfgcr2 = 0;
1180 } else /* eDP */
1181 return true;
1182
190f68c5
ACO		 1183 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1184 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1185 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1186
190f68c5 1187 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1188 if (pll == NULL) {
1189 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1190 pipe_name(intel_crtc->pipe));
1191 return false;
1192 }
1193
1194 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1195 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1196
1197 return true;
1198}
0220ab6e
DL		 1199
1200/*
1201 * Tries to find a *shared* PLL for the CRTC and store it in
1202 * intel_crtc->ddi_pll_sel.
1203 *
1204 * For private DPLLs, compute_config() should do the selection for us. This
1205 * function should be folded into compute_config() eventually.
1206 */
190f68c5
ACO		 1207bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1208 struct intel_crtc_state *crtc_state)
0220ab6e 1209{
82d35437 1210 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d
ACO		 1211 struct intel_encoder *intel_encoder =
1212 intel_ddi_get_crtc_new_encoder(intel_crtc);
190f68c5 1213 int clock = crtc_state->port_clock;
0220ab6e 1214
82d35437 1215 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1216 return skl_ddi_pll_select(intel_crtc, crtc_state,
1217 intel_encoder, clock);
82d35437 1218 else
190f68c5
ACO		 1219 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1220 intel_encoder, clock);
0220ab6e
DL		 1221}
1222
dae84799
PZ		 1223void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1224{
1225 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1227 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1228 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1229 int type = intel_encoder->type;
1230 uint32_t temp;
1231
0e32b39c 1232 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1233 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1234 switch (intel_crtc->config->pipe_bpp) {
dae84799 1235 case 18:
c9809791 1236 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1237 break;
1238 case 24:
c9809791 1239 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1240 break;
1241 case 30:
c9809791 1242 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1243 break;
1244 case 36:
c9809791 1245 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1246 break;
1247 default:
4e53c2e0 1248 BUG();
dae84799 1249 }
c9809791 1250 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1251 }
1252}
1253
0e32b39c
DA		 1254void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1255{
1256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1257 struct drm_device *dev = crtc->dev;
1258 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1259 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1260 uint32_t temp;
1261 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1262 if (state == true)
1263 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1264 else
1265 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1266 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1267}
1268
8228c251 1269void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1270{
1271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1272 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1273 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1274 struct drm_device *dev = crtc->dev;
1275 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1276 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1277 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1278 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1279 int type = intel_encoder->type;
8d9ddbcb
PZ		 1280 uint32_t temp;
1281
ad80a810
PZ		 1282 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1283 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1284 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1285
6e3c9717 1286 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1287 case 18:
ad80a810 1288 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1289 break;
1290 case 24:
ad80a810 1291 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1292 break;
1293 case 30:
ad80a810 1294 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1295 break;
1296 case 36:
ad80a810 1297 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1298 break;
1299 default:
4e53c2e0 1300 BUG();
dfcef252 1301 }
72662e10 1302
6e3c9717 1303 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1304 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1305 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1306 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1307
e6f0bfc4
PZ		 1308 if (cpu_transcoder == TRANSCODER_EDP) {
1309 switch (pipe) {
1310 case PIPE_A:
c7670b10
PZ		 1311 /* On Haswell, can only use the always-on power well for
1312 * eDP when not using the panel fitter, and when not
1313 * using motion blur mitigation (which we don't
1314 * support). */
fabf6e51 1315 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1316 (intel_crtc->config->pch_pfit.enabled ||
1317 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1318 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1319 else
1320 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1321 break;
1322 case PIPE_B:
1323 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1324 break;
1325 case PIPE_C:
1326 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1327 break;
1328 default:
1329 BUG();
1330 break;
1331 }
1332 }
1333
7739c33b 1334 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1335 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1336 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1337 else
ad80a810 1338 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1339
7739c33b 1340 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1341 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1342 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1343
1344 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1345 type == INTEL_OUTPUT_EDP) {
1346 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1347
0e32b39c
DA		 1348 if (intel_dp->is_mst) {
1349 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1350 } else
1351 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1352
1353 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1354 } else if (type == INTEL_OUTPUT_DP_MST) {
1355 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1356
1357 if (intel_dp->is_mst) {
1358 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1359 } else
1360 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1361
17aa6be9 1362 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1363 } else {
84f44ce7
VS		 1364 WARN(1, "Invalid encoder type %d for pipe %c\n",
1365 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1366 }
1367
ad80a810 1368 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1369}
72662e10 1370
ad80a810
PZ		 1371void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1372 enum transcoder cpu_transcoder)
8d9ddbcb 1373{
ad80a810 1374 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1375 uint32_t val = I915_READ(reg);
1376
0e32b39c 1377 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1378 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1379 I915_WRITE(reg, val);
72662e10
ED		 1380}
1381
bcbc889b
PZ		 1382bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1383{
1384 struct drm_device *dev = intel_connector->base.dev;
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 struct intel_encoder *intel_encoder = intel_connector->encoder;
1387 int type = intel_connector->base.connector_type;
1388 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1389 enum pipe pipe = 0;
1390 enum transcoder cpu_transcoder;
882244a3 1391 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1392 uint32_t tmp;
1393
882244a3 1394 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1395 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1396 return false;
1397
bcbc889b
PZ		 1398 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1399 return false;
1400
1401 if (port == PORT_A)
1402 cpu_transcoder = TRANSCODER_EDP;
1403 else
1a240d4d 1404 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1405
1406 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1407
1408 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1409 case TRANS_DDI_MODE_SELECT_HDMI:
1410 case TRANS_DDI_MODE_SELECT_DVI:
1411 return (type == DRM_MODE_CONNECTOR_HDMIA);
1412
1413 case TRANS_DDI_MODE_SELECT_DP_SST:
1414 if (type == DRM_MODE_CONNECTOR_eDP)
1415 return true;
bcbc889b 1416 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1417 case TRANS_DDI_MODE_SELECT_DP_MST:
1418 /* if the transcoder is in MST state then
1419 * connector isn't connected */
1420 return false;
bcbc889b
PZ		 1421
1422 case TRANS_DDI_MODE_SELECT_FDI:
1423 return (type == DRM_MODE_CONNECTOR_VGA);
1424
1425 default:
1426 return false;
1427 }
1428}
1429
85234cdc
DV		 1430bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1431 enum pipe *pipe)
1432{
1433 struct drm_device *dev = encoder->base.dev;
1434 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1435 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1436 enum intel_display_power_domain power_domain;
85234cdc
DV		 1437 u32 tmp;
1438 int i;
1439
6d129bea 1440 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1441 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1442 return false;
1443
fe43d3f5 1444 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1445
1446 if (!(tmp & DDI_BUF_CTL_ENABLE))
1447 return false;
1448
ad80a810
PZ		 1449 if (port == PORT_A) {
1450 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1451
ad80a810
PZ		 1452 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1453 case TRANS_DDI_EDP_INPUT_A_ON:
1454 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1455 *pipe = PIPE_A;
1456 break;
1457 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1458 *pipe = PIPE_B;
1459 break;
1460 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1461 *pipe = PIPE_C;
1462 break;
1463 }
1464
1465 return true;
1466 } else {
1467 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1468 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1469
1470 if ((tmp & TRANS_DDI_PORT_MASK)
1471 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 1472 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1473 return false;
1474
ad80a810
PZ		 1475 *pipe = i;
1476 return true;
1477 }
85234cdc
DV		 1478 }
1479 }
1480
84f44ce7 1481 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1482
22f9fe50 1483 return false;
85234cdc
DV		 1484}
1485
fc914639
PZ		 1486void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1487{
1488 struct drm_crtc *crtc = &intel_crtc->base;
1489 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1490 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1491 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1492 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1493
bb523fc0
PZ		 1494 if (cpu_transcoder != TRANSCODER_EDP)
1495 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1496 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1497}
1498
1499void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1500{
1501 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 1502 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1503
bb523fc0
PZ		 1504 if (cpu_transcoder != TRANSCODER_EDP)
1505 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1506 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1507}
1508
00c09d70 1509static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1510{
c19b0669 1511 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1512 struct drm_device *dev = encoder->dev;
1513 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 1514 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 1515 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1516 int type = intel_encoder->type;
6441ab5f 1517
82a4d9c0
PZ		 1518 if (type == INTEL_OUTPUT_EDP) {
1519 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1520 intel_edp_panel_on(intel_dp);
82a4d9c0 1521 }
6441ab5f 1522
efa80add 1523 if (IS_SKYLAKE(dev)) {
6e3c9717 1524 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 1525 uint32_t val;
1526
5416d871
DL		 1527 /*
1528 * DPLL0 is used for eDP and is the only "private" DPLL (as
1529 * opposed to shared) on SKL
1530 */
1531 if (type == INTEL_OUTPUT_EDP) {
1532 WARN_ON(dpll != SKL_DPLL0);
1533
1534 val = I915_READ(DPLL_CTRL1);
1535
1536 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1537 DPLL_CTRL1_SSC(dpll) |
1538 DPLL_CRTL1_LINK_RATE_MASK(dpll));
6e3c9717 1539 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 1540
1541 I915_WRITE(DPLL_CTRL1, val);
1542 POSTING_READ(DPLL_CTRL1);
1543 }
1544
1545 /* DDI -> PLL mapping */
efa80add
S		 1546 val = I915_READ(DPLL_CTRL2);
1547
1548 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1549 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1550 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1551 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1552
1553 I915_WRITE(DPLL_CTRL2, val);
5416d871 1554
efa80add 1555 } else {
6e3c9717
ACO		 1556 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1557 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 1558 }
c19b0669 1559
82a4d9c0 1560 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 1561 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1562
44905a27 1563 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1564
1565 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1566 intel_dp_start_link_train(intel_dp);
1567 intel_dp_complete_link_train(intel_dp);
23f08d83 1568 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 1569 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1570 } else if (type == INTEL_OUTPUT_HDMI) {
1571 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1572
1573 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 1574 crtc->config->has_hdmi_sink,
1575 &crtc->config->base.adjusted_mode);
c19b0669 1576 }
6441ab5f
PZ		 1577}
1578
00c09d70 1579static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1580{
1581 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1582 struct drm_device *dev = encoder->dev;
1583 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 1584 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1585 int type = intel_encoder->type;
2886e93f 1586 uint32_t val;
a836bdf9 1587 bool wait = false;
2886e93f
PZ		 1588
1589 val = I915_READ(DDI_BUF_CTL(port));
1590 if (val & DDI_BUF_CTL_ENABLE) {
1591 val &= ~DDI_BUF_CTL_ENABLE;
1592 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1593 wait = true;
2886e93f 1594 }
6441ab5f 1595
a836bdf9
PZ		 1596 val = I915_READ(DP_TP_CTL(port));
1597 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1598 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1599 I915_WRITE(DP_TP_CTL(port), val);
1600
1601 if (wait)
1602 intel_wait_ddi_buf_idle(dev_priv, port);
1603
76bb80ed 1604 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1605 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1606 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1607 intel_edp_panel_vdd_on(intel_dp);
4be73780 1608 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1609 }
1610
efa80add
S		 1611 if (IS_SKYLAKE(dev))
1612 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1613 DPLL_CTRL2_DDI_CLK_OFF(port)));
1614 else
1615 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 1616}
1617
00c09d70 1618static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1619{
6547fef8 1620 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1621 struct drm_crtc *crtc = encoder->crtc;
1622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 1623 struct drm_device *dev = encoder->dev;
72662e10 1624 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1625 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1626 int type = intel_encoder->type;
72662e10 1627
6547fef8 1628 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1629 struct intel_digital_port *intel_dig_port =
1630 enc_to_dig_port(encoder);
1631
6547fef8
PZ		 1632 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1633 * are ignored so nothing special needs to be done besides
1634 * enabling the port.
1635 */
876a8cdf 1636 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1637 intel_dig_port->saved_port_bits |
1638 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1639 } else if (type == INTEL_OUTPUT_EDP) {
1640 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1641
23f08d83 1642 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 1643 intel_dp_stop_link_train(intel_dp);
1644
4be73780 1645 intel_edp_backlight_on(intel_dp);
0bc12bcb 1646 intel_psr_enable(intel_dp);
c395578e 1647 intel_edp_drrs_enable(intel_dp);
6547fef8 1648 }
7b9f35a6 1649
6e3c9717 1650 if (intel_crtc->config->has_audio) {
d45a0bf5 1651 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 1652 intel_audio_codec_enable(intel_encoder);
7b9f35a6 1653 }
5ab432ef
DV		 1654}
1655
00c09d70 1656static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1657{
d6c50ff8 1658 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1659 struct drm_crtc *crtc = encoder->crtc;
1660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 1661 int type = intel_encoder->type;
7b9f35a6
WX		 1662 struct drm_device *dev = encoder->dev;
1663 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 1664
6e3c9717 1665 if (intel_crtc->config->has_audio) {
69bfe1a9 1666 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 1667 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1668 }
2831d842 1669
d6c50ff8
PZ		 1670 if (type == INTEL_OUTPUT_EDP) {
1671 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1672
c395578e 1673 intel_edp_drrs_disable(intel_dp);
0bc12bcb 1674 intel_psr_disable(intel_dp);
4be73780 1675 intel_edp_backlight_off(intel_dp);
d6c50ff8 1676 }
72662e10 1677}
79f689aa 1678
121643c2
S		 1679static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
1680{
1681 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
1682 uint32_t cdctl = I915_READ(CDCLK_CTL);
1683 uint32_t linkrate;
1684
1685 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
1686 WARN(1, "LCPLL1 not enabled\n");
1687 return 24000; /* 24MHz is the cd freq with NSSC ref */
1688 }
1689
1690 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
1691 return 540000;
1692
1693 linkrate = (I915_READ(DPLL_CTRL1) &
1694 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1695
1696 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
1697 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
1698 /* vco 8640 */
1699 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1700 case CDCLK_FREQ_450_432:
1701 return 432000;
1702 case CDCLK_FREQ_337_308:
1703 return 308570;
1704 case CDCLK_FREQ_675_617:
1705 return 617140;
1706 default:
1707 WARN(1, "Unknown cd freq selection\n");
1708 }
1709 } else {
1710 /* vco 8100 */
1711 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1712 case CDCLK_FREQ_450_432:
1713 return 450000;
1714 case CDCLK_FREQ_337_308:
1715 return 337500;
1716 case CDCLK_FREQ_675_617:
1717 return 675000;
1718 default:
1719 WARN(1, "Unknown cd freq selection\n");
1720 }
1721 }
1722
1723 /* error case, do as if DPLL0 isn't enabled */
1724 return 24000;
1725}
1726
ad13d604
DL		 1727static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1728{
1729 uint32_t lcpll = I915_READ(LCPLL_CTL);
1730 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1731
1732 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1733 return 800000;
1734 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1735 return 450000;
1736 else if (freq == LCPLL_CLK_FREQ_450)
1737 return 450000;
1738 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1739 return 540000;
1740 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1741 return 337500;
1742 else
1743 return 675000;
1744}
1745
1746static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
79f689aa 1747{
e39bf98a 1748 struct drm_device *dev = dev_priv->dev;
a4006641 1749 uint32_t lcpll = I915_READ(LCPLL_CTL);
e39bf98a 1750 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
a4006641 1751
ad13d604 1752 if (lcpll & LCPLL_CD_SOURCE_FCLK)
a4006641 1753 return 800000;
ad13d604 1754 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
b2b877ff 1755 return 450000;
ad13d604 1756 else if (freq == LCPLL_CLK_FREQ_450)
b2b877ff 1757 return 450000;
95626e7c 1758 else if (IS_HSW_ULT(dev))
ad13d604
DL		 1759 return 337500;
1760 else
1761 return 540000;
1762}
1763
1764int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1765{
1766 struct drm_device *dev = dev_priv->dev;
1767
121643c2
S		 1768 if (IS_SKYLAKE(dev))
1769 return skl_get_cdclk_freq(dev_priv);
1770
ad13d604
DL		 1771 if (IS_BROADWELL(dev))
1772 return bdw_get_cdclk_freq(dev_priv);
1773
1774 /* Haswell */
1775 return hsw_get_cdclk_freq(dev_priv);
79f689aa
PZ		 1776}
1777
e0b01be4
DV		 1778static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1779 struct intel_shared_dpll *pll)
1780{
3e369b76 1781 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 1782 POSTING_READ(WRPLL_CTL(pll->id));
1783 udelay(20);
1784}
1785
12030431
DV		 1786static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1787 struct intel_shared_dpll *pll)
1788{
1789 uint32_t val;
1790
1791 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 1792 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1793 POSTING_READ(WRPLL_CTL(pll->id));
1794}
1795
d452c5b6
DV		 1796static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1797 struct intel_shared_dpll *pll,
1798 struct intel_dpll_hw_state *hw_state)
1799{
1800 uint32_t val;
1801
f458ebbc 1802 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 1803 return false;
1804
1805 val = I915_READ(WRPLL_CTL(pll->id));
1806 hw_state->wrpll = val;
1807
1808 return val & WRPLL_PLL_ENABLE;
1809}
1810
ca1381b5 1811static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 1812 "WRPLL 1",
1813 "WRPLL 2",
1814};
1815
143b307c 1816static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 1817{
9cd86933
DV		 1818 int i;
1819
716c2e55 1820 dev_priv->num_shared_dpll = 2;
9cd86933 1821
716c2e55 1822 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 1823 dev_priv->shared_dplls[i].id = i;
1824 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 1825 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 1826 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 1827 dev_priv->shared_dplls[i].get_hw_state =
1828 hsw_ddi_pll_get_hw_state;
9cd86933 1829 }
143b307c
DL		 1830}
1831
d1a2dc78
S		 1832static const char * const skl_ddi_pll_names[] = {
1833 "DPLL 1",
1834 "DPLL 2",
1835 "DPLL 3",
1836};
1837
1838struct skl_dpll_regs {
1839 u32 ctl, cfgcr1, cfgcr2;
1840};
1841
1842/* this array is indexed by the *shared* pll id */
1843static const struct skl_dpll_regs skl_dpll_regs[3] = {
1844 {
1845 /* DPLL 1 */
1846 .ctl = LCPLL2_CTL,
1847 .cfgcr1 = DPLL1_CFGCR1,
1848 .cfgcr2 = DPLL1_CFGCR2,
1849 },
1850 {
1851 /* DPLL 2 */
1852 .ctl = WRPLL_CTL1,
1853 .cfgcr1 = DPLL2_CFGCR1,
1854 .cfgcr2 = DPLL2_CFGCR2,
1855 },
1856 {
1857 /* DPLL 3 */
1858 .ctl = WRPLL_CTL2,
1859 .cfgcr1 = DPLL3_CFGCR1,
1860 .cfgcr2 = DPLL3_CFGCR2,
1861 },
1862};
1863
1864static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1865 struct intel_shared_dpll *pll)
1866{
1867 uint32_t val;
1868 unsigned int dpll;
1869 const struct skl_dpll_regs *regs = skl_dpll_regs;
1870
1871 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1872 dpll = pll->id + 1;
1873
1874 val = I915_READ(DPLL_CTRL1);
1875
1876 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
1877 DPLL_CRTL1_LINK_RATE_MASK(dpll));
1878 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
1879
1880 I915_WRITE(DPLL_CTRL1, val);
1881 POSTING_READ(DPLL_CTRL1);
1882
1883 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
1884 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
1885 POSTING_READ(regs[pll->id].cfgcr1);
1886 POSTING_READ(regs[pll->id].cfgcr2);
1887
1888 /* the enable bit is always bit 31 */
1889 I915_WRITE(regs[pll->id].ctl,
1890 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
1891
1892 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
1893 DRM_ERROR("DPLL %d not locked\n", dpll);
1894}
1895
1896static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
1897 struct intel_shared_dpll *pll)
1898{
1899 const struct skl_dpll_regs *regs = skl_dpll_regs;
1900
1901 /* the enable bit is always bit 31 */
1902 I915_WRITE(regs[pll->id].ctl,
1903 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
1904 POSTING_READ(regs[pll->id].ctl);
1905}
1906
1907static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1908 struct intel_shared_dpll *pll,
1909 struct intel_dpll_hw_state *hw_state)
1910{
1911 uint32_t val;
1912 unsigned int dpll;
1913 const struct skl_dpll_regs *regs = skl_dpll_regs;
1914
1915 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1916 return false;
1917
1918 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1919 dpll = pll->id + 1;
1920
1921 val = I915_READ(regs[pll->id].ctl);
1922 if (!(val & LCPLL_PLL_ENABLE))
1923 return false;
1924
1925 val = I915_READ(DPLL_CTRL1);
1926 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
1927
1928 /* avoid reading back stale values if HDMI mode is not enabled */
1929 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
1930 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
1931 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
1932 }
1933
1934 return true;
1935}
1936
1937static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
1938{
1939 int i;
1940
1941 dev_priv->num_shared_dpll = 3;
1942
1943 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1944 dev_priv->shared_dplls[i].id = i;
1945 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
1946 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
1947 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
1948 dev_priv->shared_dplls[i].get_hw_state =
1949 skl_ddi_pll_get_hw_state;
1950 }
1951}
1952
143b307c
DL		 1953void intel_ddi_pll_init(struct drm_device *dev)
1954{
1955 struct drm_i915_private *dev_priv = dev->dev_private;
1956 uint32_t val = I915_READ(LCPLL_CTL);
1957
d1a2dc78
S		 1958 if (IS_SKYLAKE(dev))
1959 skl_shared_dplls_init(dev_priv);
1960 else
1961 hsw_shared_dplls_init(dev_priv);
79f689aa 1962
b2b877ff 1963 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
79f689aa
PZ		 1964 intel_ddi_get_cdclk_freq(dev_priv));
1965
121643c2
S		 1966 if (IS_SKYLAKE(dev)) {
1967 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
1968 DRM_ERROR("LCPLL1 is disabled\n");
1969 } else {
1970 /*
1971 * The LCPLL register should be turned on by the BIOS. For now
1972 * let's just check its state and print errors in case
1973 * something is wrong. Don't even try to turn it on.
1974 */
1975
1976 if (val & LCPLL_CD_SOURCE_FCLK)
1977 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 1978
121643c2
S		 1979 if (val & LCPLL_PLL_DISABLE)
1980 DRM_ERROR("LCPLL is disabled\n");
1981 }
79f689aa 1982}
c19b0669
PZ		 1983
1984void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1985{
174edf1f
PZ		 1986 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1987 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 1988 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 1989 enum port port = intel_dig_port->port;
c19b0669 1990 uint32_t val;
f3e227df 1991 bool wait = false;
c19b0669
PZ		 1992
1993 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1994 val = I915_READ(DDI_BUF_CTL(port));
1995 if (val & DDI_BUF_CTL_ENABLE) {
1996 val &= ~DDI_BUF_CTL_ENABLE;
1997 I915_WRITE(DDI_BUF_CTL(port), val);
1998 wait = true;
1999 }
2000
2001 val = I915_READ(DP_TP_CTL(port));
2002 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2003 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2004 I915_WRITE(DP_TP_CTL(port), val);
2005 POSTING_READ(DP_TP_CTL(port));
2006
2007 if (wait)
2008 intel_wait_ddi_buf_idle(dev_priv, port);
2009 }
2010
0e32b39c 2011 val = DP_TP_CTL_ENABLE |
c19b0669 2012 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2013 if (intel_dp->is_mst)
2014 val |= DP_TP_CTL_MODE_MST;
2015 else {
2016 val |= DP_TP_CTL_MODE_SST;
2017 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2018 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2019 }
c19b0669
PZ		 2020 I915_WRITE(DP_TP_CTL(port), val);
2021 POSTING_READ(DP_TP_CTL(port));
2022
2023 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2024 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2025 POSTING_READ(DDI_BUF_CTL(port));
2026
2027 udelay(600);
2028}
00c09d70 2029
1ad960f2
PZ		 2030void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2031{
2032 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2033 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2034 uint32_t val;
2035
2036 intel_ddi_post_disable(intel_encoder);
2037
2038 val = I915_READ(_FDI_RXA_CTL);
2039 val &= ~FDI_RX_ENABLE;
2040 I915_WRITE(_FDI_RXA_CTL, val);
2041
2042 val = I915_READ(_FDI_RXA_MISC);
2043 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2044 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2045 I915_WRITE(_FDI_RXA_MISC, val);
2046
2047 val = I915_READ(_FDI_RXA_CTL);
2048 val &= ~FDI_PCDCLK;
2049 I915_WRITE(_FDI_RXA_CTL, val);
2050
2051 val = I915_READ(_FDI_RXA_CTL);
2052 val &= ~FDI_RX_PLL_ENABLE;
2053 I915_WRITE(_FDI_RXA_CTL, val);
2054}
2055
00c09d70
PZ		 2056static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
2057{
0e32b39c
DA		 2058 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
2059 int type = intel_dig_port->base.type;
2060
2061 if (type != INTEL_OUTPUT_DISPLAYPORT &&
2062 type != INTEL_OUTPUT_EDP &&
2063 type != INTEL_OUTPUT_UNKNOWN) {
2064 return;
2065 }
00c09d70 2066
0e32b39c 2067 intel_dp_hot_plug(intel_encoder);
00c09d70
PZ		 2068}
2069
6801c18c 2070void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2071 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2072{
2073 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2074 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2075 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2076 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2077 u32 temp, flags = 0;
2078
2079 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2080 if (temp & TRANS_DDI_PHSYNC)
2081 flags |= DRM_MODE_FLAG_PHSYNC;
2082 else
2083 flags |= DRM_MODE_FLAG_NHSYNC;
2084 if (temp & TRANS_DDI_PVSYNC)
2085 flags |= DRM_MODE_FLAG_PVSYNC;
2086 else
2087 flags |= DRM_MODE_FLAG_NVSYNC;
2088
2d112de7 2089 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2090
2091 switch (temp & TRANS_DDI_BPC_MASK) {
2092 case TRANS_DDI_BPC_6:
2093 pipe_config->pipe_bpp = 18;
2094 break;
2095 case TRANS_DDI_BPC_8:
2096 pipe_config->pipe_bpp = 24;
2097 break;
2098 case TRANS_DDI_BPC_10:
2099 pipe_config->pipe_bpp = 30;
2100 break;
2101 case TRANS_DDI_BPC_12:
2102 pipe_config->pipe_bpp = 36;
2103 break;
2104 default:
2105 break;
2106 }
eb14cb74
VS		 2107
2108 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2109 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2110 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2111 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2112
2113 if (intel_hdmi->infoframe_enabled(&encoder->base))
2114 pipe_config->has_infoframe = true;
cbc572a9 2115 break;
eb14cb74
VS		 2116 case TRANS_DDI_MODE_SELECT_DVI:
2117 case TRANS_DDI_MODE_SELECT_FDI:
2118 break;
2119 case TRANS_DDI_MODE_SELECT_DP_SST:
2120 case TRANS_DDI_MODE_SELECT_DP_MST:
2121 pipe_config->has_dp_encoder = true;
2122 intel_dp_get_m_n(intel_crtc, pipe_config);
2123 break;
2124 default:
2125 break;
2126 }
10214420 2127
f458ebbc 2128 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 2129 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 2130 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 2131 pipe_config->has_audio = true;
2132 }
9ed109a7 2133
10214420
DV		 2134 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2135 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2136 /*
2137 * This is a big fat ugly hack.
2138 *
2139 * Some machines in UEFI boot mode provide us a VBT that has 18
2140 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2141 * unknown we fail to light up. Yet the same BIOS boots up with
2142 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2143 * max, not what it tells us to use.
2144 *
2145 * Note: This will still be broken if the eDP panel is not lit
2146 * up by the BIOS, and thus we can't get the mode at module
2147 * load.
2148 */
2149 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2150 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2151 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2152 }
11578553 2153
22606a18 2154 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2155}
2156
00c09d70
PZ		 2157static void intel_ddi_destroy(struct drm_encoder *encoder)
2158{
2159 /* HDMI has nothing special to destroy, so we can go with this. */
2160 intel_dp_encoder_destroy(encoder);
2161}
2162
5bfe2ac0 2163static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2164 struct intel_crtc_state *pipe_config)
00c09d70 2165{
5bfe2ac0 2166 int type = encoder->type;
eccb140b 2167 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2168
5bfe2ac0 2169 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2170
eccb140b
DV		 2171 if (port == PORT_A)
2172 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2173
00c09d70 2174 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2175 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2176 else
5bfe2ac0 2177 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2178}
2179
2180static const struct drm_encoder_funcs intel_ddi_funcs = {
2181 .destroy = intel_ddi_destroy,
2182};
2183
4a28ae58
PZ		 2184static struct intel_connector *
2185intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2186{
2187 struct intel_connector *connector;
2188 enum port port = intel_dig_port->port;
2189
2190 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
2191 if (!connector)
2192 return NULL;
2193
2194 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2195 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2196 kfree(connector);
2197 return NULL;
2198 }
2199
2200 return connector;
2201}
2202
2203static struct intel_connector *
2204intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2205{
2206 struct intel_connector *connector;
2207 enum port port = intel_dig_port->port;
2208
2209 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
2210 if (!connector)
2211 return NULL;
2212
2213 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2214 intel_hdmi_init_connector(intel_dig_port, connector);
2215
2216 return connector;
2217}
2218
00c09d70
PZ		 2219void intel_ddi_init(struct drm_device *dev, enum port port)
2220{
876a8cdf 2221 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2222 struct intel_digital_port *intel_dig_port;
2223 struct intel_encoder *intel_encoder;
2224 struct drm_encoder *encoder;
311a2094
PZ		 2225 bool init_hdmi, init_dp;
2226
2227 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2228 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2229 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2230 if (!init_dp && !init_hdmi) {
f68d697e 2231 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 2232 port_name(port));
2233 init_hdmi = true;
2234 init_dp = true;
2235 }
00c09d70 2236
b14c5679 2237 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2238 if (!intel_dig_port)
2239 return;
2240
00c09d70
PZ		 2241 intel_encoder = &intel_dig_port->base;
2242 encoder = &intel_encoder->base;
2243
2244 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2245 DRM_MODE_ENCODER_TMDS);
00c09d70 2246
5bfe2ac0 2247 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2248 intel_encoder->enable = intel_enable_ddi;
2249 intel_encoder->pre_enable = intel_ddi_pre_enable;
2250 intel_encoder->disable = intel_disable_ddi;
2251 intel_encoder->post_disable = intel_ddi_post_disable;
2252 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2253 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2254
2255 intel_dig_port->port = port;
bcf53de4
SM		 2256 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2257 (DDI_BUF_PORT_REVERSAL |
2258 DDI_A_4_LANES);
00c09d70
PZ		 2259
2260 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2261 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2262 intel_encoder->cloneable = 0;
00c09d70
PZ		 2263 intel_encoder->hot_plug = intel_ddi_hot_plug;
2264
f68d697e
CW		 2265 if (init_dp) {
2266 if (!intel_ddi_init_dp_connector(intel_dig_port))
2267 goto err;
13cf5504 2268
f68d697e
CW		 2269 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2270 dev_priv->hpd_irq_port[port] = intel_dig_port;
2271 }
21a8e6a4 2272
311a2094
PZ		 2273 /* In theory we don't need the encoder->type check, but leave it just in
2274 * case we have some really bad VBTs... */
f68d697e
CW		 2275 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2276 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2277 goto err;
21a8e6a4 2278 }
f68d697e
CW		 2279
2280 return;
2281
2282err:
2283 drm_encoder_cleanup(encoder);
2284 kfree(intel_dig_port);
00c09d70 2285}
Linux kernel - Deliverables
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