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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
32 | * them for both DP and FDI transports, allowing those ports to | |
33 | * automatically adapt to HDMI connections as well | |
34 | */ | |
35 | static const u32 hsw_ddi_translations_dp[] = { | |
36 | 0x00FFFFFF, 0x0006000E, /* DP parameters */ | |
37 | 0x00D75FFF, 0x0005000A, | |
38 | 0x00C30FFF, 0x00040006, | |
39 | 0x80AAAFFF, 0x000B0000, | |
40 | 0x00FFFFFF, 0x0005000A, | |
41 | 0x00D75FFF, 0x000C0004, | |
42 | 0x80C30FFF, 0x000B0000, | |
43 | 0x00FFFFFF, 0x00040006, | |
44 | 0x80D75FFF, 0x000B0000, | |
45244b87 ED |
45 | }; |
46 | ||
47 | static const u32 hsw_ddi_translations_fdi[] = { | |
48 | 0x00FFFFFF, 0x0007000E, /* FDI parameters */ | |
49 | 0x00D75FFF, 0x000F000A, | |
50 | 0x00C30FFF, 0x00060006, | |
51 | 0x00AAAFFF, 0x001E0000, | |
52 | 0x00FFFFFF, 0x000F000A, | |
53 | 0x00D75FFF, 0x00160004, | |
54 | 0x00C30FFF, 0x001E0000, | |
55 | 0x00FFFFFF, 0x00060006, | |
56 | 0x00D75FFF, 0x001E0000, | |
6acab15a PZ |
57 | }; |
58 | ||
59 | static const u32 hsw_ddi_translations_hdmi[] = { | |
60 | /* Idx NT mV diff T mV diff db */ | |
61 | 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */ | |
62 | 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */ | |
63 | 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */ | |
64 | 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */ | |
65 | 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */ | |
66 | 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */ | |
67 | 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */ | |
68 | 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */ | |
69 | 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */ | |
70 | 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */ | |
71 | 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */ | |
72 | 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */ | |
45244b87 ED |
73 | }; |
74 | ||
20f4dbe4 | 75 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
fc914639 | 76 | { |
0bdee30e | 77 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
78 | int type = intel_encoder->type; |
79 | ||
174edf1f | 80 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || |
00c09d70 | 81 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
174edf1f PZ |
82 | struct intel_digital_port *intel_dig_port = |
83 | enc_to_dig_port(encoder); | |
84 | return intel_dig_port->port; | |
0bdee30e | 85 | |
fc914639 PZ |
86 | } else if (type == INTEL_OUTPUT_ANALOG) { |
87 | return PORT_E; | |
0bdee30e | 88 | |
fc914639 PZ |
89 | } else { |
90 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
91 | BUG(); | |
92 | } | |
93 | } | |
94 | ||
45244b87 ED |
95 | /* On Haswell, DDI port buffers must be programmed with correct values |
96 | * in advance. The buffer values are different for FDI and DP modes, | |
97 | * but the HDMI/DVI fields are shared among those. So we program the DDI | |
98 | * in either FDI or DP modes only, as HDMI connections will work with both | |
99 | * of those | |
100 | */ | |
ad8d270c | 101 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) |
45244b87 ED |
102 | { |
103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
104 | u32 reg; | |
105 | int i; | |
ad8d270c | 106 | const u32 *ddi_translations = (port == PORT_E) ? |
45244b87 | 107 | hsw_ddi_translations_fdi : |
ad8d270c | 108 | hsw_ddi_translations_dp; |
6acab15a | 109 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
45244b87 | 110 | |
f72d19f0 PZ |
111 | for (i = 0, reg = DDI_BUF_TRANS(port); |
112 | i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
45244b87 ED |
113 | I915_WRITE(reg, ddi_translations[i]); |
114 | reg += 4; | |
115 | } | |
6acab15a PZ |
116 | /* Entry 9 is for HDMI: */ |
117 | for (i = 0; i < 2; i++) { | |
118 | I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]); | |
119 | reg += 4; | |
120 | } | |
45244b87 ED |
121 | } |
122 | ||
123 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
124 | * mode and port E for FDI. | |
125 | */ | |
126 | void intel_prepare_ddi(struct drm_device *dev) | |
127 | { | |
128 | int port; | |
129 | ||
0d536cb4 PZ |
130 | if (!HAS_DDI(dev)) |
131 | return; | |
45244b87 | 132 | |
ad8d270c PZ |
133 | for (port = PORT_A; port <= PORT_E; port++) |
134 | intel_prepare_ddi_buffers(dev, port); | |
45244b87 | 135 | } |
c82e4d26 ED |
136 | |
137 | static const long hsw_ddi_buf_ctl_values[] = { | |
138 | DDI_BUF_EMP_400MV_0DB_HSW, | |
139 | DDI_BUF_EMP_400MV_3_5DB_HSW, | |
140 | DDI_BUF_EMP_400MV_6DB_HSW, | |
141 | DDI_BUF_EMP_400MV_9_5DB_HSW, | |
142 | DDI_BUF_EMP_600MV_0DB_HSW, | |
143 | DDI_BUF_EMP_600MV_3_5DB_HSW, | |
144 | DDI_BUF_EMP_600MV_6DB_HSW, | |
145 | DDI_BUF_EMP_800MV_0DB_HSW, | |
146 | DDI_BUF_EMP_800MV_3_5DB_HSW | |
147 | }; | |
148 | ||
248138b5 PZ |
149 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
150 | enum port port) | |
151 | { | |
152 | uint32_t reg = DDI_BUF_CTL(port); | |
153 | int i; | |
154 | ||
155 | for (i = 0; i < 8; i++) { | |
156 | udelay(1); | |
157 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
158 | return; | |
159 | } | |
160 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
161 | } | |
c82e4d26 ED |
162 | |
163 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
164 | * connection to the PCH-located connectors. For this, it is necessary to train | |
165 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
166 | * | |
167 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
168 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
169 | * DDI A (which is used for eDP) | |
170 | */ | |
171 | ||
172 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
173 | { | |
174 | struct drm_device *dev = crtc->dev; | |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
176 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
04945641 | 177 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 178 | |
04945641 PZ |
179 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
180 | * mode set "sequence for CRT port" document: | |
181 | * - TP1 to TP2 time with the default value | |
182 | * - FDI delay to 90h | |
8693a824 DL |
183 | * |
184 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 PZ |
185 | */ |
186 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
187 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
188 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
189 | ||
190 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 191 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 192 | FDI_RX_PLL_ENABLE | |
627eb5a3 | 193 | FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
04945641 PZ |
194 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
195 | POSTING_READ(_FDI_RXA_CTL); | |
196 | udelay(220); | |
197 | ||
198 | /* Switch from Rawclk to PCDclk */ | |
199 | rx_ctl_val |= FDI_PCDCLK; | |
200 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
201 | ||
202 | /* Configure Port Clock Select */ | |
203 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel); | |
204 | ||
205 | /* Start the training iterating through available voltages and emphasis, | |
206 | * testing each value twice. */ | |
207 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { | |
c82e4d26 ED |
208 | /* Configure DP_TP_CTL with auto-training */ |
209 | I915_WRITE(DP_TP_CTL(PORT_E), | |
210 | DP_TP_CTL_FDI_AUTOTRAIN | | |
211 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
212 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
213 | DP_TP_CTL_ENABLE); | |
214 | ||
876a8cdf DL |
215 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
216 | * DDI E does not support port reversal, the functionality is | |
217 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
218 | * port reversal bit */ | |
c82e4d26 | 219 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 220 | DDI_BUF_CTL_ENABLE | |
33d29b14 | 221 | ((intel_crtc->config.fdi_lanes - 1) << 1) | |
04945641 PZ |
222 | hsw_ddi_buf_ctl_values[i / 2]); |
223 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
c82e4d26 ED |
224 | |
225 | udelay(600); | |
226 | ||
04945641 PZ |
227 | /* Program PCH FDI Receiver TU */ |
228 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
229 | ||
230 | /* Enable PCH FDI Receiver with auto-training */ | |
231 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
232 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
233 | POSTING_READ(_FDI_RXA_CTL); | |
234 | ||
235 | /* Wait for FDI receiver lane calibration */ | |
236 | udelay(30); | |
237 | ||
238 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
239 | temp = I915_READ(_FDI_RXA_MISC); | |
240 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
241 | I915_WRITE(_FDI_RXA_MISC, temp); | |
242 | POSTING_READ(_FDI_RXA_MISC); | |
243 | ||
244 | /* Wait for FDI auto training time */ | |
245 | udelay(5); | |
c82e4d26 ED |
246 | |
247 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
248 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 249 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
c82e4d26 ED |
250 | |
251 | /* Enable normal pixel sending for FDI */ | |
252 | I915_WRITE(DP_TP_CTL(PORT_E), | |
04945641 PZ |
253 | DP_TP_CTL_FDI_AUTOTRAIN | |
254 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
255 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
256 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 257 | |
04945641 | 258 | return; |
c82e4d26 | 259 | } |
04945641 | 260 | |
248138b5 PZ |
261 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
262 | temp &= ~DDI_BUF_CTL_ENABLE; | |
263 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
264 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
265 | ||
04945641 | 266 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
267 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
268 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
269 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
270 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
271 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
272 | ||
273 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
274 | |
275 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
276 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
248138b5 | 277 | POSTING_READ(_FDI_RXA_CTL); |
04945641 PZ |
278 | |
279 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
280 | temp = I915_READ(_FDI_RXA_MISC); | |
281 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
282 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
283 | I915_WRITE(_FDI_RXA_MISC, temp); | |
248138b5 | 284 | POSTING_READ(_FDI_RXA_MISC); |
c82e4d26 ED |
285 | } |
286 | ||
04945641 | 287 | DRM_ERROR("FDI link training failed!\n"); |
c82e4d26 | 288 | } |
0e72a5b5 | 289 | |
c7d8be30 | 290 | static void intel_ddi_mode_set(struct intel_encoder *encoder) |
72662e10 | 291 | { |
c7d8be30 DV |
292 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
293 | int port = intel_ddi_get_encoder_port(encoder); | |
294 | int pipe = crtc->pipe; | |
295 | int type = encoder->type; | |
296 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
72662e10 | 297 | |
bf98a726 | 298 | DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n", |
247d89f6 | 299 | port_name(port), pipe_name(pipe)); |
72662e10 | 300 | |
c7d8be30 | 301 | crtc->eld_vld = false; |
247d89f6 | 302 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c7d8be30 | 303 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
876a8cdf | 304 | struct intel_digital_port *intel_dig_port = |
c7d8be30 | 305 | enc_to_dig_port(&encoder->base); |
4f07854d | 306 | |
bcf53de4 | 307 | intel_dp->DP = intel_dig_port->saved_port_bits | |
876a8cdf | 308 | DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; |
17aa6be9 | 309 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
247d89f6 | 310 | |
8fed6193 TI |
311 | if (intel_dp->has_audio) { |
312 | DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n", | |
c7d8be30 | 313 | pipe_name(crtc->pipe)); |
8fed6193 TI |
314 | |
315 | /* write eld */ | |
316 | DRM_DEBUG_DRIVER("DP audio: write eld information\n"); | |
c7d8be30 | 317 | intel_write_eld(&encoder->base, adjusted_mode); |
8fed6193 TI |
318 | } |
319 | ||
247d89f6 PZ |
320 | intel_dp_init_link_config(intel_dp); |
321 | ||
322 | } else if (type == INTEL_OUTPUT_HDMI) { | |
c7d8be30 | 323 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
247d89f6 PZ |
324 | |
325 | if (intel_hdmi->has_audio) { | |
326 | /* Proper support for digital audio needs a new logic | |
327 | * and a new set of registers, so we leave it for future | |
328 | * patch bombing. | |
329 | */ | |
330 | DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n", | |
c7d8be30 | 331 | pipe_name(crtc->pipe)); |
247d89f6 PZ |
332 | |
333 | /* write eld */ | |
334 | DRM_DEBUG_DRIVER("HDMI audio: write eld information\n"); | |
c7d8be30 | 335 | intel_write_eld(&encoder->base, adjusted_mode); |
247d89f6 | 336 | } |
72662e10 | 337 | |
c7d8be30 | 338 | intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); |
247d89f6 | 339 | } |
8d9ddbcb PZ |
340 | } |
341 | ||
342 | static struct intel_encoder * | |
343 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
344 | { | |
345 | struct drm_device *dev = crtc->dev; | |
346 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
347 | struct intel_encoder *intel_encoder, *ret = NULL; | |
348 | int num_encoders = 0; | |
349 | ||
350 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
351 | ret = intel_encoder; | |
352 | num_encoders++; | |
353 | } | |
354 | ||
355 | if (num_encoders != 1) | |
84f44ce7 VS |
356 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
357 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
358 | |
359 | BUG_ON(ret == NULL); | |
360 | return ret; | |
361 | } | |
362 | ||
6441ab5f PZ |
363 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) |
364 | { | |
365 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
366 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
367 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
368 | uint32_t val; | |
369 | ||
370 | switch (intel_crtc->ddi_pll_sel) { | |
371 | case PORT_CLK_SEL_SPLL: | |
372 | plls->spll_refcount--; | |
373 | if (plls->spll_refcount == 0) { | |
374 | DRM_DEBUG_KMS("Disabling SPLL\n"); | |
375 | val = I915_READ(SPLL_CTL); | |
376 | WARN_ON(!(val & SPLL_PLL_ENABLE)); | |
377 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | |
378 | POSTING_READ(SPLL_CTL); | |
379 | } | |
380 | break; | |
381 | case PORT_CLK_SEL_WRPLL1: | |
382 | plls->wrpll1_refcount--; | |
383 | if (plls->wrpll1_refcount == 0) { | |
384 | DRM_DEBUG_KMS("Disabling WRPLL 1\n"); | |
385 | val = I915_READ(WRPLL_CTL1); | |
386 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
387 | I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); | |
388 | POSTING_READ(WRPLL_CTL1); | |
389 | } | |
390 | break; | |
391 | case PORT_CLK_SEL_WRPLL2: | |
392 | plls->wrpll2_refcount--; | |
393 | if (plls->wrpll2_refcount == 0) { | |
394 | DRM_DEBUG_KMS("Disabling WRPLL 2\n"); | |
395 | val = I915_READ(WRPLL_CTL2); | |
396 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
397 | I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); | |
398 | POSTING_READ(WRPLL_CTL2); | |
399 | } | |
400 | break; | |
401 | } | |
402 | ||
403 | WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n"); | |
404 | WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n"); | |
405 | WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n"); | |
406 | ||
407 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE; | |
408 | } | |
409 | ||
1c0b85c5 DL |
410 | #define LC_FREQ 2700 |
411 | #define LC_FREQ_2K (LC_FREQ * 2000) | |
412 | ||
413 | #define P_MIN 2 | |
414 | #define P_MAX 64 | |
415 | #define P_INC 2 | |
416 | ||
417 | /* Constraints for PLL good behavior */ | |
418 | #define REF_MIN 48 | |
419 | #define REF_MAX 400 | |
420 | #define VCO_MIN 2400 | |
421 | #define VCO_MAX 4800 | |
422 | ||
423 | #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a)) | |
424 | ||
425 | struct wrpll_rnp { | |
426 | unsigned p, n2, r2; | |
427 | }; | |
428 | ||
429 | static unsigned wrpll_get_budget_for_freq(int clock) | |
6441ab5f | 430 | { |
1c0b85c5 DL |
431 | unsigned budget; |
432 | ||
433 | switch (clock) { | |
434 | case 25175000: | |
435 | case 25200000: | |
436 | case 27000000: | |
437 | case 27027000: | |
438 | case 37762500: | |
439 | case 37800000: | |
440 | case 40500000: | |
441 | case 40541000: | |
442 | case 54000000: | |
443 | case 54054000: | |
444 | case 59341000: | |
445 | case 59400000: | |
446 | case 72000000: | |
447 | case 74176000: | |
448 | case 74250000: | |
449 | case 81000000: | |
450 | case 81081000: | |
451 | case 89012000: | |
452 | case 89100000: | |
453 | case 108000000: | |
454 | case 108108000: | |
455 | case 111264000: | |
456 | case 111375000: | |
457 | case 148352000: | |
458 | case 148500000: | |
459 | case 162000000: | |
460 | case 162162000: | |
461 | case 222525000: | |
462 | case 222750000: | |
463 | case 296703000: | |
464 | case 297000000: | |
465 | budget = 0; | |
466 | break; | |
467 | case 233500000: | |
468 | case 245250000: | |
469 | case 247750000: | |
470 | case 253250000: | |
471 | case 298000000: | |
472 | budget = 1500; | |
473 | break; | |
474 | case 169128000: | |
475 | case 169500000: | |
476 | case 179500000: | |
477 | case 202000000: | |
478 | budget = 2000; | |
479 | break; | |
480 | case 256250000: | |
481 | case 262500000: | |
482 | case 270000000: | |
483 | case 272500000: | |
484 | case 273750000: | |
485 | case 280750000: | |
486 | case 281250000: | |
487 | case 286000000: | |
488 | case 291750000: | |
489 | budget = 4000; | |
490 | break; | |
491 | case 267250000: | |
492 | case 268500000: | |
493 | budget = 5000; | |
494 | break; | |
495 | default: | |
496 | budget = 1000; | |
497 | break; | |
498 | } | |
6441ab5f | 499 | |
1c0b85c5 DL |
500 | return budget; |
501 | } | |
502 | ||
503 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
504 | unsigned r2, unsigned n2, unsigned p, | |
505 | struct wrpll_rnp *best) | |
506 | { | |
507 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 508 | |
1c0b85c5 DL |
509 | /* No best (r,n,p) yet */ |
510 | if (best->p == 0) { | |
511 | best->p = p; | |
512 | best->n2 = n2; | |
513 | best->r2 = r2; | |
514 | return; | |
515 | } | |
6441ab5f | 516 | |
1c0b85c5 DL |
517 | /* |
518 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
519 | * freq2k. | |
520 | * | |
521 | * delta = 1e6 * | |
522 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
523 | * freq2k; | |
524 | * | |
525 | * and we would like delta <= budget. | |
526 | * | |
527 | * If the discrepancy is above the PPM-based budget, always prefer to | |
528 | * improve upon the previous solution. However, if you're within the | |
529 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
530 | */ | |
531 | a = freq2k * budget * p * r2; | |
532 | b = freq2k * budget * best->p * best->r2; | |
533 | diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2)); | |
534 | diff_best = ABS_DIFF((freq2k * best->p * best->r2), | |
535 | (LC_FREQ_2K * best->n2)); | |
536 | c = 1000000 * diff; | |
537 | d = 1000000 * diff_best; | |
538 | ||
539 | if (a < c && b < d) { | |
540 | /* If both are above the budget, pick the closer */ | |
541 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
542 | best->p = p; | |
543 | best->n2 = n2; | |
544 | best->r2 = r2; | |
545 | } | |
546 | } else if (a >= c && b < d) { | |
547 | /* If A is below the threshold but B is above it? Update. */ | |
548 | best->p = p; | |
549 | best->n2 = n2; | |
550 | best->r2 = r2; | |
551 | } else if (a >= c && b >= d) { | |
552 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
553 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
554 | best->p = p; | |
555 | best->n2 = n2; | |
556 | best->r2 = r2; | |
557 | } | |
558 | } | |
559 | /* Otherwise a < c && b >= d, do nothing */ | |
560 | } | |
561 | ||
562 | static void | |
563 | intel_ddi_calculate_wrpll(int clock /* in Hz */, | |
564 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
565 | { | |
566 | uint64_t freq2k; | |
567 | unsigned p, n2, r2; | |
568 | struct wrpll_rnp best = { 0, 0, 0 }; | |
569 | unsigned budget; | |
570 | ||
571 | freq2k = clock / 100; | |
572 | ||
573 | budget = wrpll_get_budget_for_freq(clock); | |
574 | ||
575 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
576 | * and directly pass the LC PLL to it. */ | |
577 | if (freq2k == 5400000) { | |
578 | *n2_out = 2; | |
579 | *p_out = 1; | |
580 | *r2_out = 2; | |
581 | return; | |
582 | } | |
583 | ||
584 | /* | |
585 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
586 | * the WR PLL. | |
587 | * | |
588 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
589 | * Injecting R2 = 2 * R gives: | |
590 | * REF_MAX * r2 > LC_FREQ * 2 and | |
591 | * REF_MIN * r2 < LC_FREQ * 2 | |
592 | * | |
593 | * Which means the desired boundaries for r2 are: | |
594 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
595 | * | |
596 | */ | |
597 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
598 | r2 <= LC_FREQ * 2 / REF_MIN; | |
599 | r2++) { | |
600 | ||
601 | /* | |
602 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
603 | * | |
604 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
605 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
606 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
607 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
608 | * | |
609 | * Which means the desired boundaries for n2 are: | |
610 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
611 | */ | |
612 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
613 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
614 | n2++) { | |
615 | ||
616 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
617 | wrpll_update_rnp(freq2k, budget, | |
618 | r2, n2, p, &best); | |
619 | } | |
620 | } | |
6441ab5f | 621 | |
1c0b85c5 DL |
622 | *n2_out = best.n2; |
623 | *p_out = best.p; | |
624 | *r2_out = best.r2; | |
6441ab5f | 625 | |
1c0b85c5 DL |
626 | DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n", |
627 | clock, *p_out, *n2_out, *r2_out); | |
6441ab5f PZ |
628 | } |
629 | ||
ff9a6750 | 630 | bool intel_ddi_pll_mode_set(struct drm_crtc *crtc) |
6441ab5f PZ |
631 | { |
632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
633 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
068759bd | 634 | struct drm_encoder *encoder = &intel_encoder->base; |
6441ab5f PZ |
635 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
636 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
637 | int type = intel_encoder->type; | |
638 | enum pipe pipe = intel_crtc->pipe; | |
639 | uint32_t reg, val; | |
ff9a6750 | 640 | int clock = intel_crtc->config.port_clock; |
6441ab5f PZ |
641 | |
642 | /* TODO: reuse PLLs when possible (compare values) */ | |
643 | ||
644 | intel_ddi_put_crtc_pll(crtc); | |
645 | ||
068759bd PZ |
646 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
647 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
648 | ||
649 | switch (intel_dp->link_bw) { | |
650 | case DP_LINK_BW_1_62: | |
651 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; | |
652 | break; | |
653 | case DP_LINK_BW_2_7: | |
654 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; | |
655 | break; | |
656 | case DP_LINK_BW_5_4: | |
657 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; | |
658 | break; | |
659 | default: | |
660 | DRM_ERROR("Link bandwidth %d unsupported\n", | |
661 | intel_dp->link_bw); | |
662 | return false; | |
663 | } | |
664 | ||
665 | /* We don't need to turn any PLL on because we'll use LCPLL. */ | |
666 | return true; | |
667 | ||
668 | } else if (type == INTEL_OUTPUT_HDMI) { | |
1c0b85c5 | 669 | unsigned p, n2, r2; |
6441ab5f PZ |
670 | |
671 | if (plls->wrpll1_refcount == 0) { | |
672 | DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", | |
673 | pipe_name(pipe)); | |
674 | plls->wrpll1_refcount++; | |
675 | reg = WRPLL_CTL1; | |
676 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1; | |
677 | } else if (plls->wrpll2_refcount == 0) { | |
678 | DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", | |
679 | pipe_name(pipe)); | |
680 | plls->wrpll2_refcount++; | |
681 | reg = WRPLL_CTL2; | |
682 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2; | |
683 | } else { | |
684 | DRM_ERROR("No WRPLLs available!\n"); | |
685 | return false; | |
686 | } | |
687 | ||
688 | WARN(I915_READ(reg) & WRPLL_PLL_ENABLE, | |
689 | "WRPLL already enabled\n"); | |
690 | ||
1c0b85c5 | 691 | intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
6441ab5f PZ |
692 | |
693 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | | |
694 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | | |
695 | WRPLL_DIVIDER_POST(p); | |
696 | ||
697 | } else if (type == INTEL_OUTPUT_ANALOG) { | |
698 | if (plls->spll_refcount == 0) { | |
699 | DRM_DEBUG_KMS("Using SPLL on pipe %c\n", | |
700 | pipe_name(pipe)); | |
701 | plls->spll_refcount++; | |
702 | reg = SPLL_CTL; | |
703 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; | |
00037c2e DL |
704 | } else { |
705 | DRM_ERROR("SPLL already in use\n"); | |
706 | return false; | |
6441ab5f PZ |
707 | } |
708 | ||
709 | WARN(I915_READ(reg) & SPLL_PLL_ENABLE, | |
710 | "SPLL already enabled\n"); | |
711 | ||
39bc66c9 | 712 | val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; |
6441ab5f PZ |
713 | |
714 | } else { | |
715 | WARN(1, "Invalid DDI encoder type %d\n", type); | |
716 | return false; | |
717 | } | |
718 | ||
719 | I915_WRITE(reg, val); | |
720 | udelay(20); | |
721 | ||
722 | return true; | |
723 | } | |
724 | ||
dae84799 PZ |
725 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
726 | { | |
727 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
728 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
729 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
3b117c8f | 730 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
dae84799 PZ |
731 | int type = intel_encoder->type; |
732 | uint32_t temp; | |
733 | ||
734 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | |
735 | ||
c9809791 | 736 | temp = TRANS_MSA_SYNC_CLK; |
965e0c48 | 737 | switch (intel_crtc->config.pipe_bpp) { |
dae84799 | 738 | case 18: |
c9809791 | 739 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
740 | break; |
741 | case 24: | |
c9809791 | 742 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
743 | break; |
744 | case 30: | |
c9809791 | 745 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
746 | break; |
747 | case 36: | |
c9809791 | 748 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
749 | break; |
750 | default: | |
4e53c2e0 | 751 | BUG(); |
dae84799 | 752 | } |
c9809791 | 753 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
754 | } |
755 | } | |
756 | ||
8228c251 | 757 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
758 | { |
759 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
760 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 761 | struct drm_encoder *encoder = &intel_encoder->base; |
8d9ddbcb PZ |
762 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
763 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 764 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
174edf1f | 765 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 766 | int type = intel_encoder->type; |
8d9ddbcb PZ |
767 | uint32_t temp; |
768 | ||
ad80a810 PZ |
769 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
770 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 771 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 772 | |
965e0c48 | 773 | switch (intel_crtc->config.pipe_bpp) { |
dfcef252 | 774 | case 18: |
ad80a810 | 775 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
776 | break; |
777 | case 24: | |
ad80a810 | 778 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
779 | break; |
780 | case 30: | |
ad80a810 | 781 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
782 | break; |
783 | case 36: | |
ad80a810 | 784 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
785 | break; |
786 | default: | |
4e53c2e0 | 787 | BUG(); |
dfcef252 | 788 | } |
72662e10 | 789 | |
a666283e | 790 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 791 | temp |= TRANS_DDI_PVSYNC; |
a666283e | 792 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 793 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 794 | |
e6f0bfc4 PZ |
795 | if (cpu_transcoder == TRANSCODER_EDP) { |
796 | switch (pipe) { | |
797 | case PIPE_A: | |
d6dd9eb1 DV |
798 | /* Can only use the always-on power well for eDP when |
799 | * not using the panel fitter, and when not using motion | |
800 | * blur mitigation (which we don't support). */ | |
fd4daa9c | 801 | if (intel_crtc->config.pch_pfit.enabled) |
d6dd9eb1 DV |
802 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
803 | else | |
804 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
805 | break; |
806 | case PIPE_B: | |
807 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
808 | break; | |
809 | case PIPE_C: | |
810 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
811 | break; | |
812 | default: | |
813 | BUG(); | |
814 | break; | |
815 | } | |
816 | } | |
817 | ||
7739c33b PZ |
818 | if (type == INTEL_OUTPUT_HDMI) { |
819 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
8d9ddbcb PZ |
820 | |
821 | if (intel_hdmi->has_hdmi_sink) | |
ad80a810 | 822 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 823 | else |
ad80a810 | 824 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 825 | |
7739c33b | 826 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 827 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
33d29b14 | 828 | temp |= (intel_crtc->config.fdi_lanes - 1) << 1; |
7739c33b PZ |
829 | |
830 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
831 | type == INTEL_OUTPUT_EDP) { | |
832 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
833 | ||
ad80a810 | 834 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
7739c33b | 835 | |
17aa6be9 | 836 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
8d9ddbcb | 837 | } else { |
84f44ce7 VS |
838 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
839 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
840 | } |
841 | ||
ad80a810 | 842 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 843 | } |
72662e10 | 844 | |
ad80a810 PZ |
845 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
846 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 847 | { |
ad80a810 | 848 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
849 | uint32_t val = I915_READ(reg); |
850 | ||
ad80a810 PZ |
851 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); |
852 | val |= TRANS_DDI_PORT_NONE; | |
8d9ddbcb | 853 | I915_WRITE(reg, val); |
72662e10 ED |
854 | } |
855 | ||
bcbc889b PZ |
856 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
857 | { | |
858 | struct drm_device *dev = intel_connector->base.dev; | |
859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
860 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
861 | int type = intel_connector->base.connector_type; | |
862 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
863 | enum pipe pipe = 0; | |
864 | enum transcoder cpu_transcoder; | |
865 | uint32_t tmp; | |
866 | ||
867 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) | |
868 | return false; | |
869 | ||
870 | if (port == PORT_A) | |
871 | cpu_transcoder = TRANSCODER_EDP; | |
872 | else | |
1a240d4d | 873 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
874 | |
875 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
876 | ||
877 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
878 | case TRANS_DDI_MODE_SELECT_HDMI: | |
879 | case TRANS_DDI_MODE_SELECT_DVI: | |
880 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
881 | ||
882 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
883 | if (type == DRM_MODE_CONNECTOR_eDP) | |
884 | return true; | |
885 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
886 | return (type == DRM_MODE_CONNECTOR_DisplayPort); | |
887 | ||
888 | case TRANS_DDI_MODE_SELECT_FDI: | |
889 | return (type == DRM_MODE_CONNECTOR_VGA); | |
890 | ||
891 | default: | |
892 | return false; | |
893 | } | |
894 | } | |
895 | ||
85234cdc DV |
896 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
897 | enum pipe *pipe) | |
898 | { | |
899 | struct drm_device *dev = encoder->base.dev; | |
900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 901 | enum port port = intel_ddi_get_encoder_port(encoder); |
85234cdc DV |
902 | u32 tmp; |
903 | int i; | |
904 | ||
fe43d3f5 | 905 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
906 | |
907 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
908 | return false; | |
909 | ||
ad80a810 PZ |
910 | if (port == PORT_A) { |
911 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 912 | |
ad80a810 PZ |
913 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
914 | case TRANS_DDI_EDP_INPUT_A_ON: | |
915 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
916 | *pipe = PIPE_A; | |
917 | break; | |
918 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
919 | *pipe = PIPE_B; | |
920 | break; | |
921 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
922 | *pipe = PIPE_C; | |
923 | break; | |
924 | } | |
925 | ||
926 | return true; | |
927 | } else { | |
928 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
929 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
930 | ||
931 | if ((tmp & TRANS_DDI_PORT_MASK) | |
932 | == TRANS_DDI_SELECT_PORT(port)) { | |
933 | *pipe = i; | |
934 | return true; | |
935 | } | |
85234cdc DV |
936 | } |
937 | } | |
938 | ||
84f44ce7 | 939 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 940 | |
22f9fe50 | 941 | return false; |
85234cdc DV |
942 | } |
943 | ||
6441ab5f PZ |
944 | static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, |
945 | enum pipe pipe) | |
946 | { | |
947 | uint32_t temp, ret; | |
a42f704b | 948 | enum port port = I915_MAX_PORTS; |
ad80a810 PZ |
949 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
950 | pipe); | |
6441ab5f PZ |
951 | int i; |
952 | ||
ad80a810 PZ |
953 | if (cpu_transcoder == TRANSCODER_EDP) { |
954 | port = PORT_A; | |
955 | } else { | |
956 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
957 | temp &= TRANS_DDI_PORT_MASK; | |
958 | ||
959 | for (i = PORT_B; i <= PORT_E; i++) | |
960 | if (temp == TRANS_DDI_SELECT_PORT(i)) | |
961 | port = i; | |
962 | } | |
6441ab5f | 963 | |
a42f704b DL |
964 | if (port == I915_MAX_PORTS) { |
965 | WARN(1, "Pipe %c enabled on an unknown port\n", | |
966 | pipe_name(pipe)); | |
967 | ret = PORT_CLK_SEL_NONE; | |
968 | } else { | |
969 | ret = I915_READ(PORT_CLK_SEL(port)); | |
970 | DRM_DEBUG_KMS("Pipe %c connected to port %c using clock " | |
971 | "0x%08x\n", pipe_name(pipe), port_name(port), | |
972 | ret); | |
973 | } | |
6441ab5f PZ |
974 | |
975 | return ret; | |
976 | } | |
977 | ||
978 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev) | |
979 | { | |
980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
981 | enum pipe pipe; | |
982 | struct intel_crtc *intel_crtc; | |
983 | ||
984 | for_each_pipe(pipe) { | |
985 | intel_crtc = | |
986 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
987 | ||
988 | if (!intel_crtc->active) | |
989 | continue; | |
990 | ||
991 | intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv, | |
992 | pipe); | |
993 | ||
994 | switch (intel_crtc->ddi_pll_sel) { | |
995 | case PORT_CLK_SEL_SPLL: | |
996 | dev_priv->ddi_plls.spll_refcount++; | |
997 | break; | |
998 | case PORT_CLK_SEL_WRPLL1: | |
999 | dev_priv->ddi_plls.wrpll1_refcount++; | |
1000 | break; | |
1001 | case PORT_CLK_SEL_WRPLL2: | |
1002 | dev_priv->ddi_plls.wrpll2_refcount++; | |
1003 | break; | |
1004 | } | |
1005 | } | |
1006 | } | |
1007 | ||
fc914639 PZ |
1008 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1009 | { | |
1010 | struct drm_crtc *crtc = &intel_crtc->base; | |
1011 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1012 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1013 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
3b117c8f | 1014 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1015 | |
bb523fc0 PZ |
1016 | if (cpu_transcoder != TRANSCODER_EDP) |
1017 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1018 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1019 | } |
1020 | ||
1021 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1022 | { | |
1023 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3b117c8f | 1024 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1025 | |
bb523fc0 PZ |
1026 | if (cpu_transcoder != TRANSCODER_EDP) |
1027 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1028 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1029 | } |
1030 | ||
00c09d70 | 1031 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
6441ab5f | 1032 | { |
c19b0669 PZ |
1033 | struct drm_encoder *encoder = &intel_encoder->base; |
1034 | struct drm_crtc *crtc = encoder->crtc; | |
1035 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
6441ab5f PZ |
1036 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1037 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1038 | int type = intel_encoder->type; |
6441ab5f | 1039 | |
82a4d9c0 PZ |
1040 | if (type == INTEL_OUTPUT_EDP) { |
1041 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1042 | ironlake_edp_panel_vdd_on(intel_dp); | |
1043 | ironlake_edp_panel_on(intel_dp); | |
1044 | ironlake_edp_panel_vdd_off(intel_dp, true); | |
1045 | } | |
6441ab5f | 1046 | |
82a4d9c0 | 1047 | WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE); |
6441ab5f | 1048 | I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel); |
c19b0669 | 1049 | |
82a4d9c0 | 1050 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 PZ |
1051 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1052 | ||
1053 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1054 | intel_dp_start_link_train(intel_dp); | |
1055 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 ID |
1056 | if (port != PORT_A) |
1057 | intel_dp_stop_link_train(intel_dp); | |
c19b0669 | 1058 | } |
6441ab5f PZ |
1059 | } |
1060 | ||
00c09d70 | 1061 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
1062 | { |
1063 | struct drm_encoder *encoder = &intel_encoder->base; | |
1064 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1065 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1066 | int type = intel_encoder->type; |
2886e93f | 1067 | uint32_t val; |
a836bdf9 | 1068 | bool wait = false; |
2886e93f PZ |
1069 | |
1070 | val = I915_READ(DDI_BUF_CTL(port)); | |
1071 | if (val & DDI_BUF_CTL_ENABLE) { | |
1072 | val &= ~DDI_BUF_CTL_ENABLE; | |
1073 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1074 | wait = true; |
2886e93f | 1075 | } |
6441ab5f | 1076 | |
a836bdf9 PZ |
1077 | val = I915_READ(DP_TP_CTL(port)); |
1078 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1079 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1080 | I915_WRITE(DP_TP_CTL(port), val); | |
1081 | ||
1082 | if (wait) | |
1083 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1084 | ||
82a4d9c0 PZ |
1085 | if (type == INTEL_OUTPUT_EDP) { |
1086 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1087 | ironlake_edp_panel_vdd_on(intel_dp); | |
1088 | ironlake_edp_panel_off(intel_dp); | |
1089 | } | |
1090 | ||
6441ab5f PZ |
1091 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
1092 | } | |
1093 | ||
00c09d70 | 1094 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1095 | { |
6547fef8 | 1096 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1097 | struct drm_crtc *crtc = encoder->crtc; |
1098 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1099 | int pipe = intel_crtc->pipe; | |
6547fef8 | 1100 | struct drm_device *dev = encoder->dev; |
72662e10 | 1101 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1102 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1103 | int type = intel_encoder->type; | |
7b9f35a6 | 1104 | uint32_t tmp; |
72662e10 | 1105 | |
6547fef8 | 1106 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1107 | struct intel_digital_port *intel_dig_port = |
1108 | enc_to_dig_port(encoder); | |
1109 | ||
6547fef8 PZ |
1110 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1111 | * are ignored so nothing special needs to be done besides | |
1112 | * enabling the port. | |
1113 | */ | |
876a8cdf | 1114 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1115 | intel_dig_port->saved_port_bits | |
1116 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1117 | } else if (type == INTEL_OUTPUT_EDP) { |
1118 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1119 | ||
3ab9c637 ID |
1120 | if (port == PORT_A) |
1121 | intel_dp_stop_link_train(intel_dp); | |
1122 | ||
d6c50ff8 | 1123 | ironlake_edp_backlight_on(intel_dp); |
4906557e | 1124 | intel_edp_psr_enable(intel_dp); |
6547fef8 | 1125 | } |
7b9f35a6 | 1126 | |
c77bf565 | 1127 | if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) { |
7b9f35a6 WX |
1128 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
1129 | tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); | |
1130 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1131 | } | |
5ab432ef DV |
1132 | } |
1133 | ||
00c09d70 | 1134 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1135 | { |
d6c50ff8 | 1136 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1137 | struct drm_crtc *crtc = encoder->crtc; |
1138 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1139 | int pipe = intel_crtc->pipe; | |
d6c50ff8 | 1140 | int type = intel_encoder->type; |
7b9f35a6 WX |
1141 | struct drm_device *dev = encoder->dev; |
1142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1143 | uint32_t tmp; | |
d6c50ff8 | 1144 | |
c77bf565 PZ |
1145 | if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) { |
1146 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1147 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << | |
1148 | (pipe * 4)); | |
1149 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1150 | } | |
2831d842 | 1151 | |
d6c50ff8 PZ |
1152 | if (type == INTEL_OUTPUT_EDP) { |
1153 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1154 | ||
4906557e | 1155 | intel_edp_psr_disable(intel_dp); |
d6c50ff8 PZ |
1156 | ironlake_edp_backlight_off(intel_dp); |
1157 | } | |
72662e10 | 1158 | } |
79f689aa | 1159 | |
b8fc2f6a | 1160 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
79f689aa | 1161 | { |
a4006641 PZ |
1162 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
1163 | ||
1164 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
1165 | return 800000; | |
1166 | else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
b2b877ff | 1167 | return 450000; |
a4006641 | 1168 | else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450) |
b2b877ff | 1169 | return 450000; |
d567b07f | 1170 | else if (IS_ULT(dev_priv->dev)) |
b2b877ff | 1171 | return 337500; |
79f689aa | 1172 | else |
b2b877ff | 1173 | return 540000; |
79f689aa PZ |
1174 | } |
1175 | ||
1176 | void intel_ddi_pll_init(struct drm_device *dev) | |
1177 | { | |
1178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1179 | uint32_t val = I915_READ(LCPLL_CTL); | |
1180 | ||
1181 | /* The LCPLL register should be turned on by the BIOS. For now let's | |
1182 | * just check its state and print errors in case something is wrong. | |
1183 | * Don't even try to turn it on. | |
1184 | */ | |
1185 | ||
b2b877ff | 1186 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
79f689aa PZ |
1187 | intel_ddi_get_cdclk_freq(dev_priv)); |
1188 | ||
1189 | if (val & LCPLL_CD_SOURCE_FCLK) | |
1190 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
1191 | ||
1192 | if (val & LCPLL_PLL_DISABLE) | |
1193 | DRM_ERROR("LCPLL is disabled\n"); | |
1194 | } | |
c19b0669 PZ |
1195 | |
1196 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
1197 | { | |
174edf1f PZ |
1198 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
1199 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 1200 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 1201 | enum port port = intel_dig_port->port; |
c19b0669 | 1202 | uint32_t val; |
f3e227df | 1203 | bool wait = false; |
c19b0669 PZ |
1204 | |
1205 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1206 | val = I915_READ(DDI_BUF_CTL(port)); | |
1207 | if (val & DDI_BUF_CTL_ENABLE) { | |
1208 | val &= ~DDI_BUF_CTL_ENABLE; | |
1209 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1210 | wait = true; | |
1211 | } | |
1212 | ||
1213 | val = I915_READ(DP_TP_CTL(port)); | |
1214 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1215 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1216 | I915_WRITE(DP_TP_CTL(port), val); | |
1217 | POSTING_READ(DP_TP_CTL(port)); | |
1218 | ||
1219 | if (wait) | |
1220 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1221 | } | |
1222 | ||
1223 | val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | | |
1224 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; | |
1225 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) | |
1226 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
1227 | I915_WRITE(DP_TP_CTL(port), val); | |
1228 | POSTING_READ(DP_TP_CTL(port)); | |
1229 | ||
1230 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1231 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1232 | POSTING_READ(DDI_BUF_CTL(port)); | |
1233 | ||
1234 | udelay(600); | |
1235 | } | |
00c09d70 | 1236 | |
1ad960f2 PZ |
1237 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
1238 | { | |
1239 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1240 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1241 | uint32_t val; | |
1242 | ||
1243 | intel_ddi_post_disable(intel_encoder); | |
1244 | ||
1245 | val = I915_READ(_FDI_RXA_CTL); | |
1246 | val &= ~FDI_RX_ENABLE; | |
1247 | I915_WRITE(_FDI_RXA_CTL, val); | |
1248 | ||
1249 | val = I915_READ(_FDI_RXA_MISC); | |
1250 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1251 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1252 | I915_WRITE(_FDI_RXA_MISC, val); | |
1253 | ||
1254 | val = I915_READ(_FDI_RXA_CTL); | |
1255 | val &= ~FDI_PCDCLK; | |
1256 | I915_WRITE(_FDI_RXA_CTL, val); | |
1257 | ||
1258 | val = I915_READ(_FDI_RXA_CTL); | |
1259 | val &= ~FDI_RX_PLL_ENABLE; | |
1260 | I915_WRITE(_FDI_RXA_CTL, val); | |
1261 | } | |
1262 | ||
00c09d70 PZ |
1263 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
1264 | { | |
1265 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
1266 | int type = intel_encoder->type; | |
1267 | ||
1268 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) | |
1269 | intel_dp_check_link_status(intel_dp); | |
1270 | } | |
1271 | ||
045ac3b5 JB |
1272 | static void intel_ddi_get_config(struct intel_encoder *encoder, |
1273 | struct intel_crtc_config *pipe_config) | |
1274 | { | |
1275 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1276 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1277 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
1278 | u32 temp, flags = 0; | |
1279 | ||
1280 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1281 | if (temp & TRANS_DDI_PHSYNC) | |
1282 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1283 | else | |
1284 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1285 | if (temp & TRANS_DDI_PVSYNC) | |
1286 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1287 | else | |
1288 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1289 | ||
1290 | pipe_config->adjusted_mode.flags |= flags; | |
42571aef VS |
1291 | |
1292 | switch (temp & TRANS_DDI_BPC_MASK) { | |
1293 | case TRANS_DDI_BPC_6: | |
1294 | pipe_config->pipe_bpp = 18; | |
1295 | break; | |
1296 | case TRANS_DDI_BPC_8: | |
1297 | pipe_config->pipe_bpp = 24; | |
1298 | break; | |
1299 | case TRANS_DDI_BPC_10: | |
1300 | pipe_config->pipe_bpp = 30; | |
1301 | break; | |
1302 | case TRANS_DDI_BPC_12: | |
1303 | pipe_config->pipe_bpp = 36; | |
1304 | break; | |
1305 | default: | |
1306 | break; | |
1307 | } | |
eb14cb74 VS |
1308 | |
1309 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
1310 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1311 | case TRANS_DDI_MODE_SELECT_DVI: | |
1312 | case TRANS_DDI_MODE_SELECT_FDI: | |
1313 | break; | |
1314 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1315 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
1316 | pipe_config->has_dp_encoder = true; | |
1317 | intel_dp_get_m_n(intel_crtc, pipe_config); | |
1318 | break; | |
1319 | default: | |
1320 | break; | |
1321 | } | |
045ac3b5 JB |
1322 | } |
1323 | ||
00c09d70 PZ |
1324 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
1325 | { | |
1326 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
1327 | intel_dp_encoder_destroy(encoder); | |
1328 | } | |
1329 | ||
5bfe2ac0 DV |
1330 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
1331 | struct intel_crtc_config *pipe_config) | |
00c09d70 | 1332 | { |
5bfe2ac0 | 1333 | int type = encoder->type; |
eccb140b | 1334 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 1335 | |
5bfe2ac0 | 1336 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 1337 | |
eccb140b DV |
1338 | if (port == PORT_A) |
1339 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
1340 | ||
00c09d70 | 1341 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 1342 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 1343 | else |
5bfe2ac0 | 1344 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
1345 | } |
1346 | ||
1347 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
1348 | .destroy = intel_ddi_destroy, | |
1349 | }; | |
1350 | ||
00c09d70 PZ |
1351 | void intel_ddi_init(struct drm_device *dev, enum port port) |
1352 | { | |
876a8cdf | 1353 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
1354 | struct intel_digital_port *intel_dig_port; |
1355 | struct intel_encoder *intel_encoder; | |
1356 | struct drm_encoder *encoder; | |
1357 | struct intel_connector *hdmi_connector = NULL; | |
1358 | struct intel_connector *dp_connector = NULL; | |
1359 | ||
b14c5679 | 1360 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
1361 | if (!intel_dig_port) |
1362 | return; | |
1363 | ||
b14c5679 | 1364 | dp_connector = kzalloc(sizeof(*dp_connector), GFP_KERNEL); |
00c09d70 PZ |
1365 | if (!dp_connector) { |
1366 | kfree(intel_dig_port); | |
1367 | return; | |
1368 | } | |
1369 | ||
00c09d70 PZ |
1370 | intel_encoder = &intel_dig_port->base; |
1371 | encoder = &intel_encoder->base; | |
1372 | ||
1373 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
1374 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1375 | |
5bfe2ac0 | 1376 | intel_encoder->compute_config = intel_ddi_compute_config; |
c7d8be30 | 1377 | intel_encoder->mode_set = intel_ddi_mode_set; |
00c09d70 PZ |
1378 | intel_encoder->enable = intel_enable_ddi; |
1379 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
1380 | intel_encoder->disable = intel_disable_ddi; | |
1381 | intel_encoder->post_disable = intel_ddi_post_disable; | |
1382 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 1383 | intel_encoder->get_config = intel_ddi_get_config; |
00c09d70 PZ |
1384 | |
1385 | intel_dig_port->port = port; | |
bcf53de4 SM |
1386 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
1387 | (DDI_BUF_PORT_REVERSAL | | |
1388 | DDI_A_4_LANES); | |
00c09d70 PZ |
1389 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); |
1390 | ||
1391 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
1392 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1393 | intel_encoder->cloneable = false; | |
1394 | intel_encoder->hot_plug = intel_ddi_hot_plug; | |
1395 | ||
b2f246a8 | 1396 | if (!intel_dp_init_connector(intel_dig_port, dp_connector)) { |
15b1d171 PZ |
1397 | drm_encoder_cleanup(encoder); |
1398 | kfree(intel_dig_port); | |
b2f246a8 | 1399 | kfree(dp_connector); |
16c25533 | 1400 | return; |
b2f246a8 | 1401 | } |
21a8e6a4 DV |
1402 | |
1403 | if (intel_encoder->type != INTEL_OUTPUT_EDP) { | |
b14c5679 | 1404 | hdmi_connector = kzalloc(sizeof(*hdmi_connector), |
21a8e6a4 DV |
1405 | GFP_KERNEL); |
1406 | if (!hdmi_connector) { | |
1407 | return; | |
1408 | } | |
1409 | ||
1410 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
1411 | intel_hdmi_init_connector(intel_dig_port, hdmi_connector); | |
1412 | } | |
00c09d70 | 1413 | } |