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drm/i915/bdw: Broadwell has PIPEMISC
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
31/* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
34 */
35static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45244b87
ED		 45};
46
47static const u32 hsw_ddi_translations_fdi[] = {
48 0x00FFFFFF, 0x0007000E, /* FDI parameters */
49 0x00D75FFF, 0x000F000A,
50 0x00C30FFF, 0x00060006,
51 0x00AAAFFF, 0x001E0000,
52 0x00FFFFFF, 0x000F000A,
53 0x00D75FFF, 0x00160004,
54 0x00C30FFF, 0x001E0000,
55 0x00FFFFFF, 0x00060006,
56 0x00D75FFF, 0x001E0000,
6acab15a
PZ		 57};
58
59static const u32 hsw_ddi_translations_hdmi[] = {
60 /* Idx NT mV diff T mV diff db */
61 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */
62 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */
63 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */
64 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */
65 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */
66 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */
67 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */
68 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */
69 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */
70 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */
71 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */
72 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */
45244b87
ED		 73};
74
20f4dbe4 75enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
fc914639 76{
0bdee30e 77 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 78 int type = intel_encoder->type;
79
174edf1f 80 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 81 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
174edf1f
PZ		 82 struct intel_digital_port *intel_dig_port =
83 enc_to_dig_port(encoder);
84 return intel_dig_port->port;
0bdee30e 85
fc914639
PZ		 86 } else if (type == INTEL_OUTPUT_ANALOG) {
87 return PORT_E;
0bdee30e 88
fc914639
PZ		 89 } else {
90 DRM_ERROR("Invalid DDI encoder type %d\n", type);
91 BUG();
92 }
93}
94
45244b87
ED		 95/* On Haswell, DDI port buffers must be programmed with correct values
96 * in advance. The buffer values are different for FDI and DP modes,
97 * but the HDMI/DVI fields are shared among those. So we program the DDI
98 * in either FDI or DP modes only, as HDMI connections will work with both
99 * of those
100 */
ad8d270c 101static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
45244b87
ED		 102{
103 struct drm_i915_private *dev_priv = dev->dev_private;
104 u32 reg;
105 int i;
ad8d270c 106 const u32 *ddi_translations = (port == PORT_E) ?
45244b87 107 hsw_ddi_translations_fdi :
ad8d270c 108 hsw_ddi_translations_dp;
6acab15a 109 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
45244b87 110
f72d19f0
PZ		 111 for (i = 0, reg = DDI_BUF_TRANS(port);
112 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
45244b87
ED		 113 I915_WRITE(reg, ddi_translations[i]);
114 reg += 4;
115 }
6acab15a
PZ		 116 /* Entry 9 is for HDMI: */
117 for (i = 0; i < 2; i++) {
118 I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
119 reg += 4;
120 }
45244b87
ED		 121}
122
123/* Program DDI buffers translations for DP. By default, program ports A-D in DP
124 * mode and port E for FDI.
125 */
126void intel_prepare_ddi(struct drm_device *dev)
127{
128 int port;
129
0d536cb4
PZ		 130 if (!HAS_DDI(dev))
131 return;
45244b87 132
ad8d270c
PZ		 133 for (port = PORT_A; port <= PORT_E; port++)
134 intel_prepare_ddi_buffers(dev, port);
45244b87 135}
c82e4d26
ED		 136
137static const long hsw_ddi_buf_ctl_values[] = {
138 DDI_BUF_EMP_400MV_0DB_HSW,
139 DDI_BUF_EMP_400MV_3_5DB_HSW,
140 DDI_BUF_EMP_400MV_6DB_HSW,
141 DDI_BUF_EMP_400MV_9_5DB_HSW,
142 DDI_BUF_EMP_600MV_0DB_HSW,
143 DDI_BUF_EMP_600MV_3_5DB_HSW,
144 DDI_BUF_EMP_600MV_6DB_HSW,
145 DDI_BUF_EMP_800MV_0DB_HSW,
146 DDI_BUF_EMP_800MV_3_5DB_HSW
147};
148
248138b5
PZ		 149static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
150 enum port port)
151{
152 uint32_t reg = DDI_BUF_CTL(port);
153 int i;
154
155 for (i = 0; i < 8; i++) {
156 udelay(1);
157 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
158 return;
159 }
160 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
161}
c82e4d26
ED		 162
163/* Starting with Haswell, different DDI ports can work in FDI mode for
164 * connection to the PCH-located connectors. For this, it is necessary to train
165 * both the DDI port and PCH receiver for the desired DDI buffer settings.
166 *
167 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
168 * please note that when FDI mode is active on DDI E, it shares 2 lines with
169 * DDI A (which is used for eDP)
170 */
171
172void hsw_fdi_link_train(struct drm_crtc *crtc)
173{
174 struct drm_device *dev = crtc->dev;
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 177 u32 temp, i, rx_ctl_val;
c82e4d26 178
04945641
PZ		 179 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
180 * mode set "sequence for CRT port" document:
181 * - TP1 to TP2 time with the default value
182 * - FDI delay to 90h
8693a824
DL		 183 *
184 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 185 */
186 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
187 FDI_RX_PWRDN_LANE0_VAL(2) |
188 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
189
190 /* Enable the PCH Receiver FDI PLL */
3e68320e 191 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 192 FDI_RX_PLL_ENABLE |
627eb5a3 193 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
04945641
PZ		 194 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
195 POSTING_READ(_FDI_RXA_CTL);
196 udelay(220);
197
198 /* Switch from Rawclk to PCDclk */
199 rx_ctl_val |= FDI_PCDCLK;
200 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
201
202 /* Configure Port Clock Select */
203 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
204
205 /* Start the training iterating through available voltages and emphasis,
206 * testing each value twice. */
207 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
c82e4d26
ED		 208 /* Configure DP_TP_CTL with auto-training */
209 I915_WRITE(DP_TP_CTL(PORT_E),
210 DP_TP_CTL_FDI_AUTOTRAIN |
211 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
212 DP_TP_CTL_LINK_TRAIN_PAT1 |
213 DP_TP_CTL_ENABLE);
214
876a8cdf
DL		 215 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
216 * DDI E does not support port reversal, the functionality is
217 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
218 * port reversal bit */
c82e4d26 219 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 220 DDI_BUF_CTL_ENABLE |
33d29b14 221 ((intel_crtc->config.fdi_lanes - 1) << 1) |
04945641
PZ		 222 hsw_ddi_buf_ctl_values[i / 2]);
223 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 224
225 udelay(600);
226
04945641
PZ		 227 /* Program PCH FDI Receiver TU */
228 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
229
230 /* Enable PCH FDI Receiver with auto-training */
231 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
232 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
233 POSTING_READ(_FDI_RXA_CTL);
234
235 /* Wait for FDI receiver lane calibration */
236 udelay(30);
237
238 /* Unset FDI_RX_MISC pwrdn lanes */
239 temp = I915_READ(_FDI_RXA_MISC);
240 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
241 I915_WRITE(_FDI_RXA_MISC, temp);
242 POSTING_READ(_FDI_RXA_MISC);
243
244 /* Wait for FDI auto training time */
245 udelay(5);
c82e4d26
ED		 246
247 temp = I915_READ(DP_TP_STATUS(PORT_E));
248 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 249 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 250
251 /* Enable normal pixel sending for FDI */
252 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 253 DP_TP_CTL_FDI_AUTOTRAIN |
254 DP_TP_CTL_LINK_TRAIN_NORMAL |
255 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
256 DP_TP_CTL_ENABLE);
c82e4d26 257
04945641 258 return;
c82e4d26 259 }
04945641 260
248138b5
PZ		 261 temp = I915_READ(DDI_BUF_CTL(PORT_E));
262 temp &= ~DDI_BUF_CTL_ENABLE;
263 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
264 POSTING_READ(DDI_BUF_CTL(PORT_E));
265
04945641 266 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 267 temp = I915_READ(DP_TP_CTL(PORT_E));
268 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
269 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
270 I915_WRITE(DP_TP_CTL(PORT_E), temp);
271 POSTING_READ(DP_TP_CTL(PORT_E));
272
273 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 274
275 rx_ctl_val &= ~FDI_RX_ENABLE;
276 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 277 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 278
279 /* Reset FDI_RX_MISC pwrdn lanes */
280 temp = I915_READ(_FDI_RXA_MISC);
281 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
282 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
283 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 284 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 285 }
286
04945641 287 DRM_ERROR("FDI link training failed!\n");
c82e4d26 288}
0e72a5b5 289
c7d8be30 290static void intel_ddi_mode_set(struct intel_encoder *encoder)
72662e10 291{
c7d8be30
DV		 292 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
293 int port = intel_ddi_get_encoder_port(encoder);
294 int pipe = crtc->pipe;
295 int type = encoder->type;
296 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
72662e10 297
bf98a726 298 DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
247d89f6 299 port_name(port), pipe_name(pipe));
72662e10 300
c7d8be30 301 crtc->eld_vld = false;
247d89f6 302 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c7d8be30 303 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
876a8cdf 304 struct intel_digital_port *intel_dig_port =
c7d8be30 305 enc_to_dig_port(&encoder->base);
4f07854d 306
bcf53de4 307 intel_dp->DP = intel_dig_port->saved_port_bits |
876a8cdf 308 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
17aa6be9 309 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
247d89f6 310
8fed6193
TI		 311 if (intel_dp->has_audio) {
312 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
c7d8be30 313 pipe_name(crtc->pipe));
8fed6193
TI		 314
315 /* write eld */
316 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
c7d8be30 317 intel_write_eld(&encoder->base, adjusted_mode);
8fed6193 318 }
247d89f6 319 } else if (type == INTEL_OUTPUT_HDMI) {
c7d8be30 320 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
247d89f6
PZ		 321
322 if (intel_hdmi->has_audio) {
323 /* Proper support for digital audio needs a new logic
324 * and a new set of registers, so we leave it for future
325 * patch bombing.
326 */
327 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
c7d8be30 328 pipe_name(crtc->pipe));
247d89f6
PZ		 329
330 /* write eld */
331 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
c7d8be30 332 intel_write_eld(&encoder->base, adjusted_mode);
247d89f6 333 }
72662e10 334
c7d8be30 335 intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
247d89f6 336 }
8d9ddbcb
PZ		 337}
338
339static struct intel_encoder *
340intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
341{
342 struct drm_device *dev = crtc->dev;
343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
344 struct intel_encoder *intel_encoder, *ret = NULL;
345 int num_encoders = 0;
346
347 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
348 ret = intel_encoder;
349 num_encoders++;
350 }
351
352 if (num_encoders != 1)
84f44ce7
VS		 353 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
354 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 355
356 BUG_ON(ret == NULL);
357 return ret;
358}
359
6441ab5f
PZ		 360void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
361{
362 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
363 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
365 uint32_t val;
366
367 switch (intel_crtc->ddi_pll_sel) {
368 case PORT_CLK_SEL_SPLL:
369 plls->spll_refcount--;
370 if (plls->spll_refcount == 0) {
371 DRM_DEBUG_KMS("Disabling SPLL\n");
372 val = I915_READ(SPLL_CTL);
373 WARN_ON(!(val & SPLL_PLL_ENABLE));
374 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
375 POSTING_READ(SPLL_CTL);
376 }
377 break;
378 case PORT_CLK_SEL_WRPLL1:
379 plls->wrpll1_refcount--;
380 if (plls->wrpll1_refcount == 0) {
381 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
382 val = I915_READ(WRPLL_CTL1);
383 WARN_ON(!(val & WRPLL_PLL_ENABLE));
384 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
385 POSTING_READ(WRPLL_CTL1);
386 }
387 break;
388 case PORT_CLK_SEL_WRPLL2:
389 plls->wrpll2_refcount--;
390 if (plls->wrpll2_refcount == 0) {
391 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
392 val = I915_READ(WRPLL_CTL2);
393 WARN_ON(!(val & WRPLL_PLL_ENABLE));
394 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
395 POSTING_READ(WRPLL_CTL2);
396 }
397 break;
398 }
399
400 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
401 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
402 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
403
404 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
405}
406
1c0b85c5
DL		 407#define LC_FREQ 2700
408#define LC_FREQ_2K (LC_FREQ * 2000)
409
410#define P_MIN 2
411#define P_MAX 64
412#define P_INC 2
413
414/* Constraints for PLL good behavior */
415#define REF_MIN 48
416#define REF_MAX 400
417#define VCO_MIN 2400
418#define VCO_MAX 4800
419
420#define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
421
422struct wrpll_rnp {
423 unsigned p, n2, r2;
424};
425
426static unsigned wrpll_get_budget_for_freq(int clock)
6441ab5f 427{
1c0b85c5
DL		 428 unsigned budget;
429
430 switch (clock) {
431 case 25175000:
432 case 25200000:
433 case 27000000:
434 case 27027000:
435 case 37762500:
436 case 37800000:
437 case 40500000:
438 case 40541000:
439 case 54000000:
440 case 54054000:
441 case 59341000:
442 case 59400000:
443 case 72000000:
444 case 74176000:
445 case 74250000:
446 case 81000000:
447 case 81081000:
448 case 89012000:
449 case 89100000:
450 case 108000000:
451 case 108108000:
452 case 111264000:
453 case 111375000:
454 case 148352000:
455 case 148500000:
456 case 162000000:
457 case 162162000:
458 case 222525000:
459 case 222750000:
460 case 296703000:
461 case 297000000:
462 budget = 0;
463 break;
464 case 233500000:
465 case 245250000:
466 case 247750000:
467 case 253250000:
468 case 298000000:
469 budget = 1500;
470 break;
471 case 169128000:
472 case 169500000:
473 case 179500000:
474 case 202000000:
475 budget = 2000;
476 break;
477 case 256250000:
478 case 262500000:
479 case 270000000:
480 case 272500000:
481 case 273750000:
482 case 280750000:
483 case 281250000:
484 case 286000000:
485 case 291750000:
486 budget = 4000;
487 break;
488 case 267250000:
489 case 268500000:
490 budget = 5000;
491 break;
492 default:
493 budget = 1000;
494 break;
495 }
6441ab5f 496
1c0b85c5
DL		 497 return budget;
498}
499
500static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
501 unsigned r2, unsigned n2, unsigned p,
502 struct wrpll_rnp *best)
503{
504 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 505
1c0b85c5
DL		 506 /* No best (r,n,p) yet */
507 if (best->p == 0) {
508 best->p = p;
509 best->n2 = n2;
510 best->r2 = r2;
511 return;
512 }
6441ab5f 513
1c0b85c5
DL		 514 /*
515 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
516 * freq2k.
517 *
518 * delta = 1e6 *
519 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
520 * freq2k;
521 *
522 * and we would like delta <= budget.
523 *
524 * If the discrepancy is above the PPM-based budget, always prefer to
525 * improve upon the previous solution. However, if you're within the
526 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
527 */
528 a = freq2k * budget * p * r2;
529 b = freq2k * budget * best->p * best->r2;
530 diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
531 diff_best = ABS_DIFF((freq2k * best->p * best->r2),
532 (LC_FREQ_2K * best->n2));
533 c = 1000000 * diff;
534 d = 1000000 * diff_best;
535
536 if (a < c && b < d) {
537 /* If both are above the budget, pick the closer */
538 if (best->p * best->r2 * diff < p * r2 * diff_best) {
539 best->p = p;
540 best->n2 = n2;
541 best->r2 = r2;
542 }
543 } else if (a >= c && b < d) {
544 /* If A is below the threshold but B is above it? Update. */
545 best->p = p;
546 best->n2 = n2;
547 best->r2 = r2;
548 } else if (a >= c && b >= d) {
549 /* Both are below the limit, so pick the higher n2/(r2*r2) */
550 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
551 best->p = p;
552 best->n2 = n2;
553 best->r2 = r2;
554 }
555 }
556 /* Otherwise a < c && b >= d, do nothing */
557}
558
559static void
560intel_ddi_calculate_wrpll(int clock /* in Hz */,
561 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
562{
563 uint64_t freq2k;
564 unsigned p, n2, r2;
565 struct wrpll_rnp best = { 0, 0, 0 };
566 unsigned budget;
567
568 freq2k = clock / 100;
569
570 budget = wrpll_get_budget_for_freq(clock);
571
572 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
573 * and directly pass the LC PLL to it. */
574 if (freq2k == 5400000) {
575 *n2_out = 2;
576 *p_out = 1;
577 *r2_out = 2;
578 return;
579 }
580
581 /*
582 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
583 * the WR PLL.
584 *
585 * We want R so that REF_MIN <= Ref <= REF_MAX.
586 * Injecting R2 = 2 * R gives:
587 * REF_MAX * r2 > LC_FREQ * 2 and
588 * REF_MIN * r2 < LC_FREQ * 2
589 *
590 * Which means the desired boundaries for r2 are:
591 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
592 *
593 */
594 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
595 r2 <= LC_FREQ * 2 / REF_MIN;
596 r2++) {
597
598 /*
599 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
600 *
601 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
602 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
603 * VCO_MAX * r2 > n2 * LC_FREQ and
604 * VCO_MIN * r2 < n2 * LC_FREQ)
605 *
606 * Which means the desired boundaries for n2 are:
607 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
608 */
609 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
610 n2 <= VCO_MAX * r2 / LC_FREQ;
611 n2++) {
612
613 for (p = P_MIN; p <= P_MAX; p += P_INC)
614 wrpll_update_rnp(freq2k, budget,
615 r2, n2, p, &best);
616 }
617 }
6441ab5f 618
1c0b85c5
DL		 619 *n2_out = best.n2;
620 *p_out = best.p;
621 *r2_out = best.r2;
6441ab5f 622
1c0b85c5
DL		 623 DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n",
624 clock, *p_out, *n2_out, *r2_out);
6441ab5f
PZ		 625}
626
ff9a6750 627bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
6441ab5f
PZ		 628{
629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
630 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
068759bd 631 struct drm_encoder *encoder = &intel_encoder->base;
6441ab5f
PZ		 632 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
633 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
634 int type = intel_encoder->type;
635 enum pipe pipe = intel_crtc->pipe;
636 uint32_t reg, val;
ff9a6750 637 int clock = intel_crtc->config.port_clock;
6441ab5f
PZ		 638
639 /* TODO: reuse PLLs when possible (compare values) */
640
641 intel_ddi_put_crtc_pll(crtc);
642
068759bd
PZ		 643 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
644 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
645
646 switch (intel_dp->link_bw) {
647 case DP_LINK_BW_1_62:
648 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
649 break;
650 case DP_LINK_BW_2_7:
651 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
652 break;
653 case DP_LINK_BW_5_4:
654 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
655 break;
656 default:
657 DRM_ERROR("Link bandwidth %d unsupported\n",
658 intel_dp->link_bw);
659 return false;
660 }
661
662 /* We don't need to turn any PLL on because we'll use LCPLL. */
663 return true;
664
665 } else if (type == INTEL_OUTPUT_HDMI) {
1c0b85c5 666 unsigned p, n2, r2;
6441ab5f
PZ		 667
668 if (plls->wrpll1_refcount == 0) {
669 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
670 pipe_name(pipe));
671 plls->wrpll1_refcount++;
672 reg = WRPLL_CTL1;
673 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
674 } else if (plls->wrpll2_refcount == 0) {
675 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
676 pipe_name(pipe));
677 plls->wrpll2_refcount++;
678 reg = WRPLL_CTL2;
679 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
680 } else {
681 DRM_ERROR("No WRPLLs available!\n");
682 return false;
683 }
684
685 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
686 "WRPLL already enabled\n");
687
1c0b85c5 688 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
6441ab5f
PZ		 689
690 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
691 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
692 WRPLL_DIVIDER_POST(p);
693
694 } else if (type == INTEL_OUTPUT_ANALOG) {
695 if (plls->spll_refcount == 0) {
696 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
697 pipe_name(pipe));
698 plls->spll_refcount++;
699 reg = SPLL_CTL;
700 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
00037c2e
DL		 701 } else {
702 DRM_ERROR("SPLL already in use\n");
703 return false;
6441ab5f
PZ		 704 }
705
706 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
707 "SPLL already enabled\n");
708
39bc66c9 709 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
6441ab5f
PZ		 710
711 } else {
712 WARN(1, "Invalid DDI encoder type %d\n", type);
713 return false;
714 }
715
716 I915_WRITE(reg, val);
717 udelay(20);
718
719 return true;
720}
721
dae84799
PZ		 722void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
723{
724 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
726 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3b117c8f 727 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
dae84799
PZ		 728 int type = intel_encoder->type;
729 uint32_t temp;
730
731 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
732
c9809791 733 temp = TRANS_MSA_SYNC_CLK;
965e0c48 734 switch (intel_crtc->config.pipe_bpp) {
dae84799 735 case 18:
c9809791 736 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 737 break;
738 case 24:
c9809791 739 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 740 break;
741 case 30:
c9809791 742 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 743 break;
744 case 36:
c9809791 745 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 746 break;
747 default:
4e53c2e0 748 BUG();
dae84799 749 }
c9809791 750 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 751 }
752}
753
8228c251 754void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 755{
756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
757 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 758 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 759 struct drm_device *dev = crtc->dev;
760 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 761 enum pipe pipe = intel_crtc->pipe;
3b117c8f 762 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
174edf1f 763 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 764 int type = intel_encoder->type;
8d9ddbcb
PZ		 765 uint32_t temp;
766
ad80a810
PZ		 767 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
768 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 769 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 770
965e0c48 771 switch (intel_crtc->config.pipe_bpp) {
dfcef252 772 case 18:
ad80a810 773 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 774 break;
775 case 24:
ad80a810 776 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 777 break;
778 case 30:
ad80a810 779 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 780 break;
781 case 36:
ad80a810 782 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 783 break;
784 default:
4e53c2e0 785 BUG();
dfcef252 786 }
72662e10 787
a666283e 788 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 789 temp |= TRANS_DDI_PVSYNC;
a666283e 790 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 791 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 792
e6f0bfc4
PZ		 793 if (cpu_transcoder == TRANSCODER_EDP) {
794 switch (pipe) {
795 case PIPE_A:
c7670b10
PZ		 796 /* On Haswell, can only use the always-on power well for
797 * eDP when not using the panel fitter, and when not
798 * using motion blur mitigation (which we don't
799 * support). */
800 if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled)
d6dd9eb1
DV		 801 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
802 else
803 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 804 break;
805 case PIPE_B:
806 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
807 break;
808 case PIPE_C:
809 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
810 break;
811 default:
812 BUG();
813 break;
814 }
815 }
816
7739c33b
PZ		 817 if (type == INTEL_OUTPUT_HDMI) {
818 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
8d9ddbcb
PZ		 819
820 if (intel_hdmi->has_hdmi_sink)
ad80a810 821 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 822 else
ad80a810 823 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 824
7739c33b 825 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 826 temp |= TRANS_DDI_MODE_SELECT_FDI;
33d29b14 827 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
7739c33b
PZ		 828
829 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
830 type == INTEL_OUTPUT_EDP) {
831 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
832
ad80a810 833 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 834
17aa6be9 835 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 836 } else {
84f44ce7
VS		 837 WARN(1, "Invalid encoder type %d for pipe %c\n",
838 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 839 }
840
ad80a810 841 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 842}
72662e10 843
ad80a810
PZ		 844void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
845 enum transcoder cpu_transcoder)
8d9ddbcb 846{
ad80a810 847 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 848 uint32_t val = I915_READ(reg);
849
ad80a810
PZ		 850 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
851 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 852 I915_WRITE(reg, val);
72662e10
ED		 853}
854
bcbc889b
PZ		 855bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
856{
857 struct drm_device *dev = intel_connector->base.dev;
858 struct drm_i915_private *dev_priv = dev->dev_private;
859 struct intel_encoder *intel_encoder = intel_connector->encoder;
860 int type = intel_connector->base.connector_type;
861 enum port port = intel_ddi_get_encoder_port(intel_encoder);
862 enum pipe pipe = 0;
863 enum transcoder cpu_transcoder;
864 uint32_t tmp;
865
866 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
867 return false;
868
869 if (port == PORT_A)
870 cpu_transcoder = TRANSCODER_EDP;
871 else
1a240d4d 872 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 873
874 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
875
876 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
877 case TRANS_DDI_MODE_SELECT_HDMI:
878 case TRANS_DDI_MODE_SELECT_DVI:
879 return (type == DRM_MODE_CONNECTOR_HDMIA);
880
881 case TRANS_DDI_MODE_SELECT_DP_SST:
882 if (type == DRM_MODE_CONNECTOR_eDP)
883 return true;
884 case TRANS_DDI_MODE_SELECT_DP_MST:
885 return (type == DRM_MODE_CONNECTOR_DisplayPort);
886
887 case TRANS_DDI_MODE_SELECT_FDI:
888 return (type == DRM_MODE_CONNECTOR_VGA);
889
890 default:
891 return false;
892 }
893}
894
85234cdc
DV		 895bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
896 enum pipe *pipe)
897{
898 struct drm_device *dev = encoder->base.dev;
899 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 900 enum port port = intel_ddi_get_encoder_port(encoder);
85234cdc
DV		 901 u32 tmp;
902 int i;
903
fe43d3f5 904 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 905
906 if (!(tmp & DDI_BUF_CTL_ENABLE))
907 return false;
908
ad80a810
PZ		 909 if (port == PORT_A) {
910 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 911
ad80a810
PZ		 912 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
913 case TRANS_DDI_EDP_INPUT_A_ON:
914 case TRANS_DDI_EDP_INPUT_A_ONOFF:
915 *pipe = PIPE_A;
916 break;
917 case TRANS_DDI_EDP_INPUT_B_ONOFF:
918 *pipe = PIPE_B;
919 break;
920 case TRANS_DDI_EDP_INPUT_C_ONOFF:
921 *pipe = PIPE_C;
922 break;
923 }
924
925 return true;
926 } else {
927 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
928 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
929
930 if ((tmp & TRANS_DDI_PORT_MASK)
931 == TRANS_DDI_SELECT_PORT(port)) {
932 *pipe = i;
933 return true;
934 }
85234cdc
DV		 935 }
936 }
937
84f44ce7 938 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 939
22f9fe50 940 return false;
85234cdc
DV		 941}
942
6441ab5f
PZ		 943static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
944 enum pipe pipe)
945{
946 uint32_t temp, ret;
a42f704b 947 enum port port = I915_MAX_PORTS;
ad80a810
PZ		 948 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
949 pipe);
6441ab5f
PZ		 950 int i;
951
ad80a810
PZ		 952 if (cpu_transcoder == TRANSCODER_EDP) {
953 port = PORT_A;
954 } else {
955 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
956 temp &= TRANS_DDI_PORT_MASK;
957
958 for (i = PORT_B; i <= PORT_E; i++)
959 if (temp == TRANS_DDI_SELECT_PORT(i))
960 port = i;
961 }
6441ab5f 962
a42f704b
DL		 963 if (port == I915_MAX_PORTS) {
964 WARN(1, "Pipe %c enabled on an unknown port\n",
965 pipe_name(pipe));
966 ret = PORT_CLK_SEL_NONE;
967 } else {
968 ret = I915_READ(PORT_CLK_SEL(port));
969 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
970 "0x%08x\n", pipe_name(pipe), port_name(port),
971 ret);
972 }
6441ab5f
PZ		 973
974 return ret;
975}
976
977void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
978{
979 struct drm_i915_private *dev_priv = dev->dev_private;
980 enum pipe pipe;
981 struct intel_crtc *intel_crtc;
982
983 for_each_pipe(pipe) {
984 intel_crtc =
985 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
986
987 if (!intel_crtc->active)
988 continue;
989
990 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
991 pipe);
992
993 switch (intel_crtc->ddi_pll_sel) {
994 case PORT_CLK_SEL_SPLL:
995 dev_priv->ddi_plls.spll_refcount++;
996 break;
997 case PORT_CLK_SEL_WRPLL1:
998 dev_priv->ddi_plls.wrpll1_refcount++;
999 break;
1000 case PORT_CLK_SEL_WRPLL2:
1001 dev_priv->ddi_plls.wrpll2_refcount++;
1002 break;
1003 }
1004 }
1005}
1006
fc914639
PZ		 1007void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1008{
1009 struct drm_crtc *crtc = &intel_crtc->base;
1010 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1011 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1012 enum port port = intel_ddi_get_encoder_port(intel_encoder);
3b117c8f 1013 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
fc914639 1014
bb523fc0
PZ		 1015 if (cpu_transcoder != TRANSCODER_EDP)
1016 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1017 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1018}
1019
1020void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1021{
1022 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3b117c8f 1023 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
fc914639 1024
bb523fc0
PZ		 1025 if (cpu_transcoder != TRANSCODER_EDP)
1026 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1027 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1028}
1029
00c09d70 1030static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1031{
c19b0669
PZ		 1032 struct drm_encoder *encoder = &intel_encoder->base;
1033 struct drm_crtc *crtc = encoder->crtc;
1034 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
6441ab5f
PZ		 1035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1036 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1037 int type = intel_encoder->type;
6441ab5f 1038
82a4d9c0
PZ		 1039 if (type == INTEL_OUTPUT_EDP) {
1040 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1041 ironlake_edp_panel_vdd_on(intel_dp);
1042 ironlake_edp_panel_on(intel_dp);
1043 ironlake_edp_panel_vdd_off(intel_dp, true);
1044 }
6441ab5f 1045
82a4d9c0 1046 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
6441ab5f 1047 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
c19b0669 1048
82a4d9c0 1049 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669
PZ		 1050 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1051
1052 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1053 intel_dp_start_link_train(intel_dp);
1054 intel_dp_complete_link_train(intel_dp);
3ab9c637
ID		 1055 if (port != PORT_A)
1056 intel_dp_stop_link_train(intel_dp);
c19b0669 1057 }
6441ab5f
PZ		 1058}
1059
00c09d70 1060static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1061{
1062 struct drm_encoder *encoder = &intel_encoder->base;
1063 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1064 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1065 int type = intel_encoder->type;
2886e93f 1066 uint32_t val;
a836bdf9 1067 bool wait = false;
2886e93f
PZ		 1068
1069 val = I915_READ(DDI_BUF_CTL(port));
1070 if (val & DDI_BUF_CTL_ENABLE) {
1071 val &= ~DDI_BUF_CTL_ENABLE;
1072 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1073 wait = true;
2886e93f 1074 }
6441ab5f 1075
a836bdf9
PZ		 1076 val = I915_READ(DP_TP_CTL(port));
1077 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1078 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1079 I915_WRITE(DP_TP_CTL(port), val);
1080
1081 if (wait)
1082 intel_wait_ddi_buf_idle(dev_priv, port);
1083
82a4d9c0
PZ		 1084 if (type == INTEL_OUTPUT_EDP) {
1085 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1086 ironlake_edp_panel_vdd_on(intel_dp);
1087 ironlake_edp_panel_off(intel_dp);
1088 }
1089
6441ab5f
PZ		 1090 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1091}
1092
00c09d70 1093static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1094{
6547fef8 1095 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1096 struct drm_crtc *crtc = encoder->crtc;
1097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1098 int pipe = intel_crtc->pipe;
6547fef8 1099 struct drm_device *dev = encoder->dev;
72662e10 1100 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1101 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1102 int type = intel_encoder->type;
7b9f35a6 1103 uint32_t tmp;
72662e10 1104
6547fef8 1105 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1106 struct intel_digital_port *intel_dig_port =
1107 enc_to_dig_port(encoder);
1108
6547fef8
PZ		 1109 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1110 * are ignored so nothing special needs to be done besides
1111 * enabling the port.
1112 */
876a8cdf 1113 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1114 intel_dig_port->saved_port_bits |
1115 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1116 } else if (type == INTEL_OUTPUT_EDP) {
1117 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1118
3ab9c637
ID		 1119 if (port == PORT_A)
1120 intel_dp_stop_link_train(intel_dp);
1121
d6c50ff8 1122 ironlake_edp_backlight_on(intel_dp);
4906557e 1123 intel_edp_psr_enable(intel_dp);
6547fef8 1124 }
7b9f35a6 1125
c77bf565 1126 if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
7b9f35a6
WX		 1127 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1128 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1129 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1130 }
5ab432ef
DV		 1131}
1132
00c09d70 1133static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1134{
d6c50ff8 1135 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1136 struct drm_crtc *crtc = encoder->crtc;
1137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1138 int pipe = intel_crtc->pipe;
d6c50ff8 1139 int type = intel_encoder->type;
7b9f35a6
WX		 1140 struct drm_device *dev = encoder->dev;
1141 struct drm_i915_private *dev_priv = dev->dev_private;
1142 uint32_t tmp;
d6c50ff8 1143
c77bf565
PZ		 1144 if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1145 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1146 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1147 (pipe * 4));
1148 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1149 }
2831d842 1150
d6c50ff8
PZ		 1151 if (type == INTEL_OUTPUT_EDP) {
1152 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1153
4906557e 1154 intel_edp_psr_disable(intel_dp);
d6c50ff8
PZ		 1155 ironlake_edp_backlight_off(intel_dp);
1156 }
72662e10 1157}
79f689aa 1158
b8fc2f6a 1159int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
79f689aa 1160{
a4006641
PZ		 1161 uint32_t lcpll = I915_READ(LCPLL_CTL);
1162
1163 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1164 return 800000;
1165 else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
b2b877ff 1166 return 450000;
a4006641 1167 else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450)
b2b877ff 1168 return 450000;
d567b07f 1169 else if (IS_ULT(dev_priv->dev))
b2b877ff 1170 return 337500;
79f689aa 1171 else
b2b877ff 1172 return 540000;
79f689aa
PZ		 1173}
1174
1175void intel_ddi_pll_init(struct drm_device *dev)
1176{
1177 struct drm_i915_private *dev_priv = dev->dev_private;
1178 uint32_t val = I915_READ(LCPLL_CTL);
1179
1180 /* The LCPLL register should be turned on by the BIOS. For now let's
1181 * just check its state and print errors in case something is wrong.
1182 * Don't even try to turn it on.
1183 */
1184
b2b877ff 1185 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
79f689aa
PZ		 1186 intel_ddi_get_cdclk_freq(dev_priv));
1187
1188 if (val & LCPLL_CD_SOURCE_FCLK)
1189 DRM_ERROR("CDCLK source is not LCPLL\n");
1190
1191 if (val & LCPLL_PLL_DISABLE)
1192 DRM_ERROR("LCPLL is disabled\n");
1193}
c19b0669
PZ		 1194
1195void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1196{
174edf1f
PZ		 1197 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1198 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 1199 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 1200 enum port port = intel_dig_port->port;
c19b0669 1201 uint32_t val;
f3e227df 1202 bool wait = false;
c19b0669
PZ		 1203
1204 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1205 val = I915_READ(DDI_BUF_CTL(port));
1206 if (val & DDI_BUF_CTL_ENABLE) {
1207 val &= ~DDI_BUF_CTL_ENABLE;
1208 I915_WRITE(DDI_BUF_CTL(port), val);
1209 wait = true;
1210 }
1211
1212 val = I915_READ(DP_TP_CTL(port));
1213 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1214 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1215 I915_WRITE(DP_TP_CTL(port), val);
1216 POSTING_READ(DP_TP_CTL(port));
1217
1218 if (wait)
1219 intel_wait_ddi_buf_idle(dev_priv, port);
1220 }
1221
1222 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1223 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
6aba5b6c 1224 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
c19b0669
PZ		 1225 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1226 I915_WRITE(DP_TP_CTL(port), val);
1227 POSTING_READ(DP_TP_CTL(port));
1228
1229 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1230 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1231 POSTING_READ(DDI_BUF_CTL(port));
1232
1233 udelay(600);
1234}
00c09d70 1235
1ad960f2
PZ		 1236void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1237{
1238 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1239 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1240 uint32_t val;
1241
1242 intel_ddi_post_disable(intel_encoder);
1243
1244 val = I915_READ(_FDI_RXA_CTL);
1245 val &= ~FDI_RX_ENABLE;
1246 I915_WRITE(_FDI_RXA_CTL, val);
1247
1248 val = I915_READ(_FDI_RXA_MISC);
1249 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1250 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1251 I915_WRITE(_FDI_RXA_MISC, val);
1252
1253 val = I915_READ(_FDI_RXA_CTL);
1254 val &= ~FDI_PCDCLK;
1255 I915_WRITE(_FDI_RXA_CTL, val);
1256
1257 val = I915_READ(_FDI_RXA_CTL);
1258 val &= ~FDI_RX_PLL_ENABLE;
1259 I915_WRITE(_FDI_RXA_CTL, val);
1260}
1261
00c09d70
PZ		 1262static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1263{
1264 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1265 int type = intel_encoder->type;
1266
1267 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1268 intel_dp_check_link_status(intel_dp);
1269}
1270
6801c18c
VS		 1271void intel_ddi_get_config(struct intel_encoder *encoder,
1272 struct intel_crtc_config *pipe_config)
045ac3b5
JB		 1273{
1274 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1275 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1276 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1277 u32 temp, flags = 0;
1278
1279 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1280 if (temp & TRANS_DDI_PHSYNC)
1281 flags |= DRM_MODE_FLAG_PHSYNC;
1282 else
1283 flags |= DRM_MODE_FLAG_NHSYNC;
1284 if (temp & TRANS_DDI_PVSYNC)
1285 flags |= DRM_MODE_FLAG_PVSYNC;
1286 else
1287 flags |= DRM_MODE_FLAG_NVSYNC;
1288
1289 pipe_config->adjusted_mode.flags |= flags;
42571aef
VS		 1290
1291 switch (temp & TRANS_DDI_BPC_MASK) {
1292 case TRANS_DDI_BPC_6:
1293 pipe_config->pipe_bpp = 18;
1294 break;
1295 case TRANS_DDI_BPC_8:
1296 pipe_config->pipe_bpp = 24;
1297 break;
1298 case TRANS_DDI_BPC_10:
1299 pipe_config->pipe_bpp = 30;
1300 break;
1301 case TRANS_DDI_BPC_12:
1302 pipe_config->pipe_bpp = 36;
1303 break;
1304 default:
1305 break;
1306 }
eb14cb74
VS		 1307
1308 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1309 case TRANS_DDI_MODE_SELECT_HDMI:
1310 case TRANS_DDI_MODE_SELECT_DVI:
1311 case TRANS_DDI_MODE_SELECT_FDI:
1312 break;
1313 case TRANS_DDI_MODE_SELECT_DP_SST:
1314 case TRANS_DDI_MODE_SELECT_DP_MST:
1315 pipe_config->has_dp_encoder = true;
1316 intel_dp_get_m_n(intel_crtc, pipe_config);
1317 break;
1318 default:
1319 break;
1320 }
045ac3b5
JB		 1321}
1322
00c09d70
PZ		 1323static void intel_ddi_destroy(struct drm_encoder *encoder)
1324{
1325 /* HDMI has nothing special to destroy, so we can go with this. */
1326 intel_dp_encoder_destroy(encoder);
1327}
1328
5bfe2ac0
DV		 1329static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1330 struct intel_crtc_config *pipe_config)
00c09d70 1331{
5bfe2ac0 1332 int type = encoder->type;
eccb140b 1333 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 1334
5bfe2ac0 1335 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 1336
eccb140b
DV		 1337 if (port == PORT_A)
1338 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1339
00c09d70 1340 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 1341 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 1342 else
5bfe2ac0 1343 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 1344}
1345
1346static const struct drm_encoder_funcs intel_ddi_funcs = {
1347 .destroy = intel_ddi_destroy,
1348};
1349
4a28ae58
PZ		 1350static struct intel_connector *
1351intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1352{
1353 struct intel_connector *connector;
1354 enum port port = intel_dig_port->port;
1355
1356 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1357 if (!connector)
1358 return NULL;
1359
1360 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1361 if (!intel_dp_init_connector(intel_dig_port, connector)) {
1362 kfree(connector);
1363 return NULL;
1364 }
1365
1366 return connector;
1367}
1368
1369static struct intel_connector *
1370intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1371{
1372 struct intel_connector *connector;
1373 enum port port = intel_dig_port->port;
1374
1375 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1376 if (!connector)
1377 return NULL;
1378
1379 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1380 intel_hdmi_init_connector(intel_dig_port, connector);
1381
1382 return connector;
1383}
1384
00c09d70
PZ		 1385void intel_ddi_init(struct drm_device *dev, enum port port)
1386{
876a8cdf 1387 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 1388 struct intel_digital_port *intel_dig_port;
1389 struct intel_encoder *intel_encoder;
1390 struct drm_encoder *encoder;
1391 struct intel_connector *hdmi_connector = NULL;
1392 struct intel_connector *dp_connector = NULL;
311a2094
PZ		 1393 bool init_hdmi, init_dp;
1394
1395 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1396 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1397 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1398 if (!init_dp && !init_hdmi) {
1399 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
1400 port_name(port));
1401 init_hdmi = true;
1402 init_dp = true;
1403 }
00c09d70 1404
b14c5679 1405 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 1406 if (!intel_dig_port)
1407 return;
1408
00c09d70
PZ		 1409 intel_encoder = &intel_dig_port->base;
1410 encoder = &intel_encoder->base;
1411
1412 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1413 DRM_MODE_ENCODER_TMDS);
00c09d70 1414
5bfe2ac0 1415 intel_encoder->compute_config = intel_ddi_compute_config;
c7d8be30 1416 intel_encoder->mode_set = intel_ddi_mode_set;
00c09d70
PZ		 1417 intel_encoder->enable = intel_enable_ddi;
1418 intel_encoder->pre_enable = intel_ddi_pre_enable;
1419 intel_encoder->disable = intel_disable_ddi;
1420 intel_encoder->post_disable = intel_ddi_post_disable;
1421 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 1422 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 1423
1424 intel_dig_port->port = port;
bcf53de4
SM		 1425 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1426 (DDI_BUF_PORT_REVERSAL |
1427 DDI_A_4_LANES);
00c09d70
PZ		 1428
1429 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1430 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1431 intel_encoder->cloneable = false;
1432 intel_encoder->hot_plug = intel_ddi_hot_plug;
1433
4a28ae58
PZ		 1434 if (init_dp)
1435 dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
21a8e6a4 1436
311a2094
PZ		 1437 /* In theory we don't need the encoder->type check, but leave it just in
1438 * case we have some really bad VBTs... */
4a28ae58
PZ		 1439 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
1440 hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
21a8e6a4 1441
4a28ae58
PZ		 1442 if (!dp_connector && !hdmi_connector) {
1443 drm_encoder_cleanup(encoder);
1444 kfree(intel_dig_port);
21a8e6a4 1445 }
00c09d70 1446}
Linux kernel - Deliverables
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