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drm/i915: Don't depend on encoder->new_crtc in intel_hdmi_compute_config
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
45244b87
ED		 36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
10122051
JN		 40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
45244b87
ED		 50};
51
10122051
JN		 52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
6acab15a
PZ		 62};
63
10122051
JN		 64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
45244b87
ED		 78};
79
10122051
JN		 80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
300644c7
PZ		 90};
91
10122051
JN		 92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
17b523ba 98 { 0x00DB6FFF, 0x00160005 },
6805b2a7 99 { 0x80C71FFF, 0x001A0002 },
10122051
JN		 100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
e58623cb
AR		 102};
103
10122051
JN		 104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
e58623cb
AR		 114};
115
10122051
JN		 116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
a26aa8ba
DL		 128};
129
7f88e3af 130static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6c930688
DL		 131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
7f88e3af 133 { 0x00006012, 0x00000088 },
6c930688
DL		 134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
7f88e3af 136 { 0x00004014, 0x00000088 },
6c930688 137 { 0x00006012, 0x00000087 },
7f88e3af 138 { 0x00000018, 0x00000088 },
6c930688 139 { 0x00004014, 0x00000087 },
7f88e3af
DL		 140};
141
7ad14a29
SJ		 142/* eDP 1.4 low vswing translation parameters */
143static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
154};
155
156
7f88e3af
DL		 157static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
158 /* Idx NT mV T mV db */
7ff44670 159 { 0x00004014, 0x00000087 }, /* 0: 800 1000 2 */
7f88e3af
DL		 160};
161
20f4dbe4 162enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
fc914639 163{
0bdee30e 164 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 165 int type = intel_encoder->type;
166
0e32b39c
DA		 167 if (type == INTEL_OUTPUT_DP_MST) {
168 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
169 return intel_dig_port->port;
170 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 171 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
174edf1f
PZ		 172 struct intel_digital_port *intel_dig_port =
173 enc_to_dig_port(encoder);
174 return intel_dig_port->port;
0bdee30e 175
fc914639
PZ		 176 } else if (type == INTEL_OUTPUT_ANALOG) {
177 return PORT_E;
0bdee30e 178
fc914639
PZ		 179 } else {
180 DRM_ERROR("Invalid DDI encoder type %d\n", type);
181 BUG();
182 }
183}
184
e58623cb
AR		 185/*
186 * Starting with Haswell, DDI port buffers must be programmed with correct
187 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 188 * but the HDMI/DVI fields are shared among those. So we program the DDI
189 * in either FDI or DP modes only, as HDMI connections will work with both
190 * of those
191 */
ad8d270c 192static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
45244b87
ED		 193{
194 struct drm_i915_private *dev_priv = dev->dev_private;
195 u32 reg;
7ff44670 196 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 197 size;
6acab15a 198 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 199 const struct ddi_buf_trans *ddi_translations_fdi;
200 const struct ddi_buf_trans *ddi_translations_dp;
201 const struct ddi_buf_trans *ddi_translations_edp;
202 const struct ddi_buf_trans *ddi_translations_hdmi;
203 const struct ddi_buf_trans *ddi_translations;
e58623cb 204
7f88e3af
DL		 205 if (IS_SKYLAKE(dev)) {
206 ddi_translations_fdi = NULL;
207 ddi_translations_dp = skl_ddi_translations_dp;
7ad14a29
SJ		 208 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
209 if (dev_priv->vbt.edp_low_vswing) {
210 ddi_translations_edp = skl_ddi_translations_edp;
211 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
212 } else {
213 ddi_translations_edp = skl_ddi_translations_dp;
214 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
215 }
216
7ff44670
DL		 217 /*
218 * On SKL, the recommendation from the hw team is to always use
219 * a certain type of level shifter (and thus the corresponding
220 * 800mV+2dB entry). Given that's the only validated entry, we
221 * override what is in the VBT, at least until further notice.
222 */
223 hdmi_level = 0;
7f88e3af
DL		 224 ddi_translations_hdmi = skl_ddi_translations_hdmi;
225 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
7ff44670 226 hdmi_default_entry = 0;
7f88e3af 227 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 228 ddi_translations_fdi = bdw_ddi_translations_fdi;
229 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 230 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 231 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 232 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
233 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 234 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 235 hdmi_default_entry = 7;
e58623cb
AR		 236 } else if (IS_HASWELL(dev)) {
237 ddi_translations_fdi = hsw_ddi_translations_fdi;
238 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 239 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 240 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 241 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 242 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 243 hdmi_default_entry = 6;
e58623cb
AR		 244 } else {
245 WARN(1, "ddi translation table missing\n");
300644c7 246 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 247 ddi_translations_fdi = bdw_ddi_translations_fdi;
248 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 249 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 250 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
251 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 252 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 253 hdmi_default_entry = 7;
e58623cb
AR		 254 }
255
300644c7
PZ		 256 switch (port) {
257 case PORT_A:
258 ddi_translations = ddi_translations_edp;
7ad14a29 259 size = n_edp_entries;
300644c7
PZ		 260 break;
261 case PORT_B:
262 case PORT_C:
300644c7 263 ddi_translations = ddi_translations_dp;
7ad14a29 264 size = n_dp_entries;
300644c7 265 break;
77d8d009 266 case PORT_D:
7ad14a29 267 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 268 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 269 size = n_edp_entries;
270 } else {
77d8d009 271 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 272 size = n_dp_entries;
273 }
77d8d009 274 break;
300644c7 275 case PORT_E:
7f88e3af
DL		 276 if (ddi_translations_fdi)
277 ddi_translations = ddi_translations_fdi;
278 else
279 ddi_translations = ddi_translations_dp;
7ad14a29 280 size = n_dp_entries;
300644c7
PZ		 281 break;
282 default:
283 BUG();
284 }
45244b87 285
7ad14a29 286 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
10122051
JN		 287 I915_WRITE(reg, ddi_translations[i].trans1);
288 reg += 4;
289 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 290 reg += 4;
291 }
ce4dd49e
DL		 292
293 /* Choose a good default if VBT is badly populated */
294 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
295 hdmi_level >= n_hdmi_entries)
7ff44670 296 hdmi_level = hdmi_default_entry;
ce4dd49e 297
6acab15a 298 /* Entry 9 is for HDMI: */
10122051
JN		 299 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
300 reg += 4;
301 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
302 reg += 4;
45244b87
ED		 303}
304
305/* Program DDI buffers translations for DP. By default, program ports A-D in DP
306 * mode and port E for FDI.
307 */
308void intel_prepare_ddi(struct drm_device *dev)
309{
310 int port;
311
0d536cb4
PZ		 312 if (!HAS_DDI(dev))
313 return;
45244b87 314
ad8d270c
PZ		 315 for (port = PORT_A; port <= PORT_E; port++)
316 intel_prepare_ddi_buffers(dev, port);
45244b87 317}
c82e4d26 318
248138b5
PZ		 319static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
320 enum port port)
321{
322 uint32_t reg = DDI_BUF_CTL(port);
323 int i;
324
325 for (i = 0; i < 8; i++) {
326 udelay(1);
327 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
328 return;
329 }
330 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
331}
c82e4d26
ED		 332
333/* Starting with Haswell, different DDI ports can work in FDI mode for
334 * connection to the PCH-located connectors. For this, it is necessary to train
335 * both the DDI port and PCH receiver for the desired DDI buffer settings.
336 *
337 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
338 * please note that when FDI mode is active on DDI E, it shares 2 lines with
339 * DDI A (which is used for eDP)
340 */
341
342void hsw_fdi_link_train(struct drm_crtc *crtc)
343{
344 struct drm_device *dev = crtc->dev;
345 struct drm_i915_private *dev_priv = dev->dev_private;
346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 347 u32 temp, i, rx_ctl_val;
c82e4d26 348
04945641
PZ		 349 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
350 * mode set "sequence for CRT port" document:
351 * - TP1 to TP2 time with the default value
352 * - FDI delay to 90h
8693a824
DL		 353 *
354 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 355 */
356 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
357 FDI_RX_PWRDN_LANE0_VAL(2) |
358 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
359
360 /* Enable the PCH Receiver FDI PLL */
3e68320e 361 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 362 FDI_RX_PLL_ENABLE |
6e3c9717 363 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 364 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
365 POSTING_READ(_FDI_RXA_CTL);
366 udelay(220);
367
368 /* Switch from Rawclk to PCDclk */
369 rx_ctl_val |= FDI_PCDCLK;
370 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
371
372 /* Configure Port Clock Select */
6e3c9717
ACO		 373 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
374 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 375
376 /* Start the training iterating through available voltages and emphasis,
377 * testing each value twice. */
10122051 378 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 379 /* Configure DP_TP_CTL with auto-training */
380 I915_WRITE(DP_TP_CTL(PORT_E),
381 DP_TP_CTL_FDI_AUTOTRAIN |
382 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
383 DP_TP_CTL_LINK_TRAIN_PAT1 |
384 DP_TP_CTL_ENABLE);
385
876a8cdf
DL		 386 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
387 * DDI E does not support port reversal, the functionality is
388 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
389 * port reversal bit */
c82e4d26 390 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 391 DDI_BUF_CTL_ENABLE |
6e3c9717 392 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 393 DDI_BUF_TRANS_SELECT(i / 2));
04945641 394 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 395
396 udelay(600);
397
04945641
PZ		 398 /* Program PCH FDI Receiver TU */
399 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
400
401 /* Enable PCH FDI Receiver with auto-training */
402 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
403 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
404 POSTING_READ(_FDI_RXA_CTL);
405
406 /* Wait for FDI receiver lane calibration */
407 udelay(30);
408
409 /* Unset FDI_RX_MISC pwrdn lanes */
410 temp = I915_READ(_FDI_RXA_MISC);
411 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
412 I915_WRITE(_FDI_RXA_MISC, temp);
413 POSTING_READ(_FDI_RXA_MISC);
414
415 /* Wait for FDI auto training time */
416 udelay(5);
c82e4d26
ED		 417
418 temp = I915_READ(DP_TP_STATUS(PORT_E));
419 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 420 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 421
422 /* Enable normal pixel sending for FDI */
423 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 424 DP_TP_CTL_FDI_AUTOTRAIN |
425 DP_TP_CTL_LINK_TRAIN_NORMAL |
426 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
427 DP_TP_CTL_ENABLE);
c82e4d26 428
04945641 429 return;
c82e4d26 430 }
04945641 431
248138b5
PZ		 432 temp = I915_READ(DDI_BUF_CTL(PORT_E));
433 temp &= ~DDI_BUF_CTL_ENABLE;
434 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
435 POSTING_READ(DDI_BUF_CTL(PORT_E));
436
04945641 437 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 438 temp = I915_READ(DP_TP_CTL(PORT_E));
439 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
440 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
441 I915_WRITE(DP_TP_CTL(PORT_E), temp);
442 POSTING_READ(DP_TP_CTL(PORT_E));
443
444 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 445
446 rx_ctl_val &= ~FDI_RX_ENABLE;
447 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 448 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 449
450 /* Reset FDI_RX_MISC pwrdn lanes */
451 temp = I915_READ(_FDI_RXA_MISC);
452 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
453 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
454 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 455 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 456 }
457
04945641 458 DRM_ERROR("FDI link training failed!\n");
c82e4d26 459}
0e72a5b5 460
44905a27
DA		 461void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
462{
463 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
464 struct intel_digital_port *intel_dig_port =
465 enc_to_dig_port(&encoder->base);
466
467 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 468 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 469 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
470
471}
472
8d9ddbcb
PZ		 473static struct intel_encoder *
474intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
475{
476 struct drm_device *dev = crtc->dev;
477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
478 struct intel_encoder *intel_encoder, *ret = NULL;
479 int num_encoders = 0;
480
481 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
482 ret = intel_encoder;
483 num_encoders++;
484 }
485
486 if (num_encoders != 1)
84f44ce7
VS		 487 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
488 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 489
490 BUG_ON(ret == NULL);
491 return ret;
492}
493
d0737e1d
ACO		 494static struct intel_encoder *
495intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
496{
497 struct drm_device *dev = crtc->base.dev;
498 struct intel_encoder *intel_encoder, *ret = NULL;
499 int num_encoders = 0;
500
501 for_each_intel_encoder(dev, intel_encoder) {
502 if (intel_encoder->new_crtc == crtc) {
503 ret = intel_encoder;
504 num_encoders++;
505 }
506 }
507
508 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
509 pipe_name(crtc->pipe));
510
511 BUG_ON(ret == NULL);
512 return ret;
513}
514
1c0b85c5 515#define LC_FREQ 2700
27893390 516#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 517
518#define P_MIN 2
519#define P_MAX 64
520#define P_INC 2
521
522/* Constraints for PLL good behavior */
523#define REF_MIN 48
524#define REF_MAX 400
525#define VCO_MIN 2400
526#define VCO_MAX 4800
527
27893390
DL		 528#define abs_diff(a, b) ({ \
529 typeof(a) __a = (a); \
530 typeof(b) __b = (b); \
531 (void) (&__a == &__b); \
532 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5
DL		 533
534struct wrpll_rnp {
535 unsigned p, n2, r2;
536};
537
538static unsigned wrpll_get_budget_for_freq(int clock)
6441ab5f 539{
1c0b85c5
DL		 540 unsigned budget;
541
542 switch (clock) {
543 case 25175000:
544 case 25200000:
545 case 27000000:
546 case 27027000:
547 case 37762500:
548 case 37800000:
549 case 40500000:
550 case 40541000:
551 case 54000000:
552 case 54054000:
553 case 59341000:
554 case 59400000:
555 case 72000000:
556 case 74176000:
557 case 74250000:
558 case 81000000:
559 case 81081000:
560 case 89012000:
561 case 89100000:
562 case 108000000:
563 case 108108000:
564 case 111264000:
565 case 111375000:
566 case 148352000:
567 case 148500000:
568 case 162000000:
569 case 162162000:
570 case 222525000:
571 case 222750000:
572 case 296703000:
573 case 297000000:
574 budget = 0;
575 break;
576 case 233500000:
577 case 245250000:
578 case 247750000:
579 case 253250000:
580 case 298000000:
581 budget = 1500;
582 break;
583 case 169128000:
584 case 169500000:
585 case 179500000:
586 case 202000000:
587 budget = 2000;
588 break;
589 case 256250000:
590 case 262500000:
591 case 270000000:
592 case 272500000:
593 case 273750000:
594 case 280750000:
595 case 281250000:
596 case 286000000:
597 case 291750000:
598 budget = 4000;
599 break;
600 case 267250000:
601 case 268500000:
602 budget = 5000;
603 break;
604 default:
605 budget = 1000;
606 break;
607 }
6441ab5f 608
1c0b85c5
DL		 609 return budget;
610}
611
612static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
613 unsigned r2, unsigned n2, unsigned p,
614 struct wrpll_rnp *best)
615{
616 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 617
1c0b85c5
DL		 618 /* No best (r,n,p) yet */
619 if (best->p == 0) {
620 best->p = p;
621 best->n2 = n2;
622 best->r2 = r2;
623 return;
624 }
6441ab5f 625
1c0b85c5
DL		 626 /*
627 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
628 * freq2k.
629 *
630 * delta = 1e6 *
631 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
632 * freq2k;
633 *
634 * and we would like delta <= budget.
635 *
636 * If the discrepancy is above the PPM-based budget, always prefer to
637 * improve upon the previous solution. However, if you're within the
638 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
639 */
640 a = freq2k * budget * p * r2;
641 b = freq2k * budget * best->p * best->r2;
27893390
DL		 642 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
643 diff_best = abs_diff(freq2k * best->p * best->r2,
644 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 645 c = 1000000 * diff;
646 d = 1000000 * diff_best;
647
648 if (a < c && b < d) {
649 /* If both are above the budget, pick the closer */
650 if (best->p * best->r2 * diff < p * r2 * diff_best) {
651 best->p = p;
652 best->n2 = n2;
653 best->r2 = r2;
654 }
655 } else if (a >= c && b < d) {
656 /* If A is below the threshold but B is above it? Update. */
657 best->p = p;
658 best->n2 = n2;
659 best->r2 = r2;
660 } else if (a >= c && b >= d) {
661 /* Both are below the limit, so pick the higher n2/(r2*r2) */
662 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
663 best->p = p;
664 best->n2 = n2;
665 best->r2 = r2;
666 }
667 }
668 /* Otherwise a < c && b >= d, do nothing */
669}
670
11578553
JB		 671static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
672 int reg)
673{
674 int refclk = LC_FREQ;
675 int n, p, r;
676 u32 wrpll;
677
678 wrpll = I915_READ(reg);
114fe488
DV		 679 switch (wrpll & WRPLL_PLL_REF_MASK) {
680 case WRPLL_PLL_SSC:
681 case WRPLL_PLL_NON_SSC:
11578553
JB		 682 /*
683 * We could calculate spread here, but our checking
684 * code only cares about 5% accuracy, and spread is a max of
685 * 0.5% downspread.
686 */
687 refclk = 135;
688 break;
114fe488 689 case WRPLL_PLL_LCPLL:
11578553
JB		 690 refclk = LC_FREQ;
691 break;
692 default:
693 WARN(1, "bad wrpll refclk\n");
694 return 0;
695 }
696
697 r = wrpll & WRPLL_DIVIDER_REF_MASK;
698 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
699 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
700
20f0ec16
JB		 701 /* Convert to KHz, p & r have a fixed point portion */
702 return (refclk * n * 100) / (p * r);
11578553
JB		 703}
704
540e732c
S		 705static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
706 uint32_t dpll)
707{
708 uint32_t cfgcr1_reg, cfgcr2_reg;
709 uint32_t cfgcr1_val, cfgcr2_val;
710 uint32_t p0, p1, p2, dco_freq;
711
712 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
713 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
714
715 cfgcr1_val = I915_READ(cfgcr1_reg);
716 cfgcr2_val = I915_READ(cfgcr2_reg);
717
718 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
719 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
720
721 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
722 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
723 else
724 p1 = 1;
725
726
727 switch (p0) {
728 case DPLL_CFGCR2_PDIV_1:
729 p0 = 1;
730 break;
731 case DPLL_CFGCR2_PDIV_2:
732 p0 = 2;
733 break;
734 case DPLL_CFGCR2_PDIV_3:
735 p0 = 3;
736 break;
737 case DPLL_CFGCR2_PDIV_7:
738 p0 = 7;
739 break;
740 }
741
742 switch (p2) {
743 case DPLL_CFGCR2_KDIV_5:
744 p2 = 5;
745 break;
746 case DPLL_CFGCR2_KDIV_2:
747 p2 = 2;
748 break;
749 case DPLL_CFGCR2_KDIV_3:
750 p2 = 3;
751 break;
752 case DPLL_CFGCR2_KDIV_1:
753 p2 = 1;
754 break;
755 }
756
757 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
758
759 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
760 1000) / 0x8000;
761
762 return dco_freq / (p0 * p1 * p2 * 5);
763}
764
765
766static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 767 struct intel_crtc_state *pipe_config)
540e732c
S		 768{
769 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 770 int link_clock = 0;
771 uint32_t dpll_ctl1, dpll;
772
134ffa44 773 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 774
775 dpll_ctl1 = I915_READ(DPLL_CTRL1);
776
777 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
778 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
779 } else {
780 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
781 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
782
783 switch (link_clock) {
784 case DPLL_CRTL1_LINK_RATE_810:
785 link_clock = 81000;
786 break;
a8f3ef61
SJ		 787 case DPLL_CRTL1_LINK_RATE_1080:
788 link_clock = 108000;
789 break;
540e732c
S		 790 case DPLL_CRTL1_LINK_RATE_1350:
791 link_clock = 135000;
792 break;
a8f3ef61
SJ		 793 case DPLL_CRTL1_LINK_RATE_1620:
794 link_clock = 162000;
795 break;
796 case DPLL_CRTL1_LINK_RATE_2160:
797 link_clock = 216000;
798 break;
540e732c
S		 799 case DPLL_CRTL1_LINK_RATE_2700:
800 link_clock = 270000;
801 break;
802 default:
803 WARN(1, "Unsupported link rate\n");
804 break;
805 }
806 link_clock *= 2;
807 }
808
809 pipe_config->port_clock = link_clock;
810
811 if (pipe_config->has_dp_encoder)
2d112de7 812 pipe_config->base.adjusted_mode.crtc_clock =
540e732c
S		 813 intel_dotclock_calculate(pipe_config->port_clock,
814 &pipe_config->dp_m_n);
815 else
2d112de7 816 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
540e732c
S		 817}
818
3d51278a 819static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 820 struct intel_crtc_state *pipe_config)
11578553
JB		 821{
822 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 823 int link_clock = 0;
824 u32 val, pll;
825
26804afd 826 val = pipe_config->ddi_pll_sel;
11578553
JB		 827 switch (val & PORT_CLK_SEL_MASK) {
828 case PORT_CLK_SEL_LCPLL_810:
829 link_clock = 81000;
830 break;
831 case PORT_CLK_SEL_LCPLL_1350:
832 link_clock = 135000;
833 break;
834 case PORT_CLK_SEL_LCPLL_2700:
835 link_clock = 270000;
836 break;
837 case PORT_CLK_SEL_WRPLL1:
838 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
839 break;
840 case PORT_CLK_SEL_WRPLL2:
841 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
842 break;
843 case PORT_CLK_SEL_SPLL:
844 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
845 if (pll == SPLL_PLL_FREQ_810MHz)
846 link_clock = 81000;
847 else if (pll == SPLL_PLL_FREQ_1350MHz)
848 link_clock = 135000;
849 else if (pll == SPLL_PLL_FREQ_2700MHz)
850 link_clock = 270000;
851 else {
852 WARN(1, "bad spll freq\n");
853 return;
854 }
855 break;
856 default:
857 WARN(1, "bad port clock sel\n");
858 return;
859 }
860
861 pipe_config->port_clock = link_clock * 2;
862
863 if (pipe_config->has_pch_encoder)
2d112de7 864 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 865 intel_dotclock_calculate(pipe_config->port_clock,
866 &pipe_config->fdi_m_n);
867 else if (pipe_config->has_dp_encoder)
2d112de7 868 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 869 intel_dotclock_calculate(pipe_config->port_clock,
870 &pipe_config->dp_m_n);
871 else
2d112de7 872 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
11578553
JB		 873}
874
3d51278a 875void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 876 struct intel_crtc_state *pipe_config)
3d51278a 877{
22606a18
DL		 878 struct drm_device *dev = encoder->base.dev;
879
880 if (INTEL_INFO(dev)->gen <= 8)
881 hsw_ddi_clock_get(encoder, pipe_config);
882 else
883 skl_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 884}
885
1c0b85c5 886static void
d664c0ce
DL		 887hsw_ddi_calculate_wrpll(int clock /* in Hz */,
888 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 889{
890 uint64_t freq2k;
891 unsigned p, n2, r2;
892 struct wrpll_rnp best = { 0, 0, 0 };
893 unsigned budget;
894
895 freq2k = clock / 100;
896
897 budget = wrpll_get_budget_for_freq(clock);
898
899 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
900 * and directly pass the LC PLL to it. */
901 if (freq2k == 5400000) {
902 *n2_out = 2;
903 *p_out = 1;
904 *r2_out = 2;
905 return;
906 }
907
908 /*
909 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
910 * the WR PLL.
911 *
912 * We want R so that REF_MIN <= Ref <= REF_MAX.
913 * Injecting R2 = 2 * R gives:
914 * REF_MAX * r2 > LC_FREQ * 2 and
915 * REF_MIN * r2 < LC_FREQ * 2
916 *
917 * Which means the desired boundaries for r2 are:
918 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
919 *
920 */
921 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
922 r2 <= LC_FREQ * 2 / REF_MIN;
923 r2++) {
924
925 /*
926 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
927 *
928 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
929 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
930 * VCO_MAX * r2 > n2 * LC_FREQ and
931 * VCO_MIN * r2 < n2 * LC_FREQ)
932 *
933 * Which means the desired boundaries for n2 are:
934 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
935 */
936 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
937 n2 <= VCO_MAX * r2 / LC_FREQ;
938 n2++) {
939
940 for (p = P_MIN; p <= P_MAX; p += P_INC)
941 wrpll_update_rnp(freq2k, budget,
942 r2, n2, p, &best);
943 }
944 }
6441ab5f 945
1c0b85c5
DL		 946 *n2_out = best.n2;
947 *p_out = best.p;
948 *r2_out = best.r2;
6441ab5f
PZ		 949}
950
0220ab6e 951static bool
d664c0ce 952hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 953 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 954 struct intel_encoder *intel_encoder,
955 int clock)
6441ab5f 956{
d664c0ce 957 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 958 struct intel_shared_dpll *pll;
716c2e55 959 uint32_t val;
1c0b85c5 960 unsigned p, n2, r2;
6441ab5f 961
d664c0ce 962 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 963
114fe488 964 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 965 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
966 WRPLL_DIVIDER_POST(p);
967
190f68c5 968 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 969
190f68c5 970 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 971 if (pll == NULL) {
972 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
973 pipe_name(intel_crtc->pipe));
974 return false;
0694001b 975 }
d452c5b6 976
190f68c5 977 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 978 }
979
6441ab5f
PZ		 980 return true;
981}
982
82d35437
S		 983struct skl_wrpll_params {
984 uint32_t dco_fraction;
985 uint32_t dco_integer;
986 uint32_t qdiv_ratio;
987 uint32_t qdiv_mode;
988 uint32_t kdiv;
989 uint32_t pdiv;
990 uint32_t central_freq;
991};
992
993static void
994skl_ddi_calculate_wrpll(int clock /* in Hz */,
995 struct skl_wrpll_params *wrpll_params)
996{
997 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 998 uint64_t dco_central_freq[3] = {8400000000ULL,
999 9000000000ULL,
1000 9600000000ULL};
82d35437
S		 1001 uint32_t min_dco_deviation = 400;
1002 uint32_t min_dco_index = 3;
1003 uint32_t P0[4] = {1, 2, 3, 7};
1004 uint32_t P2[4] = {1, 2, 3, 5};
1005 bool found = false;
1006 uint32_t candidate_p = 0;
1007 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
1008 uint32_t candidate_p2[3] = {0};
1009 uint32_t dco_central_freq_deviation[3];
1010 uint32_t i, P1, k, dco_count;
1011 bool retry_with_odd = false;
1012 uint64_t dco_freq;
1013
1014 /* Determine P0, P1 or P2 */
1015 for (dco_count = 0; dco_count < 3; dco_count++) {
1016 found = false;
1017 candidate_p =
1018 div64_u64(dco_central_freq[dco_count], afe_clock);
1019 if (retry_with_odd == false)
1020 candidate_p = (candidate_p % 2 == 0 ?
1021 candidate_p : candidate_p + 1);
1022
1023 for (P1 = 1; P1 < candidate_p; P1++) {
1024 for (i = 0; i < 4; i++) {
1025 if (!(P0[i] != 1 || P1 == 1))
1026 continue;
1027
1028 for (k = 0; k < 4; k++) {
1029 if (P1 != 1 && P2[k] != 2)
1030 continue;
1031
1032 if (candidate_p == P0[i] * P1 * P2[k]) {
1033 /* Found possible P0, P1, P2 */
1034 found = true;
1035 candidate_p0[dco_count] = P0[i];
1036 candidate_p1[dco_count] = P1;
1037 candidate_p2[dco_count] = P2[k];
1038 goto found;
1039 }
1040
1041 }
1042 }
1043 }
1044
1045found:
1046 if (found) {
1047 dco_central_freq_deviation[dco_count] =
1048 div64_u64(10000 *
1049 abs_diff((candidate_p * afe_clock),
1050 dco_central_freq[dco_count]),
1051 dco_central_freq[dco_count]);
1052
1053 if (dco_central_freq_deviation[dco_count] <
1054 min_dco_deviation) {
1055 min_dco_deviation =
1056 dco_central_freq_deviation[dco_count];
1057 min_dco_index = dco_count;
1058 }
1059 }
1060
1061 if (min_dco_index > 2 && dco_count == 2) {
1062 retry_with_odd = true;
1063 dco_count = 0;
1064 }
1065 }
1066
1067 if (min_dco_index > 2) {
1068 WARN(1, "No valid values found for the given pixel clock\n");
1069 } else {
1070 wrpll_params->central_freq = dco_central_freq[min_dco_index];
1071
1072 switch (dco_central_freq[min_dco_index]) {
21318cce 1073 case 9600000000ULL:
82d35437
S		 1074 wrpll_params->central_freq = 0;
1075 break;
21318cce 1076 case 9000000000ULL:
82d35437
S		 1077 wrpll_params->central_freq = 1;
1078 break;
21318cce 1079 case 8400000000ULL:
82d35437
S		 1080 wrpll_params->central_freq = 3;
1081 }
1082
1083 switch (candidate_p0[min_dco_index]) {
1084 case 1:
1085 wrpll_params->pdiv = 0;
1086 break;
1087 case 2:
1088 wrpll_params->pdiv = 1;
1089 break;
1090 case 3:
1091 wrpll_params->pdiv = 2;
1092 break;
1093 case 7:
1094 wrpll_params->pdiv = 4;
1095 break;
1096 default:
1097 WARN(1, "Incorrect PDiv\n");
1098 }
1099
1100 switch (candidate_p2[min_dco_index]) {
1101 case 5:
1102 wrpll_params->kdiv = 0;
1103 break;
1104 case 2:
1105 wrpll_params->kdiv = 1;
1106 break;
1107 case 3:
1108 wrpll_params->kdiv = 2;
1109 break;
1110 case 1:
1111 wrpll_params->kdiv = 3;
1112 break;
1113 default:
1114 WARN(1, "Incorrect KDiv\n");
1115 }
1116
1117 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
1118 wrpll_params->qdiv_mode =
1119 (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
1120
1121 dco_freq = candidate_p0[min_dco_index] *
1122 candidate_p1[min_dco_index] *
1123 candidate_p2[min_dco_index] * afe_clock;
1124
1125 /*
1126 * Intermediate values are in Hz.
1127 * Divide by MHz to match bsepc
1128 */
1129 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
1130 wrpll_params->dco_fraction =
1131 div_u64(((div_u64(dco_freq, 24) -
1132 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
1133
1134 }
1135}
1136
1137
1138static bool
1139skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1140 struct intel_crtc_state *crtc_state,
82d35437
S		 1141 struct intel_encoder *intel_encoder,
1142 int clock)
1143{
1144 struct intel_shared_dpll *pll;
1145 uint32_t ctrl1, cfgcr1, cfgcr2;
1146
1147 /*
1148 * See comment in intel_dpll_hw_state to understand why we always use 0
1149 * as the DPLL id in this function.
1150 */
1151
1152 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1153
1154 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1155 struct skl_wrpll_params wrpll_params = { 0, };
1156
1157 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1158
1159 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
1160
1161 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1162 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1163 wrpll_params.dco_integer;
1164
1165 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1166 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1167 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1168 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1169 wrpll_params.central_freq;
1170 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1171 struct drm_encoder *encoder = &intel_encoder->base;
1172 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1173
1174 switch (intel_dp->link_bw) {
1175 case DP_LINK_BW_1_62:
1176 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
1177 break;
1178 case DP_LINK_BW_2_7:
1179 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
1180 break;
1181 case DP_LINK_BW_5_4:
1182 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
1183 break;
1184 }
1185
1186 cfgcr1 = cfgcr2 = 0;
1187 } else /* eDP */
1188 return true;
1189
190f68c5
ACO		 1190 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1191 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1192 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1193
190f68c5 1194 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1195 if (pll == NULL) {
1196 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1197 pipe_name(intel_crtc->pipe));
1198 return false;
1199 }
1200
1201 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1202 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1203
1204 return true;
1205}
0220ab6e
DL		 1206
1207/*
1208 * Tries to find a *shared* PLL for the CRTC and store it in
1209 * intel_crtc->ddi_pll_sel.
1210 *
1211 * For private DPLLs, compute_config() should do the selection for us. This
1212 * function should be folded into compute_config() eventually.
1213 */
190f68c5
ACO		 1214bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1215 struct intel_crtc_state *crtc_state)
0220ab6e 1216{
82d35437 1217 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d
ACO		 1218 struct intel_encoder *intel_encoder =
1219 intel_ddi_get_crtc_new_encoder(intel_crtc);
190f68c5 1220 int clock = crtc_state->port_clock;
0220ab6e 1221
82d35437 1222 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1223 return skl_ddi_pll_select(intel_crtc, crtc_state,
1224 intel_encoder, clock);
82d35437 1225 else
190f68c5
ACO		 1226 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1227 intel_encoder, clock);
0220ab6e
DL		 1228}
1229
dae84799
PZ		 1230void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1231{
1232 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1234 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1235 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1236 int type = intel_encoder->type;
1237 uint32_t temp;
1238
0e32b39c 1239 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1240 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1241 switch (intel_crtc->config->pipe_bpp) {
dae84799 1242 case 18:
c9809791 1243 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1244 break;
1245 case 24:
c9809791 1246 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1247 break;
1248 case 30:
c9809791 1249 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1250 break;
1251 case 36:
c9809791 1252 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1253 break;
1254 default:
4e53c2e0 1255 BUG();
dae84799 1256 }
c9809791 1257 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1258 }
1259}
1260
0e32b39c
DA		 1261void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1262{
1263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1264 struct drm_device *dev = crtc->dev;
1265 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1266 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1267 uint32_t temp;
1268 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1269 if (state == true)
1270 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1271 else
1272 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1273 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1274}
1275
8228c251 1276void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1277{
1278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1279 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1280 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1281 struct drm_device *dev = crtc->dev;
1282 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1283 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1284 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1285 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1286 int type = intel_encoder->type;
8d9ddbcb
PZ		 1287 uint32_t temp;
1288
ad80a810
PZ		 1289 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1290 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1291 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1292
6e3c9717 1293 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1294 case 18:
ad80a810 1295 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1296 break;
1297 case 24:
ad80a810 1298 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1299 break;
1300 case 30:
ad80a810 1301 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1302 break;
1303 case 36:
ad80a810 1304 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1305 break;
1306 default:
4e53c2e0 1307 BUG();
dfcef252 1308 }
72662e10 1309
6e3c9717 1310 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1311 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1312 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1313 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1314
e6f0bfc4
PZ		 1315 if (cpu_transcoder == TRANSCODER_EDP) {
1316 switch (pipe) {
1317 case PIPE_A:
c7670b10
PZ		 1318 /* On Haswell, can only use the always-on power well for
1319 * eDP when not using the panel fitter, and when not
1320 * using motion blur mitigation (which we don't
1321 * support). */
fabf6e51 1322 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1323 (intel_crtc->config->pch_pfit.enabled ||
1324 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1325 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1326 else
1327 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1328 break;
1329 case PIPE_B:
1330 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1331 break;
1332 case PIPE_C:
1333 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1334 break;
1335 default:
1336 BUG();
1337 break;
1338 }
1339 }
1340
7739c33b 1341 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1342 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1343 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1344 else
ad80a810 1345 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1346
7739c33b 1347 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1348 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1349 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1350
1351 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1352 type == INTEL_OUTPUT_EDP) {
1353 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1354
0e32b39c
DA		 1355 if (intel_dp->is_mst) {
1356 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1357 } else
1358 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1359
1360 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1361 } else if (type == INTEL_OUTPUT_DP_MST) {
1362 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1363
1364 if (intel_dp->is_mst) {
1365 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1366 } else
1367 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1368
17aa6be9 1369 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1370 } else {
84f44ce7
VS		 1371 WARN(1, "Invalid encoder type %d for pipe %c\n",
1372 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1373 }
1374
ad80a810 1375 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1376}
72662e10 1377
ad80a810
PZ		 1378void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1379 enum transcoder cpu_transcoder)
8d9ddbcb 1380{
ad80a810 1381 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1382 uint32_t val = I915_READ(reg);
1383
0e32b39c 1384 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1385 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1386 I915_WRITE(reg, val);
72662e10
ED		 1387}
1388
bcbc889b
PZ		 1389bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1390{
1391 struct drm_device *dev = intel_connector->base.dev;
1392 struct drm_i915_private *dev_priv = dev->dev_private;
1393 struct intel_encoder *intel_encoder = intel_connector->encoder;
1394 int type = intel_connector->base.connector_type;
1395 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1396 enum pipe pipe = 0;
1397 enum transcoder cpu_transcoder;
882244a3 1398 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1399 uint32_t tmp;
1400
882244a3 1401 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1402 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1403 return false;
1404
bcbc889b
PZ		 1405 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1406 return false;
1407
1408 if (port == PORT_A)
1409 cpu_transcoder = TRANSCODER_EDP;
1410 else
1a240d4d 1411 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1412
1413 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1414
1415 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1416 case TRANS_DDI_MODE_SELECT_HDMI:
1417 case TRANS_DDI_MODE_SELECT_DVI:
1418 return (type == DRM_MODE_CONNECTOR_HDMIA);
1419
1420 case TRANS_DDI_MODE_SELECT_DP_SST:
1421 if (type == DRM_MODE_CONNECTOR_eDP)
1422 return true;
bcbc889b 1423 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1424 case TRANS_DDI_MODE_SELECT_DP_MST:
1425 /* if the transcoder is in MST state then
1426 * connector isn't connected */
1427 return false;
bcbc889b
PZ		 1428
1429 case TRANS_DDI_MODE_SELECT_FDI:
1430 return (type == DRM_MODE_CONNECTOR_VGA);
1431
1432 default:
1433 return false;
1434 }
1435}
1436
85234cdc
DV		 1437bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1438 enum pipe *pipe)
1439{
1440 struct drm_device *dev = encoder->base.dev;
1441 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1442 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1443 enum intel_display_power_domain power_domain;
85234cdc
DV		 1444 u32 tmp;
1445 int i;
1446
6d129bea 1447 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1448 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1449 return false;
1450
fe43d3f5 1451 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1452
1453 if (!(tmp & DDI_BUF_CTL_ENABLE))
1454 return false;
1455
ad80a810
PZ		 1456 if (port == PORT_A) {
1457 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1458
ad80a810
PZ		 1459 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1460 case TRANS_DDI_EDP_INPUT_A_ON:
1461 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1462 *pipe = PIPE_A;
1463 break;
1464 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1465 *pipe = PIPE_B;
1466 break;
1467 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1468 *pipe = PIPE_C;
1469 break;
1470 }
1471
1472 return true;
1473 } else {
1474 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1475 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1476
1477 if ((tmp & TRANS_DDI_PORT_MASK)
1478 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 1479 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1480 return false;
1481
ad80a810
PZ		 1482 *pipe = i;
1483 return true;
1484 }
85234cdc
DV		 1485 }
1486 }
1487
84f44ce7 1488 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1489
22f9fe50 1490 return false;
85234cdc
DV		 1491}
1492
fc914639
PZ		 1493void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1494{
1495 struct drm_crtc *crtc = &intel_crtc->base;
1496 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1497 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1498 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1499 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1500
bb523fc0
PZ		 1501 if (cpu_transcoder != TRANSCODER_EDP)
1502 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1503 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1504}
1505
1506void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1507{
1508 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 1509 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1510
bb523fc0
PZ		 1511 if (cpu_transcoder != TRANSCODER_EDP)
1512 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1513 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1514}
1515
00c09d70 1516static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1517{
c19b0669 1518 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1519 struct drm_device *dev = encoder->dev;
1520 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 1521 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 1522 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1523 int type = intel_encoder->type;
6441ab5f 1524
82a4d9c0
PZ		 1525 if (type == INTEL_OUTPUT_EDP) {
1526 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1527 intel_edp_panel_on(intel_dp);
82a4d9c0 1528 }
6441ab5f 1529
efa80add 1530 if (IS_SKYLAKE(dev)) {
6e3c9717 1531 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 1532 uint32_t val;
1533
5416d871
DL		 1534 /*
1535 * DPLL0 is used for eDP and is the only "private" DPLL (as
1536 * opposed to shared) on SKL
1537 */
1538 if (type == INTEL_OUTPUT_EDP) {
1539 WARN_ON(dpll != SKL_DPLL0);
1540
1541 val = I915_READ(DPLL_CTRL1);
1542
1543 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1544 DPLL_CTRL1_SSC(dpll) |
1545 DPLL_CRTL1_LINK_RATE_MASK(dpll));
6e3c9717 1546 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 1547
1548 I915_WRITE(DPLL_CTRL1, val);
1549 POSTING_READ(DPLL_CTRL1);
1550 }
1551
1552 /* DDI -> PLL mapping */
efa80add
S		 1553 val = I915_READ(DPLL_CTRL2);
1554
1555 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1556 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1557 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1558 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1559
1560 I915_WRITE(DPLL_CTRL2, val);
5416d871 1561
efa80add 1562 } else {
6e3c9717
ACO		 1563 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1564 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 1565 }
c19b0669 1566
82a4d9c0 1567 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 1568 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1569
44905a27 1570 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1571
1572 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1573 intel_dp_start_link_train(intel_dp);
1574 intel_dp_complete_link_train(intel_dp);
23f08d83 1575 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 1576 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1577 } else if (type == INTEL_OUTPUT_HDMI) {
1578 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1579
1580 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 1581 crtc->config->has_hdmi_sink,
1582 &crtc->config->base.adjusted_mode);
c19b0669 1583 }
6441ab5f
PZ		 1584}
1585
00c09d70 1586static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1587{
1588 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1589 struct drm_device *dev = encoder->dev;
1590 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 1591 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1592 int type = intel_encoder->type;
2886e93f 1593 uint32_t val;
a836bdf9 1594 bool wait = false;
2886e93f
PZ		 1595
1596 val = I915_READ(DDI_BUF_CTL(port));
1597 if (val & DDI_BUF_CTL_ENABLE) {
1598 val &= ~DDI_BUF_CTL_ENABLE;
1599 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1600 wait = true;
2886e93f 1601 }
6441ab5f 1602
a836bdf9
PZ		 1603 val = I915_READ(DP_TP_CTL(port));
1604 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1605 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1606 I915_WRITE(DP_TP_CTL(port), val);
1607
1608 if (wait)
1609 intel_wait_ddi_buf_idle(dev_priv, port);
1610
76bb80ed 1611 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1612 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1613 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1614 intel_edp_panel_vdd_on(intel_dp);
4be73780 1615 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1616 }
1617
efa80add
S		 1618 if (IS_SKYLAKE(dev))
1619 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1620 DPLL_CTRL2_DDI_CLK_OFF(port)));
1621 else
1622 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 1623}
1624
00c09d70 1625static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1626{
6547fef8 1627 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1628 struct drm_crtc *crtc = encoder->crtc;
1629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 1630 struct drm_device *dev = encoder->dev;
72662e10 1631 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1632 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1633 int type = intel_encoder->type;
72662e10 1634
6547fef8 1635 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1636 struct intel_digital_port *intel_dig_port =
1637 enc_to_dig_port(encoder);
1638
6547fef8
PZ		 1639 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1640 * are ignored so nothing special needs to be done besides
1641 * enabling the port.
1642 */
876a8cdf 1643 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1644 intel_dig_port->saved_port_bits |
1645 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1646 } else if (type == INTEL_OUTPUT_EDP) {
1647 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1648
23f08d83 1649 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 1650 intel_dp_stop_link_train(intel_dp);
1651
4be73780 1652 intel_edp_backlight_on(intel_dp);
0bc12bcb 1653 intel_psr_enable(intel_dp);
c395578e 1654 intel_edp_drrs_enable(intel_dp);
6547fef8 1655 }
7b9f35a6 1656
6e3c9717 1657 if (intel_crtc->config->has_audio) {
d45a0bf5 1658 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 1659 intel_audio_codec_enable(intel_encoder);
7b9f35a6 1660 }
5ab432ef
DV		 1661}
1662
00c09d70 1663static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1664{
d6c50ff8 1665 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1666 struct drm_crtc *crtc = encoder->crtc;
1667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 1668 int type = intel_encoder->type;
7b9f35a6
WX		 1669 struct drm_device *dev = encoder->dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 1671
6e3c9717 1672 if (intel_crtc->config->has_audio) {
69bfe1a9 1673 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 1674 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1675 }
2831d842 1676
d6c50ff8
PZ		 1677 if (type == INTEL_OUTPUT_EDP) {
1678 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1679
c395578e 1680 intel_edp_drrs_disable(intel_dp);
0bc12bcb 1681 intel_psr_disable(intel_dp);
4be73780 1682 intel_edp_backlight_off(intel_dp);
d6c50ff8 1683 }
72662e10 1684}
79f689aa 1685
121643c2
S		 1686static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
1687{
1688 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
1689 uint32_t cdctl = I915_READ(CDCLK_CTL);
1690 uint32_t linkrate;
1691
1692 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
1693 WARN(1, "LCPLL1 not enabled\n");
1694 return 24000; /* 24MHz is the cd freq with NSSC ref */
1695 }
1696
1697 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
1698 return 540000;
1699
1700 linkrate = (I915_READ(DPLL_CTRL1) &
1701 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1702
1703 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
1704 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
1705 /* vco 8640 */
1706 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1707 case CDCLK_FREQ_450_432:
1708 return 432000;
1709 case CDCLK_FREQ_337_308:
1710 return 308570;
1711 case CDCLK_FREQ_675_617:
1712 return 617140;
1713 default:
1714 WARN(1, "Unknown cd freq selection\n");
1715 }
1716 } else {
1717 /* vco 8100 */
1718 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1719 case CDCLK_FREQ_450_432:
1720 return 450000;
1721 case CDCLK_FREQ_337_308:
1722 return 337500;
1723 case CDCLK_FREQ_675_617:
1724 return 675000;
1725 default:
1726 WARN(1, "Unknown cd freq selection\n");
1727 }
1728 }
1729
1730 /* error case, do as if DPLL0 isn't enabled */
1731 return 24000;
1732}
1733
ad13d604
DL		 1734static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1735{
1736 uint32_t lcpll = I915_READ(LCPLL_CTL);
1737 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1738
1739 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1740 return 800000;
1741 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1742 return 450000;
1743 else if (freq == LCPLL_CLK_FREQ_450)
1744 return 450000;
1745 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1746 return 540000;
1747 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1748 return 337500;
1749 else
1750 return 675000;
1751}
1752
1753static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
79f689aa 1754{
e39bf98a 1755 struct drm_device *dev = dev_priv->dev;
a4006641 1756 uint32_t lcpll = I915_READ(LCPLL_CTL);
e39bf98a 1757 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
a4006641 1758
ad13d604 1759 if (lcpll & LCPLL_CD_SOURCE_FCLK)
a4006641 1760 return 800000;
ad13d604 1761 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
b2b877ff 1762 return 450000;
ad13d604 1763 else if (freq == LCPLL_CLK_FREQ_450)
b2b877ff 1764 return 450000;
95626e7c 1765 else if (IS_HSW_ULT(dev))
ad13d604
DL		 1766 return 337500;
1767 else
1768 return 540000;
1769}
1770
1771int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1772{
1773 struct drm_device *dev = dev_priv->dev;
1774
121643c2
S		 1775 if (IS_SKYLAKE(dev))
1776 return skl_get_cdclk_freq(dev_priv);
1777
ad13d604
DL		 1778 if (IS_BROADWELL(dev))
1779 return bdw_get_cdclk_freq(dev_priv);
1780
1781 /* Haswell */
1782 return hsw_get_cdclk_freq(dev_priv);
79f689aa
PZ		 1783}
1784
e0b01be4
DV		 1785static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1786 struct intel_shared_dpll *pll)
1787{
3e369b76 1788 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 1789 POSTING_READ(WRPLL_CTL(pll->id));
1790 udelay(20);
1791}
1792
12030431
DV		 1793static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1794 struct intel_shared_dpll *pll)
1795{
1796 uint32_t val;
1797
1798 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 1799 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1800 POSTING_READ(WRPLL_CTL(pll->id));
1801}
1802
d452c5b6
DV		 1803static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1804 struct intel_shared_dpll *pll,
1805 struct intel_dpll_hw_state *hw_state)
1806{
1807 uint32_t val;
1808
f458ebbc 1809 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 1810 return false;
1811
1812 val = I915_READ(WRPLL_CTL(pll->id));
1813 hw_state->wrpll = val;
1814
1815 return val & WRPLL_PLL_ENABLE;
1816}
1817
ca1381b5 1818static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 1819 "WRPLL 1",
1820 "WRPLL 2",
1821};
1822
143b307c 1823static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 1824{
9cd86933
DV		 1825 int i;
1826
716c2e55 1827 dev_priv->num_shared_dpll = 2;
9cd86933 1828
716c2e55 1829 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 1830 dev_priv->shared_dplls[i].id = i;
1831 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 1832 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 1833 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 1834 dev_priv->shared_dplls[i].get_hw_state =
1835 hsw_ddi_pll_get_hw_state;
9cd86933 1836 }
143b307c
DL		 1837}
1838
d1a2dc78
S		 1839static const char * const skl_ddi_pll_names[] = {
1840 "DPLL 1",
1841 "DPLL 2",
1842 "DPLL 3",
1843};
1844
1845struct skl_dpll_regs {
1846 u32 ctl, cfgcr1, cfgcr2;
1847};
1848
1849/* this array is indexed by the *shared* pll id */
1850static const struct skl_dpll_regs skl_dpll_regs[3] = {
1851 {
1852 /* DPLL 1 */
1853 .ctl = LCPLL2_CTL,
1854 .cfgcr1 = DPLL1_CFGCR1,
1855 .cfgcr2 = DPLL1_CFGCR2,
1856 },
1857 {
1858 /* DPLL 2 */
1859 .ctl = WRPLL_CTL1,
1860 .cfgcr1 = DPLL2_CFGCR1,
1861 .cfgcr2 = DPLL2_CFGCR2,
1862 },
1863 {
1864 /* DPLL 3 */
1865 .ctl = WRPLL_CTL2,
1866 .cfgcr1 = DPLL3_CFGCR1,
1867 .cfgcr2 = DPLL3_CFGCR2,
1868 },
1869};
1870
1871static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1872 struct intel_shared_dpll *pll)
1873{
1874 uint32_t val;
1875 unsigned int dpll;
1876 const struct skl_dpll_regs *regs = skl_dpll_regs;
1877
1878 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1879 dpll = pll->id + 1;
1880
1881 val = I915_READ(DPLL_CTRL1);
1882
1883 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
1884 DPLL_CRTL1_LINK_RATE_MASK(dpll));
1885 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
1886
1887 I915_WRITE(DPLL_CTRL1, val);
1888 POSTING_READ(DPLL_CTRL1);
1889
1890 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
1891 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
1892 POSTING_READ(regs[pll->id].cfgcr1);
1893 POSTING_READ(regs[pll->id].cfgcr2);
1894
1895 /* the enable bit is always bit 31 */
1896 I915_WRITE(regs[pll->id].ctl,
1897 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
1898
1899 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
1900 DRM_ERROR("DPLL %d not locked\n", dpll);
1901}
1902
1903static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
1904 struct intel_shared_dpll *pll)
1905{
1906 const struct skl_dpll_regs *regs = skl_dpll_regs;
1907
1908 /* the enable bit is always bit 31 */
1909 I915_WRITE(regs[pll->id].ctl,
1910 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
1911 POSTING_READ(regs[pll->id].ctl);
1912}
1913
1914static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1915 struct intel_shared_dpll *pll,
1916 struct intel_dpll_hw_state *hw_state)
1917{
1918 uint32_t val;
1919 unsigned int dpll;
1920 const struct skl_dpll_regs *regs = skl_dpll_regs;
1921
1922 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1923 return false;
1924
1925 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1926 dpll = pll->id + 1;
1927
1928 val = I915_READ(regs[pll->id].ctl);
1929 if (!(val & LCPLL_PLL_ENABLE))
1930 return false;
1931
1932 val = I915_READ(DPLL_CTRL1);
1933 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
1934
1935 /* avoid reading back stale values if HDMI mode is not enabled */
1936 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
1937 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
1938 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
1939 }
1940
1941 return true;
1942}
1943
1944static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
1945{
1946 int i;
1947
1948 dev_priv->num_shared_dpll = 3;
1949
1950 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1951 dev_priv->shared_dplls[i].id = i;
1952 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
1953 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
1954 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
1955 dev_priv->shared_dplls[i].get_hw_state =
1956 skl_ddi_pll_get_hw_state;
1957 }
1958}
1959
143b307c
DL		 1960void intel_ddi_pll_init(struct drm_device *dev)
1961{
1962 struct drm_i915_private *dev_priv = dev->dev_private;
1963 uint32_t val = I915_READ(LCPLL_CTL);
1964
d1a2dc78
S		 1965 if (IS_SKYLAKE(dev))
1966 skl_shared_dplls_init(dev_priv);
1967 else
1968 hsw_shared_dplls_init(dev_priv);
79f689aa 1969
b2b877ff 1970 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
79f689aa
PZ		 1971 intel_ddi_get_cdclk_freq(dev_priv));
1972
121643c2
S		 1973 if (IS_SKYLAKE(dev)) {
1974 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
1975 DRM_ERROR("LCPLL1 is disabled\n");
1976 } else {
1977 /*
1978 * The LCPLL register should be turned on by the BIOS. For now
1979 * let's just check its state and print errors in case
1980 * something is wrong. Don't even try to turn it on.
1981 */
1982
1983 if (val & LCPLL_CD_SOURCE_FCLK)
1984 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 1985
121643c2
S		 1986 if (val & LCPLL_PLL_DISABLE)
1987 DRM_ERROR("LCPLL is disabled\n");
1988 }
79f689aa 1989}
c19b0669
PZ		 1990
1991void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1992{
174edf1f
PZ		 1993 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1994 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 1995 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 1996 enum port port = intel_dig_port->port;
c19b0669 1997 uint32_t val;
f3e227df 1998 bool wait = false;
c19b0669
PZ		 1999
2000 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2001 val = I915_READ(DDI_BUF_CTL(port));
2002 if (val & DDI_BUF_CTL_ENABLE) {
2003 val &= ~DDI_BUF_CTL_ENABLE;
2004 I915_WRITE(DDI_BUF_CTL(port), val);
2005 wait = true;
2006 }
2007
2008 val = I915_READ(DP_TP_CTL(port));
2009 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2010 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2011 I915_WRITE(DP_TP_CTL(port), val);
2012 POSTING_READ(DP_TP_CTL(port));
2013
2014 if (wait)
2015 intel_wait_ddi_buf_idle(dev_priv, port);
2016 }
2017
0e32b39c 2018 val = DP_TP_CTL_ENABLE |
c19b0669 2019 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2020 if (intel_dp->is_mst)
2021 val |= DP_TP_CTL_MODE_MST;
2022 else {
2023 val |= DP_TP_CTL_MODE_SST;
2024 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2025 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2026 }
c19b0669
PZ		 2027 I915_WRITE(DP_TP_CTL(port), val);
2028 POSTING_READ(DP_TP_CTL(port));
2029
2030 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2031 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2032 POSTING_READ(DDI_BUF_CTL(port));
2033
2034 udelay(600);
2035}
00c09d70 2036
1ad960f2
PZ		 2037void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2038{
2039 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2040 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2041 uint32_t val;
2042
2043 intel_ddi_post_disable(intel_encoder);
2044
2045 val = I915_READ(_FDI_RXA_CTL);
2046 val &= ~FDI_RX_ENABLE;
2047 I915_WRITE(_FDI_RXA_CTL, val);
2048
2049 val = I915_READ(_FDI_RXA_MISC);
2050 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2051 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2052 I915_WRITE(_FDI_RXA_MISC, val);
2053
2054 val = I915_READ(_FDI_RXA_CTL);
2055 val &= ~FDI_PCDCLK;
2056 I915_WRITE(_FDI_RXA_CTL, val);
2057
2058 val = I915_READ(_FDI_RXA_CTL);
2059 val &= ~FDI_RX_PLL_ENABLE;
2060 I915_WRITE(_FDI_RXA_CTL, val);
2061}
2062
00c09d70
PZ		 2063static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
2064{
0e32b39c
DA		 2065 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
2066 int type = intel_dig_port->base.type;
2067
2068 if (type != INTEL_OUTPUT_DISPLAYPORT &&
2069 type != INTEL_OUTPUT_EDP &&
2070 type != INTEL_OUTPUT_UNKNOWN) {
2071 return;
2072 }
00c09d70 2073
0e32b39c 2074 intel_dp_hot_plug(intel_encoder);
00c09d70
PZ		 2075}
2076
6801c18c 2077void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2078 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2079{
2080 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2081 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2082 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2083 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2084 u32 temp, flags = 0;
2085
2086 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2087 if (temp & TRANS_DDI_PHSYNC)
2088 flags |= DRM_MODE_FLAG_PHSYNC;
2089 else
2090 flags |= DRM_MODE_FLAG_NHSYNC;
2091 if (temp & TRANS_DDI_PVSYNC)
2092 flags |= DRM_MODE_FLAG_PVSYNC;
2093 else
2094 flags |= DRM_MODE_FLAG_NVSYNC;
2095
2d112de7 2096 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2097
2098 switch (temp & TRANS_DDI_BPC_MASK) {
2099 case TRANS_DDI_BPC_6:
2100 pipe_config->pipe_bpp = 18;
2101 break;
2102 case TRANS_DDI_BPC_8:
2103 pipe_config->pipe_bpp = 24;
2104 break;
2105 case TRANS_DDI_BPC_10:
2106 pipe_config->pipe_bpp = 30;
2107 break;
2108 case TRANS_DDI_BPC_12:
2109 pipe_config->pipe_bpp = 36;
2110 break;
2111 default:
2112 break;
2113 }
eb14cb74
VS		 2114
2115 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2116 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2117 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2118 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2119
2120 if (intel_hdmi->infoframe_enabled(&encoder->base))
2121 pipe_config->has_infoframe = true;
cbc572a9 2122 break;
eb14cb74
VS		 2123 case TRANS_DDI_MODE_SELECT_DVI:
2124 case TRANS_DDI_MODE_SELECT_FDI:
2125 break;
2126 case TRANS_DDI_MODE_SELECT_DP_SST:
2127 case TRANS_DDI_MODE_SELECT_DP_MST:
2128 pipe_config->has_dp_encoder = true;
2129 intel_dp_get_m_n(intel_crtc, pipe_config);
2130 break;
2131 default:
2132 break;
2133 }
10214420 2134
f458ebbc 2135 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 2136 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 2137 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 2138 pipe_config->has_audio = true;
2139 }
9ed109a7 2140
10214420
DV		 2141 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2142 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2143 /*
2144 * This is a big fat ugly hack.
2145 *
2146 * Some machines in UEFI boot mode provide us a VBT that has 18
2147 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2148 * unknown we fail to light up. Yet the same BIOS boots up with
2149 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2150 * max, not what it tells us to use.
2151 *
2152 * Note: This will still be broken if the eDP panel is not lit
2153 * up by the BIOS, and thus we can't get the mode at module
2154 * load.
2155 */
2156 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2157 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2158 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2159 }
11578553 2160
22606a18 2161 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2162}
2163
00c09d70
PZ		 2164static void intel_ddi_destroy(struct drm_encoder *encoder)
2165{
2166 /* HDMI has nothing special to destroy, so we can go with this. */
2167 intel_dp_encoder_destroy(encoder);
2168}
2169
5bfe2ac0 2170static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2171 struct intel_crtc_state *pipe_config)
00c09d70 2172{
5bfe2ac0 2173 int type = encoder->type;
eccb140b 2174 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2175
5bfe2ac0 2176 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2177
eccb140b
DV		 2178 if (port == PORT_A)
2179 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2180
00c09d70 2181 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2182 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2183 else
5bfe2ac0 2184 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2185}
2186
2187static const struct drm_encoder_funcs intel_ddi_funcs = {
2188 .destroy = intel_ddi_destroy,
2189};
2190
4a28ae58
PZ		 2191static struct intel_connector *
2192intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2193{
2194 struct intel_connector *connector;
2195 enum port port = intel_dig_port->port;
2196
2197 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
2198 if (!connector)
2199 return NULL;
2200
2201 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2202 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2203 kfree(connector);
2204 return NULL;
2205 }
2206
2207 return connector;
2208}
2209
2210static struct intel_connector *
2211intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2212{
2213 struct intel_connector *connector;
2214 enum port port = intel_dig_port->port;
2215
2216 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
2217 if (!connector)
2218 return NULL;
2219
2220 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2221 intel_hdmi_init_connector(intel_dig_port, connector);
2222
2223 return connector;
2224}
2225
00c09d70
PZ		 2226void intel_ddi_init(struct drm_device *dev, enum port port)
2227{
876a8cdf 2228 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2229 struct intel_digital_port *intel_dig_port;
2230 struct intel_encoder *intel_encoder;
2231 struct drm_encoder *encoder;
311a2094
PZ		 2232 bool init_hdmi, init_dp;
2233
2234 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2235 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2236 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2237 if (!init_dp && !init_hdmi) {
f68d697e 2238 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 2239 port_name(port));
2240 init_hdmi = true;
2241 init_dp = true;
2242 }
00c09d70 2243
b14c5679 2244 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2245 if (!intel_dig_port)
2246 return;
2247
00c09d70
PZ		 2248 intel_encoder = &intel_dig_port->base;
2249 encoder = &intel_encoder->base;
2250
2251 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2252 DRM_MODE_ENCODER_TMDS);
00c09d70 2253
5bfe2ac0 2254 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2255 intel_encoder->enable = intel_enable_ddi;
2256 intel_encoder->pre_enable = intel_ddi_pre_enable;
2257 intel_encoder->disable = intel_disable_ddi;
2258 intel_encoder->post_disable = intel_ddi_post_disable;
2259 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2260 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2261
2262 intel_dig_port->port = port;
bcf53de4
SM		 2263 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2264 (DDI_BUF_PORT_REVERSAL |
2265 DDI_A_4_LANES);
00c09d70
PZ		 2266
2267 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2268 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2269 intel_encoder->cloneable = 0;
00c09d70
PZ		 2270 intel_encoder->hot_plug = intel_ddi_hot_plug;
2271
f68d697e
CW		 2272 if (init_dp) {
2273 if (!intel_ddi_init_dp_connector(intel_dig_port))
2274 goto err;
13cf5504 2275
f68d697e
CW		 2276 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2277 dev_priv->hpd_irq_port[port] = intel_dig_port;
2278 }
21a8e6a4 2279
311a2094
PZ		 2280 /* In theory we don't need the encoder->type check, but leave it just in
2281 * case we have some really bad VBTs... */
f68d697e
CW		 2282 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2283 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2284 goto err;
21a8e6a4 2285 }
f68d697e
CW		 2286
2287 return;
2288
2289err:
2290 drm_encoder_cleanup(encoder);
2291 kfree(intel_dig_port);
00c09d70 2292}
Linux kernel - Deliverables
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